Stress simulation system for chip-level layout and computer equipment

Abstract

The invention provides a stress simulation system for chip-level layout and computer equipment, and belongs to the field of semiconductor device manufacturing. According to the stress management simulation system, a virtual simulation framework of a material attribute database, a simulation engine module, a thermal cycle simulation module and a layout configuration optimization module is adopted, thermal expansion and stress analysis of a material on a chip are simulated through the simulation engine module, and initialized stress data are generated; the layout of the material is optimized and adjusted through a layout configuration optimization module according to the initialized stress data; stress accumulation in a repeated thermal cycle scene is simulated through the thermal cycle simulation module, and the long-term reliability of the device is evaluated in a design stage, so that failures caused by structural problems in a later stage are avoided. Layout and materials can be optimized in the early stage, defects caused by stress are reduced, cost is reduced, and the efficiency and reliability of semiconductor device design are improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device manufacturing, and more specifically to a chip-level layout stress simulation system and computer equipment. Background Technology

[0002] In the field of semiconductor device manufacturing, especially in BCD (Bipolar-Complementary Metal-Oxide-Semiconductor-DMOS) processes, chip-level layout design is crucial for device performance and reliability. BCD processes allow the integration of bipolar, complementary metal-oxide-semiconductor, and DMOS technologies on the same chip to achieve high-performance analog and digital circuits.

[0003] In BCD (Block Continuous Deposition) technology, chip-level layout typically involves multiple different materials. These materials have different coefficients of thermal expansion, and therefore expand and contract at different rates under operating conditions. The differences in thermal expansion between these materials lead to thermal mismatch stress, which can severely impact the structural integrity of the chip.

[0004] To optimize thermal stress, existing techniques typically involve physical testing for each layout and material combination. While this approach provides accurate stress assessments, its high cost and time-consuming nature limit its application in the early design stages. Furthermore, this method cannot predict and optimize thermal stress early in the design phase, leading to extended design cycles, increased development costs, and the potential discovery of serious structural problems later in the process. Summary of the Invention

[0005] To address the aforementioned technical deficiencies, this invention provides a chip-level layout stress simulation system. Employing an innovative virtual simulation framework, it constructs a simulation model for chip-level layout in custom BCD processes, manages systemic thermal mismatch stress, and can identify potential stress problems in advance during the design phase. This optimizes material selection and layout design, reduces reliance on physical testing, significantly shortens the development cycle, lowers costs, and improves the overall performance and reliability of the product.

[0006] The chip-level layout stress simulation system provided by this invention includes: a material property database, a simulation engine module, a thermal cycling simulation module, and a layout configuration optimization module; The material property database is used to store the property parameters and layout parameters of various materials used in chip manufacturing processes; The simulation engine module is used to obtain the property parameters and layout parameters of the corresponding material from the material property database, perform thermal expansion and stress analysis based on the property parameters and layout parameters of the corresponding material, generate initial stress data, and pass the initial stress data to the layout configuration optimization module. The layout configuration optimization module is used to optimize and adjust the material layout based on the initial stress data, and return the optimized layout parameters to the simulation engine module. The simulation engine module is also used to perform simulation calculations based on the optimized and adjusted layout parameters, generate cyclic stress data, and transfer the cyclic stress data to the thermal cycling simulation module. The thermal cycling simulation module is used to simulate the long-term stress accumulation of chip layout in different temperature ranges or repeated thermal cycling scenarios based on cyclic stress data.

[0007] In this embodiment of the invention, the thermal cycling simulation module is further used to generate cumulative damage data based on stress cycling data using Miner's linear cumulative damage theory, and then transmit the cumulative damage data to the simulation engine module.

[0008] In this embodiment of the invention, the simulation engine module is also used to determine whether the current cumulative chip damage data is within the standard range. If so, it outputs the stress field data corresponding to the current chip-level layout.

[0009] In this embodiment of the invention, when the simulation engine module determines that the current cumulative chip damage data exceeds the standard range, it triggers the layout configuration optimization module to perform a re-layout.

[0010] In this embodiment of the invention, the system further includes: an interactive visualization module for stress points; The stress point interactive visualization module is connected to the simulation engine module and is used to display the stress field data output by the simulation engine module in a 3D view.

[0011] In this embodiment of the invention, the thermal cycling simulation module is configured with thermal cycling condition parameters, which include at least one of the following: temperature range, number of cycles, and heating and cooling rates.

[0012] In this embodiment of the invention, the simulation engine module obtains thermal cycling condition parameters from the thermal cycling simulation module, performs thermal-structural coupling simulation calculations based on the optimized layout parameters and thermal cycling conditions, and generates cyclic stress data based on the stress state of each cycle.

[0013] In this embodiment of the invention, the simulation engine module includes: a preprocessing unit, a solver, and a postprocessing unit; The preprocessing unit is used to simulate the thermal expansion and contraction behavior of materials on the chip and the interface stress caused by thermal expansion and contraction based on the material's property parameters and layout parameters, using finite element analysis technology, and generate initial stress data. The solver uses an implicit algorithm to solve nonlinear thermal-structural coupling and obtain cyclic stress data; The post-processing unit is used to extract stress tensor, strain distribution and displacement field from cyclic stress data, and generate stress field data and stress cycle curves.

[0014] In this embodiment of the invention, the property parameters of various materials stored in the material property database include at least one of the following: coefficient of thermal expansion, elastic modulus, Poisson's ratio, temperature-sensitive properties, and the correlation between materials and processes; The layout parameters include at least one of the following: material location, material angle, material type combination, material area, and layer thickness.

[0015] In this embodiment of the invention, the layout configuration optimization module includes a user interaction layer and an algorithm layer; The user interaction layer includes a visual interface, which is used to adjust the material's layer thickness and area, as well as set boundary conditions. The algorithm layer integrates optimization algorithms, using objective functions that aim to minimize peak stress and material cost to optimize layout parameters.

[0016] The present invention also provides a computer device including the above-described chip-level layout stress simulation system.

[0017] The stress management simulation system of this invention employs a virtual simulation framework comprising a material property database, a simulation engine module, a thermal cycling simulation module, and a layout optimization module. The simulation engine module simulates the thermal expansion and contraction behavior of materials on the chip, as well as the interfacial stresses generated by thermal expansion and contraction, generating initial stress data. The layout optimization module optimizes and adjusts the material layout based on this initial stress data. The thermal cycling simulation module simulates stress accumulation in repeated thermal cycling scenarios, assessing the long-term reliability of the device during the design phase, thereby avoiding failures caused by structural problems later on. This invention, on the one hand, can optimize layout and materials in the early stages to reduce stress-induced defects, lower costs, and increase yield. On the other hand, by utilizing the material property database and the thermal expansion stress simulation engine, it helps designers select the optimal material combination to improve device performance. This stress simulation system can significantly improve the efficiency and reliability of semiconductor device design, promoting the development of BCD process technology.

[0018] Other features and advantages of the technical solution of the present invention will be described in detail in the following detailed embodiments section. Attached Figure Description

[0019] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings: Figure 1This is a schematic diagram of the structure of the chip-level layout stress simulation system provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the logical architecture of the chip-level layout stress simulation system provided in an embodiment of the present invention. Detailed Implementation

[0020] To make the technical solutions and advantages of the embodiments of the present invention clearer, the exemplary embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of the present invention can be combined with each other.

[0021] In the description of this invention, unless otherwise explicitly specified and limited, terms such as "connected" and "linked" should be interpreted broadly. For example, they can refer to mechanical connections, electrical connections, or connections that allow for communication; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to the internal connection of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0022] This invention provides a chip-level layout stress simulation system. Employing an innovative virtual simulation framework, it constructs simulation models for chip-level layout in custom BCD (Bipolar-Complementary Metal-Oxide-Semiconductor-DMOS) processes, managing systemic thermal mismatch stress. The system integrates multiple simulation and prediction tool modules, including a simulation engine module, a thermal cycling simulation module, and a layout configuration optimization module. It achieves full-process coverage from material property databases to thermal cycling simulation, enabling early identification of potential stress problems during the design phase, optimizing material selection and layout design, reducing reliance on physical testing, significantly shortening development cycles, reducing costs, and improving overall product performance and reliability.

[0023] Figure 1 This is a schematic diagram of the chip-level layout stress simulation system provided in an embodiment of the present invention. Figure 1As shown, the chip-level layout stress simulation system provided in this embodiment includes: a material property database, a simulation engine module, a thermal cycling simulation module, a layout configuration optimization module, and a stress point interactive visualization module. The material property database stores the property parameters and layout parameters of various materials used in the chip manufacturing process. The simulation engine module retrieves the corresponding material property parameters and layout parameters from the material property database, performs thermal expansion and stress analysis based on these parameters, generates initial stress data, and transmits the initial stress data to the layout configuration optimization module. The layout configuration optimization module optimizes the material layout based on the initial stress data and returns the optimized layout parameters to the simulation engine module. The simulation engine module also performs simulation calculations based on the optimized layout parameters, generates cyclic stress data, and transmits the cyclic stress data to the thermal cycling simulation module. The thermal cycling simulation module simulates the long-term stress accumulation of the chip layout in different temperature ranges or repeated thermal cycling scenarios (simulating actual operating conditions) based on the cyclic stress data.

[0024] In a specific embodiment, the material property database employs a relational database (such as MySQL / PostgreSQL) or a distributed database, storing the thermal and mechanical property parameters of various materials used in the BCD process, including but not limited to one or more of the following: basic properties such as coefficient of thermal expansion, elastic modulus, and Poisson's ratio; temperature-sensitive properties (parameter curves changing with temperature); and a table showing the correlation between materials and process steps. The material property database also stores initial layout parameters, including but not limited to one or more of the following: material location, material angle, material type combination, material area, and layer thickness.

[0025] The material property database supports data import from Excel and API interface integration (such as linking with material supplier databases). Data retrieval offers fuzzy search and multi-condition filtering (such as filtering by process node and material type). Data updates employ a version control mechanism, recording the iteration history of material parameters. The extended interface uses a RESTful API to provide parameters to the simulation engine in real time, supporting the dynamic loading of new material data. The material property database provides accurate material property data; users can directly input the required material properties or select pre-loaded values, thereby simplifying the simulation setup process and ensuring the accuracy of simulation results.

[0026] In a specific embodiment, the simulation engine module employs a thermal expansion and stress simulation engine as the core of the system. This simulation engine uses finite element analysis (FEA) technology to simulate the thermal expansion and contraction behavior of materials on the chip, and the resulting interface stresses. By visualizing stress distribution, this simulation engine identifies areas prone to cracking or delamination, providing intuitive feedback on thermal mismatch analysis. Furthermore, through interface stress mapping, it highlights areas that may exhibit defects due to thermal property mismatches, assisting design engineers in targeted design optimization.

[0027] In a specific embodiment, the simulation engine module obtains the corresponding material's property parameters and layout parameters through the RESTful API interface of the material property database. The simulation engine module is built on finite element analysis (FEA) technology to construct a core calculation module, including a preprocessing unit, a solver, and a post-processing unit. The preprocessing unit constructs a geometric model and performs mesh generation (tetrahedral / hexahedral mesh). Based on the material's property parameters and layout parameters, it uses finite element analysis technology to simulate the thermal expansion and contraction behavior of the material on the chip, as well as the interface stresses generated by thermal expansion and contraction, generating initial stress data. The solver, based on the coupled heat conduction equation and elasticity equation, uses implicit algorithms (such as the Newton-Raphson method) to solve the nonlinear thermal-structural coupling, obtaining cyclic stress data. During the solution process, incremental solving optimizes the cyclic calculation efficiency, reusing the mesh state of the previous cycle and updating only the temperature load and boundary conditions. The post-processing unit extracts stress tensors (such as von Mises stress, principal stresses), strain distribution, and displacement fields from the cyclic stress data, generating stress field data and stress cycle curves. The simulation engine module provides intuitive feedback to users by visualizing stress distribution and identifying areas prone to cracking or delamination; it also highlights areas that may have defects due to thermal property mismatch, helping users to optimize their designs accordingly.

[0028] The layout configuration optimization module comprises a user interaction layer and an algorithm layer. The user interaction layer includes a visual interface developed using Qt or WebGL, supporting drag-and-drop of material layers, adjustment of layer thickness / area, and setting of boundary conditions (such as fixed constraints and temperature loads). The algorithm layer integrates optimization algorithms (genetic algorithm / particle swarm optimization algorithm) to generate layout schemes and optimize layout parameters with the objective functions of minimizing peak stress and minimizing material cost.

[0029] The layout optimization module employs parametric modeling, abstracting the layout into parameters such as material layer coordinates, thickness, and thermal mismatch coefficients. These parameters are then passed to the simulation engine module via API. Modifications to the layout by the optimization module trigger rapid recalculation by the simulation engine, providing real-time feedback on stress change trends. Furthermore, the module incorporates built-in process rules (such as minimum metal layer spacing and dielectric layer thickness limits) to prevent the generation of unmanufacturable designs. The module features a user interface where users can specify the material layout on the chip and modify the configuration based on simulation results to reduce thermal mismatch. The system provides automated layout suggestions based on user-defined constraints (such as material placement or structural area occupancy) to minimize thermal stress and thus optimize the design.

[0030] In a specific embodiment, the thermal cycling simulation module is configured with thermal cycling condition parameters, including: temperature range (e.g., -40℃ to 125℃), number of cycles, heating / cooling rates, and other parameter information. Users can select a temperature range in the thermal cycling simulation module to simulate stress in different temperature ranges or cycles to evaluate performance under different conditions. The simulation engine module obtains the thermal cycling condition parameters from the thermal cycling simulation module and performs multi-step thermo-structural coupling simulation calculations in the simulation engine based on the optimized layout parameters and thermal cycling conditions. It records the stress peak value and distribution changes in each cycle and generates cycle stress data based on the stress state (stress peak value and distribution changes) in each cycle. For long-cycle cycles, the equivalent load method (equivalent to a few characteristic cycles) is used to reduce the computational load. The thermal cycling simulation module can store historical cycle data, supporting rapid backtracking of the stress state of a specific cycle.

[0031] In an optional embodiment, the thermal cycling simulation module employs Miner's linear cumulative damage theory to generate cumulative damage data based on stress cycling data (such as stress cycling curves) to assess the risk of fatigue failure. This cumulative damage data is then transmitted to the simulation engine module. The simulation engine module determines whether the current chip cumulative damage data is within the standard range. If so, it outputs the stress field data corresponding to the current chip-level layout to the stress point interactive visualization module for display. If not, it triggers the layout configuration optimization module to perform a re-layout until the current chip cumulative damage data is within the standard range.

[0032] The stress point interactive visualization module is built on a WebGL / Three.js 3D rendering engine and integrates a data mapping module and interactive tools. The data mapping module maps stress values ​​to color gradients (such as Jet color scales), transparency, or geometric deformations (such as displacement magnification). The interactive tools support mouse drag rotation, scroll wheel zoom, and bounding box selection for analysis. Clicking on a stress point displays its specific values ​​(stress components in the X, Y, and Z directions).

[0033] The interactive stress point visualization module features GPU-accelerated rendering, sectioning, and data export capabilities. It utilizes WebGL shaders for real-time rendering of large-scale data, avoiding interface lag. It supports planar / curved surface sectioning to view the internal stress distribution of the chip, aiding in locating stress concentration issues at interface layers (such as metal-dielectric interfaces). This module can generate or export stress contour maps, animated videos, or CSV format data.

[0034] The stress point interactive visualization module connects to the simulation engine module and the layout configuration optimization module to display the stress field data (stress concentration areas) output by the simulation engine module in a 3D view. Engineers can adjust the viewing angle through the interactive interface to confirm whether the stress concentration is caused by material interface mismatch (such as the α difference between SiO2 and Al) or unreasonable layout (such as sharp corners). They can then manually fine-tune the layout or change the material, repeating the above process until the design goals are met.

[0035] Figure 2 This is a schematic diagram of the logical architecture of the chip-level layout stress simulation system provided in an embodiment of the present invention. Figure 2 As shown, the stress simulation system includes: a material property database, a simulation engine module, a thermal cycling simulation module, a layout optimization module, and a stress point interactive visualization module. The data interaction logic between these modules is as follows: The simulation engine module retrieves material property parameters from the material property database for thermal expansion and stress analysis, generates initial stress data, and transmits it to the layout optimization module. The layout optimization module optimizes the material layout based on the initial stress data and returns the optimized layout parameters to the simulation engine module. The simulation engine module performs simulation calculations based on the optimized layout parameters, generates cyclic stress data, and transmits it to the thermal cycling simulation module. The thermal cycling simulation module performs thermal cycling simulations based on the cyclic stress data, simulates long-term stress behavior, generates cumulative damage data, and transmits it to the simulation engine module. The simulation engine module determines whether the current chip cumulative damage data is within the standard range, determines the final stress field data, and outputs it to the stress point interactive visualization module for display. The stress point interactive visualization module responds to user operations, generates user interaction commands, and transmits them to the layout optimization module, triggering the layout optimization module to perform re-layout optimization, generating optimized layout parameters, which are then transmitted to the simulation engine module. Thermal expansion and stress simulation calculations are then performed again until the final stress field data meets the requirements.

[0036] The collaborative workflow between the various modules in the stress simulation system is as follows: Step 1: Initial Modeling. Engineers define the chip layer structure (such as silicon substrate, oxide layer, and metal interconnect layer) through the layout configuration module and retrieve the material parameters (coefficient of thermal expansion, elastic modulus, etc.) of each layer from the material property database. The layout parameters (layer thickness, area, and position) are passed to the simulation engine in JSON format. The engine generates a finite element model and meshes it (e.g., dividing the chip into 100,000 tetrahedral elements).

[0037] Step 2: Static Thermal Stress Analysis. The simulation engine module performs steady-state thermal analysis, calculating the difference in thermal expansion of the chip at the target temperature (e.g., 100℃), and generating a stress distribution matrix (containing the von Mises stress value of each element). The results are returned to the layout configuration module. If the stress peak exceeds a threshold (e.g., 200MPa), an optimization algorithm is triggered to automatically adjust the layer thickness or material combination (e.g., replacing a metal layer with an alloy with better thermal matching).

[0038] Step 3: Thermal Cycling Reliability Assessment. The optimized layout scheme is again fed into the simulation engine module, while the thermal cycling simulation module is configured with cycling conditions (e.g., -40℃ to 125℃, 1000 cycles). The simulation engine module performs transient thermo-structural coupling analysis, returning stress amplitude data to the thermal cycling simulation module after each cycle. The module calculates the cumulative damage degree according to the Miner criterion (e.g., D=0.3 indicates approaching the failure threshold). If the damage degree exceeds the limit, the module automatically adjusts the cycling parameters (e.g., reducing the temperature range) or triggers layout re-optimization.

[0039] Step 4: Visualization and Decision Making. The simulation engine module transmits the final stress field data to the stress point interactive visualization module, highlighting high-stress areas in red. Users can adjust the viewing angle through the interactive interface to confirm whether the stress concentration is caused by material interface mismatch (such as the α difference between SiO2 and Al) or unreasonable layout (such as sharp corners). Then, they can manually fine-tune the layout or change materials, repeating the above process until the design goal is met.

[0040] The data transfer process between the thermal cycling simulation module and the simulation engine module includes: the thermal cycling simulation module sending cycle control commands to the simulation engine module (e.g., "Cycle 1: Heating rate 5℃ / min, hold at 125℃ for 30 minutes"); and the simulation engine module returning stress response data (e.g., the stress peak sequence and cumulative plastic strain within that cycle) to the thermal cycling simulation module after each single-step cycle calculation. The thermal cycling simulation module and the simulation engine module collaborate technically. The simulation engine module optimizes cycle calculation efficiency through incremental solving, reusing the mesh state from the previous cycle and updating only the temperature load and boundary conditions. Based on the stress-cycle number curve output by the engine, the thermal cycling module fits a fatigue life prediction model (e.g., the Basquin equation), providing a quantitative basis for process reliability.

[0041] Through the aforementioned technical means and collaborative mechanisms, this stress simulation system achieves a closed-loop process from material parameter input to layout optimization, stress simulation, and reliability prediction, significantly improving the efficiency and accuracy of thermal compatibility analysis for BCD process chips. This system provides semiconductor design engineers with an efficient method to optimize material selection and layout design during the design phase, reduce stress-induced defects, increase chip yield and reliability, reduce reliance on physical prototype testing, significantly shorten development cycles, lower costs, and improve overall product performance and reliability.

[0042] The chip-level layout stress simulation system provided in this invention addresses the stress in custom BCD process chip-level layout by employing thermal cycling simulation technology to predict stress accumulation under multiple temperature variations. By simulating stress accumulation under actual operating conditions, the system can anticipate reliability issues, prevent chip cracking and structural deformation, and enable designers to assess device long-term reliability during the design phase, thereby avoiding failures caused by structural problems later on. On one hand, an automated layout optimization module provides layout adjustment suggestions to minimize high-stress areas, optimizing layout and materials in the early stages to reduce stress-induced defects, lower costs, and increase yield. On the other hand, a material property database and thermal expansion stress simulation engine provide a scientific basis for material selection. By providing accurate material property data, it helps designers select the optimal material combination to improve device performance. This stress simulation system significantly improves the efficiency and reliability of semiconductor device design, promoting the development of BCD process technology.

[0043] The present invention also provides a computer device, which includes the above-described chip-level layout stress simulation system.

[0044] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The solutions in the embodiments of the present invention can be implemented using various computer languages, such as the object-oriented programming language Java and the interpreted scripting language JavaScript.

[0045] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0046] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0047] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0048] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention. Clearly, those skilled in the art can make various alterations and modifications to the invention without departing from its spirit and scope. Thus, if these modifications and modifications of the invention fall within the scope of the claims and their equivalents, the invention is also intended to include these modifications and modifications.

Claims

1. A chip-level layout stress simulation system, characterized in that, include: Material property database, simulation engine module, thermal cycling simulation module, and layout configuration optimization module; The material property database is used to store the property parameters and layout parameters of various materials used in chip manufacturing processes; The simulation engine module is used to obtain the property parameters and layout parameters of the corresponding material from the material property database, perform thermal expansion and stress analysis based on the property parameters and layout parameters of the corresponding material, generate initial stress data, and pass the initial stress data to the layout configuration optimization module. The layout configuration optimization module is used to optimize and adjust the material layout based on the initial stress data, and return the optimized layout parameters to the simulation engine module. The simulation engine module is also used to perform simulation calculations based on the optimized and adjusted layout parameters, generate cyclic stress data, and transfer the cyclic stress data to the thermal cycling simulation module. The thermal cycling simulation module is used to simulate the long-term stress accumulation of chip layout in different temperature ranges or repeated thermal cycling scenarios based on cyclic stress data.

2. The chip-level layout stress simulation system according to claim 1, characterized in that, The thermal cycling simulation module is also used to generate cumulative damage data based on stress cycling data using Miner's linear cumulative damage theory, and then transmit the cumulative damage data to the simulation engine module.

3. The chip-level layout stress simulation system according to claim 2, characterized in that, The simulation engine module is also used to determine whether the current cumulative chip damage data is within the standard range. If so, it outputs the stress field data corresponding to the current chip-level layout.

4. The chip-level layout stress simulation system according to claim 3, characterized in that, When the simulation engine module determines that the current cumulative chip damage data exceeds the standard range, it triggers the layout configuration optimization module to perform a re-layout.

5. The chip-level layout stress simulation system according to claim 3, characterized in that, The system also includes: an interactive visualization module for stress points; The stress point interactive visualization module is connected to the simulation engine module and is used to display the stress field data output by the simulation engine module in a 3D view.

6. The chip-level layout stress simulation system according to claim 1, characterized in that, The thermal cycling simulation module is configured with thermal cycling condition parameters, which include at least one of the following: temperature range, number of cycles, and heating and cooling rates.

7. The chip-level layout stress simulation system according to claim 6, characterized in that, The simulation engine module obtains thermal cycling condition parameters from the thermal cycling simulation module, performs thermal-structural coupling simulation calculations based on the optimized layout parameters and thermal cycling conditions, and generates cyclic stress data based on the stress state of each cycle.

8. The chip-level layout stress simulation system according to claim 1, characterized in that, The simulation engine module includes: a preprocessing unit; The preprocessing unit is used to simulate the thermal expansion and contraction behavior of materials on the chip and the interface stress caused by thermal expansion and contraction based on the material's property parameters and layout parameters, using finite element analysis technology, and generate initial stress data.

9. The chip-level layout stress simulation system according to claim 8, characterized in that, The simulation engine module includes: a solver and a post-processing unit; The solver uses an implicit algorithm to solve nonlinear thermal-structural coupling and obtain cyclic stress data; The post-processing unit is used to extract stress tensor, strain distribution and displacement field from cyclic stress data, and generate stress field data and stress cycle curves.

10. The chip-level layout stress simulation system according to claim 1, characterized in that, The material property database stores various material property parameters including at least one of the following: coefficient of thermal expansion, elastic modulus, Poisson's ratio, temperature-sensitive properties, and the relationship between materials and processes; The layout parameters include at least one of the following: material location, material angle, material type combination, material area, and layer thickness.

11. The chip-level layout stress simulation system according to claim 1, characterized in that, The layout configuration optimization module includes a user interaction layer and an algorithm layer; The user interaction layer includes a visual interface, which is used to adjust the material's layer thickness and area, as well as set boundary conditions. The algorithm layer integrates optimization algorithms, using objective functions that aim to minimize peak stress and material cost to optimize layout parameters.

12. A computer device, characterized in that, The computer device includes the chip-level layout stress simulation system according to any one of claims 1-11.

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