Chip product generation method and device, computer equipment, readable storage medium and program product
By generating target function netlists and physical layouts, the chip design process is optimized, solving the problem of low efficiency in the R&D and manufacturing of multi-chip integrated products, and achieving automated processes and compatibility.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI LINGRUI INTELLIGENT CORE COMPUTING TECHNOLOGY CO LTD
- Filing Date
- 2026-01-15
- Publication Date
- 2026-05-08
AI Technical Summary
In the existing technology, the research and development and manufacturing efficiency of multi-chip integrated products is low. Different versions of chips need to be designed separately and undergo independent design, verification and tape-out processes, resulting in low efficiency.
By using interconnect logic generation strategies, layout generation algorithms, and verification strategies, target functional netlists and physical layouts are generated, and virtual assembly and verification are performed to optimize physical design constraints, ensure lithography compliance, and realize automated processes for chip products.
It improves the efficiency and quality of chip design, ensures the compatibility and flexibility of the final physical design, and supports the manufacturing of different products.
Smart Images
Figure CN121997876A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit design and manufacturing technology, and in particular to a method, apparatus, computer equipment, readable storage medium and program product for generating a chip product. Background Technology
[0002] As semiconductor technology continues to advance and approaches physical limits, the design of large-sized single chips faces increasing complexity. Against this backdrop, multi-chip integration technology, particularly wafer-level integrated interconnect (ICI) technology, which uses high-density interconnection of multiple smaller wafers (or chiplets) on a plane to build larger-scale computing systems, has become an important development direction in the industry.
[0003] In related technologies, monolithic dies with different functions or sizes are designed for different target markets (such as mid-range and high-end), and dedicated chip versions with different physical layouts and interconnect interfaces are designed for scenarios requiring multi-chip integration. These different versions of chips need to undergo independent and complete design, verification, and tape-out processes, resulting in low efficiency in chip product development and manufacturing. Summary of the Invention
[0004] Therefore, it is necessary to provide a method, apparatus, computer equipment, readable storage medium, and program product for generating chip products that can improve the efficiency of chip product research and development and manufacturing, in response to the above-mentioned technical problems.
[0005] In a first aspect, this application provides a method for manufacturing a chip product, including:
[0006] Based on the interconnect logic generation strategy, the initial functional netlist and chip design data are processed to obtain the target functional netlist of the chip to be generated.
[0007] Based on the layout generation algorithm, the target functional netlist, and the chip design data, a target physical layout generation strategy is determined.
[0008] In the virtual assembly module, the chip to be generated is virtually assembled based on the target functional netlist and the target physical layout generation strategy to obtain an initial system-level layout; the initial system-level layout is verified based on the verification strategy to obtain the verification result; if the verification result meets the preset verification completion condition, the physical design data corresponding to the system-level layout that meets the verification completion condition is output.
[0009] In one embodiment, the process of processing the initial functional netlist and chip design data based on the interconnect logic generation strategy to obtain the target functional netlist of the chip to be generated includes:
[0010] Based on the chip design data, determine the interconnect interfaces to be processed for the chip to be generated;
[0011] Each interconnection interface that meets the activation conditions is activated to obtain an activated interconnection interface; based on a redundancy processing strategy, each interconnection interface that does not meet the activation conditions is redundant to obtain a redundant interface.
[0012] Based on the preset IP library, each of the activated interconnect interfaces is instantiated to obtain each instantiated interconnect module;
[0013] Based on each instantiated interconnect module and each redundant interface, the initial functional netlist is updated to determine the target functional netlist of the chip to be generated.
[0014] In one embodiment, the chip design data includes at least the physical layout data of the chip to be generated; determining the target physical layout generation strategy based on the layout generation algorithm, the target functional netlist, and the chip design data includes:
[0015] Based on the physical layout data, position constraint strategies are generated for each instantiated interconnect module in the target functional netlist; based on the target functional netlist, interconnect links between chips to be generated are determined; based on the chip design data, interconnect routing channel constraint strategies for each interconnect link are determined; based on interconnect channel delay thresholds, timing constraint strategies for each interconnect link are determined.
[0016] Based on the location constraint strategy, the interconnect wiring channel constraint strategy, and the timing constraint strategy, the target physical layout generation strategy is determined.
[0017] In one embodiment, determining the target physical layout generation strategy based on the location constraint strategy, the interconnect routing channel constraint strategy, and the timing constraint strategy includes:
[0018] If the interconnect routing channel constraint strategy does not meet the screening conditions, the interconnect routing channel constraint strategy is optimized to obtain an optimized interconnect routing channel strategy.
[0019] If the timing constraint strategy does not meet the screening conditions, the timing constraint strategy is optimized to obtain a timing optimization strategy.
[0020] Based on the location constraint strategy, the interconnect wiring channel optimization strategy, and the timing optimization strategy, a target physical layout generation strategy is determined.
[0021] In one embodiment, the verification result includes size comparison result and signal verification result. The verification of the initial system-level layout based on the verification strategy to obtain the verification result includes:
[0022] Determine the bounding box size of the initial system-level layout, compare the bounding box size with a preset size threshold, and obtain the size comparison result;
[0023] Based on a systematic verification strategy, the timing information and signal integrity information of the initial system-level layout are verified to obtain the signal verification results.
[0024] In one embodiment, the method further includes:
[0025] If the size comparison result is that the bounding box size is greater than or equal to the preset size threshold, and / or the signal verification result is that the timing information exceeds the preset timing range and the signal integrity information does not meet the preset integrity condition, then it is determined that the verification result does not meet the preset verification completion condition, and the deviation data of the initial system-level layout is determined. In the correspondence between the deviation data and the optimization strategy, the target optimization strategy corresponding to the deviation data is generated.
[0026] Based on the target optimization strategy, the target physical layout generation strategy is modified to obtain a modified physical layout generation strategy. Based on the modified physical layout generation strategy, the step of virtually assembling the chip to be generated in the virtual assembly module based on the target functional netlist and the target physical layout generation strategy to obtain an initial system-level layout is continued until the verification result meets the verification completion condition.
[0027] Secondly, this application also provides a chip product manufacturing apparatus, comprising:
[0028] The processing module is used to process the initial functional netlist and chip design data based on the interconnect logic generation strategy to obtain the target functional netlist of the chip to be generated.
[0029] The determination module is used to determine the target physical layout generation strategy based on the layout generation algorithm, the target functional netlist, and the chip design data;
[0030] The verification module is used in the virtual assembly module to virtually assemble the chip to be generated based on the target functional netlist and the target physical layout generation strategy to obtain an initial system-level layout; to verify the initial system-level layout based on the verification strategy to obtain a verification result; and to output the physical design data corresponding to the system-level layout that meets the verification completion conditions if the verification result meets the preset verification completion conditions.
[0031] Thirdly, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to perform the following steps:
[0032] Based on the interconnect logic generation strategy, the initial functional netlist and chip design data are processed to obtain the target functional netlist of the chip to be generated.
[0033] Based on the layout generation algorithm, the target functional netlist, and the chip design data, a target physical layout generation strategy is determined.
[0034] In the virtual assembly module, the chip to be generated is virtually assembled based on the target functional netlist and the target physical layout generation strategy to obtain an initial system-level layout; the initial system-level layout is verified based on the verification strategy to obtain the verification result; if the verification result meets the preset verification completion condition, the physical design data corresponding to the system-level layout that meets the verification completion condition is output.
[0035] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, performs the following steps:
[0036] Based on the interconnect logic generation strategy, the initial functional netlist and chip design data are processed to obtain the target functional netlist of the chip to be generated.
[0037] Based on the layout generation algorithm, the target functional netlist, and the chip design data, a target physical layout generation strategy is determined.
[0038] In the virtual assembly module, the chip to be generated is virtually assembled based on the target functional netlist and the target physical layout generation strategy to obtain an initial system-level layout; the initial system-level layout is verified based on the verification strategy to obtain the verification result; if the verification result meets the preset verification completion condition, the physical design data corresponding to the system-level layout that meets the verification completion condition is output.
[0039] Fifthly, this application also provides a computer program product, including a computer program that, when executed by a processor, performs the following steps:
[0040] Based on the interconnect logic generation strategy, the initial functional netlist and chip design data are processed to obtain the target functional netlist of the chip to be generated.
[0041] Based on the layout generation algorithm, the target functional netlist, and the chip design data, a target physical layout generation strategy is determined.
[0042] In the virtual assembly module, the chip to be generated is virtually assembled based on the target functional netlist and the target physical layout generation strategy to obtain an initial system-level layout; the initial system-level layout is verified based on the verification strategy to obtain the verification result; if the verification result meets the preset verification completion condition, the physical design data corresponding to the system-level layout that meets the verification completion condition is output.
[0043] The aforementioned chip product generation method, apparatus, computer equipment, readable storage medium, and program product, through processing the initial functional netlist and chip design data based on an interconnect logic generation strategy, obtain the target functional netlist of the chip to be generated, enabling pre-configuration of each interface module to facilitate reuse of the chip product in subsequent incremental tape-outs, thereby improving chip design efficiency; based on the layout generation algorithm, the target functional netlist, and the chip design data, a target physical layout generation strategy is determined; in the virtual assembly module, based on the target functional netlist and the target physical layout generation strategy, the chip to be generated is virtually assembled to obtain an initial system-level version. The diagram shows that, based on the verification strategy, the initial system-level layout is verified to obtain the verification result. If the verification result meets the preset verification completion conditions, the physical design data corresponding to the system-level layout that meets the verification completion conditions is output. By generating physical design constraints and performing virtual assembly and lithography compliance testing of multi-chip systems, the physical layout constraint strategies of each target are verified. Only when the verification is passed is the final physical design data output. This constructs a complete automated process, improves the efficiency and quality of chip design, ensures that the final physical design is fully compatible with the same set of photomasks, and allows for the flexible selection of post-manufacturing processes to derive different products. Attached Figure Description
[0044] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0045] Figure 1 This is a flowchart illustrating a method for generating a chip product in one embodiment;
[0046] Figure 2 This is a flowchart illustrating a method for generating a chip product in one embodiment;
[0047] Figure 3 This is a flowchart illustrating a method for generating a chip product in one embodiment;
[0048] Figure 4This is a flowchart illustrating a method for generating a chip product in one embodiment;
[0049] Figure 5 This is a structural block diagram of a chip product manufacturing apparatus in one embodiment;
[0050] Figure 6 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation
[0051] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0052] In one exemplary embodiment, such as Figure 1 As shown, a method for generating a chip product is provided. This embodiment illustrates the application of this method to a terminal. It is understood that this method can also be applied to a server, and further to a system including both a terminal and a server, and is implemented through interaction between the terminal and the server. In this embodiment, the method includes the following steps:
[0053] Step 101: Based on the interconnect logic generation strategy, process the initial functional netlist and chip design data to obtain the target functional netlist of the chip to be generated.
[0054] The interconnect logic generation strategy is a design strategy for the functional logic of the chip to be generated. This strategy is used to configure redundant interconnect interface modules for the chip. The functional netlist is a structured text file describing the logical functions of the chip. Optionally, this structured text data is a file describing each circuit element and their interconnection relationships. It is the output of logic synthesis and the input of physical design. For example, circuit elements include gate circuits, transistors, etc. The initial functional netlist can include structured text files of the existing logical functions of the chip to be generated, that is, the chip to be generated can be a chip for incremental tape-out. Chip design data can be chip definition data, which can include the type of system-level layout, bandwidth, etc. The type of system-level layout can include one of single-chip, dual-chip, and multi-chip. The specific bandwidth data of each type of chip in each system-level layout can be designed based on the actual application scenario and is not specifically limited here. Optionally, the interconnect logic generation strategy can be executed on the die-to-die (D2D) redundancy module automatic configuration engine. The target function netlist is a structured text file of logical functions generated from chip design data. The target function netlist includes each instantiated interconnect module and each redundant interface on the chip to be generated.
[0055] Specifically, the terminal determines the interconnect interfaces to be processed for the chip to be generated based on the chip design data; activates the interconnect interfaces that meet the activation conditions to obtain activated interconnect interfaces; performs redundancy processing on the interconnect interfaces that do not meet the activation conditions based on the redundancy processing strategy to obtain redundant interfaces; instantiates the activated interconnect interfaces based on the preset IP library to obtain instantiated interconnect modules; and updates the initial functional netlist based on the instantiated interconnect modules and the redundant interfaces to determine the target functional netlist for the chip to be generated.
[0056] Step 102: Based on the layout generation algorithm, target functional netlist, and chip design data, determine the target physical layout generation strategy.
[0057] The layout generation algorithm is used to generate physical layout constraints for the D2D redundant interfaces or activation modules of the chip to be generated, where the activation module refers to the instantiated interconnect module. Chip design data includes the physical layout data of the chip to be generated, which at least includes the placement location of the chip. The target physical layout generation strategy includes at least a location constraint strategy, an interconnect routing channel constraint strategy, and a timing constraint strategy. Optionally, the layout generation algorithm can run on a product-pattern-based automatic physical layout constraint generation engine and an Inter-Chip Interconnect (ICI)-aware layout optimization engine.
[0058] Specifically, based on physical layout data, the terminal generates position constraint strategies corresponding to each instantiated interconnect module in the target functional netlist; based on the target functional netlist, it determines the interconnect links between the chips to be generated; based on chip design data, it determines the interconnect routing channel constraint strategy for each interconnect link; based on the interconnect channel delay threshold, it determines the timing constraint strategy for each interconnect link; and based on the position constraint strategy, interconnect routing channel constraint strategy, and timing constraint strategy, it determines the target physical layout generation strategy.
[0059] Step 103: In the virtual assembly module, based on the target functional netlist and the target physical layout generation strategy, the chip to be generated is virtually assembled to obtain the initial system-level layout; based on the verification strategy, the initial system-level layout is verified to obtain the verification result; if the verification result meets the preset verification completion conditions, the physical design data corresponding to the system-level layout that meets the verification completion conditions is output.
[0060] The virtual assembly module can be a random access memory (RAM) that virtually assembles multiple wafers. In a computer-aided design environment, the virtual assembly module digitizes and combines the physical layout data of multiple wafers (dies) according to predetermined relative positions to form a virtual model of a complete system. The system-level layout refers to the complete physical layout covering all wafers, interconnections between wafers, and peripheral auxiliary structures. The initial system-level layout is a virtual system-level layout. The verification results include the size comparison results of the peripheral boxes in the initial system-level layout and the signal verification results. Optionally, the signal verification results include timing information and signal integrity verification results. The preset verification completion condition is that the verification results are within a preset deviation range. Optionally, the deviation data between the verification results and the corresponding preset threshold, i.e., the preset verification completion condition, is that the deviation data of the verification results is within the preset deviation range.
[0061] Specifically, in the virtual assembly module, the chips to be generated are virtually assembled based on the target functional netlist and the target physical layout generation strategy to obtain an initial system-level layout; based on the verification strategy, the initial system-level layout is verified to obtain the verification result; if the verification result meets the preset verification completion conditions, the physical design data corresponding to the system-level layout that meets the verification completion conditions is output.
[0062] The aforementioned chip product generation method processes the initial functional netlist and chip design data based on an interconnect logic generation strategy to obtain the target functional netlist of the chip to be generated. This allows for the pre-configuration of each interface module, facilitating reuse of the chip product in subsequent incremental tape-outs and improving chip design efficiency. Based on the layout generation algorithm, the target functional netlist, and the chip design data, a target physical layout generation strategy is determined. In the virtual assembly module, the chip to be generated is virtually assembled based on the target functional netlist and the target physical layout generation strategy to obtain an initial system-level layout. The initial system-level layout is verified based on a verification strategy, and verification results are obtained. If the verification results meet preset verification completion conditions, the physical design data corresponding to the system-level layout that meets the verification completion conditions is output. By generating physical design constraints and performing multi-wafer system virtual assembly and lithography compliance testing, the target physical layout constraint strategies are verified. Only when verification is passed is the final physical design data output. This constructs a complete automated process, improving chip design efficiency and quality, ensuring that the final physical design is fully compatible with the same photomask, and allowing for the flexible selection of post-manufacturing processes to derive different products.
[0063] In an exemplary embodiment, the specific implementation process of step 101, "processing the initial functional netlist and chip design data based on the interconnect logic generation strategy to obtain the target functional netlist of the chip to be generated," may include:
[0064] Based on chip design data, the interconnect interfaces to be processed for the chip to be generated are determined; the interconnect interfaces that meet the activation conditions are activated to obtain activated interconnect interfaces; based on a redundancy processing strategy, the interconnect interfaces that do not meet the activation conditions are redundantly processed to obtain redundant interfaces; based on a preset IP library, the activated interconnect interfaces are instantiated to obtain instantiated interconnect modules; based on the instantiated interconnect modules and the redundant interfaces, the initial functional netlist is updated to determine the target functional netlist for the chip to be generated.
[0065] The interconnect interfaces to be processed are all physical interfaces related to the chip data. Activation conditions determine whether each interconnect interface needs to be activated; different chip design data correspond to different activation conditions. The preset IP library can be a pre-verified IP library. The redundancy handling strategy generates physical placeholder units and disables interface logic for physical interfaces that do not meet the activation conditions. The physical placeholder units are physically placed on the chip to be processed, and these physical placeholder units can be symmetrically placed on the chip with the activated interconnect interfaces. Optionally, the instantiated interconnect module is a D2D IP core. An IP core refers to a pre-designed, verified, and reusable circuit functional module. The instantiated interconnect module is provided by the D2D interface in the form of a hard IP core.
[0066] Specifically, the terminal can parse the chip design data to obtain the interconnect interfaces to be processed for the chip to be generated. Based on the correspondence between the chip design data and activation conditions, the terminal can determine the activation conditions corresponding to the chip design data; identify the interconnect interfaces to be processed that meet the activation conditions, and activate these interconnect interfaces to obtain activated interconnect interfaces; optionally, the identifiers of the interconnect interfaces to be processed that meet the activation conditions can be updated to activation identifiers. The terminal can identify the interconnect interfaces to be processed that do not meet the activation conditions, and based on a redundancy processing strategy, perform redundancy processing on these interconnect interfaces to obtain redundant interfaces; optionally, redundancy processing includes generating physical station units for inactive physical interfaces and logically disabling redundant interfaces through a logic disable module, which can be a power supply or gating mechanism. From a preset IP library, the terminal selects and instantiates each activated interconnect interface to obtain instantiated interconnect modules; based on each instantiated interconnect module and each redundant interface, the initial functional netlist is updated to determine the target functional netlist for the chip to be generated. Optionally, the terminal can select an IP core corresponding to the activated interconnect interface from a preset IP library, instantiate the IP core to obtain the instantiated IP core, and connect the instantiated IP core to the internal bus of the chip to generate an instantiated interconnect module.
[0067] For example, the chip design data indicates that the chip to be generated is a single chip. The activation condition for this single chip is to activate one side of the interconnect interface. The specific side of the interconnect interface to be activated is related to the placement position of the chip defined in the chip design data. Optionally, if the physical layout data of the chip design data defines the chip as a left chip, then the right side interface of the chip to be generated needs to be activated. It should be understood that the example here is only for illustration and does not constitute a specific limitation.
[0068] In this embodiment, the initial functional netlist and chip design data are processed through an interconnect logic generation strategy to obtain the target functional netlist of the chip to be generated. This enables different chip designs based on product definitions, achieves automatic adaptation to different product requirements, realizes chip design reuse, and improves chip design efficiency.
[0069] In one exemplary embodiment, the chip design data includes at least the physical layout data of the chip to be generated; such as Figure 2 As shown, the specific implementation process of step 102, "determine the target physical layout generation strategy based on the layout generation algorithm, the target functional netlist, and chip design data," may include:
[0070] Step 201: Based on the physical layout data, generate the position constraint strategy corresponding to each instantiated interconnect module in the target functional netlist; based on the target functional netlist, determine the interconnect links between the chips to be generated; based on the chip design data, determine the interconnect routing channel constraint strategy for each interconnect link; based on the interconnect channel delay threshold, determine the timing constraint strategy for each interconnect link.
[0071] Physical layout data refers to the relative positions of the chips to be generated. Position constraint strategies are strategies that constrain the specific positions of each instantiated interconnect module on the chip plane. Interconnect routing channel constraint strategies are channel constraint strategies in physical design that connect the laid-out units with metal lines according to circuit logic relationships. Interconnect routing channel constraint strategies automatically reserve high-layer metal routing channels and designate them as the preferred layers for ICI interconnects. ICI interconnects refer to a high-density, high-performance electrical connection technology between two or more dies achieved at the wafer level through direct bonding of the top metal layer.
[0072] Specifically, based on physical layout data, the terminal generates position constraint strategies corresponding to each instantiated interconnect module in the target functional netlist. Optionally, edge alignment constraints are generated for each activated instantiated interconnect module, forcing it to be placed in the position specified in the target functional netlist. Based on the target functional netlist, interconnect links between the chips to be generated are determined. Based on chip design data, interconnect routing channel constraint strategies for each interconnect link are determined. Optionally, the chip to be generated includes at least multiple metal layers. The terminal can configure routing only for the higher metal layers, generate interconnect routing channel constraint strategies, reserve higher metal routing channels, and designate the higher metal routing channels as the preferred layers for ICI interconnects. The specific number of reserved higher metal layers is related to the actual application scenario and is not specifically limited here.
[0073] The terminal determines the timing constraint strategy for each interconnection link based on the interconnection channel delay threshold. Optionally, it determines the timing constraint strategy for cross-die links based on the interconnection delay requirement, where the interconnection delay requirement refers to the period of path bits.
[0074] Step 202: Determine the target physical layout generation strategy based on the location constraint strategy, interconnection routing channel constraint strategy, and timing constraint strategy.
[0075] Specifically, the constraint strategies and timing constraints of each interconnect cabling channel are verified to obtain the verification results. Based on the verification results, corresponding optimization strategies are generated. Based on each optimization strategy and the location constraint strategy, the target physical layout generation strategy is determined.
[0076] In this embodiment, the target physical layout generation strategy is determined by using a layout generation algorithm, a target functional netlist, and chip design data. Priority is given to ensuring the performance and reliability of the ICI interconnect. Furthermore, the constraint strategies are verified, and an optimization strategy for the constraint strategies is generated, which further improves the performance and reliability of the interconnect.
[0077] In an exemplary embodiment, the specific implementation process of the step "determining the target physical layout generation strategy based on location constraint strategy, interconnect wiring channel constraint strategy, and timing constraint strategy" may include:
[0078] If the interconnect routing channel constraint strategy does not meet the screening conditions, the interconnect routing channel constraint strategy is optimized to obtain the interconnect routing channel optimization strategy; if the timing constraint strategy does not meet the screening conditions, the timing constraint strategy is optimized to obtain the timing optimization strategy; based on the location constraint strategy, the interconnect routing channel optimization strategy, and the timing optimization strategy, the target physical layout generation strategy is determined.
[0079] Among them, the screening criteria are the conditions used to determine the interconnect cabling channel constraint strategy and timing constraint strategy in relation to the design requirements.
[0080] Specifically, if the interconnect cabling channel constraint strategy does not meet the preset cabling rules, then it is determined that the interconnect cabling channel constraint strategy does not meet the screening conditions. Optionally, the preset cabling rule is uniform cabling. The terminal can detect the cabling utilization rate through detection tools, and determine whether the preset cabling rule is met based on the cabling utilization rate and the cabling threshold.
[0081] The terminal can identify the delay duration of each interconnect path corresponding to the timing constraint strategy, compare the delay duration with the preset total delay duration, and if the delay duration is greater than the preset total delay duration, it is determined that the timing constraint strategy does not meet the screening conditions, and the timing constraint strategy is optimized to obtain the timing optimization strategy; optionally, the terminal can optimize the timing by selecting driver enhancement and buffer insertion in the interconnect link.
[0082] Optionally, the target physical layout generation strategy may include a location constraint strategy, an interconnect routing channel optimization strategy, and a timing optimization strategy, or may include a location constraint strategy, an interconnect routing channel optimization strategy, and a timing optimization strategy, or may include a location constraint strategy, an interconnect routing channel optimization strategy, and a timing constraint strategy, or may include a location constraint strategy, an interconnect routing channel constraint strategy, and a timing constraint strategy.
[0083] In this embodiment, the target physical layout generation strategy is determined based on location constraint strategy, interconnect wiring channel constraint strategy and timing constraint strategy, thereby optimizing each constraint strategy and improving the reliability of the target physical layout generation strategy.
[0084] In an exemplary embodiment, the verification results include size comparison results and signal verification results. The specific implementation process of step 103, "verifying the initial system-level layout based on the verification strategy to obtain the verification results," may include:
[0085] The bounding box size of the initial system-level layout is determined, and the bounding box size is compared with a preset size threshold to obtain the size comparison result. Based on a systematic verification strategy, the timing information and signal integrity information of the initial system-level layout are verified to obtain the signal verification result.
[0086] The bounding box is defined as the smallest bounding rectangle or cube that can completely enclose all physical elements of the initial system layout. Optionally, the bounding box includes the physical areas of all dies, inter-die interconnects / wiring channels, process margins, etc. The preset size threshold is determined based on the field of view of a single exposure of the lithography machine. Lithography is a key process in semiconductor manufacturing, transferring circuit patterns onto a silicon wafer using light. The lithography field of view refers to the maximum area that can be covered by a single exposure of the lithography machine; the preset size threshold is smaller than the size of this maximum area. The systematic verification strategy involves performing system-level timing analysis and signal integrity analysis, including interconnect parasitic parameters. Interconnect parasitic parameters are the physical and electrical characteristics of interconnect links, generated by the wires in the interconnect links. Optionally, physical and electrical characteristics include data such as the resistance, capacitance, and inductance of the interconnect links, determined by the material, length, and spacing of the wires. Timing information verifies the timeliness of signal transmission. It verifies delays caused by quantization interconnect parasitic parameters and whether the transmitted signals in the interconnect link meet clock synchronization requirements. Signal integrity information verifies signal fidelity during transmission. It verifies signal distortion caused by quantization interconnect parasitic parameters and whether the receiver correctly identifies the signal.
[0087] Specifically, the terminal can obtain the coordinate data of each position of the initial system-level layout in the virtual assembly module, calculate the bounding box size of the initial system-level layout based on the position coordinate data, and compare the bounding box size with a preset size threshold to obtain the size comparison result. Optionally, the bounding box size can be the width, length, or area of the bounding box, etc.
[0088] The terminal can analyze the total delay data of each interconnect link based on timing analysis tools and parasitic parameters; compare the total delay data with preset delay data to obtain timing comparison results; perform simulation tests on the initial system-level layout based on time-domain / frequency-domain analysis simulation tools to obtain signal integrity indicators; and verify the signal integrity information based on preset integrity conditions to obtain signal integrity comparison results. The signal verification results include timing comparison results and signal integrity results. Optionally, the signal integrity information includes at least crosstalk data, overshoot / undershoot data, and reflection loss data, and the preset integrity conditions include at least a crosstalk threshold, a preset waveform range, and a reflection signal threshold.
[0089] In this embodiment, the size and signals of the initial system-level layout are verified by a verification strategy, thereby verifying the target physical layout generation strategy. This makes the chip layout more reasonable and more in line with the actual application scenario. Furthermore, the final physical design is fully compatible with the same photomask, and different products can be derived through flexible selection of post-manufacturing processes.
[0090] In one exemplary embodiment, such as Figure 3 As shown, the method for manufacturing chip products also includes:
[0091] Step 301: If the size comparison result is that the bounding box size is greater than or equal to the preset size threshold, and / or the signal verification result is that the timing information exceeds the preset timing range and the signal integrity information does not meet the preset integrity condition, then it is determined that the verification result does not meet the preset verification completion condition, and the deviation data of the initial system-level layout is determined. In the correspondence between the deviation data and the optimization strategy, the target optimization strategy corresponding to the deviation data is generated.
[0092] The optimization strategy is a strategy that optimizes the target physical layout generation strategy. That is, the target optimization strategy can be a strategy that optimizes the location constraint strategy, the interconnect routing channel constraint strategy, and the timing constraint strategy, or a strategy that optimizes at least one of the interconnect routing channel optimization strategy and the timing optimization strategy.
[0093] Specifically, if the size comparison result shows that the bounding box size is greater than or equal to a preset size threshold, then the verification result is determined not to meet the preset verification completion condition; if the signal verification result shows that the timing information exceeds the maximum time window and the signal integrity information does not meet the preset integrity condition, then the verification result is determined not to meet the preset verification completion condition; if the size comparison result shows that the bounding box size is greater than or equal to a preset size threshold, and the signal verification result shows that the timing information exceeds a preset timing range and the signal integrity information does not meet the preset integrity condition, then the verification result is determined not to meet the preset verification completion condition; if at least one of the above conditions is met, then the verification result is determined not to meet the preset verification completion condition. The terminal can determine the deviation data between the verification result and the preset verification completion condition. The terminal can pre-store the correspondence between the deviation data and the optimization type, and determine the target optimization strategy corresponding to the deviation data in the correspondence. Optionally, the terminal can store the correspondence between the stored deviation data and the optimization type in a preset strategy library.
[0094] Optionally, if the size comparison result indicates that the bounding box size is greater than a preset size threshold, then it is determined that the verification result does not meet the preset verification completion condition, and the deviation data between the bounding box size and the preset size threshold is determined. In the correspondence between the deviation data and the optimization type, the target optimization strategy corresponding to the bounding box size exceeding the standard is determined to be increasing the physical interface density. Optionally, if the signal verification result is a timing violation, i.e., the actual delay of the signal on the transmission path is greater than the maximum time window allowed by clock synchronization, the target optimization strategy is determined to be enhancing the critical link drive, etc. This is only for example and does not constitute a specific limitation. In addition, the terminal can determine the degree of deviation based on the deviation data, and determine the specific optimization strategy corresponding to the degree of deviation based on the correspondence between the degree of deviation and the optimization strategy. For example, when the deviation degree of the bounding box size exceeding the standard is the first deviation, the corresponding target optimization strategy is to increase the physical interface density by a preset multiple. This specific value may be related to the actual application scenario and is not specifically limited here.
[0095] Step 302: Based on the target optimization strategy, modify the target physical layout generation strategy to obtain the modified physical layout generation strategy. Based on the modified physical layout generation strategy, continue to execute the steps in the virtual assembly module to virtually assemble the chip to be generated based on the target functional netlist and the target physical layout generation strategy to obtain the initial system-level layout, until the verification result meets the verification completion conditions.
[0096] Specifically, the terminal can modify the constraint strategies or optimization strategies in the target physical layout generation strategy based on the target optimization strategy to obtain a modified physical layout generation strategy. Based on the modified physical layout generation strategy, the terminal can continue to perform virtual assembly of the chip to be generated in the virtual assembly module based on the target functional netlist and the modified physical layout generation strategy to obtain an initial system-level layout. Based on the verification strategy, the initial system-level layout is verified to obtain a verification result. This process continues until the verification result meets the preset verification completion conditions.
[0097] In this embodiment, the target physical layout generation strategy is modified based on the verification results to obtain the modified physical layout generation strategy. The assembly verification process is repeated until the preset verification is met. This realizes the modification of the target physical layout generation strategy, making the final output physical design data more in line with the actual application scenario, and ensuring that the chip is designed under the same underlying photomask, thereby improving the efficiency and reliability of chip production.
[0098] In one instance, such as Figure 4As shown, the chip product generation method is applied to a chip product generation system. This chip generation system includes a D2D redundancy module automatic configuration engine, a product pattern-based physical layout constraint automatic generation engine, an ICI-aware layout optimization engine, a multi-die system virtual assembly and lithography compliance detection engine, and an optimization feedback and analysis engine. The chip product generation method specifically includes the following steps:
[0099] The D2D redundancy module automatically configures the engine, parses the product definition, and determines the logical and physical interfaces that need to be activated. From the pre-verified IP library, it automatically selects and instantiates the corresponding D2D interface IP cores and connects them to the chip's internal bus. For inactive interfaces, it generates physical placeholder units to ensure manufacturing uniformity and the reusability of some photomasks, while also disabling logic through power gating and other methods.
[0100] The product-pattern-based physical layout constraint automatic generation engine generates edge alignment constraints for each active D2D module, forcing it to be placed close to specific chip edges, thus generating a position constraint strategy; it automatically reserves high-layer metal routing channels and designates them as the preferred layers for ICI interconnects, thus generating an interconnect routing channel constraint strategy; and it automatically derives timing constraints across die paths based on interconnect delay requirements, thus generating a timing constraint strategy.
[0101] The timing constraint strategy is validated using the ICI-aware layout optimization engine, and the validation results are obtained. Based on the validation results, all cross-die paths are identified, and optimizations such as driver enhancement and buffer insertion are prioritized to generate a timing optimization strategy. The interconnect routing channel constraint strategy is validated, and the validation results are obtained. Based on the validation results, the location of routing congestion is determined, and the interconnect routing channel optimization strategy is obtained. Based on the location constraint strategy, the interconnect routing channel optimization strategy, and the timing optimization strategy, the target physical layout generation strategy is determined.
[0102] Through a multi-die system virtual assembly and lithography compliance inspection engine, the layouts of multiple dies are virtually stitched together in random access memory according to the product definition to form an initial system-level layout. The bounding box size of the system layout is calculated and compared with the exposure field size of the lithography machine to obtain the size comparison result. System-level timing and signal integrity analysis including interconnect parasitic parameters is performed to obtain the signal verification result.
[0103] By optimizing the feedback and analysis engine, if the verification result meets the preset verification completion conditions, the physical design data corresponding to the system-level layout that meets the verification completion conditions will be output. If the verification result does not meet the preset verification completion conditions, the verification result is classified and quantitatively analyzed. If the size comparison result is that the bounding box size is greater than or equal to the preset size threshold, and / or the signal verification result is that the timing information exceeds the preset timing range and the signal integrity information does not meet the preset integrity conditions, then it is determined that the verification result does not meet the preset verification completion conditions, and the deviation data of the initial system-level layout is determined. In the correspondence between the deviation data and the optimization strategy, the target optimization strategy corresponding to the deviation data is generated. Based on the target optimization strategy, the target physical layout generation strategy is modified to obtain the modified physical layout generation strategy. The modified physical layout generation strategy is then converted into a quantization instruction and fed back to the layout or constraint generation engine. Based on the modified physical layout generation strategy, the steps of virtually assembling the chip to be generated in the virtual assembly module based on the target functional netlist and the target physical layout generation strategy are continued to obtain the initial system-level layout until the verification result meets the verification completion conditions. For example, the quantization instruction can be to increase the ICI bus width from 1024-bit to 1280-bit.
[0104] In this embodiment, a product-defined, fully automated chip design method is proposed. By automatically configuring redundant D2D interconnect modules in the logic design stage and automatically generating the physical layout in the physical implementation stage through a closed-loop optimization process integrating virtual assembly and photolithography compliance testing, a single design source can flexibly derive various chip product forms such as single-chip, dual-chip, and multi-chip designs by only changing the limited high-layer metal of the photomask without changing the underlying photomask. In the subsequent manufacturing process, according to the product definition, spliced or unspliced high-layer metal masks can be used to create the design reuse and manufacturing cost optimization.
[0105] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.
[0106] Based on the same inventive concept, this application also provides a chip product generating apparatus for implementing the chip product generating method described above. The solution provided by this apparatus is similar to the implementation described in the above method; therefore, the specific limitations in one or more chip product generating apparatus embodiments provided below can be found in the limitations of the chip product generating method described above, and will not be repeated here.
[0107] In one exemplary embodiment, such as Figure 5 As shown, a chip product generation apparatus 50 is provided, including: a processing module 51, a determining module 52, and a verification module 53, wherein:
[0108] Processing module 51 is used to process the initial functional netlist and chip design data based on the interconnect logic generation strategy to obtain the target functional netlist of the chip to be generated.
[0109] The determination module 52 is used to determine the target physical layout generation strategy based on the layout generation algorithm, the target functional netlist, and the chip design data;
[0110] The verification module 53 is used in the virtual assembly module to virtually assemble the chip to be generated based on the target functional netlist and the target physical layout generation strategy to obtain an initial system-level layout; to verify the initial system-level layout based on the verification strategy to obtain a verification result; and to output the physical design data corresponding to the system-level layout that meets the verification completion conditions if the verification result meets the preset verification completion conditions.
[0111] In one embodiment, the processing module 51 is specifically used to determine each interconnect interface to be processed of the chip to be generated based on the chip design data.
[0112] Each interconnection interface that meets the activation conditions is activated to obtain an activated interconnection interface; based on a redundancy processing strategy, each interconnection interface that does not meet the activation conditions is redundant to obtain a redundant interface.
[0113] Based on the preset IP library, each of the activated interconnect interfaces is instantiated to obtain each instantiated interconnect module;
[0114] Based on each instantiated interconnect module and each redundant interface, the initial functional netlist is updated to determine the target functional netlist of the chip to be generated.
[0115] In one embodiment, the chip design data includes at least physical layout data of the chips to be generated; the determining module 52 is configured to generate, based on the physical layout data, a position constraint strategy corresponding to each of the instantiated interconnect modules in the target functional netlist; determine the interconnect links between the chips to be generated based on the target functional netlist; determine the interconnect routing channel constraint strategy for each interconnect link based on the chip design data; and determine the timing constraint strategy for each interconnect link based on the interconnect channel delay threshold.
[0116] Based on the location constraint strategy, the interconnect wiring channel constraint strategy, and the timing constraint strategy, the target physical layout generation strategy is determined.
[0117] In one embodiment, the determining module 52 is specifically used to optimize the interconnect wiring channel constraint strategy if the interconnect wiring channel constraint strategy does not meet the screening conditions, so as to obtain an interconnect wiring channel optimization strategy.
[0118] If the timing constraint strategy does not meet the screening conditions, the timing constraint strategy is optimized to obtain a timing optimization strategy.
[0119] Based on the location constraint strategy, the interconnect wiring channel optimization strategy, and the timing optimization strategy, a target physical layout generation strategy is determined.
[0120] In one embodiment, the verification result includes a size comparison result and a signal verification result. The verification module 53 is specifically used to determine the bounding box size of the initial system-level layout, compare the bounding box size with a preset size threshold, and obtain the size comparison result.
[0121] Based on a systematic verification strategy, the timing information and signal integrity information of the initial system-level layout are verified to obtain the signal verification results.
[0122] In one embodiment, the chip product manufacturing apparatus further includes:
[0123] The generation module is configured to determine that the verification result does not meet the preset verification completion condition if the size comparison result is that the bounding box size is greater than or equal to the preset size threshold, and / or the signal verification result is that the timing information exceeds the preset timing range and the signal integrity information does not meet the preset integrity condition, and to determine the deviation data of the initial system-level layout, and to generate the target optimization strategy corresponding to the deviation data in the correspondence between the deviation data and the optimization strategy;
[0124] The correction module is used to correct the target physical layout generation strategy based on the target optimization strategy to obtain a corrected physical layout generation strategy, and based on the corrected physical layout generation strategy, continue to execute the step of virtually assembling the chip to be generated in the virtual assembly module based on the target functional netlist and the target physical layout generation strategy to obtain an initial system-level layout, until the verification result meets the verification completion condition.
[0125] Each module in the aforementioned chip product manufacturing apparatus can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware within or independently of the processor in a computer device, or stored in software within the memory of the computer device, so that the processor can invoke and execute the operations corresponding to each module.
[0126] In one exemplary embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 6 As shown, the computer device includes a processor, memory, input / output interfaces, a communication interface, a display unit, and an input device. The processor, memory, and input / output interfaces are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interfaces. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The input / output interfaces are used for exchanging information between the processor and external devices. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, Near Field Communication (NFC), or other technologies. When the computer program is executed by the processor, it implements a method for generating a chip product. The display unit is used to form a visually visible image and can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The input device of the computer device can be a touch layer covering the display screen, or buttons, trackballs, or touchpads set on the casing of the computer device, or external keyboards, touchpads, or mice, etc.
[0127] Those skilled in the art will understand that Figure 6The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.
[0128] In one embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above-described method embodiments.
[0129] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above method embodiments.
[0130] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.
[0131] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.
[0132] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.
[0133] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.
[0134] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.
Claims
1. A method for manufacturing a chip product, characterized in that, The method includes: Based on the interconnect logic generation strategy, the initial functional netlist and chip design data are processed to obtain the target functional netlist of the chip to be generated. Based on the layout generation algorithm, the target functional netlist, and the chip design data, a target physical layout generation strategy is determined. In the virtual assembly module, the chip to be generated is virtually assembled based on the target functional netlist and the target physical layout generation strategy to obtain an initial system-level layout; the initial system-level layout is verified based on the verification strategy to obtain the verification result; if the verification result meets the preset verification completion condition, the physical design data corresponding to the system-level layout that meets the verification completion condition is output.
2. The method according to claim 1, characterized in that, The interconnect logic-based generation strategy processes the initial functional netlist and chip design data to obtain the target functional netlist of the chip to be generated, including: Based on the chip design data, determine the interconnect interfaces to be processed for the chip to be generated; Each interconnection interface that meets the activation conditions is activated to obtain an activated interconnection interface; based on a redundancy processing strategy, each interconnection interface that does not meet the activation conditions is redundant to obtain a redundant interface. Based on the preset IP library, each of the activated interconnect interfaces is instantiated to obtain each instantiated interconnect module; Based on each instantiated interconnect module and each redundant interface, the initial functional netlist is updated to determine the target functional netlist of the chip to be generated.
3. The method according to claim 2, characterized in that, The chip design data includes at least the physical layout data of the chip to be generated; the determination of the target physical layout generation strategy based on the layout generation algorithm, the target functional netlist, and the chip design data includes: Based on the physical layout data, position constraint strategies are generated for each instantiated interconnect module in the target functional netlist; based on the target functional netlist, interconnect links between chips to be generated are determined; based on the chip design data, interconnect routing channel constraint strategies for each interconnect link are determined; based on interconnect channel delay thresholds, timing constraint strategies for each interconnect link are determined. Based on the location constraint strategy, the interconnect wiring channel constraint strategy, and the timing constraint strategy, the target physical layout generation strategy is determined.
4. The method according to claim 3, characterized in that, The step of determining the target physical layout generation strategy based on the location constraint strategy, the interconnect routing channel constraint strategy, and the timing constraint strategy includes: If the interconnect routing channel constraint strategy does not meet the screening conditions, the interconnect routing channel constraint strategy is optimized to obtain an optimized interconnect routing channel strategy. If the timing constraint strategy does not meet the screening conditions, the timing constraint strategy is optimized to obtain a timing optimization strategy. Based on the location constraint strategy, the interconnect wiring channel optimization strategy, and the timing optimization strategy, a target physical layout generation strategy is determined.
5. The method according to claim 1, characterized in that, The verification results include size comparison results and signal verification results. The initial system-level layout is verified based on the verification strategy to obtain verification results, including: Determine the bounding box size of the initial system-level layout, compare the bounding box size with a preset size threshold, and obtain the size comparison result; Based on a systematic verification strategy, the timing information and signal integrity information of the initial system-level layout are verified to obtain the signal verification results.
6. The method according to claim 5, characterized in that, The method further includes: If the size comparison result is that the bounding box size is greater than or equal to the preset size threshold, and / or the signal verification result is that the timing information exceeds the preset timing range and the signal integrity information does not meet the preset integrity condition, then it is determined that the verification result does not meet the preset verification completion condition, and the deviation data of the initial system-level layout is determined. In the correspondence between the deviation data and the optimization strategy, the target optimization strategy corresponding to the deviation data is generated. Based on the target optimization strategy, the target physical layout generation strategy is modified to obtain a modified physical layout generation strategy. Based on the modified physical layout generation strategy, the step of virtually assembling the chip to be generated in the virtual assembly module based on the target functional netlist and the target physical layout generation strategy to obtain an initial system-level layout is continued until the verification result meets the verification completion condition.
7. A chip product manufacturing apparatus, characterized in that, The device includes: The processing module is used to process the initial functional netlist and chip design data based on the interconnect logic generation strategy to obtain the target functional netlist of the chip to be generated. The determination module is used to determine the target physical layout generation strategy based on the layout generation algorithm, the target functional netlist, and the chip design data; The verification module is used in the virtual assembly module to virtually assemble the chip to be generated based on the target functional netlist and the target physical layout generation strategy to obtain an initial system-level layout; to verify the initial system-level layout based on the verification strategy to obtain a verification result; and to output the physical design data corresponding to the system-level layout that meets the verification completion conditions if the verification result meets the preset verification completion conditions.
8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 6.
9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.
10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.