Device and method for eliminating nonlinearity of electronic system

Abstract

The invention discloses an apparatus and method for non-linearity cancellation in an electronic system. In some embodiments, an electronic system includes two or more circuit channels that process a common input signal in parallel, each circuit channel including at least one instance of a non-linear behavior circuit. Thus, a non-linear circuit is replicated and included in each circuit channel at least once. Each circuit channel has an input scaling factor and an output scaling factor that can be changed from one circuit channel to another. The scaled output signals of the circuit channels are combined to generate a combined output signal. The input and output scaling factors are selected to eliminate or reduce nonlinearity.

Description

Technical Field

[0001] The disclosed technology generally relates to electronics, and more specifically to the elimination of nonlinearity in circuit blocks. Background Technology

[0003] Some circuits require linear operation, meaning the output signal changes linearly with respect to the applied input signal. However, various non-ideals can cause the output signal to exhibit a non-linear relationship with respect to the applied input signal. This non-linear behavior can originate from a wide variety of sources, including but not limited to component mismatch, process variations, power supply voltage constraints, temperature variations, signal amplitude saturation, and / or various other sources. Summary of the Invention

[0004] This invention discloses apparatus and methods for nonlinear cancellation in electronic systems. In some embodiments, the electronic system includes two or more circuit channels that process a common input signal in parallel, each circuit channel including at least one instance of a circuit with nonlinear behavior. Therefore, the nonlinear circuit is replicated and included at least once in each circuit channel. Each circuit channel has an input scaling factor and an output scaling factor that can be changed from one circuit channel to another. The scaled output signals of the circuit channels are combined to generate a combined output signal. The input and output scaling factors are selected to eliminate or reduce nonlinearity. Thus, nonlinear cancellation can be achieved by selecting appropriate values ​​for the input and output scaling factors. For example, the teachings herein can be used to eliminate or reduce various nonlinearities, including but not limited to third-order harmonic distortion. The nonlinear cancellation schemes of this invention can have relatively low complexity and / or high speed compared to calibration schemes suffering from additive sequences and / or convergence delays. Nonlinear cancellation techniques can be applied to a wide variety of electronic systems, including, for example, data conversion systems and phased array antenna systems.

[0005] In one aspect, an electronic system includes two or more circuit channels configured to process input signals in parallel to generate two or more output signals. The two or more circuit channels include a first circuit channel comprising a first circuit block configured to receive an input signal scaled by a first input scaling factor, the first circuit channel being configured to generate a first output signal based on scaling the output of the first circuit block by a first output scaling factor. The two or more circuit channels also include a second circuit channel comprising a second circuit block configured to receive an input signal scaled by a second input scaling factor, the second circuit channel being configured to generate a second output signal based on scaling the output of the second circuit block by a second output scaling factor, wherein the first circuit block and the second circuit block have nonlinearities. The electronic system further includes an output combiner configured to combine the two or more output signals, including the first output signal and the second output signal, to produce a combined output signal with nonlinearities eliminated.

[0006] In another aspect, a method for nonlinear cancellation includes processing an input signal in parallel using two or more circuit channels to generate two or more output signals. Processing the input signal includes scaling the input signal with a first input scaling factor to generate a first scaled input signal for a first circuit block of a first circuit channel; generating a first output signal based on scaling the output of the first circuit block with a first output scaling factor; scaling the input signal with a second input scaling factor to generate a second scaled input signal for a second circuit block of a second circuit channel; and generating a second output signal based on scaling the output of the second circuit block with a second output scaling factor. The first circuit block and the second circuit block have nonlinearities, and the method further includes using an output combiner to combine the two or more output signals, including the first output signal and the second output signal, to generate a combined output signal with nonlinearity cancelled. Attached Figure Description

[0007] Figure 1A This is a schematic diagram of an electronic system according to one embodiment.

[0008] Figure 1B This is a schematic diagram of an electronic system according to another embodiment.

[0009] Figure 2 This is a schematic diagram of a data conversion system according to one embodiment.

[0010] Figure 3A This is a schematic diagram of a data conversion system according to another embodiment.

[0011] Figure 3B This is a schematic diagram of a data conversion system according to another embodiment.

[0012] Figure 4This is a schematic diagram of an electronic system according to another embodiment.

[0013] Figure 5A This is a schematic diagram of one embodiment of a phased array antenna system.

[0014] Figure 5B yes Figure 5A A schematic diagram of an embodiment of the receiver chip of a phased array antenna system. Detailed Implementation

[0015] The following detailed description of embodiments presents various descriptions of specific embodiments of the invention. However, the invention can be embodied in many different ways. Reference is made in this specification to the accompanying drawings. It should be understood that the elements shown in the drawings are not necessarily drawn to scale. Furthermore, it should be understood that some embodiments may include more elements and / or a subset of the elements shown in the drawings than are shown. Additionally, some embodiments may combine any suitable combination of features from two or more drawings.

[0016] This invention discloses apparatus and methods for nonlinear elimination in electronic systems. In some embodiments, the electronic system includes two or more circuit channels that process a common input signal in parallel, each circuit channel including at least one instance of a circuit with nonlinear behavior. Therefore, the nonlinear circuit is replicated and included at least once in each circuit channel. Each circuit channel has an input scaling factor and an output scaling factor that can be changed from one circuit channel to another. The scaled output signals of the circuit channels are combined to generate a combined output signal. The input and output scaling factors are selected to eliminate or reduce nonlinearity.

[0017] Therefore, nonlinearity elimination can be achieved by selecting appropriate values ​​for the input and output scaling factors. For example, the teachings of this paper can be used to eliminate or reduce various nonlinearities, including but not limited to third-order nonlinearities such as third-order harmonic distortion.

[0018] Compared to calibration schemes that suffer from additive sequences and / or convergence delays, the nonlinear elimination scheme presented in this paper can have relatively low complexity and / or high speed.

[0019] Nonlinearity elimination techniques can be applied to a wide variety of electronic systems, including, for example, data conversion systems. For instance, in some implementations, the nonlinear behavior of the circuit corresponds to an analog-to-digital converter (ADC) that is replicated and included in the circuit path.

[0020] Another application of the teachings in this paper is mitigating the effects of harmonic distortion in phased array antenna systems. For example, a phased array antenna system may include multiple transmit and / or receive channels for processing input signals received from the antenna array. While increasing the number of receivers in a phased array system can improve array gain and noise and single-tone spurious performance, intermodulation products can remain correlated and therefore do not improve with array gain. Thus, nonlinearities such as intermodulation distortion can become an increasingly significant performance problem in phased array systems. The teachings in this paper can be applied to phased arrays and / or other electronic systems to eliminate or reduce intermodulation distortion.

[0021] Figure 1A This is a schematic diagram of an electronic system 10 according to one embodiment. The electronic system 10 includes input modulators 3a, 3b, ... 3k, circuit blocks 6a, 6b, ... 6k, output modulators 4a, 4b, ... 4k, and output combiner 5.

[0022] In the illustrated embodiment, the electronic system 10 includes J+1 circuit channels, where J is an integer greater than or equal to 1. Each circuit channel includes a corresponding input modulator, circuit block, and output modulator. Furthermore, each of the circuit blocks 6a, 6b, ... 6k is a copy of each other and can correspond to a circuit that ideally has a linear relationship. However, due to various non-ideals, the circuit blocks 6a, 6b, ... 6k exhibit non-linear characteristics.

[0023] like Figure 1A As shown, the electronic system 10 includes an input terminal that receives an input signal x. in In some implementations, this signal is either analog or radio frequency (RF). Input signal x in The input modulators 3a, 3b, ... 3k are each supplied with an input scaling factor S. 0,0 S 1,0 …S J,0 To scale the input signal x in Input scaling factor S 0,0 S 1,0 …S J,0 In this paper, it is also referred to as the modulation factor.

[0024] Continue to refer to Figure 1A The scaled input signal is provided to circuit blocks 6a, 6b, ... 6k, which can correspond to various types of electronic circuits, including but not limited to ADCs. Circuit blocks 6a, 6b, ... 6k generate output signals, which are provided to output modulators 4a, 4b, ... 4k, which are scaled by an output scaling factor S. 0,1 S 1,1 …S J,1 The output signal is scaled. The output scaling factor is S.0,1 S 1,1 …S J,1 In this paper, it is also referred to as the demodulation factor.

[0025] like Figure 1A As shown, the output combiner 5 combines the scaled output signals together to generate a combined output signal y at the output terminal. out .

[0026] In the illustrated embodiment, circuit blocks 6a, 6b, ... 6k correspond to copies of each other and process the same input signal x in parallel. in However, they have different input scaling factors. Although the transfer functions of circuit blocks 6a, 6b, ... 6k are nonlinear, the input scaling factor S can be selected. 0,0 S 1,0 …S J,0 and output scaling factor S 0,1 S 1,1 …S J,1 The value of the scaling factor is used to eliminate or otherwise reduce nonlinearity. For example, by appropriately selecting the scaling factor, even though each of the circuit blocks 6a, 6b, ... 6k has a nonlinear transfer function, the combined output signal y can be reduced. out It can also be relative to the input signal x in It exhibits an improved linear relationship. Therefore, an appropriate selection of the scaling factor will result in an improved linear relationship from the combined output signal y. out Eliminate one or more nonlinearities.

[0027] The following will refer to Figures 3A-3B The example further discusses in detail the selection of an appropriate scaling factor to achieve nonlinearity elimination.

[0028] Figure 1B This is a schematic diagram of an electronic system 20 according to another embodiment. The electronic system 20 includes input modulators 3a, 3b, ... 3k, circuit blocks 6a1, 6a2, ... 6ax, 6b1, 6b2, ... 6by, ... 6k1, 6k2, ... 6kz, combiners 7a, 7b, ... 7k, output modulators 4a, 4b, ... 4k, and output combiner 5. The values ​​of x, y, and z, and the corresponding number of circuit blocks, can be selected as any positive integer values ​​required for a particular application. The values ​​of x, y, and z can be the same or different, depending on the implementation. The values ​​of x, y, and z are also referred to as the number of sub-channels associated with each channel.

[0029] Figure 1B The electronic system 20 is similar to Figure 1A Electronic system 10, in addition to Figure 1B The circuit system 20 includes multiple circuit blocks placed in parallel within each circuit channel and scaled by the same input and output scaling factors. For example, Figure 1B The electronic system 20 includes J+1 circuit channels, each circuit channel including multiple copies of nonlinear circuit blocks operating in parallel, operating as sub-channels.

[0030] For example, in Figure 1B In the embodiment, circuit blocks 6a1, 6a2, ... 6ax all use input modulator 3a with scaling factor S. 0,0 Scaling is then performed. Furthermore, the output signals from circuit blocks 6a1, 6a2, ... 6ax are combined using combiner 7a, and then scaled using output modulator 4a with a scaling factor S. 0,1 Scaling is then applied. Similarly, circuit blocks 6b1, 6b2, ... 6by all use input modulator 3b with a scaling factor S. 1,0 Scaling is performed. The output signals from circuit blocks 6b1, 6b2, ... 6by are combined using combiner 7b, and then scaled by output modulator 4b with a scaling factor S. 1,1 Scaling is performed. Furthermore, circuit blocks 6k1, 6k2, ... 6kz all use input modulator 3k with a scaling factor S. J,0 Scaling is performed. The output signals from circuit blocks 6k1, 6k2, ... 6kz are combined using combiner 7k, and then scaled using output modulator 4k with a scaling factor S. J,1 Scaling is performed.

[0031] Noise per channel can be reduced by including multiple circuit blocks in parallel and scaling them using the same scaling factor. Furthermore, parallelizing circuit blocks in this way allows for changes in path gain, thereby altering the scaling factor required to achieve nonlinearity cancellation. Therefore, the number of parallel circuit blocks per circuit channel can be strategically chosen based on noise constraints and / or the desired scaling factor relevant to a specific application.

[0032] Any embodiment described herein may include one or more circuit channels in which nonlinear circuit blocks are connected in parallel.

[0033] Figure 2 This is a schematic diagram of a data conversion system 40 according to one embodiment. The data conversion system 40 includes input modulators 3a, 3b, ... 3k, ADCs 26a, 26b, ... 26k, output modulators 4a, 4b, ... 4k, and output combiner 5.

[0034] Figure 2 Data conversion system 40 is similar to Figure 1A Electronic system 10, in addition to Figure 2 Digital conversion system 40 will Figure 1A The circuits 6a, 6b, ... 6k are implemented as ADCs 26a, 26b, ... 26k. Therefore, in this embodiment, each circuit channel includes an ADC.

[0035] ADCs 26a, 26b, ... 26k operate in parallel to each other to process the analog input signal x(t), thereby generating the digital output signal y[n]. ADCs 26a, 26b, ... 26k are connected to any desired number of parallel sub-channels N0, N1, ... N... J The ADCs 26a, 26b, ..., 26k are modeled using switches 31a, 31b, ..., 31k, transfer functions 32a, 32b, ..., 32k, Δ scaling factors 33a, 33b, ..., 33k, and additive error sources 34a, 34b, ..., 34k. Furthermore, the Δ scaling factors 33a, 33b, ..., 33k provide 1 / Δ scaling, while the additive error sources 34a, 34b, ..., 34k provide additive noise e. 0,i [n]、e 1,i [n]、…e J,i [n]. The scaling factors 33a, 33b, ... 33k and the additive error sources 34a, 34b, ... 34k together represent the quantizers of ADCs 26a, 26b, ... 26k.

[0036] Figure 2 The transfer functions 32a, 32b, ..., 32k in the equation can be expressed as f(w) = w + a2w 2 + a3w 3 + … and the harmonic distortion (HD) components that need to be eliminated can correspond to HDp0, …HDp J–1 , where p0, ... p J–1 It is an integer greater than 1. Furthermore, the output signal y[n] of the data conversion system 40 can be represented by the following Equation 1.

[0037] Equation 1

[0038]

[0039]

[0040] The above expression for Equation 1 can be written more concisely using Equation 2 below.

[0041] Equation 2

[0042]

[0043] In equation 2, for p=1, the term The expected value is 1, and for p = p0, … p J–1 The expected value is 0. This can be represented by Equation 3 below, where matrix S is defined.

[0044] Equation 3

[0045]

[0046] Therefore, as long as the matrix S is invertible, the input scaling factor S can be chosen. 0,0 S 1,0 …S J,0 Any value of . Furthermore, the output scaling factor S for nonlinear cancellation. 0,1 S 1,1 …S J,1 It can be represented by the following equation 4.

[0047] Equation 4

[0048]

[0049] Continue to refer to Figure 2 You can select a scaling factor to eliminate unwanted harmonic distortion components.

[0050] In some embodiments, the J+1 circuit channel is used to eliminate the J harmonic distortion component.

[0051] For example, in the first example, two circuit channels (e.g., each channel includes an ADC) are used to eliminate third-order harmonic distortion (HD3).

[0052] In the second example, three circuit channels are used to eliminate second-order harmonic distortion (HD2) and HD3.

[0053] In the third example, three circuit channels are used to eliminate HD3 and fifth harmonic distortion (HD5).

[0054] In the fourth example, four circuit channels are used, where S 0,0 = 1, S 0,1 = 1, S 1,0 = –1 and S 1,1 = –1, S 2,0 = i and S 2,1 = –i,S 3,0 = –i and S 3,1 = i. Implementing the coefficients in this way eliminates all HD components except for the 5th, 9th, 13th, etc. In this example, the coefficients for nonlinear elimination include complex numbers.

[0055] Figure 3AThis is a schematic diagram of a data conversion system 60 according to another embodiment. The data conversion system 60 includes a first input modulator 3a, a second input modulator 3b, a first data conversion channel 52a, a second data conversion channel 52b, a first output modulator 4a, a second output modulator 4b, and an output combiner 5b. The first data conversion channel 52a includes a first ADC represented by a switch 53a and a transfer function 54a, while the second data conversion channel 52b includes a second ADC represented by a switch 53b and a transfer function 54b.

[0056] like Figure 3A As shown, the first input modulator 3A provides a scaling factor S. 0,0 The second input modulator 3b provides the scaling factor S. 1,0 In addition, the first output modulator 4a provides a scaling factor S. 0,1 The second output modulator 4b provides the scaling factor S. 1,1 .

[0057] In the illustrated embodiment, the transfer function 54a / 54b is represented as w + a3w. 3 Furthermore, input and output scaling factors are selected to achieve HD3 elimination. For example, the output signal y[n] can be given by Equation 5 below.

[0058] Equation 5

[0059]

[0060] To eliminate HD3, equation 6 can be solved.

[0061] Equation 6

[0062]

[0063] The expression for Equation 6 can be represented in matrix form using Equation 7 below, where matrix S is defined.

[0064] Equation 7

[0065]

[0066] Continue to refer to Figure 3A The output scaling factor S can be found by solving Equation 8 below. 0,1 and S 1,1 The value of the scaling factor S. 0,0 and S 1,0 The value of can be any value, as long as the matrix S is invertible.

[0067] Equation 8

[0068]

[0069] For example, when the input scaling factor S 0,0 = 1 and S 1,0 When = 0.5, the output scaling factor that achieves HD3 cancellation corresponds to S 0,1 = –0.3334 and S 1,1 = 2.6667, as Figure 3A As shown. In another example, when the input scaling factor S... 0,0 = 1 and S 1,0 When = –1.5, the output scaling factor that achieves HD3 cancellation corresponds to S 0,1 = 1.8 and S 1,1 = 0.5334.

[0070] Therefore, the input scaling factor and / or the number of circuit channels can be selected such that matrix S is invertible (e.g., with a condition number less than a threshold). Furthermore, the input scaling factor can be selected to provide the desired output scaling factor for nonlinearity elimination. For example, certain scaling factors may be better suited for implementation in electronic systems due to circuit design considerations and / or other factors.

[0071] Figure 3B This is a schematic diagram of a data conversion system 70 according to another embodiment. The data conversion system 70 includes a first input modulator 3a, a second input modulator 3b, a first data conversion channel 62a, a second data conversion channel 62b, a first output modulator 4a, a second output modulator 4b, and an output combiner 5b. The first data conversion channel 62a includes a first ADC represented by a switch 63a and a transfer function 64a, while the second data conversion channel 52b includes a second ADC and a third ADC connected in parallel. The second ADC is represented by a switch 63b1 and a transfer function 64b1, while the third ADC is represented by a switch 63b2 and a transfer function 64b2. The outputs of the second ADC and the third ADC are combined using a combiner 65.

[0072] Figure 3B The data conversion system 70 in the middle is similar to Figure 3A The data conversion system 60 in the middle, except that the data conversion system 70 uses two parallel ADCs to implement the second data conversion channel 62b.

[0073] By implementing the second data conversion channel in this way, the transfer function of the data conversion system 70 is changed, which leads to different choices of scaling factors to achieve HD3 elimination.

[0074] For example, when the transfer function 64a / 64b is expressed as w + a3w 3 When the output signal y[n] is given by the following equation 9.

[0075] Equation 9

[0076]

[0077] To achieve HD3 elimination, the scaling factor can be selected according to Equation 10 below.

[0078] Equation 10

[0079]

[0080] The expression for Equation 10 can be represented in matrix form using Equation 11, which defines matrix S.

[0081] Equation 11

[0082]

[0083] Output scaling factor S 0,1 and S 1,1 The value of can be found by solving Equation 12 below. Input scaling factor S 0,0 and S 1,0 The value of can be any value, as long as the matrix S is invertible.

[0084] Equation 12

[0085]

[0086] For example, when the input scaling factor S 0,0 = 1 and S 1,0 When = 0.5, the output scaling factor that achieves HD3 cancellation corresponds to S 0,1 = –0.3334 and S 1,1 = 1.3334, such as Figure 3B As shown.

[0087] like Figure 3A and Figure 3B As shown in the example scaling factor comparison in the annotations, the scaling factor for HD3 cancellation can vary when circuit blocks for a given circuit channel are placed in parallel. Therefore, parallelizing circuit blocks (such as ADCs) is an effective technique for achieving the output scaling factor required for a specific application. Furthermore, placing circuit blocks in parallel can reduce noise.

[0088] Figure 4 This is a schematic diagram of an electronic system 100 according to another embodiment. The electronic system 100 includes input modulators 3a, 3b, ... 3k, circuit blocks 6a, 6b, ... 6k, output modulators 4a, 4b, ... 4k, output combiner 5, and calibration circuit 91.

[0089] Figure 4 The electronic system 100 is similar to the electronic system 10 in Figure 1, except that the electronic system 100 also includes a calibration circuit 91.

[0090] In the illustrated embodiment, the calibration circuit 91 detects the input scaling factor S. 0,0 S 1,0 …S J,0 The value includes any changes in the input scaling factor caused by variations in process, temperature, and / or voltage (PVT). Furthermore, the detected input scaling factor is used to generate the output scaling factor S. 0,1 S 1,1 …S J,1 It is calibrated to account for PVT variations.

[0091] Figure 5A This is a schematic diagram of one embodiment of a phased array antenna system 110. The phased array antenna system 110 includes digital processing circuitry 101, data conversion circuitry 102, transceiver 103, RF front-ends 105a, 105b, ... 105n, and an antenna array including antennas 106a, 106b, ... 106n. Although an example system with three RF front-ends and three antennas is shown, the phased array antenna system 110 may include more or fewer RF front-ends and / or more or fewer antennas, as shown by the ellipse. Furthermore, in some implementations, the phased array antenna system 110 is implemented using separate antennas for transmitting and receiving signals.

[0092] Phased array antenna system 110 illustrates an embodiment of an electronic system that can be implemented with nonlinearity cancellation according to the teachings herein. For example, while the number of receivers in a phased array system can be increased to improve array gain and noise and single-tone spurious performance, intermodulation products can remain correlated and therefore do not improve with array gain. Thus, nonlinearities such as intermodulation distortion can become increasingly significant performance problems in phased array systems. The teachings herein can be applied to such phased array antenna systems to eliminate or reduce nonlinearities, including but not limited to HD3.

[0093] While nonlinear cancellation can be applied to phased array antenna system 110, the nonlinear cancellation scheme disclosed herein can be used in a wide range of electronic products. The phased array antenna system is also referred to herein as an active scanning electronic steering array or a beamforming communication system.

[0094] like Figure 5AAs shown, transceiver 103 is coupled to antennas 106a, 106b, ... 106n via RF front-ends 105a, 105b, ... 105n, respectively. In this embodiment, transceiver 103 includes frequency up / down conversion circuitry 108 and phase and amplitude control circuitry 109. Transceiver 103 provides RF signal processing for transmitted and received RF signals. In the illustrated embodiment, each communication channel is associated with a corresponding RF front-end and antenna. However, other implementations are also possible.

[0095] Continue to refer to Figure 5A The digital processing circuit 101 generates digital transmit data for controlling the transmit beams radiated from antennas 106a, 106b, ... 106n. The digital processing circuit 101 also processes digital receive data representing the receive beams received by antennas 106a, 106b, ... 106n in response to received radio waves. In some implementations, the digital processing circuit 101 includes one or more baseband processors.

[0096] like Figure 5A As shown, digital processing circuit 101 is coupled to data conversion circuit 102, which may include a digital-to-analog converter (DAC) circuit for converting digital transmitted data into one or more baseband transmitted signals and an analog-to-digital converter (ADC) circuit for converting one or more baseband received signals into digital received data.

[0097] In this embodiment, the frequency up / down conversion circuit 108 provides frequency upsampling from baseband to RF and frequency downsampling from RF to baseband. However, other implementations are also possible, such as a configuration where the phased array antenna system 110 operates partially at intermediate frequency (IF), or a configuration where the RF data converter provides direct conversion between digital and RF.

[0098] In this embodiment, transceiver 103 further includes phase and / or amplitude control circuitry 109 for controlling the gain and phase of beamforming and / or other desired functions. However, other implementations are also possible. For example, beamforming may be implemented entirely or partially in the digital domain (e.g., in digital processing circuitry 101).

[0099] Regarding signal transmission, the RF signals radiated from antennas 106a, 106b, ... 106n are converged together through constructive and destructive interference to jointly generate a transmit beam with a specific direction. Regarding signal reception, a receive beam is generated by combining the RF signals received from antennas 106a, 106b, ... 106n after amplitude scaling and / or phase shifting.

[0100] Phased array antenna systems are used in a wide variety of applications, including but not limited to mobile communications, military and defense systems and / or radar technology.

[0101] Figure 5B yes Figure 5A A schematic diagram of an embodiment of the receiver chip 130 of the phased array antenna system 110. The receiver chip 130 is coupled to the antenna 116 and includes a digital processing circuit 111, a data conversion circuit 112, an RF downconversion circuit 113, and a front end 115.

[0102] In the illustrated embodiment, the front-end system includes a low-noise amplifier 122 and a transmit / receive switch 121 for selectively connecting the input of the low-noise amplifier 122 to the antenna 116. The RF down-conversion circuit 113 includes an input filter 123, a down-conversion mixer 124, a receive amplifier 125, an output filter 126, and a local oscillator 127. The input filter 123 is coupled to the output of the low-noise amplifier 122 and generates a filtered RF received signal, which is provided to the down-conversion mixer 124. The down-conversion mixer 124 uses a local oscillator clock signal from the local oscillator 127 to down-convert the filtered RF received signal to generate a down-converted received signal. The down-converted received signal is amplified by the receive amplifier 125 and filtered by the output filter 126 to generate an input signal x for the data conversion circuit 112. in .

[0103] Continue to refer to Figure 5B The conversion circuit 112 is implemented using input modulators 3a, 3b, ... 3k to scale the input signal x provided to the ADCs 26a, 26b, ... 26k. in Furthermore, the digital processing circuit 111 includes output modulators 4a, 4b, ... 4k for scaling the output signals from each of the ADCs 26a, 26b, ... 26k, respectively, and a combiner 5 for combining the scaled output signals to generate an output signal y. out .

[0104] By selecting an appropriate scaling factor, the output signal y can be reduced or eliminated. out Nonlinear components (such as HD3 or other harmonic distortion components) in the signal.

[0105] in conclusion

[0106] The above description may refer to elements or features as “connected” or “coupled” together. As used herein, unless otherwise expressly stated, “connected” means that one element / feature is directly or indirectly connected to another element or feature, and is not necessarily a mechanical connection. Similarly, unless otherwise expressly stated, “coupled” means that one element / feature is directly or indirectly coupled to another element or feature, and is not necessarily a mechanical coupling. Therefore, although the various schematic diagrams shown in the figures depict exemplary arrangements of elements and components, additional intervening elements, devices, features, or components may be present in actual embodiments (assuming that the function of the depicted circuit is not adversely affected).

[0107] While certain embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of this disclosure. In fact, the novel apparatuses, methods, and systems described herein can be embodied in a variety of other forms; furthermore, various omissions, substitutions, and changes can be made to the form of the methods and systems described herein without departing from the spirit of this disclosure. For example, while the disclosed embodiments are presented with a given arrangement, alternative embodiments may perform similar functions using different components and / or circuit topologies, and some elements may be deleted, moved, added, subdivided, combined, and / or modified. Each of these elements can be implemented in a variety of different ways. Any suitable combination of elements and actions of the various embodiments described above can be combined to provide further embodiments. Therefore, the scope of the invention is defined only by reference to the appended claims.

[0108] Although the claims presented herein were filed with the U.S. Patent and Trademark Office in a single-dependency format, it should be understood that any claim may depend on any prior claim of the same type unless it is clearly not technically feasible.

Claims

1. An electronic system comprising: Two or more circuit channels are configured to process input signals in parallel to generate two or more output signals, wherein the two or more circuit channels include: A first circuit channel, including a first circuit block, is configured to receive an input signal scaled by a first input scaling factor, and the first circuit channel is configured to generate a first output signal based on the output of the first circuit block scaled by a first output scaling factor; and A second circuit channel, including a second circuit block, is configured to receive an input signal scaled by a second input scaling factor, the second circuit channel being configured to generate a second output signal based on the output of the second circuit block scaled by a second output scaling factor, wherein the first circuit block and the second circuit block are nonlinear; and An output combiner is configured to combine two or more output signals, including the first output signal and the second output signal, to produce a combined output signal with nonlinearity eliminated.

2. The electronic system according to claim 1, wherein the two or more circuit channels further include: A third circuit channel, including a third circuit block, is configured to receive an input signal scaled by a third input scaling factor, the third circuit channel being configured to generate a third output signal from the two or more output signals based on the output of the third circuit block scaled by a third output scaling factor.

3. The electronic system of claim 1, wherein the first circuit block is a first analog-to-digital converter (ADC) and the second circuit block is a second ADC.

4. The electronic system of claim 3, wherein the input signal is an analog or radio frequency signal, and the output signal is a digital signal.

5. The electronic system of claim 1, comprising a plurality of input scaling factor definition matrices of the first input scaling factor and the second input scaling factor, and comprising a plurality of output scaling factors of the first output scaling factor and the second output scaling factor based on the inverse of the matrix.

6. The electronic system according to claim 1, wherein the nonlinearity is a harmonic distortion component.

7. The electronic system of claim 1 further includes a calibration circuit configured to calibrate the first output scaling factor based on a detected value of the first input scaling factor, and to calibrate the second output scaling factor based on a detected value of the second input scaling factor.

8. The electronic system of claim 1, wherein the second circuit channel further comprises one or more additional circuit blocks connected in parallel with the second circuit block, each of the one or more additional circuit blocks receiving an input signal scaled by the second input scaling factor.

9. The electronic system of claim 8, wherein the second circuit channel is further configured to generate the second output signal by combining the output of each of the one or more additional circuit blocks with the output of the second circuit block.

10. The electronic system of claim 1, wherein the second circuit block is a copy of the first circuit block.

11. The electronic system according to claim 1, implemented in a phased array antenna.

12. A method for nonlinear elimination, the method comprising: Two or more circuit channels are used to process input signals in parallel to generate two or more output signals, wherein processing the input signals includes: The input signal is scaled by a first input scaling factor to generate a first scaled input signal for a first circuit block of a first circuit channel; The first output signal is generated by scaling the output of the first circuit block with a first output scaling factor. The input signal is scaled by a second input scaling factor to generate a second scaled input signal for the second circuit block of the second circuit channel; A second output signal is generated by scaling the output of the second circuit block with a second output scaling factor, wherein the first and second circuit blocks are nonlinear; and An output combiner is used to combine two or more output signals, including the first output signal and the second output signal, to generate a combined output signal in which nonlinearity is eliminated.

13. The method of claim 12, further comprising: The input signal is scaled by a third input scaling factor to generate a third scaled input signal for the third circuit block of the third circuit channel; and The third output signal is generated by scaling the output of the third circuit block with a third output scaling factor.

14. The method of claim 12, wherein the first circuit block is a first analog-to-digital converter (ADC) and the second circuit block is a second ADC.

15. The method of claim 14, wherein the input signal is an analog or radio frequency signal, and the output signal is a digital signal.

16. The method of claim 12, further comprising a plurality of input scaling factor definition matrices of the first input scaling factor and the second input scaling factor, and further comprising a plurality of output scaling factors of the first output scaling factor and the second output scaling factor based on the inverse of the matrix.

17. The method of claim 12, wherein the nonlinearity is a harmonic distortion component.

18. The method of claim 12, further comprising calibrating the first output scaling factor based on the detected value of the first input scaling factor, and calibrating the second output scaling factor based on the detected value of the second input scaling factor.

19. The method of claim 12, wherein the second circuit channel further comprises one or more additional circuit blocks parallel to the second circuit block, the method further comprising providing each of the one or more additional circuit blocks with an input signal scaled by the second input scaling factor, and generating the second output signal based on combining the output of each of the one or more additional circuit blocks with the output of the second circuit block.

20. The method of claim 12, wherein the second circuit block is a copy of the first circuit block.

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