Packaging detection method and system of FRD device

Abstract

The invention provides a packaging detection method and system of an FRD device. According to the method, packaging structure information of a to-be-tested FRD packaging device is acquired, a packaging parasitic network model of the FRD packaging device is established based on the packaging structure information, then a test excitation signal is applied to an external pin of the FRD packaging device, so that a plurality of FRD chips generate packaging response signals associated with the test excitation signal in a packaging state, and the packaging response signals are transmitted to the FRD packaging device. The method comprises the following steps: firstly, packaging a plurality of FRD chips to obtain a packaging response signal, sampling the packaging response signal to obtain a packaging sampling signal, and then, based on a packaging parasitic network model, performing parameter inversion processing on the packaging sampling signal to obtain a plurality of core particle electrical parameters corresponding to the plurality of FRD chips respectively, thereby determining abnormal core particles in the FRD packaging device based on the plurality of core particle electrical parameters. Therefore, the parallel FRD core particles can be effectively detected in a packaging completion state.

Description

Technical Field

[0001] This application relates to device packaging and testing technology, and more particularly to a packaging and testing method and system for FRD devices. Background Technology

[0002] Fast recovery diodes (FRDs) are typical power semiconductor devices and are widely used in high-frequency, high-power electronic systems such as switching power supplies, frequency converters, motor drives, and automotive power supplies.

[0003] As power and current ratings continue to increase, the infinite expansion of single-chip area will lead to problems such as decreased yield, uneven heat distribution, and increased mechanical stress. Therefore, the industry generally adopts a packaging form in which multiple FRD chips are connected in parallel within the same package. Through interconnection structures such as lead frames, copper substrates, DBC substrates, or metal busbars, the anodes and cathodes of multiple FRD chips are connected to a limited number of external power pins, so that the device appears as a single high-current FRD device externally.

[0004] In such multi-chip parallel FRD packages, each chip should achieve approximately equal current distribution to ensure a balanced distribution of junction temperature, thermal stress, and lifespan. If a chip's forward voltage drop, reverse recovery characteristics, or leakage current deviates abnormally, it may cause internal current redistribution, local overheating, or even premature failure of the entire device. Therefore, there is an urgent need for a method that can effectively detect parallel FRD chips in the packaged state. Summary of the Invention This application provides a packaging inspection method and system for FRD devices, which enables effective inspection of parallel FRD chips in the packaged state.

[0005] In a first aspect, this application provides a packaging inspection method for an FRD device, comprising: Obtain the package structure information of the FRD packaged device under test. The package structure information characterizes the package interconnection structure between multiple FRD chips connected in parallel within the FRD packaged device and external pins. Based on the packaging structure information, a packaging parasitic network model of the FRD packaged device is established; A test excitation signal is applied to the external pin of the FRD package device, and the corresponding package response signal is determined, so as to sample the package response signal to obtain the package sample signal; Based on the encapsulation parasitic network model, parameter inversion processing is performed on the encapsulation sampling signal to obtain multiple chip electrical parameters corresponding to the multiple FRD chips respectively. Based on the multiple chip electrical parameters, it is determined whether there are abnormal chips inside the FRD packaged device.

[0006] Secondly, this application provides a packaging inspection system for FRD devices, comprising: The acquisition module is used to acquire the package structure information of the FRD packaged device under test. The package structure information characterizes the package interconnection structure between multiple FRD chips connected in parallel within the FRD packaged device and external pins. The processing module is used to establish a parasitic network model of the FRD packaged device based on the packaged structure information. The processing module is further configured to apply a test excitation signal to the external pin of the FRD package device and determine the corresponding package response signal, so as to perform sampling on the package response signal to obtain a package sampling signal; The processing module is further configured to perform parameter inversion processing on the packaged sampling signal based on the packaged parasitic network model, so as to obtain multiple chip electrical parameters corresponding to the multiple FRD chips respectively; The determination module is used to determine whether there are abnormal cores inside the FRD packaged device based on the multiple core electrical parameters.

[0007] The FRD device packaging inspection method and system provided in this application acquires the packaging structure information of the FRD device under test, establishes a packaging parasitic network model of the FRD device based on the packaging structure information, and then applies a test excitation signal to the external pins of the FRD device to cause multiple FRD chips to generate packaging response signals associated with the test excitation signal in the packaged state. The packaging response signals are then sampled to obtain packaging sampling signals. Next, based on the packaging parasitic network model, parameter inversion processing is performed on the packaging sampling signals to obtain multiple chip electrical parameters corresponding to the multiple FRD chips. Based on the multiple chip electrical parameters, abnormal chips inside the FRD device are determined, so as to achieve effective detection of parallel FRD chips in the packaged state. Attached Figure Description

[0008] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0009] Figure 1 This is a schematic flowchart illustrating a packaging inspection method for an FRD device according to an example embodiment of this application; Figure 2 This is a schematic flowchart of a packaging inspection method for an FRD device according to another example embodiment of this application; Figure 3 This is a schematic diagram of the packaging and inspection system for an FRD device according to an example embodiment of this application; Figure 4 This is a schematic diagram of the structure of an electronic device according to an example embodiment of this application.

[0010] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0011] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0012] In existing technologies, the factory testing of FRD devices after packaging mainly relies on overall static and dynamic electrical parameter tests. These tests include measuring the overall forward voltage VF at a given current point, measuring the overall leakage current IR at a specific reverse voltage, evaluating the overall breakdown voltage, and obtaining the overall reverse recovery time Trr, reverse recovery charge Qrr, and reverse recovery peak current through methods such as double pulses. These testing methods can characterize device performance well in single-chip FRD packages, but when used in multi-chip parallel packages, they can only obtain the equivalent parameters of multiple parallel chips stacked together, and cannot distinguish the specific electrical behavior and current distribution state of each chip.

[0013] Meanwhile, the parasitic resistance and inductance network formed by the common lead frame, copper substrate and external pins is common in multi-chip parallel packages. During fast switching and reverse recovery tests, these package parasitic parameters have a significant filtering and coupling effect on the overall current and voltage waveforms, further masking the intrinsic characteristics of individual chips.

[0014] Furthermore, if a core particle experiences an open bond or localized degradation of the sintered layer, it may become almost nonconductive under most operating conditions, with other core particles acting as current shunts. Such defects are often averaged out in the overall IV and recovery waveforms, making it difficult to identify them in a timely manner using overall detection methods.

[0015] While existing technologies include adding intermediate test pins to the package structure or dissecting the package to achieve chip-level testing, the former increases packaging complexity and cost and is not conducive to the compatibility of standardized products and systems, while the latter is destructive sampling, which is inefficient and not suitable for mass production online screening.

[0016] Therefore, in the mass production testing scenario of multi-chip parallel FRD packaged devices, under the premise of keeping the external pin configuration of the package basically unchanged and without damaging the package structure, the existing technology cannot perform chip-level electrical parameter detection and abnormal chip identification for multiple parallel FRD chips inside the package: On the one hand, traditional detection methods can only obtain the overall equivalent IV and dynamic recovery characteristics, and it is difficult to decouple the forward voltage drop, reverse recovery parameters and leakage current offset of a single chip from the overall response.

[0017] On the other hand, existing electrical testing procedures do not incorporate modeling and parameter inversion based on specific package structures and parasitic networks, failing to leverage differences in package parasitic parameters to enhance the observability of individual chip behavior. Consequently, even if the overall parameters of multi-chip parallel FRD packages meet specifications, significant defects such as uneven current distribution between chips, individual chip disconnections, or significant drift in critical parameters may exist that cannot be detected during factory testing, posing a substantial risk to the reliability of subsequent applications.

[0018] Therefore, there is an urgent need for a packaging inspection method that is tightly coupled with the FRD multi-chip parallel packaging structure. By modeling the package parasitic network and inverting the test waveform parameters, the core-level electrical parameters of the parallel FRD cores can be extracted and failure identification can be achieved without adding functional pins or damaging the package, so as to solve the above-mentioned core technical problems.

[0019] To address the aforementioned issues, the embodiments provided in this application first obtain the package structure information of the FRD packaged device under test. This package structure information characterizes the package interconnection structure between multiple parallel FRD chips within the package and external power pins. Based on this package structure information, a package parasitic network model is constructed, comprising multiple chip parasitic parameters and common parasitic parameters. The multiple chip parasitic parameters characterize the package-specific parasitic resistance, parasitic inductance, and other characteristics corresponding to each FRD chip, while the common parasitic parameters characterize the parasitic characteristics of the common lead frame, pins, and other common interconnection structures within the package.

[0020] Based on this, a test stimulus signal of a predetermined form is applied to the external pins of the FRD packaged device. This triggers multiple FRD chips to generate package response signals associated with the test stimulus signal, provided the device remains in its intact package and is not opened. The package response signals are then sampled and preprocessed in the time domain by a sampling circuit to obtain a package sampling signal that meets the bandwidth and resolution requirements.

[0021] Subsequently, based on the aforementioned package parasitic network model, an equivalent circuit equation is constructed. The relationship between the test excitation signal, multiple chip electrical parameters, and the package sampling signal is formalized. Numerical solution and fitting algorithms are then used to perform parameter inversion processing on the equivalent circuit equation, thereby deriving multiple chip electrical parameters corresponding to multiple FRD chips at the package level.

[0022] After obtaining the above-mentioned chip electrical parameters, by comparing the electrical parameters of each chip with the target design specification value or parallel balance index, abnormal chips inside the FRD packaged device and their corresponding package abnormality types are identified and marked. This enables chip-level electrical performance detection and abnormality identification of multi-chip parallel FRD packaged devices, thereby solving the technical problem that traditional detection methods are difficult to distinguish between single chip failure or parameter drift without damaging the package.

[0023] Figure 1 This is a schematic flowchart illustrating a packaging and inspection method for an FRD device according to an example embodiment of this application. Figure 1 As shown, the packaging inspection method for FRD devices provided in this embodiment includes: S110. Obtain the package structure information of the FRD packaged device under test.

[0024] In this step, the package structure information of the FRD packaged device under test is obtained. The package structure information characterizes the package interconnection structure between multiple FRD chips connected in parallel within the FRD packaged device and external pins.

[0025] Specifically, it can involve obtaining layout design data and / or 3D package structure design data of FRD packaged devices. The layout design data and 3D package structure design data are used to characterize the chip size, chip position, chip orientation, and package interconnection path between multiple FRD chips and external pins.

[0026] Then, based on the layout design data and / or 3D package structure design data, the chip soldering area, bonding line routing, metal wiring routing, lead frame structure and power pin structure corresponding to each FRD chip are extracted to form package interconnect structure description information corresponding to multiple FRD chips.

[0027] Next, the package interconnect structure description information is used as package structure information to establish the package parasitic network model of the FRD packaged device.

[0028] S120. Based on the packaging structure information, establish a packaging parasitic network model for the FRD packaged device.

[0029] In this step, a parasitic network model of the FRD packaged device can be established based on the package structure information. The packaged parasitic network model includes multiple chip parasitic parameters corresponding to multiple FRD chips and common parasitic parameters corresponding to the common interconnect structure of the FRD packaged device.

[0030] In one possible implementation, electromagnetic simulation of the FRD packaged device can be performed based on the package structure information to obtain multiple chip parasitic resistance parameters and multiple chip parasitic inductance parameters corresponding to multiple FRD chips respectively. Then, the multiple chip parasitic resistance parameters, multiple chip parasitic inductance parameters and common parasitic parameters are combined to form an equivalent package parasitic network for characterizing the FRD packaged device.

[0031] Specifically, a three-dimensional electromagnetic simulation model of the FRD packaged device can be constructed based on the package structure information. This model includes at least the chip pad areas, bonding wire structures, internal metal wiring structures, lead frame structures, substrate metal layer structures, and external pin structures of multiple FRD chips. Then, within the three-dimensional electromagnetic simulation model, the conductive paths from the chip pads to the corresponding external pins of each FRD chip are partitioned and labeled to form multiple package interconnect conductive paths corresponding to each FRD chip. Under preset excitation conditions, electromagnetic field solutions are performed on the three-dimensional electromagnetic simulation model to obtain the AC impedance parameters of the multiple package interconnect conductive paths. Next, based on the AC impedance parameters, multiple chip parasitic resistance parameters and multiple chip parasitic inductance parameters corresponding to each FRD chip are extracted at preset frequency points or within a preset frequency range.

[0032] Then, the conductor and dielectric material parameters from the package structure information are imported into the electromagnetic simulation tool. The conductor material parameters include at least conductivity and temperature coefficient, and the dielectric material parameters include at least dielectric constant and dielectric loss tangent. Boundary conditions and port excitation methods are set for the 3D electromagnetic simulation model, using the anode and cathode interconnect regions of multiple FRD chips as solution ports. Based on the boundary conditions and port excitation methods, the multi-port S-parameters or Z-parameters of the FRD packaged device within a predetermined frequency range are obtained, and from these, multiple chip parasitic resistance parameters and multiple chip parasitic inductance parameters corresponding to the multiple FRD chips are calculated.

[0033] The common parasitic parameters include at least one of the following: Common parasitic resistance and common parasitic inductance parameters of the common anode bus region of FRD packaged devices; Common parasitic resistance and common parasitic inductance parameters of the common cathode bus region of FRD packaged devices; The parasitic resistance and inductance parameters of the pins between the common external pins and the internal bus region of the FRD packaged device.

[0034] Next, the parasitic resistance and inductance parameters of each FRD chip are connected in series or parallel to the anode and cathode conduction paths of the corresponding FRD chips to form multiple chip-package parasitic branches corresponding to each FRD chip. The common parasitic resistance and inductance parameters of the common anode bus region are connected between the anode bus node of each of the multiple chip-package parasitic branches and the corresponding anode external pin. The common parasitic resistance and inductance parameters of the common cathode bus region are connected between the cathode bus node of each of the multiple chip-package parasitic branches and the corresponding cathode external pin. The pin parasitic resistance and inductance parameters are connected between the external pin and the external test circuit interface to form an equivalent package parasitic network for an FRD packaged device with at least two ports.

[0035] S130. Apply a test excitation signal to the external pin of the FRD packaged device.

[0036] In this step, a test stimulus signal is applied to the external pins of the FRD package device to cause multiple FRD chips to generate package response signals associated with the test stimulus signal in the packaged state.

[0037] In one possible implementation, a forward-biased on-current pulse and a reverse-biased off-current voltage pulse are applied to an external pin of the FRD package to obtain the package response current and package response voltage during the reverse recovery process of the FRD package. The package response signal includes the package response current and / or package response voltage.

[0038] Optionally, for applying a forward conduction current pulse and a reverse turn-off voltage pulse at the external pins of the FRD packaged device, a controllable current source can be connected between the anode external pin and the cathode external pin of the FRD packaged device. Under a predetermined duty cycle and a predetermined pulse width, a forward conduction current pulse with an amplitude of a first predetermined current level is output, so that multiple FRD chips are in a forward conduction state, and a minority carrier distribution is established inside the multiple FRD chips under the action of the forward conduction current pulse.

[0039] The first predetermined current level is determined based on the rated current parameters of the FRD packaged device. Specifically, the first predetermined current level can be set to 10% to 80% of the rated average forward current of the FRD packaged device, so as to match the forward conduction state of multiple FRD chips with the actual application conditions without exceeding the safe operating area of ​​the device.

[0040] Furthermore, for applying a reverse turn-off voltage pulse at the external pins of the FRD packaged device, a controllable voltage source can be connected between the anode external pin and the cathode external pin of the FRD packaged device. Within a predetermined time window at or after the end of the conduction phase of the forward conduction current pulse, the voltage between the anode external pin and the cathode external pin is changed from a forward conduction voltage to a reverse turn-off voltage pulse with an amplitude of a first predetermined reverse voltage, so as to trigger multiple FRD chips to enter the reverse recovery process.

[0041] The first predetermined reverse voltage can be determined based on the rated reverse withstand voltage parameters of the FRD packaged device. Specifically, the first predetermined reverse voltage can be set to 10% to 80% of the rated repetitive peak reverse voltage of the FRD packaged device, so as to simulate the reverse turn-off condition in actual application while avoiding overvoltage damage to the FRD packaged device during the mass production testing stage. Furthermore, regarding the timing relationship of the applied forward conduction current pulse and reverse turn-off voltage pulse, the forward conduction current pulse can be kept in a stable conduction state within a preset conduction time to enable stable carrier storage within multiple FRD chips. Then, the reverse turn-off voltage pulse is initiated within a first predetermined time resolution at the end of the preset conduction time, ensuring that the rising edge of the reverse turn-off voltage pulse and the turn-off edge of the forward conduction current pulse occur within a predetermined time overlap interval, thereby forming a repeatable reverse recovery test condition.

[0042] Furthermore, to obtain the package response current during the reverse recovery process of the FRD packaged device, a current sampling element or current sensor can be connected in series in the power circuit of the FRD packaged device. During the application of a forward conduction current pulse and a reverse turn-off voltage pulse, the transient current flowing through the FRD packaged device is detected to obtain the package response current waveform characterizing the reverse recovery process of the FRD packaged device. The current sampling element can include at least one of the following: a low-resistance sampling resistor connected in series in the power circuit of the FRD packaged device, and a current probe or current transformer for detecting current changes in the power circuit of the FRD packaged device.

[0043] Furthermore, to obtain the package response voltage during the reverse recovery process of the FRD packaged device, a voltage sampling circuit can be connected between the anode and cathode external pins of the FRD packaged device. During the application of a forward conduction current pulse and a reverse turn-off voltage pulse, the transient voltage between the anode and cathode external pins is detected to obtain the package response voltage waveform characterizing the reverse recovery process of the FRD packaged device. The voltage sampling circuit includes at least one of the following: a high-bandwidth voltage probe for directly measuring the voltage between the anode and cathode external pins, and a voltage divider network connected in series in the power circuit of the FRD packaged device, with the output of the voltage divider network connected to the voltage measurement terminal of the test instrument.

[0044] Optionally, the waveform parameters of the aforementioned forward conduction current pulse and reverse turn-off voltage pulse include at least one of the following: The rise time, fall time, pulse width, and repetition frequency of the forward conduction current pulse; Rise time, fall time, pulse width, and peak amplitude of the reverse turn-off voltage pulse; The time delay parameter or phase relationship parameter between the forward conduction current pulse and the reverse turn-off voltage pulse.

[0045] Furthermore, the test circuit that applies the test excitation signal operates in single-pulse mode or low duty cycle pulse mode to limit the average power consumption and junction temperature rise of the FRD packaged device, and to avoid temperature-related interference to the package response current and package response voltage due to excessive junction temperature.

[0046] Furthermore, the specific test conditions for the test excitation signal are pre-configured based on the target application scenario of the FRD packaged device. Specifically, the nominal values ​​of the first predetermined current level and the first predetermined reverse voltage can be determined based on the typical operating current and operating voltage of the FRD packaged device in the target application scenario. Then, based on the typical switching frequency and switching transient characteristics of the FRD packaged device in the target application scenario, the waveform edge time and pulse width of the forward conduction current pulse and the reverse turn-off voltage pulse are determined so that the package response current and package response voltage can reflect the reverse recovery behavior of multiple FRD chips under actual application conditions.

[0047] S140. Sample the package response signal to obtain the package sample signal.

[0048] In this step, the packaged response signal can be sampled in the time domain using a sampling circuit to obtain a packaged sampled signal with a predetermined sampling bandwidth and sampling resolution. Furthermore, the packaged sampled signal can be preprocessed to obtain a preprocessed sampled signal for parameter inversion processing.

[0049] Specifically, the preprocessing described above may involve performing bandwidth limiting filtering on the packaged sampling signal to suppress high-frequency noise components; and performing waveform alignment processing on the filtered packaged sampling signal to establish the time correspondence between the test excitation signal and the packaged sampling signal.

[0050] S150. Based on the encapsulation parasitic network model, parameter inversion processing is performed on the encapsulated sampled signal.

[0051] In this step, parameter inversion processing can be performed on the packaged sampling signal based on the packaged parasitic network model to obtain multiple chip electrical parameters corresponding to multiple FRD chips respectively.

[0052] Optionally, the above-mentioned multiple chip electrical parameters include at least one of the following: Forward voltage drop parameters of each FRD chip under a predetermined forward current; Reverse recovery charge parameters of each FRD chip during the reverse recovery process; Reverse recovery time parameters for each FRD chip during the reverse recovery process; Reverse leakage current parameters of each FRD chip under a predetermined reverse voltage.

[0053] Specifically, the equivalent circuit equations of the FRD packaged device can be constructed based on the package parasitic network model. These equations characterize the relationship between the test excitation signal, multiple chip electrical parameters, and the package sampling signal. Then, the equivalent circuit equations are numerically solved to determine the multiple chip electrical parameters corresponding to each of the multiple FRD chips. Optionally, a least-squares fitting algorithm can be used to minimize the error metric between the simulated response signal calculated from the package parasitic network model and the package sampling signal, thereby obtaining estimates of the multiple chip electrical parameters.

[0054] Specifically, for constructing the equivalent circuit equations of an FRD packaged device based on a package parasitic network model, multiple chip electrical parameters corresponding to multiple FRD chips can be used as unknown parameters to be determined, while the waveform parameters of the test excitation signal and the parasitic parameters in the package parasitic network model are used as known parameters. Based on circuit topology and circuit laws, a set of differential or difference equations describing the equivalent electrical behavior of the FRD packaged device is established. This set of differential or difference equations characterizes the correspondence between the test excitation signal, multiple chip electrical parameters, and the package sampling signal. The aforementioned set of differential or difference equations includes at least one of the following: A set of ordinary differential equations describing the relationship between transient voltage and transient current of FRD packaged devices established in the continuous time domain; A set of difference equations is established in the discrete-time domain based on the discretization of the circuit differential equations. The sampling time interval of the set of difference equations is consistent with the sampling time interval of the packaged sampling signal.

[0055] To construct the equivalent circuit equations for FRD packaged devices, one approach is to cascade multiple chip parasitic parameters corresponding to various FRD chips with their respective intrinsic FRD chip models within the package parasitic network model, forming multiple chip equivalent branches. Then, these multiple chip equivalent branches are connected to the common parasitic parameters characterizing the common interconnect structure of the FRD packaged device according to the connection relationships corresponding to the package structure information, forming the overall equivalent circuit of the FRD packaged device. Finally, based on the overall equivalent circuit, the equivalent circuit equations are established according to the voltage-current relationship and the node current conservation relationship. Furthermore, to perform numerical solutions to the equivalent circuit equations to determine the multiple chip electrical parameters corresponding to the multiple FRD chips, the packaged sampling signal can be used as observation data, and the simulated response signal calculated from the equivalent circuit equations under given initial values ​​of the chip electrical parameters can be used as fitting data. A parameter inversion problem can then be constructed with the error between the observed data and the fitted data as the objective function. Next, an iterative optimization algorithm is used to solve the objective function to obtain the estimated results of the multiple chip electrical parameters.

[0056] The iterative optimization algorithm mentioned above includes at least one of the following: Nonlinear least squares solution algorithms based on gradient descent or quasi-Newton methods; A damped least squares solution algorithm based on the Levenberg-Marquardt algorithm; Global optimization solution algorithms based on particle swarm optimization, genetic algorithms, or other swarm intelligence optimization algorithms.

[0057] Furthermore, for numerical solutions to the equivalent circuit equations, initial values ​​and range constraints can be set for multiple chip electrical parameters based on the product specifications or process design parameters of the FRD packaged device before executing the iterative optimization algorithm. Then, during the iterative solution process, the multiple chip electrical parameters are restricted to their corresponding physically reasonable ranges to avoid generating inversion results that do not conform to the physical characteristics of the FRD device.

[0058] Furthermore, for constructing a parameter inversion problem with the error between observed and fitted data as the objective function, the difference between the simulated response signal and the encapsulated sampled signal can be calculated at the time sampling points of the encapsulated sampled signal. Then, the difference is accumulated or integrated according to a preset error metric to form the objective function. The error metric includes at least one of the following: squared error metric, weighted squared error metric, and absolute value error metric.

[0059] The aforementioned weighted squared error measure includes: To determine the importance of different time intervals in the encapsulated sampled signal, an error weighting coefficient corresponding to the time interval is set. The deviations between the simulated response signal and the packaged sampled signal in different time intervals are squared and weighted summation operations, respectively, to improve the parameter inversion accuracy in the critical time interval of FRD reverse recovery.

[0060] Furthermore, by performing numerical solutions to the equivalent circuit equations, in each iteration, the corresponding simulated response signals can be obtained by solving the equivalent circuit equations based on the currently estimated multiple chip electrical parameters. Based on the difference between the simulated response signals and the packaged sampling signals, the estimated values ​​of multiple chip electrical parameters are updated until a preset convergence criterion is met or a preset maximum number of iterations is reached.

[0061] The pre-defined convergence criteria include at least one of the following: The change in the objective function between two consecutive iterations is less than the preset convergence threshold; The changes in multiple core electrical parameters in two consecutive iterations are less than the preset parameter change threshold; The normalized error metric between the simulated response signal and the packaged sampled signal is less than the preset target error threshold.

[0062] Furthermore, to improve the stability of the numerical solution, the equivalent circuit equations can be normalized during numerical solution processing. This ensures that the test excitation signal, package sampling signal, and multiple chip electrical parameters are within a range suitable for numerical calculation in terms of dimensions and magnitude. A regularization term is introduced into the objective function to constrain the variation amplitude or differences among the multiple chip electrical parameters, thereby suppressing ill-conditioned solutions and overfitting.

[0063] The regularization term includes at least one of the following: L1 norm regularization term based on the sum of absolute values ​​of multiple core electrical parameters; L2 norm regularization term based on the sum of squares of multiple core electrical parameters; A parameter difference penalty term, constructed based on the prior information that the electrical parameters of parallel FRD chips should be basically consistent under normal operating conditions, is used to constrain the deviation between the electrical parameters of multiple chips belonging to normal chips.

[0064] Furthermore, by performing numerical solutions to the equivalent circuit equations, the correction amounts of common parasitic parameters corresponding to the common interconnect structure of the FRD packaged device can be simultaneously estimated during the parameter inversion process. These correction amounts, along with multiple chip electrical parameters, are then jointly solved as optimization variables to compensate for the impact of process deviations and modeling errors on the inversion accuracy. Specifically, the correction amounts of the common parasitic parameters are subject to amplitude and rate-of-change constraints to ensure that the corrected common parasitic parameters still conform to the reasonable physical range corresponding to the package structure information and electromagnetic simulation results.

[0065] S160. Based on multiple chip electrical parameters, determine whether there are abnormal chips inside the FRD packaged device.

[0066] In this step, statistical analysis can be performed on multiple chip electrical parameters corresponding to multiple FRD chips to obtain the statistical distribution characteristics of various chip electrical parameters in the target product family or the same batch of FRD packaged devices. Then, the multiple chip electrical parameters corresponding to each FRD chip in the FRD packaged device under test are compared with the statistical distribution characteristics to identify abnormal chip electrical parameters outside the preset tolerance range.

[0067] This process involves performing statistical analysis on multiple core particle electrical parameters. This can be based on historical mass production data or process design target data, calculating the mean, standard deviation, and / or median and quantiles for each type of core particle electrical parameter. Then, based on the statistical analysis results, corresponding normal parameter ranges and anomaly detection thresholds are set for each type of core particle electrical parameter. These normal parameter ranges and anomaly detection thresholds are then stored as a parameter reference library for subsequent abnormal core particle identification.

[0068] To compare the multiple chip electrical parameters corresponding to each FRD chip in the FRD packaged device under test with statistical distribution characteristics, it can be done by determining whether the various chip electrical parameters of each FRD chip fall within the corresponding normal parameter range. If a chip electrical parameter exceeds the corresponding anomaly judgment threshold, the chip electrical parameter is marked as an abnormal parameter, and the corresponding FRD chip is marked as a suspected abnormal chip. Then, based on the judgment rules for single parameter anomalies or multi-parameter combination anomalies, further anomaly confirmation is performed on the suspected abnormal chips.

[0069] The judgment rules for the above-mentioned multi-parameter combination anomalies include at least one of the following: When the forward voltage drop parameter of the same FRD chip is higher than the upper limit of the corresponding normal parameter range and the reverse recovery time parameter is significantly shortened, it is determined that the FRD chip has an anomaly caused by a reduction in junction area or poor local soldering.

[0070] When the reverse recovery charge parameter of the same FRD chip is higher than the upper limit of the corresponding normal parameter range and the reverse leakage current parameter increases, it is determined that the FRD chip has an anomaly caused by junction defects or surface passivation failure.

[0071] Furthermore, based on multiple chip electrical parameters, abnormal chips within the FRD packaged device and their corresponding package abnormalities can be identified. Relative comparative analysis can also be performed on the corresponding chip electrical parameters of multiple FRD chips within the same FRD packaged device to obtain a measure of inconsistency between chips. When the deviation of the chip electrical parameters of a certain FRD chip from the chip electrical parameters of other FRD chips within the same package exceeds a preset relative deviation threshold, that FRD chip is identified as an abnormal chip. The aforementioned inconsistency measure includes at least one of the following: The range, standard deviation, or maximum / minimum ratio of the forward voltage drop parameters of each FRD chip within the same package; The range, standard deviation, or maximum / minimum ratio of the reverse recovery charge parameters of each FRD chip within the same package; The range, standard deviation, or maximum / minimum ratio of the reverse leakage current parameters of each FRD chip within the same package.

[0072] Optionally, when the forward voltage drop parameter of a certain FRD chip is significantly higher than that of other FRD chips in the same package or higher than the upper limit of the corresponding normal parameter range under a predetermined forward current, the FRD chip is identified as an abnormal chip with an abnormal forward voltage drop, and the corresponding packaging abnormality is identified as a package interconnection abnormality caused by increased voids in the chip solder layer, pad contamination, or increased contact resistance of the bonding wires. Conversely, when the forward voltage drop parameter of a certain FRD chip is significantly lower than that of other FRD chips in the same package or lower than the lower limit of the corresponding normal parameter range under a predetermined forward current, the FRD chip is identified as an abnormal chip with excessive conduction or threshold drift, and the corresponding packaging abnormality is identified as an abnormality caused by chip selection mixing, doping deviation, or local short circuit.

[0073] Optionally, when the reverse leakage current parameter of a certain FRD chip is significantly higher than the upper limit of the corresponding normal parameter range under a predetermined reverse voltage, the FRD chip is identified as an abnormal chip with leakage current anomaly. Furthermore, the packaging anomaly corresponding to the leakage current anomaly is identified as a packaging reliability anomaly caused by chip surface contamination, encapsulation resin cracking, ion contamination, metal migration, or chip edge passivation failure.

[0074] Optionally, when the reverse recovery charge parameter and / or reverse recovery time parameter of a certain FRD chip deviate significantly from the corresponding normal parameter range, the FRD chip is identified as an abnormal chip with abnormal reverse recovery characteristics. Furthermore, the packaging abnormality corresponding to the abnormal reverse recovery characteristics is identified as a packaging structure abnormality caused by chip junction structure deviation, local overheating, welding stress, or abnormal parasitic parameters of the packaging leads.

[0075] Optionally, when the various chip electrical parameters corresponding to a certain FRD chip are simultaneously close to the boundaries of their respective normal parameter ranges, and are systematically higher or lower than the chip electrical parameters corresponding to other FRD chips in the same package, the FRD chip is identified as a sub-healthy chip with process drift or aging trends. Furthermore, the packaging anomalies corresponding to the sub-healthy chip are identified as potential failure risks caused by solder aging, interface fatigue, or packaging stress accumulation.

[0076] Optionally, when multiple chip electrical parameters corresponding to a certain FRD chip deviate significantly from their corresponding normal parameter ranges and differ significantly from other FRD chips in the same package, the FRD chip is identified as a severely abnormal chip, and the FRD packaged device is marked as a failed device. Conversely, when the chip electrical parameters corresponding to all FRD chips fall within their corresponding normal parameter ranges and the inconsistency measure between chips is below a preset threshold, the FRD packaged device is marked as a qualified device.

[0077] Furthermore, the die electrical parameters corresponding to each FRD chip can be matched with pre-established electrical parameter feature templates for different package failure modes to obtain the matching degree of the package failure mode corresponding to each FRD chip. Then, based on the matching degree, the package failure type and confidence level corresponding to each abnormal die are output. The aforementioned electrical parameter feature templates include at least one of the following: Electrical parameter feature templates are used to characterize wire breakage or poor wire soldering. The electrical parameter feature templates correspond to a combination of features: increased forward voltage drop parameter, decreased reverse recovery charge parameter, and significantly reduced branch current. Electrical parameter feature templates are used to characterize excessive voids in chips or solder layer delamination. The electrical parameter feature templates correspond to a combination of features including increased forward voltage drop, prolonged reverse recovery time, and slightly increased reverse leakage current. Electrical parameter feature templates are used to characterize cracking or moisture intrusion in the encapsulation resin. These templates correspond to a combination of features, including a significant increase in the reverse leakage current parameter and an increase in the fluctuation of the reverse recovery charge parameter.

[0078] Furthermore, each abnormal chip is assigned a packaging abnormality level identifier, which includes at least one of the following: fatal abnormality, severe abnormality, minor abnormality, or sub-optimal condition. Based on the packaging abnormality level identifier, sorting decisions or quality traceability records are generated for the corresponding FRD packaged devices to guide subsequent factory classification, failure analysis, or process adjustments.

[0079] In this embodiment, the packaging structure information of the FRD packaged device under test is obtained, and a packaging parasitic network model of the FRD packaged device is established based on the packaging structure information. Then, a test excitation signal is applied to the external pins of the FRD packaged device to make multiple FRD chips generate packaging response signals associated with the test excitation signal in the packaged state. The packaging response signals are sampled to obtain packaging sampling signals. Then, based on the packaging parasitic network model, parameter inversion processing is performed on the packaging sampling signals to obtain multiple chip electrical parameters corresponding to the multiple FRD chips. Based on the multiple chip electrical parameters, abnormal chips inside the FRD packaged device are determined to achieve effective detection of parallel FRD chips in the packaged state.

[0080] Building upon the above embodiments, it is worth noting that in multi-chip parallel FRD packaged devices, multiple FRD chips are connected in parallel to external power pins through the internal lead frame, bonding wires, and solder layer, thereby sharing the forward current and reverse recovery current during device operation. Existing mass production testing methods often involve applying voltage or current to external power pins and measuring the overall current and voltage waveforms. This only provides macroscopic electrical parameters such as the total forward voltage drop, total reverse leakage current, and overall reverse recovery characteristics of the entire packaged device, and cannot distinguish the individual conduction current and electrical parameters of each parallel FRD chip. Meanwhile, while conventional structural inspection methods such as X-rays and acoustic scanning can detect internal voids and cracks to some extent, they cannot quantitatively reflect the current sharing status and conduction anomalies of each chip in terms of electrical performance. This leads to insufficient identification of electrical anomalies in individual chips during the production and screening process of multi-chip parallel FRD packages.

[0081] Therefore, addressing the limitations of existing technologies that can only acquire overall package electrical parameters and cannot distinguish the conduction current and current sharing status of each parallel FRD chip in the packaged state, making it difficult to promptly detect package interconnection anomalies such as open circuits, cold solder joints, disconnections, and forward voltage drop drift in individual chips, this application further addresses these issues by configuring an independent chip current sensing branch for each FRD chip within the package and acquiring branch voltages through auxiliary test pads. This allows for independent measurement and judgment of the branch current of each chip without disassembling the package. The core technical problem to be solved is: how to achieve online sensing of the branch current of each parallel FRD chip while maintaining the integrity of the FRD package structure and the basic unchanged pin definitions at the application end, in order to support the determination of chip-level conduction status and parallel current sharing status.

[0082] in, Figure 2 This is a schematic flowchart illustrating a packaging inspection method for an FRD device according to another example embodiment of this application. Figure 2 As shown, the packaging inspection method for FRD devices provided in this embodiment further includes: S210. Apply a positive test current between the power pins of the FRD packaged device.

[0083] Optionally, the aforementioned FRD packaged device under test further includes multiple chip current sensing branches corresponding to multiple FRD chips. Each chip current sensing branch has a sensing resistor connected in series in the power conduction path of the corresponding FRD chip, and at least one auxiliary test pad is led out. The sensing resistor is placed between the chip pad of the corresponding FRD chip and the package lead frame, or in the bonding loop of the corresponding FRD chip, to reduce the impact on the overall package size and lead layout of the FRD packaged device. Furthermore, the auxiliary test pad is arranged on the internal substrate or lead frame of the package and electrically connected to one or both ends of the sensing resistor via wires, bonding wires, or metal traces to extract the branch voltage. Optionally, the sensing resistor is a thick-film resistor, a metal film resistor, a metal alloy resistor, or an equivalent chip resistor formed by a locally narrowed structure of the lead frame. The resistance value of the sensing resistor is selected to ensure that the additional voltage drop on the conduction voltage of each FRD chip is within a preset allowable range, while ensuring that the branch voltage is measurable.

[0084] In this step, a constant amplitude DC forward test current can be applied between the positive and negative power pins of the FRD packaged device using a constant current source, or a pulsed forward test current with a preset amplitude, duty cycle, and frequency can be applied. Then, the amplitude of the forward test current is set to not exceed the rated forward operating current of the FRD packaged device and to be greater than the minimum test current threshold required to trigger the conduction of each FRD chip, ensuring that each FRD chip is in a stable forward conduction state without damaging the FRD packaged device.

[0085] S220, Perform a potential measurement on the auxiliary test pads.

[0086] In this step, the potential of the auxiliary test pads may be measured to obtain multiple branch voltages corresponding to multiple FRD chips.

[0087] Optionally, the auxiliary test pad is electrically connected to the test fixture during the mass production testing phase, but not connected to the external circuit during the actual application phase, or electrically connected to the power pin through an internal shorting structure. Optionally, during the actual application phase, a solderable shorting metal bridge can be set between the auxiliary test pad and the corresponding power pin. After the FRD packaged device completes mass production testing, the shorting metal bridge is electrically connected or disconnected from the auxiliary test pad and the power pin during the factory packaging process through soldering or ablation, so that the auxiliary test pad is no longer exposed to the outside of the package as an independent pin in the final application form, or maintains the same potential as the power pin.

[0088] Furthermore, the potential of the auxiliary test pads is measured to obtain multiple branch voltages corresponding to the multiple FRD chips. This can be achieved by using a multi-channel voltage measurement circuit electrically connected to each auxiliary test pad to synchronously acquire the potential of each auxiliary test pad. Then, based on a predetermined reference potential node, the voltage difference between the potential of each auxiliary test pad and the reference potential node is taken as the branch voltage of the corresponding chip current sensing branch. Alternatively, the voltage difference between two auxiliary test pads located at both ends of the same chip current sensing branch can be taken as the branch voltage of the corresponding chip current sensing branch.

[0089] Specifically, for the use of a multi-channel voltage measurement circuit to electrically connect to each auxiliary test pad, elastic probes or clamp-type contact terminals corresponding one-to-one with the auxiliary test pads can be set on the test fixture to achieve a reliable electrical connection between the auxiliary test pads and the multi-channel voltage measurement circuit during the mass production testing stage. Furthermore, before performing potential measurements, zero-point calibration and gain calibration are performed on each measurement channel to reduce the impact of measurement errors on the branch voltage calculation results.

[0090] S230: Determine the conduction status and parallel current sharing status of each FRD chip based on the branch current.

[0091] Based on the voltage of multiple branches and the resistance value of sensing resistors, the branch current of multiple FRD chips is calculated, and the conduction state and parallel current sharing state of each FRD chip are determined based on the branch current.

[0092] Optionally, the deviation between the current in each branch and the target current sharing current can be compared. If the target branch current is close to zero or less than the target current sharing current, it is determined that the corresponding FRD chip has an open circuit, poor soldering, or disconnection anomaly. If the target branch current is significantly greater than the target current sharing current, it is determined that the corresponding FRD chip has an abnormal forward voltage drop or an abnormal electrical parameter drift.

[0093] Furthermore, based on the voltages of multiple branches and the resistance values ​​of the sensing resistors, the branch currents of multiple FRD chips are calculated. This can be achieved by performing a division operation on the branch voltage using the nominal resistance value and the temperature-corrected actual resistance value of the corresponding sensing resistor for each chip's current sensing branch, thus obtaining the branch current corresponding to that chip's current sensing branch. Then, the calculated branch currents are compared with the total forward test current value to verify the accuracy of the branch current calculation results.

[0094] The actual resistance value of each sensing resistor after temperature correction can be obtained by measuring the initial branch voltage of the FRD packaged device under low or no current conditions before applying the forward test current, and then using the pre-stored temperature coefficient of the sensing resistor to perform temperature compensation on the nominal resistance value of the sensing resistor to obtain the corresponding actual resistance value. Alternatively, a temperature sensing structure can be arranged inside the FRD packaged device, and the nominal resistance value of the sensing resistor can be corrected based on the internal temperature information output by the temperature sensing structure to obtain the corresponding actual resistance value.

[0095] Furthermore, when applying a forward test current between the power pins of an FRD-packaged device, the terminal voltage and total current changes of the FRD-packaged device can be monitored during the application of the forward test current to ensure that the FRD-packaged device operates within a predetermined safe test range. When the terminal voltage or total current exceeds a preset protection threshold, the constant current source or power supply module is controlled to reduce or shut off the forward test current to prevent damage to the FRD-packaged device due to overstress.

[0096] It is worth further explaining that, Figure 1 Based on the embodiments shown, when package-level failures such as wire breakage, cold solder joints, solder voids, or increased contact resistance occur in the package interconnect structure, their impact on the waveform of external terminals is highly similar to the abnormal intrinsic electrical parameters of the chip, making it difficult to distinguish between package interconnect failure and chip failure itself.

[0097] In another possible implementation, the aforementioned packaged parasitic network model can also be configured with multiple interconnect health parameters corresponding to each of the multiple FRD chips. These interconnect health parameters characterize the electrical connection state and contact resistance state of the packaged interconnect structure along the power conduction path of each FRD chip. The interconnect health parameters include the equivalent series resistance parameter and / or the interconnect conduction state parameter corresponding to each FRD chip. The interconnect conduction state parameter characterizes whether the corresponding FRD chip participates in parallel conduction through the packaged interconnect structure, and the equivalent series resistance parameter characterizes the contact resistance of the corresponding packaged interconnect structure.

[0098] By configuring interconnect health parameters corresponding to each FRD chip in the package parasitic network model, and specifically defining the interconnect health parameters as interconnect equivalent series resistance parameters and / or interconnect conduction state parameters, the intrinsic electrical parameters of each chip and the equivalent electrical connection characteristics of each package interconnect path can be solved simultaneously during parameter inversion.

[0099] On the one hand, when the interconnect conduction status parameters corresponding to a certain chip indicate that it has not participated in parallel conduction through the package interconnect structure, or when its interconnect equivalent series resistance parameter is significantly greater than the normal range, it is possible to clearly identify package interconnect abnormalities such as broken solder wires, poor soldering, or significantly increased contact resistance in the branch where the chip is located.

[0100] On the other hand, when the interconnect health parameters are within the normal physical range but the forward voltage drop parameter, reverse recovery charge parameter, or reverse leakage current parameter of a certain chip is abnormal, the abnormality can be attributed to the drift or degradation of the chip's intrinsic electrical parameters. This allows the chip's intrinsic failure to be distinguished from the package interconnect failure in the same detection process, thereby solving the problem of not being able to distinguish between the two types of failure sources.

[0101] Figure 3 This is a schematic diagram of the packaging and inspection system for an FRD device according to an example embodiment of this application. Figure 3 As shown, the FRD device packaging and inspection system 300 provided in this embodiment includes: The acquisition module 310 is used to acquire the package structure information of the FRD packaged device under test. The package structure information characterizes the package interconnection structure between multiple FRD chips connected in parallel within the FRD packaged device and external pins. Processing module 320 is used to establish a parasitic network model of the FRD packaged device based on the packaged structure information; The processing module 320 is further configured to apply a test excitation signal to the external pin of the FRD package device and determine the corresponding package response signal, so as to perform sampling on the package response signal to obtain a package sampling signal; The processing module 320 is further configured to perform parameter inversion processing on the packaged sampling signal based on the packaged parasitic network model, so as to obtain multiple chip electrical parameters corresponding to the multiple FRD chips respectively; The determination module 330 is used to determine whether there are abnormal chips inside the FRD packaged device based on the multiple chip electrical parameters.

[0102] Figure 4 This is a schematic diagram of the structure of an electronic device according to an example embodiment of this application. For example... Figure 4 As shown, the electronic device 400 provided in this embodiment includes: a processor 401 and a memory 402; wherein: Memory 402 is used to store computer programs, and the memory may also be flash memory.

[0103] Processor 401 is used to execute the execution instructions stored in the memory to implement the various steps in the above method. For details, please refer to the relevant descriptions in the preceding method embodiments.

[0104] Alternatively, the memory 402 can be either standalone or integrated with the processor 401.

[0105] When the memory 402 is a device independent of the processor 401, the electronic device 400 may further include: Bus 403 is used to connect the memory 402 and the processor 401.

[0106] This embodiment also provides a readable storage medium storing a computer program, which, when executed by at least one processor of an electronic device, enables the electronic device to perform the methods provided in the various embodiments described above.

[0107] This embodiment also provides a program product including a computer program stored in a readable storage medium. At least one processor of an electronic device can read the computer program from the readable storage medium, and the at least one processor executes the computer program to cause the electronic device to perform the methods provided in the various embodiments described above.

[0108] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the claims.

[0109] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A packaging inspection method for an FRD device, characterized in that, include: Obtain the package structure information of the FRD packaged device under test. The package structure information characterizes the package interconnection structure between multiple FRD chips connected in parallel within the FRD packaged device and external pins. Based on the packaging structure information, a packaging parasitic network model of the FRD packaged device is established; A test excitation signal is applied to the external pin of the FRD package device, and the corresponding package response signal is determined, so as to sample the package response signal to obtain the package sample signal; Based on the encapsulation parasitic network model, parameter inversion processing is performed on the encapsulation sampling signal to obtain multiple chip electrical parameters corresponding to the multiple FRD chips respectively. Based on the multiple chip electrical parameters, it is determined whether there are abnormal chips inside the FRD packaged device.

2. The packaging and testing method for FRD devices according to claim 1, characterized in that, Based on the packaging structure information, a packaging parasitic network model of the FRD packaged device is established, including: Based on the packaging structure information, electromagnetic simulation is performed on the FRD packaged device to obtain multiple chip parasitic resistance parameters and multiple chip parasitic inductance parameters corresponding to the multiple FRD chips respectively. The equivalent package parasitic network used to characterize the FRD packaged device is determined based on the plurality of core parasitic resistance parameters and the plurality of core parasitic inductance parameters.

3. The packaging and testing method for FRD devices according to claim 1, characterized in that, A test stimulus signal is applied to the external pins of the FRD package device to cause the plurality of FRD chips to generate a package response signal associated with the test stimulus signal in the packaged state, including: A forward conduction current pulse and a reverse turn-off voltage pulse are applied to the external pins of the FRD package device to obtain the package response current and package response voltage during the reverse recovery process of the FRD package device. The package response signal includes the package response current and / or the package response voltage.

4. The packaging and testing method for FRD devices according to claim 1, characterized in that, Sampling the package response signal to obtain a package sample signal includes: The package response signal is sampled in the time domain using a sampling circuit to obtain the package sample signal with a predetermined sampling bandwidth and sampling resolution; The encapsulated sampled signal is preprocessed to obtain a preprocessed sampled signal for parameter inversion processing.

5. The packaging and testing method for FRD devices according to claim 4, characterized in that, Preprocessing is performed on the encapsulated sampled signal, including: The encapsulated sampled signal is subjected to bandwidth-limiting filtering to suppress high-frequency noise components; and The filtered packaged sampling signal is subjected to waveform alignment processing to establish a time correspondence between the test excitation signal and the packaged sampling signal.

6. The packaging and testing method for FRD devices according to claim 1, characterized in that, Based on the encapsulation parasitic network model, parameter inversion processing is performed on the encapsulation sampling signal to obtain multiple chip electrical parameters corresponding to the multiple FRD chips, including: The equivalent circuit of the FRD packaged device is constructed based on the packaged parasitic network model. Based on the equivalent circuit, determine multiple chip electrical parameters corresponding to the multiple FRD chips respectively.

7. The packaging and testing method for FRD devices according to claim 6, characterized in that, The step of determining the multiple chip electrical parameters corresponding to the multiple FRD chips based on the equivalent circuit includes: The estimated values ​​of the plurality of chip electrical parameters are determined based on the error metric between the simulated response signal determined by the package parasitic network model and the package sampling signal.

8. The packaging and testing method for FRD devices according to claim 1, characterized in that, The plurality of core electrical parameters include at least one of the following: Forward voltage drop parameters of each FRD chip under a predetermined forward current; Reverse recovery charge parameters of each FRD chip during the reverse recovery process; Reverse recovery time parameters for each FRD chip during the reverse recovery process; Reverse leakage current parameters of each FRD chip under a predetermined reverse voltage.

9. The packaging and testing method for FRD devices according to claim 1, characterized in that, The FRD packaged device under test also includes multiple chip current sensing branches corresponding to the multiple FRD chips respectively.

10. A packaging and inspection system for an FRD device, characterized in that, include: The acquisition module is used to acquire the package structure information of the FRD packaged device under test. The package structure information characterizes the package interconnection structure between multiple FRD chips connected in parallel within the FRD packaged device and external pins. The processing module is used to establish a parasitic network model of the FRD packaged device based on the packaged structure information. The processing module is further configured to apply a test excitation signal to the external pin of the FRD package device and determine the corresponding package response signal, so as to sample the package response signal to obtain a package sampling signal; The processing module is further configured to perform parameter inversion processing on the packaged sampling signal based on the packaged parasitic network model, so as to obtain multiple chip electrical parameters corresponding to the multiple FRD chips respectively; The determination module is used to determine whether there are abnormal cores inside the FRD packaged device based on the multiple core electrical parameters.

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