Adaptation method of error correction capability, equipment and storage medium

Abstract

The invention discloses an error correction capability adaptation method and device and a storage medium, and the method comprises the steps: responding to an error correction capability adaptation instruction, and obtaining an address offset parameter of a storage bank based on the error correction capability adaptation instruction; reading a plurality of data blocks in the memory bank according to the address offset parameter; determining error data exceeding the capacity of a single error correction processing unit in the plurality of data blocks; dividing the error data into a plurality of error subsets according to a mapping relation between physical distribution characteristics of the error data and logic addresses, and distributing the plurality of error subsets to a plurality of error correction processing units for parallel error correction decoding; according to the decoding result of each error correction processing unit, judging whether error correction of the error data is successful or not; and if the error correction is successful, setting the address offset parameter as an address offset configuration for performing read-write operation on the same kind of data. Through sensing error physical distribution and intelligent segmentation parallel processing, the technical effect of improving the error correction success rate and the system adaptation capability is achieved.

Description

Technical Field

[0001] This application relates to the field of data error correction technology for storage devices, and more particularly to an adaptation method, device and storage medium for error correction capability. Background Technology

[0002] In NAND flash memory-based storage devices, the main controller ensures data reliability through error correction codes (such as BCH codes and LDPC codes). Error correction processing is typically performed in units of fixed-length data units (such as 1KB DMA regions). However, the physical page length of a flash memory chip (e.g., 18,368 bytes) is fixed, while the parity check region length required by the main controller to match different error correction levels (different ECC matrices) may vary. When the effective data length of a physical page is not divisible by the length of the error correction unit, a "residual data area" is generated at the end of the page that cannot be covered by any complete error correction unit. During subsequent reads, if an error occurs in this residual data area, it will manifest as an error data burst exceeding the capacity of a single error correction unit (such as the decoding unit corresponding to a DMA).

[0003] The traditional solution employs "address offset" programming and reading techniques. By shifting the column address sequence forward during programming, residual data is distributed and written to the end of multiple consecutive data blocks (DMA). During reading and error correction, errors that were originally concentrated are distributed across multiple error correction processing units. However, this error data "distribution" strategy is usually mechanical, average, or based solely on simple address offset calculations, completely ignoring the actual physical distribution characteristics of error data in the storage medium and the complex mapping relationship between these physical distributions and logical addresses.

[0004] The physical characteristics of flash memory cells (such as process variations, erase / write wear, and interference from neighboring cells) mean that errors are not completely uniform or randomly distributed; their distribution often exhibits spatial correlation. Simple average distribution may split strongly correlated error bits across different error correction units, disrupting the inherent clustering characteristics of errors and potentially exceeding the error correction capability of each unit for random errors. Alternatively, failure to effectively segment errors according to their actual physical clusters may result in some error correction units still being assigned an excessive number of correlated errors, leading to decoding failures. Furthermore, different address mapping strategies (such as wear leveling and remapping introduced by bad block management) cause the correspondence between logical addresses and physical cells to change dynamically, further increasing the unpredictability of error distribution.

[0005] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is prior art. Summary of the Invention

[0006] The main objective of this application is to provide an adaptation method, device, and storage medium for error correction capabilities, aiming to solve the technical problem that existing error correction methods neglect the physical distribution and address mapping of errors, resulting in low error correction efficiency.

[0007] To achieve the above objectives, this application proposes a method for adapting error correction capabilities, the method comprising: In response to the error correction capability adaptation instruction, the address offset parameter of the memory bank is obtained based on the error correction capability adaptation instruction; Multiple data blocks are read from the memory according to the address offset parameter; Among the plurality of data blocks, erroneous data exceeding the capacity of a single error correction processing unit is identified; Based on the mapping relationship between the physical distribution characteristics of the erroneous data and the logical address, the erroneous data is divided into multiple erroneous subsets, and the multiple erroneous subsets are assigned to multiple error correction processing units for parallel error correction and decoding. Based on the decoding results of each error correction processing unit, it is determined whether the error data has been successfully corrected; If the error correction is successful, the address offset parameter will be set to the address offset configuration for reading and writing the same type of data.

[0008] In one embodiment, before the step of responding to an error correction capability adaptation instruction and obtaining the address offset parameter of the memory bank based on the error correction capability adaptation instruction, the method further includes: In response to a target data write command, the data length of the target data is determined; Calculate the difference between the data length and the preset error correction data length, and generate an initial address offset parameter based on the difference; Based on the initial address offset parameter, adjust the starting write address of the target data in the memory. The target data is written to the storage at the adjusted starting write address.

[0009] In one embodiment, the step of adjusting the starting write address of the target data in the memory based on the initial address offset parameter includes: Obtain the historical error correction success rate and current operating performance parameters of the storage unit; A weighted evaluation value is calculated based on the historical error correction success rate and the current working performance parameters, and the initial address offset parameter is dynamically optimized based on the weighted evaluation value to obtain the optimized address offset parameter. Based on the optimized address offset parameters, the starting write address of the target data is determined.

[0010] In one embodiment, the step of writing the target data to the memory at the adjusted starting write address includes: The target data is split into multiple consecutive data segments; Generate an address offset sequence based on the address offset parameters; According to the address offset sequence, the starting write address of each data segment is determined sequentially; Each of the data segments is written to the memory at the determined starting write address.

[0011] In one embodiment, the step of writing each of the data segments into the memory at the determined starting write address includes: The end address is calculated based on the start write address and the length of the data segment, and it is determined whether both the start write address and the end address are within the effective addressing range of the memory. If so, continue writing the data segment based on the starting write address; If not, the write process is interrupted, the address out-of-bounds information is recorded, and a preset address out-of-bounds handling strategy is executed. The preset address out-of-bounds handling strategy includes address correction or error report generation operations.

[0012] In one embodiment, the step of segmenting the erroneous data into multiple erroneous subsets based on the mapping relationship between the physical distribution characteristics of the erroneous data and logical addresses, and allocating the multiple erroneous subsets to multiple error correction processing units for parallel error correction decoding, includes: Analyze the error patterns and distribution characteristics of the erroneous data; Based on the distribution characteristics, the erroneous data is divided into multiple erroneous subsets; The real-time load rate of each error correction processing unit is polled, and each error subset is assigned to an error correction processing unit whose real-time load rate is less than a first load threshold for parallel processing.

[0013] In one embodiment, the step of polling the real-time load rate of each of the error correction processing units and allocating each of the error subsets to error correction processing units with real-time load rates less than a first threshold for parallel processing includes: Monitor the processing progress of each error correction processing unit on the assigned subset of errors; If the processing progress of the error correction processing unit is detected to be less than a preset progress threshold, or the real-time load rate is greater than a second load threshold, then the subset of errors that have not been decoded by the error correction processing unit will be redistributed to the error correction processing unit with the lowest current load rate, wherein the second load threshold is greater than or equal to the first load threshold.

[0014] In one embodiment, the method for adapting the error correction capability further includes: The error correction performance metrics of similar data that are read and written using the address offset parameter are monitored. When the error correction performance index is lower than the preset performance threshold for multiple consecutive operation cycles, a recalculation and adaptation process for the address offset parameters of the same type of data is triggered. The read / write operation offset configuration for the same type of data is updated using the recalculated address offset parameters.

[0015] In addition, to achieve the above objectives, this application also proposes an adaptation device for error correction capability, the device comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the error correction capability adaptation method as described above.

[0016] In addition, to achieve the above objectives, this application also proposes a storage medium, which is a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it implements the steps of the adaptation method for error correction capability as described above.

[0017] One or more technical solutions proposed in this application have at least the following technical effects: The technical solution of this application responds to an error correction capability adaptation instruction and obtains the address offset parameter of the memory bank based on the error correction capability adaptation instruction; reads multiple data blocks in the memory bank according to the address offset parameter; identifies erroneous data exceeding the capacity of a single error correction processing unit among the multiple data blocks; divides the erroneous data into multiple erroneous subsets according to the mapping relationship between the physical distribution characteristics of the erroneous data and logical addresses, and assigns the multiple erroneous subsets to multiple error correction processing units for parallel error correction decoding; determines whether the erroneous data has been successfully corrected based on the decoding results of each error correction processing unit; if the error correction is successful, the address offset parameter is set to the address offset configuration for reading and writing similar data.

[0018] This application achieves the technical effect of improving error correction success rate and system adaptability by perceiving the physical distribution of errors and intelligently segmenting and processing them in parallel. Attached Figure Description

[0019] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0020] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a flowchart illustrating the first embodiment of the error correction capability adaptation method of this application; Figure 2 This is a detailed step diagram based on step S40 in the first embodiment; Figure 3 This is a flowchart illustrating the second embodiment of the error correction capability adaptation method of the present invention; Figure 4 This is a detailed step diagram based on step S90 in the second embodiment; Figure 5 This is a detailed step diagram based on step S100 in the second embodiment; Figure 6 This is a flowchart illustrating the third embodiment of the error correction capability adaptation method of the present invention; Figure 7 This is a schematic diagram of the device structure of the hardware operating environment involved in the error correction capability adaptation method in the embodiments of this application.

[0022] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0023] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0024] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0025] The main solution of this application embodiment is as follows: responding to the error correction capability adaptation instruction, and obtaining the address offset parameter of the storage bank based on the error correction capability adaptation instruction; reading multiple data blocks in the storage bank according to the address offset parameter; identifying erroneous data exceeding the capacity of a single error correction processing unit in the multiple data blocks; dividing the erroneous data into multiple erroneous subsets according to the mapping relationship between the physical distribution characteristics of the erroneous data and the logical address, and allocating the multiple erroneous subsets to multiple error correction processing units for parallel error correction decoding; determining whether the erroneous data has been successfully corrected according to the decoding results of each error correction processing unit; if the error correction is successful, setting the address offset parameter to the address offset configuration for reading and writing similar data.

[0026] In existing technologies, the physical characteristics of flash memory cells (such as process variations, erase / write wear, and interference from neighboring cells) cause errors to be neither completely uniform nor randomly distributed; their distribution exhibits spatial correlation. Simple average distribution may split strongly correlated error bits across different error correction units, disrupting the inherent clustering characteristics of errors and potentially exceeding the error correction capability of each unit for random errors. Alternatively, failure to effectively segment errors according to their actual physical clusters may result in some error correction units still being assigned an excessive number of correlated errors, leading to decoding failures. Furthermore, different address mapping strategies (such as wear leveling and remapping introduced by bad block management) cause the correspondence between logical addresses and physical cells to change dynamically, further increasing the unpredictability of error distribution.

[0027] This application provides a solution that improves the success rate of error correction and enhances system adaptability by perceiving the physical distribution of errors and intelligently segmenting and processing them in parallel.

[0028] Based on this, embodiments of this application provide a method for adapting error correction capabilities, referring to... Figure 1 , Figure 1 This is a flowchart illustrating the first embodiment of the error correction capability adaptation method of this application. In this embodiment, the error correction capability adaptation method includes steps S10 to S60: Step S10: In response to the error correction capability adaptation instruction, obtain the address offset parameter of the memory bank based on the error correction capability adaptation instruction; In this embodiment, the operation of the address offset parameter obtained based on the error correction capability adaptation instruction is the initialization and parameter configuration stage. The core data processing logic of this initialization and parameter configuration stage is that the system changes from passively executing standard read and write operations to actively executing them once, realizing the adaptation process of evaluating and optimizing the error correction performance of a specific physical storage area.

[0029] Specifically, the error correction capability adaptation instruction is the command source that triggers this dedicated process. This source can be a pre-set periodic maintenance task in the firmware, an internal instruction automatically generated by the controller when it detects that the raw bit error rate (RBER) of a specific logical unit (LUN) or physical block exceeds a predetermined threshold, or an external test command received through the host interface.

[0030] Furthermore, the address offset parameter is a key input variable for performing subsequent non-standard data read operations, defining the initial offset when reading data from the physical starting address of the storage medium. The address offset parameter is not a fixed value and may originate from multiple configuration sources. In specific implementations, the address offset parameter is pre-stored in the configuration register of the main controller or in a specific area of ​​the non-volatile memory (NVM), and is associated with different storage blocks or error correction levels. In another implementation, the address offset parameter is dynamically calculated by the algorithm module of the main controller based on the logical address of the current region to be adapted, combined with the bad block management table and wear leveling mapping table of the memory bank to generate an initial trial value.

[0031] The specific implementation process of obtaining the address offset parameter involves the instruction parsing unit of the main controller decoding the error correction capability adaptation instruction to determine the target operation object (such as a specific flash channel, chip, and physical page address). Subsequently, the storage interface controller of the main controller retrieves or calculates the initial address offset parameter corresponding to the target operation object from the internal parameter table or by querying the mapping management layer based on the decoding result. The output of the address offset parameter is a definite value that can guide the accurate reading of unaligned data in subsequent operations, thereby laying the data access foundation for analyzing the correlation between error distribution and address mapping.

[0032] Step S20: Read multiple data blocks from the memory according to the address offset parameter; In this embodiment, during the data acquisition phase, a continuous data reading operation with a non-standard starting address is performed using the determined address offset parameter to completely cover all data within a physical page, including the residual data area, thus providing raw data samples for subsequent error analysis.

[0033] It is understood that the address offset parameter determines the number of bytes to skip starting from the starting column address of the physical page. Therefore, this read operation does not start from logical sector 0 of the physical page, but rather from the column address specified by the address offset parameter, continuously reading a data amount exceeding the length of one physical page. In specific implementation, the main controller sends a read command sequence containing the target physical page address and the starting column address to the memory via its flash interface (such as a Toggle or ONFI protocol interface), where the starting column address is set by the address offset parameter.

[0034] Because the read operation crosses physical page boundaries, implementation typically requires reading the contents of two or more physical pages consecutively, or reading the entire contents of one physical page plus the beginning of the next physical page, to ensure that all "residual data" scattered at the end of multiple consecutive data blocks due to address offset programming is completely included in the read data stream. The read raw data is transferred to the internal buffer of the main controller and organized sequentially into the multiple data blocks. The length of each data block is aligned with the basic data unit length used by the main controller for error correction processing (e.g., 1KB corresponding to a DMA transfer). The key technical means of this read process lies in precisely controlling the addressing of the flash memory interface, ensuring flexible addressing based on dynamic address offset parameters, thereby capturing logically continuous but physically fragmented data sequences that may be scattered due to offset programming.

[0035] Step S30: Among the plurality of data blocks, identify erroneous data that exceeds the capacity of a single error correction processing unit; In this embodiment, during the error identification and quantization stage, the original state of the read multiple data blocks is analyzed to identify data segments that have excessively high error bit counts or error pattern complexity, making them uncorrectable by an independent error correction processing unit (such as an LDPC decoder with a specific ECC matrix).

[0036] First, for each of the multiple data blocks, preliminary adjoint calculations or hard-decision decoding attempts are performed using the same error correction coding parameters (generating polynomials or parity-check matrices) as during writing. If the error in a data block is within the error correction capability (e.g., the threshold for the number of correctable random error bits) of a single error correction processing unit, that error correction processing unit is marked as a correctable unit. The key point of the above identification is to identify data areas that fail in the preliminary verification, or whose number of error bits or error cluster size, estimated by soft-decision information (e.g., the LLR value of the memory cell threshold voltage distribution read from flash memory), significantly exceed the design tolerance of the single error correction processing unit. The "error data exceeding the capacity of a single error correction processing unit" manifests as a continuous logical data segment, presenting a large number of errors concentrated during reading due to physically correlated errors (e.g., severe interference or wear of a local memory cell array).

[0037] Furthermore, the specific implementation of this determination process involves the pre-decoding analysis module of the ECC engine of the main controller. This module statistically analyzes the parity weight and convergence of the initial iteration decoding for each data block, or assesses the severity and clustering characteristics of the error by analyzing the statistical characteristics of the LLR value. By comparing with a preset capacity threshold, the multiple data blocks can be divided into a set that can be normally corrected and a set containing erroneous data exceeding the capacity of a single error correction processing unit, requiring special processing.

[0038] Step S40: Based on the mapping relationship between the physical distribution characteristics of the error data and the logical address, the error data is divided into multiple error subsets, and the multiple error subsets are assigned to multiple error correction processing units for parallel error correction and decoding. In this embodiment, based on the mapping relationship between the physical distribution characteristics of the error data and the logical address, the error data is divided into multiple error subsets, and the multiple error subsets are assigned to multiple error correction processing units for parallel error correction and decoding.

[0039] In this error correction and decoding process, we need to abandon the simple and uniform division of error data. Instead, we need to implement an intelligent and adaptive segmentation strategy based on the actual cluster characteristics of errors on the physical medium and their dynamic mapping relationship with logical addresses. The aim is to match the error correction difficulty of each error subset generated after segmentation with the actual capability of an error correction processing unit.

[0040] First, the physical distribution characteristics of the erroneous data need to be analyzed. This is achieved by analyzing the spatial distribution pattern of soft information (such as fine LLR values) corresponding to the location of the erroneous data read from flash memory. Specifically, the error feature analysis module within the controller identifies whether the erroneous bits exhibit spatial clustering. For example, whether the high error rate is concentrated in a local area of ​​a physical word line or bit line, or whether it exhibits a specific two-dimensional pattern.

[0041] Secondly, based on the mapping relationship between logical addresses and physical addresses, the Flash Translation Layer (FTL) of the main controller provides a query interface to obtain the specific physical unit information mapped to the logical address range corresponding to the erroneous data, including the physical block, page, and metadata such as the historical write / erase count and neighborhood interference records of the physical unit. Based on the physical distribution characteristics and the mapping relationship, a segmentation algorithm is executed. For example, if analysis reveals that errors are highly clustered in a certain physical sub-block and the logical addresses are continuous, the continuous logical addresses may be considered as the entire cluster, and the entire cluster as a subset of errors; if a logically continuous error segment actually maps to two physically isolated regions with independent error characteristics, segmentation is performed at the corresponding physical boundary. The goal of this segmentation is to maximize the error correlation within each subset of errors (to utilize the fault tolerance characteristics of error correction codes for sudden errors), while ensuring that the number or complexity of errors in each subset does not exceed the processing limit of an error correction processing unit. After segmentation, each subset of errors, along with its corresponding original data block portion, is allocated to multiple available error correction processing units (such as multiple LDPC decoder instances) within the main controller. The aforementioned processing units operate in parallel, with each independently decoding and correcting the assigned subset of errors and its context data.

[0042] Step S50: Determine whether the error data has been successfully corrected based on the decoding results of each error correction processing unit; In this embodiment, the process of determining whether error correction is successful based on the decoding results of the aforementioned error correction processing unit is the result synthesis and judgment stage of this technical solution. The core data processing logic of this result synthesis and judgment stage lies in collecting and analyzing the decoding outputs of all parallel error correction processing units for their respective assigned error subsets, and making a final decision on the overall success or failure of error correction for the entire original "error data exceeding the capacity of a single error correction processing unit" region based on comprehensive judgment rules.

[0043] Specifically, after completing decoding, each error correction processing unit outputs a status flag and a potentially corrected data segment. The status flag indicates whether the decoding of the assigned error subset by the error correction processing unit was successful, failed, or failed to converge after reaching the maximum number of iterations. The determination logic is executed by the error correction management unit of the main controller. During this execution, the decoding status of all parallel processing units is first checked. The basic rule for determining the decoding status is: when all error correction processing units involved in processing the erroneous data report successful decoding, the entire erroneous data is determined to have been successfully corrected.

[0044] However, in the actual implementation process, even if a certain processing unit fails, if the corresponding error subset is analyzed and deemed to have an acceptable impact on the overall data reliability (such as only being a specific type of fill data), and other key error subsets have been successfully decoded, it can be judged as conditionally successful or partially successful at a higher level, and the log is recorded.

[0045] Secondly, the successfully decoded data segments need to be reassembled. The error correction management unit, based on a pre-recorded segmentation mapping relationship, reassembles the corrected data segments output by each error correction processing unit according to their original logical order to restore the complete, error-corrected data region. Finally, the determination result (success / failure / conditional success) is generated, along with necessary metadata, such as the identifier of the failed processing unit and the estimated error mode. This determination result is the direct basis for deciding whether to update the system configuration. Furthermore, this process relies on the result bus and status register interaction within the main controller, as well as a central adjudication logic, to ensure reliable collection and consistent judgment of the distributed decoding results.

[0046] Step S60: If the error correction is successful, the address offset parameter is set to the address offset configuration for reading and writing the same type of data.

[0047] In this embodiment, after the error correction is determined to be successful, a parameter optimization and solidification stage is performed. The core data processing logic in this parameter optimization and solidification stage is to upgrade the address offset parameter that has been verified to be effective in this error correction capability adaptation process from a one-time trial value to a persistent operation configuration for specific types or specific regions of data, thereby guiding the standard read and write process for this type of data in the future, so as to achieve long-term and stable error dispersion optimization.

[0048] That is, after determining "error correction successful", the currently used address offset parameter is confirmed. Combined with the segmentation strategy implemented based on the physical distribution characteristics of the error, they together constitute an effective solution that can properly handle the residual data area errors generated by this storage area under specific wear states and mapping relationships. At this time, the configuration management module of the main controller performs a parameter update operation. The "address offset parameter" is written into the configuration file associated with the specific area of ​​the storage. The configuration file can be stored in the non-volatile configuration memory of the main controller, and the index key value based on this storage can be a logical unit number (LUN), a physical block address range, or an identifier related to data characteristics (such as the namespace or stream identifier), thereby defining what constitutes "same type of data". For example, if this adaptation is performed on a specific physical block, the successful address offset parameter will be recorded as an attribute of that specific physical block. When performing standard programming (writing) operations on the specific physical block or data logically mapped to the specific physical block in subsequent operations, the firmware will automatically call the stored address offset parameter to guide the column address setting of the flash programming command, achieving optimized "address offset programming". Similarly, in subsequent read operations, the same offset is used to read data to ensure the consistency of the error distribution pattern.

[0049] In this embodiment, the one-time adaptive learning result is transformed into a persistent performance optimization configuration, realizing a closed loop from diagnosis to treatment.

[0050] Furthermore, you can also view Figure 2 , Figure 2 This is a detailed step diagram based on step S40 in the first embodiment. Figure 2 The steps of dividing the erroneous data into multiple erroneous subsets based on the mapping relationship between the physical distribution characteristics and logical addresses of the erroneous data, and allocating the multiple erroneous subsets to multiple error correction processing units for parallel error correction and decoding, include S41~43: Step S41: Analyze the error patterns and distribution characteristics of the erroneous data; Step S42: Based on the distribution characteristics, the erroneous data is divided into multiple erroneous subsets; Step S43: Poll the real-time load rate of each error correction processing unit, and assign each error subset to the error correction processing unit whose real-time load rate is less than the first load threshold for parallel processing.

[0051] In this embodiment, the step of dividing the error data into multiple error subsets according to the mapping relationship between the physical distribution characteristics of the error data and the logical address, and allocating the multiple error subsets to multiple error correction processing units for parallel error correction and decoding, includes the following specific implementation process.

[0052] Specifically, the analysis of the error patterns and distribution characteristics of the erroneous data involves the following data processing logic: deep analysis of the original state information of the identified erroneous data is performed to extract the error cluster characteristics and pattern information of the original state information in the physical space of the storage medium, providing a quantitative basis for subsequent segmentation decisions based on physical correlation. In the specific implementation process, the error feature extraction module of the main controller processes the original read signals corresponding to the erroneous data. The key technical means of this processing lies in utilizing the soft decision information read from the storage unit, namely the sequence of log-likelihood ratio (LLR) values ​​corresponding to each storage unit.

[0053] The error feature extraction module performs spatial analysis on the LLR value sequence to identify the degree and range of error bit clustering. For example, by setting an LLR amplitude threshold, cell positions below the threshold are marked as suspected error bits. Then, two-dimensional spatial clustering analysis (such as density clustering based on the row and column addresses of physical pages) is performed on the marked positions to identify several independent error clusters.

[0054] Simultaneously, the analysis module calculates the statistical characteristics of each error cluster, such as the number of error bits within the cluster, the physical size of the cluster (spanning multiple word lines and bit lines), the average reliability of the LLR value within the cluster, and the physical distance between clusters. Furthermore, this analysis incorporates physical mapping information obtained in real-time from the main controller's Flash Translation Layer (FTL) to confirm the specific set of physical cells (such as physical block number, physical page number, and word line index) currently mapped to the logical address range containing the error data, and associates the logical address with the row and column coordinates of the physical cells.

[0055] Based on the distribution characteristics, the erroneous data is divided into multiple erroneous subsets. The distribution characteristics of these erroneous subsets, particularly the physical boundaries and logical-physical mapping relationships of the erroneous clusters, are used to formulate a segmentation strategy. This strategy divides logically continuous erroneous data segments into several erroneous subsets. Each erroneous subset aims to contain one or more erroneous clusters that are highly correlated in physical space, and its error correction complexity is adapted to the processing capacity of a single error correction processing unit.

[0056] Subsequently, in the specific implementation process, the dynamic segmentation strategy module of the main controller performs the partitioning process. This module receives the analysis results from the error feature extraction module and the mapping relationship provided by the FTL. Specifically, the dynamic segmentation strategy does not simply divide according to a fixed length, but follows these principles: First, it prioritizes dividing identified, physically independent error clusters into independent error subsets; second, if the size of one or more error clusters exceeds the theoretical error correction capacity of a single error correction processing unit, a secondary partition is performed based on the internal physical structure of this error cluster (e.g., mainly distributed along a certain word line); third, considering the continuity of logical addresses, it avoids forcibly keeping a logically continuous segment mapped to multiple physically isolated and differently patterned physical sub-regions within a single error subset. The partitioning algorithm outputs a list of partition points, whose positions in the logical data stream define the boundaries of each error subset. Simultaneously, the algorithm records the main physical location associated with each error subset and the estimated error intensity.

[0057] Subsequently, the real-time load rate of each error correction processing unit is polled, and each error subset is assigned to an error correction processing unit with a real-time load rate less than a first load threshold for parallel processing. During the task scheduling and execution phase, after intelligent segmentation, the generated multiple error subsets are treated as independent tasks and efficiently and evenly scheduled onto the available hardware resources of multiple error correction processing units within the main controller to maximize parallel processing throughput and reduce overall decoding latency.

[0058] In specific implementation, the task scheduler of the main controller maintains a list containing the status (idle, busy, load rate) of all available error correction processing units. The load rate can be quantified by the current task queue length of the available error correction processing unit or the percentage of the current decoding iteration progress. In addition, the first load threshold is a preset value used to determine whether the processing unit is in a "light load" state that can accept new tasks.

[0059] During the allocation process, the task scheduler sequentially searches for a suitable processing unit for each generated error subset. The scheduler polls the real-time load rate of all error correction processing units, selects the first error correction processing unit with a load rate lower than a first load threshold, and allocates the current error subset and its associated data context (original data fragment, LLR value subset) to it. After allocation, the load status of this error correction processing unit is updated. This process is repeated until all error subsets are allocated. Each error correction processing unit is activated and begins to independently and in parallel perform decoding operations (such as LDPC iterative decoding) on ​​its assigned error subset. This dynamic load balancing mechanism ensures full utilization of computing resources and avoids situations where some units are overloaded while others are idle.

[0060] Furthermore, based on the embodiment of step S43 above, this step is further refined, namely, polling the real-time load rate of each of the error correction processing units and allocating each of the error subsets to the error correction processing units with real-time load rates less than a first threshold for parallel processing, including steps S43-1 to S43-2: Step S43-1: Monitor the processing progress of each error correction processing unit on the assigned error subset; Step S43-2: If the processing progress of the error correction processing unit is detected to be less than a preset progress threshold, or the real-time load rate is greater than a second load threshold, then the undecoded subset of errors of the error correction processing unit is redistributed to the error correction processing unit with the lowest current load rate, wherein the second load threshold is greater than or equal to the first load threshold.

[0061] In this embodiment, during the process of polling the real-time load rate of each error correction processing unit and allocating each error subset to the error correction processing unit with a real-time load rate less than a first threshold for parallel processing, this specific parallel processing process is achieved by monitoring the processing progress of each error correction processing unit on the allocated error subset.

[0062] Specifically, in the monitoring phase of the dynamic load balancing and fault recovery mechanism, after the parallel decoding task starts, the execution status and progress of each error correction processing unit are continuously tracked to provide real-time data support for possible task rescheduling decisions. In practice, this is executed by the monitoring submodule in the task scheduler of the main controller. The monitoring submodule periodically or event-triggeredly queries each error correction processing unit for the processing progress of its current task. This processing progress can be quantified in ways including, but not limited to, the ratio of consumed iterations to the preset maximum number of iterations, the remaining number of checksums that do not satisfy the equation, or the completion percentage estimated based on time slices.

[0063] Meanwhile, the monitoring submodule continuously updates the real-time load rate of each error correction processing unit previously acquired. The progress and load status information represented by the real-time load rate of all error correction processing units is summarized and maintained in a global task status table. This proactive monitoring mechanism enables the system to promptly detect cases where error correction processing units may be stuck (e.g., extremely slow iteration convergence) or encounter unforeseen complex error patterns, resulting in processing stagnation.

[0064] If the processing progress of the error correction processing unit is detected to be less than a preset progress threshold, or the real-time load rate is greater than a second load threshold, then the subset of errors that have not been decoded on the error correction processing unit will be redistributed to the error correction processing unit with the lowest current load rate, wherein the second load threshold is greater than or equal to the first load threshold.

[0065] Furthermore, the decision-making and execution phases of the dynamic load balancing and fault recovery mechanism intervene in processing tasks that exhibit anomalies or are expected to experience severe delays based on monitoring feedback. By migrating tasks to more suitable processing resources, the robustness and timeliness of the overall error correction process are ensured. Specifically, a critical point in time or iteration progress is set as a preset progress threshold. For example, if the progress falls below a certain percentage of the expected value after a specific period of time following task allocation, it is considered slow progress. The second load threshold is defined as a load level threshold that is higher than or equal to the first load threshold, used to identify error correction processing units that have transitioned from a "lightly loaded" to an "overloaded" state. When the monitoring submodule detects that any error correction processing unit meets any of the following conditions, a reallocation process is triggered: First, the processing progress of the current error correction processing unit is lower than the preset progress threshold, indicating that the error correction processing unit may not be able to successfully decode the allocated error subset within an acceptable time; Second, the real-time load rate of the error correction processing unit rises and exceeds the second load threshold, possibly due to the abnormal complexity of the tasks processed by the error correction processing unit, consuming excessive computing resources. Based on the above conditions, once the trigger condition is met, the task scheduler first suspends the processing of the incompletely decoded error subset on the target error correction processing unit (if the hardware supports it) and saves its current decoding context state (such as intermediate LLR values ​​and check node information). Subsequently, the scheduler scans the global state table to find the available error correction processing unit with the lowest current real-time load. Finally, the saved task context of the error subset is migrated to the selected error correction processing unit with the lowest load, and the error correction processing unit resumes or restarts the decoding process from its current decoding process breakpoint. The resources of the original error correction processing unit are released and can be used for other decoding tasks. This dynamic reallocation mechanism effectively addresses the load imbalance caused by uneven distribution of error subset complexity or momentary hardware unit anomalies, improving the system's robustness in handling sudden complex error scenarios.

[0066] Furthermore, you can also view 3. Figure 3 This is a flowchart illustrating the second embodiment of the error correction capability adaptation method of the present invention, based on the shown... Figure 3 Before the step of responding to the error correction capability adaptation instruction and obtaining the address offset parameter of the memory bank based on the error correction capability adaptation instruction, the method further includes steps S70~S100: Step S70: In response to the target data write instruction, determine the data length of the target data; Step S80: Calculate the difference between the data length and the preset error correction data length, and generate an initial address offset parameter based on the difference; Step S90: Adjust the starting write address of the target data in the memory according to the initial address offset parameter; Step S100: Write the target data to the storage at the adjusted starting write address.

[0067] In this embodiment, before responding to the error correction capability adaptation instruction and obtaining the address offset parameter of the memory based on the error correction capability adaptation instruction, a detailed setting process for the address offset parameter needs to be set based on relevant processing.

[0068] Specifically, in the initialization phase of the data writing process, in response to the target data write instruction, the data length of the target data is determined. The data write request issued by the host is received and parsed to clarify the scale of the target data to be written, providing basic input for subsequent judgments on whether and how to apply address offset programming. In specific implementation, the main controller's command queue and parsing unit receive the target data write instruction from the host interface (such as NVMe, SATA). The target data write instruction includes the target logical address (LBA) and the target data. The data buffer management module within the main controller is responsible for temporarily storing the target data and accurately calculating the data length, which is typically measured in bytes. Specific methods for determining the data length include: directly parsing the data length field carried in the write instruction; or counting the number of bytes of the received data payload through the data buffer management module. The number of bytes represents a precise data length value of the target data, which will be used for comparison and analysis with the inherent physical structure parameters of the storage device.

[0069] The difference between the target data length and the preset error correction data length is calculated, and an initial address offset parameter is generated based on the difference. By quantitatively comparing the user data length with the standard length of the error correction processing unit inside the storage system (i.e., the preset error correction data length), situations that will lead to a "residual data area" at the end of the physical page are identified, and a preliminary address offset is calculated based on this identification result. The preliminary address offset is intended to initiate the error dispersion mechanism from the start of data writing.

[0070] Additionally, the preset error correction data length refers to the standard length of the data unit processed by the main controller in a single error correction encoding or decoding operation, such as 1KB or 4KB corresponding to a DMA transfer. The calculation module performs a modulo operation between the data length and the preset error correction data length, and the remainder is the difference. The difference represents the amount of tail data remaining after dividing into complete error correction units, which is insufficient to fill a complete error correction unit. In the process of generating the initial address offset parameter based on the difference, the initial address offset parameter is set to a function value equal to or based on the difference. In a direct implementation, the initial address offset parameter is set to the opposite of the difference or a calibrated offset, such that during programming, writing begins with an offset of this parameter value from the physical page start address, thereby ensuring that the end part (i.e., the residual part) of the target data can be physically stored contiguously with the start part of the subsequent data and combined into the coverage of the next error correction processing unit. The parameter generation algorithm is fine-tuned in conjunction with the alignment requirements of the physical page size of the memory.

[0071] Based on the initial address offset parameter, the starting address for writing the target data in the memory is adjusted. This process is defined as the physical addressing translation stage. The data processing logic of the physical addressing translation stage is to apply the calculated, logically meaningful initial address offset parameter to the mapping and translation process from the logical address space to the physical address space, thereby determining the specific starting column address for programming operations on the flash physical page.

[0072] In practice, this is accomplished collaboratively by the flash translation layer (FTL) and the physical address generation circuit of the main controller. First, the FTL allocates the target physical page based on the logical address in the target data write instruction, combined with wear leveling and bad block management strategies. Then, the physical address generation circuit receives the initial address offset parameter and the starting physical address of the target physical page. This adjustment process is manifested in that when sending the page programming command sequence to the flash memory chip, the specified column address does not start from the normal starting position of the indicated physical page (usually 0), but is set to the value indicated by the initial address offset parameter. This setting indicates that the first byte of the target data will be written to the physical page at a position offset from the initial address offset parameter, rather than at the beginning of the page.

[0073] The target data is written to the memory at the adjusted starting write address. This writing process is defined as the physical programming execution phase. In the physical programming execution phase, a complete flash page programming operation is performed based on the determined non-standard starting address to actually write the target data in the buffer to the flash cell array, thereby realizing the physical landing of address offset programming.

[0074] In the specific implementation process, the flash interface controller of the main controller sends a command sequence containing the target physical page address and the adjusted start column address according to the programming timing requirements of the flash memory chip. Subsequently, the target data in the data buffer management module is transmitted serially or in parallel to the page cache register of the memory bank via the data bus. The target data fills the page cache starting from the adjusted start write address and may cross the physical page boundary. Finally, the flash interface controller issues a programming confirmation command, and the flash memory chip programs the data in the page cache register into the corresponding memory cell.

[0075] In this embodiment, the initial address offset parameter is used to perform a pre-distributed write operation on the user data that may generate residual data areas, laying the foundation for the physical data layout for the error correction capability adaptation process that may be triggered during subsequent reading.

[0076] Furthermore, you can also view Figure 4 , Figure 4 Based on the detailed step diagram of step S90 in the second embodiment, this step is analyzed in detail, namely, the step of adjusting the starting write address of the target data in the memory according to the initial address offset parameter, including S91~93: S91, obtain the historical error correction success rate and current working status performance parameters of the storage; S92, calculate a weighted evaluation value based on the historical error correction success rate and the current working state performance parameters, and dynamically optimize the initial address offset parameters based on the weighted evaluation value to obtain the optimized address offset parameters; S93, determine the starting write address of the target data based on the optimized address offset parameters.

[0077] In this embodiment, the starting address for writing the target data in the memory is adjusted based on the initial address offset parameter. During this adjustment process, the initial address offset parameter is optimized by calculating a weighted evaluation value using the historical error correction success rate of the memory and the current operating performance parameters. The starting address for writing the target data is then determined based on this optimized initial address offset parameter.

[0078] In the data foundation construction phase of dynamic optimization decision-making, multi-dimensional quantitative indicators reflecting the reliability and performance status of a specific area (or the whole) of the memory are extracted from historical records and real-time monitoring modules, providing factual basis for subsequent intelligent parameter optimization. Specifically, the reliability management module of the main controller retrieves the historical error correction success rate of the region associated with the current target write address (such as the same physical block or word line group) from the non-volatile log memory. This historical error correction success rate can be expressed as the percentage of data units that successfully passed error correction decoding in the associated region during the most recent read operations, or the success rate of a specific error correction level (such as soft decoding of LDPC low-density parity-check codes). Simultaneously, the system monitoring module collects the current operating status performance parameters in real time. These parameters include the current operating temperature of the memory or target chip, the average number of erase / write cycles (P / E Cycles) of the physical unit to which the target data is to be written, the estimated intensity index of neighboring cell interference (PD), and the instantaneous value of the raw bit error rate (RBER) obtained from recent read operations. The acquisition of the above parameters involves querying temperature sensor readings, accessing the FTL metadata table, and the preprocessing statistics unit of the ECC engine.

[0079] A weighted evaluation value is calculated based on the historical error correction success rate and the current operating state performance parameters. This weighted evaluation value is then used to dynamically optimize the initial address offset parameters, resulting in optimized address offset parameters. In the core calculation and decision-making stage of this optimization process, a predefined evaluation model integrates the acquired multi-source heterogeneous state parameters into a single quantitative score representing the current storage environment's "error risk level" or "performance stress level." Based on this score, the generated, generalized initial address offset parameters are adaptively corrected.

[0080] In the specific implementation process, the parameter optimization algorithm module of the main controller performs the operation. First, the parameter optimization algorithm module maps each acquired parameter (such as historical success rate, temperature, P / E count, RBER) to a unified scoring range using its respective normalization function. Then, based on preset weight coefficients (which can be obtained from experimental data or trained using a machine learning model), the weighted evaluation value is calculated. For example, in scenarios with high P / E counts and high current temperatures, the weight configuration tends to reduce the optimistic estimate of the error correction success rate, increase the weighted evaluation value, and characterize a higher error risk. Subsequently, the optimization algorithm of the parameter optimization algorithm module dynamically adjusts the initial address offset parameter based on the weighted evaluation value.

[0081] One implementation of this dynamic adjustment is defined as follows: A threshold matrix for evaluation values ​​is set, with different threshold ranges corresponding to different address offset fine-tuning strategies. For example, when the weighted evaluation value indicates a low risk, the optimized address offset parameter may directly adopt the initial address offset parameter; when the evaluation value indicates an increased risk, the algorithm searches for a better offset within a preset range (e.g., ±N bytes). This offset aims to offset the expected residual data area from known, error-prone (e.g., based on historical error bitmaps) physical unit areas, or to make it cross different word lines to disperse interference risk. Finally, the optimization algorithm of the parameter optimization model outputs the optimized address offset parameter after environmental state awareness optimization.

[0082] Based on the optimized address offset parameters, the starting write address of the target data is determined. In this determination process, the environment-aware optimized offset parameters output from the above decision are applied to the physical address generation process, replacing the original general parameters, thereby determining the specific column address for the final programming operation. Specifically, the input parameter is the optimized address offset parameter. The physical address generation circuit of the main controller receives the target physical page base address from the FTL and the optimized address offset parameters. This execution address calculation involves adding (or subtracting, depending on the implementation) the optimized address offset parameters to the starting column address of the physical page to generate the final starting column address value used for flash memory programming commands. This generation process ensures that the address offset during writing is no longer a fixed or simple calculation based solely on data length, but rather an intelligent decision result that integrates the current health status and historical performance of the storage medium, thus providing a better starting point for improving the error correction success rate of subsequent reads at the physical data layout level.

[0083] Furthermore, you can also view Figure 5 , Figure 5 As a detailed step diagram based on step S100 in the second embodiment, this step is analyzed in detail, namely, the step of writing the target data to the memory according to the adjusted starting write address, including S101~104: S101, the target data is split into multiple consecutive data segments; S102, Generate an address offset sequence based on the address offset parameter; S103, determine the starting write address of each data segment sequentially according to the address offset sequence; S104, each of the data segments is written to the memory at the determined starting write address.

[0084] In this embodiment, the target data is written to the memory bank according to the adjusted starting write address, and the target data is split into multiple consecutive data segments. During this splitting process, to adapt to the physical characteristics of flash memory programming (such as page cache size and bus width) and facilitate complex address offset sequence management, the logically continuous target data is virtually segmented in the controller buffer to form a series of sub-units that are easy to process sequentially. This splitting is specifically implemented by the data path management module of the main controller. The splitting principle is mainly based on two factors: first, the inherent size of the physical pages of the memory bank or its subpage structure; and second, the preferred data block length of the internal data transmission channel (such as DMA) of the main controller.

[0085] Typically, the target data is equally divided into multiple consecutive data segments of equal length, each segment being equal to the preset error-correcting data length (e.g., 1KB), until the remaining tail data may form a shorter segment. The splitting operation is performed logically within the main controller's internal buffer and does not alter the data's continuity. Each data segment is assigned a segment number and associated with its logical offset in the original data for subsequent addressing and reassembly.

[0086] During the generation of the address offset sequence based on the address offset parameters, a potentially dynamically changing column address increment sequence is derived based on a single starting address offset parameter (whether initial or optimized). This ensures that the entire data stream's writes on the physical page can accurately achieve the predetermined distributed layout. Specifically, the address offset parameter (as the starting offset of the first data segment) determined by the address sequence generator of the main controller serves as input. The address offset sequence is a list where each element corresponds to the column address offset of a data segment relative to the starting address of its physical page during programming. Furthermore, this generation logic needs to consider cases where data segments cross physical page boundaries. For example, the first data segment uses the address offset parameter; subsequent data segments are based on the end address of the previous segment, with the data segment length added, and automatically handle situations where, when the accumulated address exceeds the physical page size, it jumps to the next physical page starting address and may apply new offset rules (such as zeroing or maintaining a fixed offset). The sequence ensures that, when data is written in order, the "residual data" resulting from the original data length not being divisible can be naturally distributed to the tail region of multiple physical data blocks.

[0087] According to the address offset sequence, the starting write address of each data segment is determined sequentially. The generated logical address offset sequence is combined with the actual physical page base address allocated by the Flash Translation Layer (FTL) to calculate a precise absolute physical address (including chip, block, page, and column addresses) that can be recognized by the flash interface for each data segment to be written. In specific implementation, this is done by the physical address synthesis circuit of the main controller. For the i-th data segment in the sequence, the physical address synthesis circuit performs the following operations: First, based on the global logical order of the data segment and the physical page size, it determines the target physical page (which may involve multiple physical pages) to be written to. Then, it obtains the starting physical address (row address) of the target physical page. Finally, it adds the i-th offset in the address offset sequence to the starting column address of the target physical page to obtain the specific starting column address of the data segment within the target physical page. The synthesized complete physical address (row address + column address) is passed to the flash interface controller as the address part of the programming command for that data segment.

[0088] Each data segment is written to the memory at the determined starting write address. During this writing process, a series of flash page programming sub-operations are executed cyclically based on the precise physical address calculated for each data segment, physically writing all data segments to the flash cell array. The specific implementation is iterative: for the first data segment, the flash interface controller of the main controller sends a page programming setting command containing the corresponding starting write address to its target flash chip. Then, the contents of the data segment in the buffer are transferred to the page cache register of the flash chip via the data bus. Finally, a programming confirmation command is issued to initiate the charge injection process. The above process is repeated for subsequent data segments. If the data segment is located on a different physical page, the programming cycle of the previous physical page needs to be completed before programming the new physical page.

[0089] In this embodiment, the logically continuous target data is persistently stored in the flash memory cells of the storage bank according to a predetermined, possibly non-contiguous, physical address sequence with a specific offset pattern, thus completing a complete physical write closed loop for address offset programming.

[0090] Furthermore, based on the embodiment of step S104 above, this step is further refined, and the step of writing each data segment into the memory according to the determined starting write address includes S104-1 to S104-3: S104-1, Calculate the end address based on the start write address and the length of the data segment, and determine whether the start write address and the end address are both within the effective addressing range of the memory. S104-2, If so, continue writing the data segment based on the starting write address; S104-3, If not, interrupt the write process, record the address out-of-bounds information, and execute the preset address out-of-bounds handling strategy, which includes address correction or error report generation operation.

[0091] In this embodiment, during the process of writing each data segment into the memory at the determined starting write address, the ending address is calculated based on the starting write address and the data segment length, and it is determined whether the starting write address and the ending address are both within the effective addressing range of the memory.

[0092] During the security boundary check phase before a write operation, the calculated physical address is validated before executing any actual flash programming commands. This prevents writing to illegal or unaddressable storage areas due to address calculation errors, abnormal offset parameters, or corrupted mapping tables, thereby avoiding data loss or hardware operation errors. This process is performed by the address verification module of the main controller. For any data segment to be written, the address verification module receives the starting write address and the data segment length from the physical address synthesis circuit. The formula for calculating the ending address is: starting write address + data segment length - 1.

[0093] Subsequently, the address verification module compares the starting write address and the ending address with the effective addressing range of the memory bank. The effective addressing range is typically defined as a region starting from zero and extending to the total physical capacity of the memory bank minus one, excluding physical blocks marked as unusable by the bad block management table. The determination logic is as follows: only when both the starting write address and the ending address are not less than zero and neither are greater than the maximum effective physical address, and the address interval spanned between the starting write address and the ending address does not contain any regions marked as bad blocks, is it determined to be within the effective addressing range. This check ensures that the entire data segment will be completely written into a known, good, and accessible physical space.

[0094] If so, the data segment is continued to be written based on the starting write address. Once the address verification passes, confirming address security, a standard flash page programming sub-process is triggered, writing the content of the current data segment to the verified physical address. In specific implementation, the address verification module sends a verification pass signal to the flash interface controller, a component of the above write loop. The flash interface controller then executes the complete programming sequence for the data segment without hindrance. This complete programming sequence includes loading the address, transmitting data, and issuing a programming pulse.

[0095] If not, the write process is interrupted, address out-of-bounds information is recorded, and a preset address out-of-bounds handling strategy is executed. This preset strategy includes address correction or error report generation. The above execution is defined as an exception handling branch. The core data processing logic of this branch is to immediately suspend the current and subsequent write operations when a potential address out-of-bounds risk is detected, preventing destructive actions. It also attempts to repair the problem or report the fault through the system's fault-tolerance mechanism, ensuring system robustness.

[0096] The above implementation is handled by the exception handling unit of the main controller. Once the address verification module determines that the address is invalid, it immediately sends an interrupt signal to the data path management module and the flash interface controller, suspending any ongoing or upcoming data write operations. Simultaneously, the exception handling unit records detailed address out-of-bounds information in the non-volatile error log. The information recorded in the non-volatile error log includes: the identifier of the data segment that triggered the exception, the calculated illegal start and end addresses, the expected valid range, and the offset parameters at that time.

[0097] Subsequently, the preset address out-of-bounds handling strategy is executed. The address correction strategy may include: recalculating the address offset sequence, particularly checking whether the offset parameter has overflowed due to a software error; or, reallocating a completely new physical page within the valid range via FTL, recalculating the write address of the data segment and subsequent affected data segments based on the new physical page, and then attempting to resume the write process from the breakpoint. If address correction fails or the problem is determined to be serious (e.g., a corrupted mapping table), the error report generation operation is performed, i.e., a detailed error descriptor is generated and reported to the upper-layer system or management software via the host interface, while simultaneously marking this write operation as failed.

[0098] Furthermore, you can also view 6. Figure 6 This is a flowchart illustrating the third embodiment of the error correction capability adaptation method of the present invention, based on the shown... Figure 6 The method for adapting the error correction capability further includes steps S110-130: S110, Monitor the error correction performance indicators of similar data that are read and written using the address offset parameter; S120, when the error correction performance index is lower than the preset performance threshold for multiple consecutive operation cycles, a recalculation and adaptation process for the address offset parameters of the same type of data is triggered. S130, using the recalculated address offset parameters, update the read / write operation offset configuration for the same type of data.

[0099] In this embodiment, the error correction performance metrics of similar data that are read and written using the address offset parameter are monitored. This monitoring process is defined as a continuous data collection phase for feedback information. The core data processing logic in this continuous collection phase is that, after the address offset parameter is configured for read and write operations on the same type of data, it is not considered fixed, but rather a long-term performance monitoring system is established to continuously track and quantify the effectiveness of the parameter configuration in the actual operating environment.

[0100] This specific implementation is executed by the performance monitoring module of the main controller. The monitoring object during execution based on the performance monitoring model is all subsequent read / write operations logically categorized as "same type of data." "Same type of data" can be defined as data sharing the same namespace, stream identifier, or mapped to the same set of physical blocks. The error correction performance metric is defined as a multi-dimensional quantized dataset. Its collection sources and calculation methods include: First, in each read operation, recording the result of error correction decoding on the data read using the address offset parameter. Core metrics include decoding success / failure flags, the number of iterations consumed for successful decoding, the estimated number of error bits (RBER) of the original data before decoding, and error pattern characteristics detected in the checksum calculation. Second, in write operations, recording the environmental parameters during writing. These environmental parameters include the number of erase / write operations on the written physical unit, operating temperature, etc., and can serve as auxiliary variables for performance trend analysis. The performance monitoring module collects the above-mentioned raw data at a predetermined sampling period or per read / write event and calculates aggregated performance metrics, such as the average decoding success rate, average number of iterations, and error rate trend slope of the same type of data within the most recent time window. The above metrics are stored in a structured manner in a cyclic performance log.

[0101] When the error correction performance metric falls below a preset performance threshold for multiple consecutive operating cycles, a recalculation and adaptation process for the address offset parameters of the same type of data is triggered. This recalculation and adaptation process is defined as the performance degradation judgment and re-optimization triggering phase. The data processing logic of the aforementioned performance degradation judgment and re-optimization triggering phase is as follows: by analyzing accumulated time-series performance data, it intelligently identifies that the effectiveness of the currently deployed address offset parameters is continuously decreasing, and automatically initiates a new round of parameter optimization. The preset performance threshold is a threshold value set for one or more of the error correction performance metrics, for example, requiring an average decoding success rate of not less than 99.9%, or an average number of iterations not exceeding a certain limit. The multiple consecutive operating cycles can avoid misjudgments caused by a single accidental read interference or instantaneous noise, ensuring the robustness of the triggering decision. The performance analysis algorithm periodically (e.g., after completing N reads of the same type of data) checks the cyclic performance log.

[0102] Furthermore, the algorithm calculates the average or trend of various performance indicators over the most recent M consecutive monitoring cycles and compares them with their respective preset performance thresholds. If the algorithm determines that one or more key performance indicators (such as decoding success rate) are consistently below their corresponding thresholds within the aforementioned multiple operation cycles, an internal trigger signal is generated. This internal trigger signal is essentially a new round of "error correction capability adaptation instructions" for specific data of the same type. Its objective is the same as the initial instruction defined above, but the triggering reason changes from periodic maintenance or external commands to adaptive requirements based on performance degradation. The trigger signal is transmitted to the scheduling management unit of the main controller, which then arranges the execution of a re-adaptation task for the same type of data.

[0103] The read / write operation offset configuration for the same type of data is updated using the recalculated address offset parameters. This update process is defined as the dynamic refresh phase of the configuration. The core data processing logic of the dynamic refresh phase is to execute a new round of parameter optimization process triggered for a specific data category, and to formally update the system configuration with the new parameters obtained from the optimization, replacing the old parameters that may have become invalid, thereby completing the self-correction of the strategy.

[0104] In the specific implementation process, the complete "error correction capability adaptation" process defined above is reused and may be enhanced. Using the aforementioned similar data as the target, in response to the generated internal triggering instructions, a trial address offset parameter is reacquired or generated, data is read, errors are analyzed, intelligent segmentation and decoding based on the latest error distribution characteristics are performed, and it is determined whether error correction under the new parameters is successful. If the above round of re-adaptation is successful, the same logic as the successful adaptation is followed, and the output result, i.e., the recalculated address offset parameter, is written to the configuration file corresponding to the similar data, overwriting the previously stored old parameters that have been detected as having insufficient performance. This update operation involves write operations to the non-volatile configuration memory. After the update is completed, all subsequent standard read and write operations on the same similar data will automatically use the newly effective address offset parameter for address offset programming and reading, thereby realizing online and dynamic optimization of the error correction strategy, enabling the system to continuously adapt to the characteristics changes of the flash memory medium over time (such as increased wear and tear, changes in interference patterns). If re-adaptation fails, an alarm can be recorded, and higher-level maintenance operations (such as data migration, block retirement) may be triggered.

[0105] It should be noted that the above examples are only for understanding this application and do not constitute a limitation on the adaptation method of the error correction capability of this application. Any simple modifications based on this technical concept are within the protection scope of this application.

[0106] This application provides an adaptation device for error correction capability, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the error correction capability adaptation method in the first embodiment described above.

[0107] The following is for reference. Figure 7 The diagram illustrates a structural schematic of an adapter device suitable for implementing the error correction capabilities of embodiments of this application. The adapter device for error correction capabilities in embodiments of this application may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Description), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 7 The illustrated error correction capability adapter is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of this application.

[0108] like Figure 7 As shown, the error correction capability adapter may include a processing device 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 1002 or a program loaded from storage device 1003 into random access memory (RAM) 1004. RAM 1004 also stores various programs and data required for the operation of the error correction capability adapter. The processing device 1001, ROM 1002, and RAM 1004 are interconnected via bus 1005. Input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems can be connected to I / O interface 1006: input devices 1007 including, for example, touchscreens, touchpads, keyboards, mice, image sensors, microphones, accelerometers, gyroscopes, etc.; output devices 1008 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 1003 including, for example, magnetic tapes, hard disks, etc.; and communication devices 1009. Communication device 1009 allows the error-correcting adapter to communicate wirelessly or wiredly with other devices to exchange data. Although the figures show adapters with various error-correcting capabilities, it should be understood that it is not required to implement or possess all of the systems shown. More or fewer systems may be implemented alternatively.

[0109] Specifically, according to the embodiments disclosed in this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments disclosed in this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from ROM 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this application.

[0110] The error correction capability adaptation device provided in this application, employing the error correction capability adaptation method in the above embodiments, can solve the technical problem of low error correction efficiency caused by existing error correction methods neglecting the physical distribution and address mapping of errors. Compared with the prior art, the beneficial effects of the error correction capability adaptation device provided in this application are the same as those of the error correction capability adaptation method provided in the above embodiments, and other technical features in this error correction capability adaptation device are the same as those disclosed in the previous embodiment method, and will not be repeated here.

[0111] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0112] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0113] This application provides a storage medium, which is a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, which are used to execute the error correction capability adaptation method in the above embodiments.

[0114] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, system, or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0115] The aforementioned computer-readable storage medium may be included in an adapter device with error correction capabilities; or it may exist independently and not assembled into an adapter device with error correction capabilities.

[0116] The aforementioned computer-readable storage medium carries one or more programs, which, when executed by an error correction capability adaptation device, enable the error correction capability adaptation device to implement the technical content of the error correction capability adaptation method embodiment shown above.

[0117] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a Local Area Network (LAN) or a Wide Area Network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0118] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0119] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0120] The readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the above-described error correction capability adaptation method. This solves the technical problem of low error correction efficiency caused by existing error correction methods neglecting the physical distribution and address mapping of errors. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as the beneficial effects of the error correction capability adaptation method provided in the above embodiments, and will not be repeated here.

Claims

1. A method for adapting error correction capabilities, characterized in that, The method for adapting the error correction capability includes the following steps: In response to the error correction capability adaptation instruction, the address offset parameter of the memory bank is obtained based on the error correction capability adaptation instruction; Multiple data blocks are read from the memory according to the address offset parameter; Among the plurality of data blocks, erroneous data exceeding the capacity of a single error correction processing unit is identified; Based on the mapping relationship between the physical distribution characteristics of the erroneous data and the logical address, the erroneous data is divided into multiple erroneous subsets, and the multiple erroneous subsets are assigned to multiple error correction processing units for parallel error correction and decoding. Based on the decoding results of each error correction processing unit, it is determined whether the error data has been successfully corrected; If the error correction is successful, the address offset parameter will be set to the address offset configuration for reading and writing the same type of data.

2. The method for adapting error correction capabilities as described in claim 1, characterized in that, Before the step of responding to the error correction capability adaptation instruction and obtaining the address offset parameter of the memory bank based on the error correction capability adaptation instruction, the method further includes: In response to a target data write command, the data length of the target data is determined; Calculate the difference between the data length and the preset error correction data length, and generate an initial address offset parameter based on the difference; Based on the initial address offset parameter, adjust the starting write address of the target data in the memory. The target data is written to the storage at the adjusted starting write address.

3. The method for adapting error correction capabilities as described in claim 2, characterized in that, The step of adjusting the starting write address of the target data in the memory based on the initial address offset parameter includes: Obtain the historical error correction success rate and current operating performance parameters of the storage unit; A weighted evaluation value is calculated based on the historical error correction success rate and the current working performance parameters, and the initial address offset parameter is dynamically optimized based on the weighted evaluation value to obtain the optimized address offset parameter. Based on the optimized address offset parameters, the starting write address of the target data is determined.

4. The method for adapting error correction capabilities as described in claim 2, characterized in that, The step of writing the target data to the memory bank according to the adjusted starting write address includes: The target data is split into multiple consecutive data segments; Generate an address offset sequence based on the address offset parameters; According to the address offset sequence, the starting write address of each data segment is determined sequentially; Each of the data segments is written to the memory at the determined starting write address.

5. The method for adapting error correction capabilities as described in claim 4, characterized in that, The step of writing each of the data segments into the memory bank according to the determined starting write address includes: The end address is calculated based on the start write address and the length of the data segment, and it is determined whether both the start write address and the end address are within the effective addressing range of the memory. If so, continue writing the data segment based on the starting write address; If not, the write process is interrupted, the address out-of-bounds information is recorded, and a preset address out-of-bounds handling strategy is executed. The preset address out-of-bounds handling strategy includes address correction or error report generation operations.

6. The method for adapting error correction capabilities as described in claim 1, characterized in that, Based on the mapping relationship between the physical distribution characteristics and logical addresses of the erroneous data, the steps of segmenting the erroneous data into multiple erroneous subsets and assigning these subsets to multiple error correction processing units for parallel error correction and decoding include: Analyze the error patterns and distribution characteristics of the erroneous data; Based on the distribution characteristics, the erroneous data is divided into multiple erroneous subsets; The real-time load rate of each error correction processing unit is polled, and each error subset is assigned to an error correction processing unit whose real-time load rate is less than a first load threshold for parallel processing.

7. The method for adapting error correction capabilities as described in claim 6, characterized in that, The step of polling the real-time load rate of each error correction processing unit and allocating each error subset to error correction processing units with a real-time load rate less than a first threshold for parallel processing includes: Monitor the processing progress of each error correction processing unit on the assigned subset of errors; If the processing progress of the error correction processing unit is detected to be less than a preset progress threshold, or the real-time load rate is greater than a second load threshold, then the subset of errors that have not been decoded by the error correction processing unit will be redistributed to the error correction processing unit with the lowest current load rate, wherein the second load threshold is greater than or equal to the first load threshold.

8. The method for adapting error correction capability as described in claim 1, characterized in that, The method for adapting the error correction capability also includes: The error correction performance metrics of similar data that are read and written using the address offset parameter are monitored. When the error correction performance index is lower than the preset performance threshold for multiple consecutive operation cycles, a recalculation and adaptation process for the address offset parameters of the same type of data is triggered. The read / write operation offset configuration for the same type of data is updated using the recalculated address offset parameters.

9. An adapter device with error correction capability, characterized in that, The error correction capability adaptation device stores a computer program, which, when executed by a processor, implements the error correction capability adaptation method according to any one of claims 1-8.

10. A storage medium, characterized in that, The storage medium stores a computer program, which, when executed by a processor, implements the adaptation method for error correction capability as described in any one of claims 1-8.

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