GPU-oriented integer division hardware acceleration method, electronic equipment and storage medium

Abstract

The invention relates to the field of chip design, in particular to a GPU-oriented integer division hardware acceleration method, electronic equipment and a storage medium, and the method comprises the steps: configuring a trial quotient hardware circuit and a result correction hardware circuit, and respectively obtaining a trial quotient function and a correction function of the trial quotient hardware circuit and the result correction hardware circuit; after an estimation quotient q is obtained through a Newton iteration algorithm, two trial quotient functions and one correction function are called in sequence, and then a final integer quotient is obtained. Compared with the prior art, the calculation speed is greatly improved, the integer division method is no longer the bottleneck of performance, the hardware circuit occupies a small hardware area, the throughput of the integer division method is greatly improved, and the good universality of the GPU is kept.

Description

Technical Field

[0001] This invention relates to the field of chip design, and in particular to a hardware acceleration method for integer division for GPUs, an electronic device, and a storage medium. Background Technology

[0002] Integer division instructions have significantly higher latency than other arithmetic instructions. When executed alongside other instructions, they are difficult to pipeline, reducing instruction throughput. Therefore, integer division instructions lead to more complex pipeline control logic, and their complete implementation occupies more chip area. Furthermore, the application scenarios for integer division in scientific computing are significantly fewer than those for integer addition and multiplication. Therefore, GPUs prioritizing high instruction throughput generally do not include integer division instructions in their cores, opting instead for software implementation.

[0003] Currently, the most commonly used integer division method in GPUs is the one proposed in "Software Integer Division," published by Thomas L. Rodeheffer in 2008. This method, based on Newton's iteration, designs an efficient software algorithm for integer division. It can be roughly divided into four steps: estimating the initial value of the reciprocal, using integer Newton iteration to reduce the estimation error of the reciprocal, using trial division to find the exact quotient, and handling special values. Because this paper was published relatively early, and GPUs based on SIMT were not yet widespread, this method does not take into account the weakness of GPU branch instructions. It requires multiple branch instructions to implement. When integer division is infrequent, GPUs can effectively mask the latency of branch instructions by switching thread groups. However, when encountering AI frameworks that heavily utilize integer division, such as Baidu's PaddlePaddle, the latency of branch instructions cannot be masked by warp scheduling. This latency leads to performance degradation, especially in applications requiring a large number of integer division operations, where this performance degradation becomes more pronounced, making integer division a performance bottleneck. Summary of the Invention

[0004] To address the aforementioned technical problems, the present invention adopts the following technical solution: a hardware acceleration method for integer division on GPUs, comprising the following steps: configuring a trial quotient hardware circuit, wherein the inputs of the trial quotient hardware circuit are the dividend x, the divisor y, and the estimated quotient q, and the relationship between x, y, and q satisfies: when xq×y≥y, the estimated quotient q is updated to q+1 and output; otherwise, q is output; configuring two types of result correction hardware circuits, wherein the first type is an unsigned correction hardware circuit, the inputs of which are the x, y, and the q output by the trial quotient hardware circuit, wherein when x and y satisfy: when y=0, an invalid value is output; otherwise, q is output; wherein the second type is a signed correction. The hardware circuit includes a signed correction hardware circuit whose inputs are x, y, and the output q of the trial quotient hardware circuit. The signed correction hardware circuit converts the value of q to an integer to obtain q′, and obtains the XOR value sign of y and x. When sign is not 0, the value of q′ is updated to -q′; when y = 0, the value of q′ is updated to the invalid value. The behavior and function of the trial quotient hardware circuit, the unsigned correction hardware circuit, and the signed correction hardware circuit are described in code and encapsulated as a trial quotient function, an unsigned correction function, and a signed correction function, respectively. After obtaining the estimated quotient q through Newton's iterative algorithm, the trial quotient function is called twice and a correction function of one type is called once in sequence to obtain the final integer quotient.

[0005] Furthermore, the present invention also provides a non-transitory computer-readable storage medium storing at least one instruction or at least one program segment, wherein the at least one instruction or the at least one program segment is loaded and executed by a processor to implement the above-described method.

[0006] In addition, the present invention provides an electronic device including a processor and the aforementioned non-transitory computer-readable storage medium.

[0007] The present invention has at least the following beneficial effects:

[0008] This invention provides a hardware acceleration method, electronic device, and storage medium for integer division on GPUs. It configures a trial quotient hardware circuit and a result correction hardware circuit, and obtains the trial quotient function and correction function of these circuits respectively. After obtaining the estimated quotient q using Newton's iterative algorithm, the trial quotient function is called twice and the correction function is called once to obtain the final integer quotient. Since the trial quotient and correction steps rely on the configured hardware circuit, the calculation speed is significantly improved, making integer division no longer a performance bottleneck. Furthermore, the hardware circuit occupies a very small hardware area, which not only greatly improves the throughput of integer division but also maintains the good versatility of GPUs. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a flowchart of a GPU-oriented integer division hardware acceleration method provided in an embodiment of the present invention. Detailed Implementation

[0011] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0012] Unless otherwise defined, all technical and scientific terms used in the embodiments of this invention have the same meaning as commonly understood by those skilled in the art.

[0013] Please see Figure 1 The diagram illustrates a hardware acceleration method for integer division on a GPU according to an embodiment of the present invention. The method includes the following steps:

[0014] S100, Configure the trial quotient hardware circuit. The inputs of the trial quotient hardware circuit are the dividend x, the divisor y, and the estimated quotient q. The relationship between x, y, and q satisfies the following: when xq×y≥y, the estimated quotient q is updated to q+1 and output; otherwise, q is output.

[0015] The estimated quotient q is obtained through Newton's iteration algorithm. Specifically, the traditional Newton's iteration algorithm includes the following steps: estimating the initial value of the reciprocal, integer Newton iteration, calculating the quotient, calculating the remainder, first trial division, second trial division, and correcting the result. The estimated quotient q is the result obtained from the quotient calculation step. The hardware acceleration method provided in this embodiment accelerates the three steps of calculating the remainder, the first trial division, the second trial division, and correcting the division by zero in the Newton's iteration algorithm.

[0016] In this context, both the dividend x and the divisor y are specified by the user.

[0017] In one embodiment, the trial quotient hardware circuit includes a multiplier, a subtractor, a first comparator, an adder, and a first multiplexer; wherein: the multiplier is used to calculate the product of y and q and output the result q×y. The subtractor is used to calculate x minus the output result of the multiplier. The first comparator is used to compare the output result of the subtractor with the magnitude of y; when the output result of the subtractor is greater than or equal to y, it outputs a high level; otherwise, it outputs a low level. The adder is used to output the result q+1. The first multiplexer is used to output the output result of the adder when the first comparator outputs a high level; and to output q when the first comparator outputs a low level. It should be noted that in this trial quotient hardware circuit, only the multiplier, subtractor, comparator, adder, and multiplexer are included. These components are all existing components inside the GPU, and no new components need to be added; only new connections are needed, resulting in a very small increase in chip area. The speed of hardware implementation of the remainder and the trial quotient is significantly improved compared to the original software implementation.

[0018] Other hardware circuits used to implement the functions of the trial hardware circuit also fall within the protection scope of this invention.

[0019] S200, configure two types of result correction hardware circuits. The first type is an unsigned correction hardware circuit, whose inputs are x, y, and q output by the trial quotient hardware circuit. When x and y satisfy: when y = 0, output an invalid value; otherwise, output q. The second type is a signed correction hardware circuit, whose inputs are x, y, and q output by the trial quotient hardware circuit. The signed correction hardware circuit converts the value of q to an integer to obtain q′, obtains the XOR value sign of y and x, and updates the value of q′ to -q′ when sign is not 0; when y = 0, updates the value of q′ to the invalid value.

[0020] The unsigned correction hardware circuit refers to the circuit used to correct for cases where the divisor is zero, and the data type it corrects is an unsigned integer. An unsigned integer is a data type used only to represent non-negative integers.

[0021] The signed correction hardware circuit is used to correct the sign of the quotient and whether the quotient is 0. The data type it corrects is a signed integer. A signed integer is a data type used to represent positive, negative, or 0 numbers.

[0022] In one embodiment, the unsigned correction hardware circuit includes a second comparator, a first inverter, and a second multiplexer; wherein: the second comparator is used to compare the relationship between y and 0, outputting a high level when y equals 0; otherwise, outputting a low level. The first inverter is used to invert the bits of y. The second multiplexer is used to output the output of the first inverter when the second comparator outputs a high level; and to output q when the second comparator outputs a low level. It should be noted that this unsigned correction hardware circuit only includes a comparator, an inverter, and a multiplexer. Similarly, these components are all existing components inside the GPU; therefore, no new components need to be added, only new connections are needed, resulting in a very small increase in chip area. Furthermore, the speed of hardware implementation of unsigned correction is significantly improved compared to the original software implementation.

[0023] Other hardware circuits used to implement the unsigned correction hardware circuit function also fall within the protection scope of this invention.

[0024] In one embodiment, the signed correction hardware circuit includes an XOR gate, a third comparator, a fourth comparator, and a second inverter. The XOR gate outputs 0 when the signs of the inputs y and x are the same, and outputs 1 when the signs of the inputs y and x are different. The third comparator updates the value of q′ to -q′ when the output of the XOR gate is not equal to 0. The second inverter inverts the bits of y. The fourth comparator updates the value of q′ to the output of the second inverter when y equals 0. It should be noted that this signed correction hardware circuit only includes an XOR gate, a comparator, and an inverter. These components are already present in the GPU; no new components are needed, only new wiring is required, resulting in a very small increase in chip area. Furthermore, the speed of hardware implementation of signed correction is significantly improved compared to the original software implementation.

[0025] Other hardware circuits used to implement the signed correction hardware circuit function also fall within the protection scope of this invention.

[0026] It should be noted that the steps of S100 and S200 can be interchanged or executed simultaneously, and there is no restriction on the order of their implementation.

[0027] S300 controls the trial business hardware circuit, unsigned correction hardware circuit, and signed correction hardware circuit to perform specific calculation tasks through software code, and encapsulates the corresponding software code into trial business interface program, unsigned correction interface program, and signed correction interface program, respectively.

[0028] As an example, the pseudocode of the trial division program interface program is as follows: Define a trial division function, whose input parameters include q, x, and y. The function of the trial division function is to obtain the result of the hardware calculation of xq×y≥y. If the calculation result is true, return q-1; otherwise, return q.

[0029] It should be noted that hardware-accelerated computing tasks are implemented by calling the hardware through corresponding interface programs. This utilizes the characteristics of specific hardware, such as the parallel processing capabilities of GPUs, to improve computing efficiency.

[0030] S400: After obtaining the estimated quotient q through Newton's iterative algorithm, the trial quotient interface program is called twice and the correction interface program of a certain type is called once in sequence to obtain the final integer quotient.

[0031] It should be noted that the trial division hardware circuit replaces the purely software-implemented steps of finding the remainder and trial division in the original Newton's iterative algorithm. Similarly, the result correction hardware circuit replaces the purely software-implemented step of correcting the result in the original Newton's iterative algorithm. Therefore, the steps of the original Newton's iterative algorithm are updated in this embodiment of the invention as follows: estimating the initial value of the reciprocal, performing integer Newton iterations, finding the quotient, calling the trial division interface program twice for hardware-accelerated trial division, and calling a correction interface program of a certain type once for hardware-accelerated result correction.

[0032] In one implementation, when the user specifies unsigned, a type of correction function called is the unsigned correction interface program.

[0033] In one implementation, when the user specifies it as signed, a type of correction function called is a signed correction interface program.

[0034] In one implementation, the invalid value is the value obtained by inverting the bits of y. Configuring this invalid value as the bit-inverted value of y does not introduce other complex circuit components, resulting in a simple structure and logic, and reducing the area of ​​the hardware circuit. Other types of invalid values ​​also fall within the protection scope of this invention.

[0035] It should be noted that other circuits used to separately implement the trial quotient hardware circuit and the result correction hardware circuit, or other circuits used to simultaneously implement the trial quotient and the result correction through a single hardware circuit, also fall within the protection scope of this invention.

[0036] As an example, for ease of understanding, let's take the input data x = 1023U, y = 17U, where "U" indicates that x and y are both 32-bit unsigned integers, and the task is to calculate q = x / y. Using the Newton-Raphson iteration algorithm provided by this invention: First, estimate the initial value of the reciprocal as 252645104U; second, use integer Newton iteration to obtain 252645135U; third, calculate the quotient to obtain 60U; fourth, obtain 60U by calling the trial quotient interface program; fifth, obtain 60U by calling the trial quotient interface program a second time; sixth, obtain 60U by calling the unsigned correction interface program, which is the final integer quotient of 60.

[0037] In summary, this invention provides a hardware acceleration method for integer division on GPUs. It configures a quotient calculation hardware circuit and a result correction hardware circuit, and obtains the quotient calculation function and correction function of these two circuits respectively. After obtaining the estimated quotient q using Newton's iterative algorithm, the quotient calculation function is called twice and the correction function is called once to obtain the final integer quotient. Since the quotient calculation and correction steps rely on hardware circuitry, and this hardware circuitry can be implemented using components already available in the GPU for basic arithmetic operations, the added hardware area is only the wiring, resulting in a very small hardware footprint while significantly increasing computational speed, thus eliminating integer division as a performance bottleneck. Furthermore, the added instructions are very simple and have no impact on the instruction execution pipeline, not only greatly improving the throughput of integer division but also maintaining the good versatility of the GPU.

[0038] Embodiments of the present invention also provide a non-transitory computer-readable storage medium that can be disposed in an electronic device to store at least one instruction or at least one program related to implementing a method in the method embodiments, wherein the at least one instruction or the at least one program is loaded and executed by the processor to implement the method provided in the above embodiments.

[0039] Embodiments of the present invention also provide an electronic device, including a processor and the aforementioned non-transitory computer-readable storage medium.

[0040] Embodiments of the present invention also provide a computer program product including program code, which, when the program product is run on an electronic device, causes the electronic device to perform the steps of the methods described above in various exemplary embodiments of the present invention.

[0041] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is used as an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0042] While specific embodiments of the invention have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the invention. The scope of this invention is defined by the appended claims.

Claims

1. A hardware acceleration method for integer division on GPUs, characterized in that, The method includes the following steps: Configure a trial quotient hardware circuit. The inputs of the trial quotient hardware circuit are the dividend x, the divisor y, and the estimated quotient q. The relationship between x, y, and q satisfies the following: when xq×y≥y, the estimated quotient q is updated to q+1 and output. Otherwise, output q; Two types of result correction hardware circuits are configured. The first type is an unsigned correction hardware circuit, whose inputs are x, y, and q output by the trial quotient hardware circuit. When x and y satisfy the following conditions: when y = 0, an invalid value is output; otherwise, q is output. The second type is a signed correction hardware circuit, whose inputs are x, y, and q output by the trial quotient hardware circuit. The signed correction hardware circuit converts the value of q to an integer to obtain q′, obtains the XOR value sign of y and x, and updates the value of q′ to -q′ when sign is not 0; when y = 0, the value of q′ is updated to the invalid value. Describe the behavior and function of the trial division hardware circuit, the unsigned correction hardware circuit, and the signed correction hardware circuit using code, and encapsulate them as trial division function, unsigned correction function, and signed correction function, respectively. After obtaining the estimated quotient q through Newton's iterative algorithm, the trial quotient function is called twice and a correction function of a certain type is called once in sequence to obtain the final integer quotient.

2. The method according to claim 1, characterized in that, When the user specifies unsigned, the type of correction function called is the unsigned correction function.

3. The method according to claim 1, characterized in that, When the user specifies that it is signed, the type of correction function called is the signed correction function.

4. The method according to claim 1, characterized in that, The invalid value is the value obtained by inverting the bits of y.

5. The method according to claim 1, characterized in that, The prototype hardware circuit includes a multiplier, a subtractor, a first comparator, an adder, and a first multiplexer; wherein: The multiplier is used to calculate the product of y and q and output the result of q×y; The subtractor is used to calculate the value of x minus the output of the multiplier; The first comparator is used to compare the output of the subtractor with the magnitude of y. When the output of the subtractor is greater than or equal to y, it outputs a high level; otherwise, it outputs a low level. The adder is used to output the result of q+1; The first multiplexer is used to output the output result of the adder when the first comparator outputs a high level, and to output q when the first comparator outputs a low level.

6. The method according to claim 1, characterized in that, The unsigned correction hardware circuit includes a second comparator, a first inverter, and a second multiplexer; wherein: The second comparator is used to compare the relationship between y and 0. When y equals 0, it outputs a high level; otherwise, it outputs a low level. The first inverter is used to invert the y-bit sequence; The second multiplexer is used to output the output result of the first inverter when the second comparator outputs a high level, and to output q when the second comparator outputs a low level.

7. The method according to claim 1, characterized in that, The signed correction hardware circuit includes an XOR gate, a third comparator, a fourth comparator, and a second inverter, wherein: The XOR gate is used to output 0 when the signs of the input y and x are the same, and to output 1 when the signs of the input y and x are different; The third comparator is used to update the value of q′ to -q′ when the output of the XOR gate is not equal to 0; The second inverter is used to invert the y-bit sequence; The fourth comparator is used to update the value of q′ to the output of the second inverter when y equals 0.

8. A non-transitory computer-readable storage medium, wherein the storage medium stores at least one instruction or at least one program segment, characterized in that, The at least one instruction or the at least one program segment is loaded and executed by the processor to implement the method as described in any one of claims 1-7.

9. An electronic device, characterized in that, Includes a processor and the non-transitory computer-readable storage medium as described in claim 8.

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