VCSEL chip and manufacturing method thereof

Abstract

The embodiment of the invention relates to a VCSEL chip and a manufacturing method thereof, and the chip comprises a plurality of light-emitting areas, each light-emitting area is provided with a same or different number of light-emitting holes; the at least two conductive structures are positioned on one side of the light-emitting area; the number of the light-emitting holes in each light-emitting area is related to the length of the conductive structure in the horizontal direction. On one hand, the edge effect is reduced by increasing the number of the edges; and on the other hand, the current injection uniformity is improved by increasing the number of the bonding pads.

Description

Technical Field

[0001] This application relates to the field of semiconductor laser technology, and in particular to a VCSEL chip and its manufacturing method. Background Technology

[0002] In recent years, with the development of LiDAR technology, vertical cavity surface-emitting laser (VCSEL) array light sources have attracted increasing attention in the LiDAR application market due to their advantages of low manufacturing cost, small temperature drift coefficient, and ease of two-dimensional integration.

[0003] However, while VCSEL arrays can achieve higher power density and lower divergence angles to meet the development needs of long-range lidar applications, current conventional multi-aperture array designs, often with high aspect ratios, exhibit a significant "edge effect," where the current density at the edges is higher than at the center.

[0004] 1. Current accumulation at the edge of the metal layer: The injection of a single Pad causes current lines to "accumulate" at the edge of the finite metal layer, with a higher density than in the central region;

[0005] 2. Current path impedance difference: The edge emitter has the advantage of low inductance and low resistance transient path, as well as local congestion caused by insufficient current diffusion speed, and becomes the area with the highest current density. Summary of the Invention

[0006] Therefore, it is necessary to provide a VCSEL chip and its manufacturing method to address the aforementioned technical problems and overcome the issue of uneven current distribution.

[0007] In a first aspect, this application provides a VCSEL chip, comprising:

[0008] Multiple light-emitting areas, each of which has the same or different number of light-emitting holes;

[0009] At least two conductive structures are located on one side of the light-emitting region;

[0010] The number of light-emitting holes in each of the light-emitting regions is related to the length of the conductive structure in the horizontal direction.

[0011] In one possible embodiment, the number of the conductive structures is multiple.

[0012] In one possible embodiment, the number of conductive structures is three.

[0013] In one possible embodiment, the conductive structures are of the same size.

[0014] In one possible embodiment, the conductive structures have different dimensions.

[0015] In one possible embodiment, the size of the conductive structure on the side of the light-emitting region near the edge of the plurality of light-emitting regions is smaller than the size of the conductive structure on the side of the light-emitting region located in the middle region.

[0016] In one possible embodiment, the number of light-emitting holes in the light-emitting region is positively correlated with the length of the conductive structure in the horizontal direction.

[0017] In one possible embodiment, the spacing between two adjacent light-emitting regions is equal.

[0018] In one possible embodiment, the spacing is 5 μm.

[0019] Secondly, this application also provides a method for manufacturing a VCSEL chip, the method comprising:

[0020] A VCSEL chip is provided, the VCSEL chip comprising a substrate, a bottom mirror structure, an active layer and a top mirror structure stacked sequentially.

[0021] Multiple vias are formed on the VCSEL chip to create multiple light-emitting regions in the VCSEL chip; wherein each light-emitting region has the same or different number of light-emitting vias;

[0022] An electrode is formed within each of the aforementioned vias;

[0023] Multiple conductive structures are formed on the top reflector structure, and each conductive structure is connected to the electrode; wherein the number of light-emitting holes in each light-emitting region is related to the length of the conductive structure in the horizontal direction.

[0024] In one possible embodiment, the number of conductive structures is three.

[0025] In one possible embodiment, the conductive structures are of the same size.

[0026] The aforementioned VCSEL chip and its manufacturing method involve setting the VCSEL chip into multiple light-emitting regions, each of which has the same or different number of light-emitting holes; and setting at least two conductive structures on one side of each light-emitting region; wherein the number of light-emitting holes in each light-emitting region is related to the length of the conductive structure in the horizontal direction. This application can reduce the edge effect of the VCSEL chip and improve the current injection uniformity. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the structure of an existing VCSEL chip;

[0028] Figure 2This is a schematic diagram of the structure of a VCSEL chip according to one embodiment of this application;

[0029] Figure 3 for Figure 2 A top view of a VCSEL chip is shown.

[0030] Figure 4 This is a top view of another VCSEL chip in one embodiment of this application;

[0031] Figure 5 This is a schematic flowchart of a VCSEL chip manufacturing method according to an embodiment of this application;

[0032] Figure 6 To Figure 5 This is a schematic diagram of the structure of a VCSEL chip after vias are opened in a VCSEL chip manufacturing method.

[0033] Figure 7 To Figure 6 The diagram shows the structure of the VCSEL chip after the electrodes and pads are formed.

[0034] The objectives, features, and advantages of this invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0036] It is understood that the terms "first," "second," etc., used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first client may be referred to as a second client, and similarly, a second client may be referred to as a first client.

[0037] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. "Multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. "Several" means at least one, such as one, two, etc., unless otherwise explicitly specified.

[0038] like Figure 1As shown, a typical VCSEL chip 10 includes a substrate, a bottom mirror structure, an active layer, and a top mirror structure stacked sequentially. A pad 12 is usually placed on one side of either the top mirror structure 11 or the bottom mirror structure. However, single pad injection can lead to current lines "accumulating" at the edges of the finite metal layer, resulting in a higher density than the central region. Furthermore, there is a difference in current path impedance: the edge emitter, due to its low inductance and low resistance transient path advantage, and the local congestion caused by insufficient current diffusion speed, becomes the region with the highest current density.

[0039] Based on this, this application creatively proposes a VCSEL chip, aiming to solve the aforementioned technical problems.

[0040] Firstly, such as Figure 2 As shown, this application provides a VCSEL chip, comprising:

[0041] Multiple light-emitting areas 1, each of which is provided with the same or different number of light-emitting holes;

[0042] At least two conductive structures 2 are located on one side of the light-emitting area 1;

[0043] The number of light-emitting holes in each of the light-emitting regions 1 is related to the length of the conductive structure 2 in the horizontal direction.

[0044] The conductive structure 2 is a pad, which can be a P-type pad or an N-type pad. The material of the pad can be a highly conductive metal such as Au, Al, or Cu, and is not specifically limited here.

[0045] In one possible embodiment, the number of conductive structures 2 is multiple.

[0046] Optionally, the number of conductive structures 2 is three.

[0047] In one possible embodiment, the conductive structures 2 are of the same size, such as Figure 3 As shown, the horizontal length, width and thickness of the three conductive structures 2 are consistent, and the spacing between adjacent conductive structures 2 is equal. Each conductive structure 2 and its corresponding light-emitting area 1 are arranged symmetrically.

[0048] It is understandable that by setting the conductive structure 2 to be of the same size, the diffusion path of current from Pad to Emitter (light-emitting hole) can be made to be of equal length; the number of Emitter segments is the same, the total power consumption is close, and the heat distribution is uniform.

[0049] In one possible embodiment, the conductive structures 2 have different dimensions, such as Figure 4As shown, the horizontal length of each conductive structure 2 is designed differently, and the width and thickness can be kept consistent or adjusted synchronously according to actual needs. The size difference between the edge conductive structure and the middle conductive structure is controlled within a threshold range, which not only ensures the suppression effect of the edge effect, but also avoids current shunting imbalance caused by excessive size difference.

[0050] Optionally, the threshold range can be 5%-30%.

[0051] In one possible embodiment, the size of the conductive structure 2 located on the side of the light-emitting region 1 at the edge is smaller than the size of the conductive structure 2 located on the side of the light-emitting region 1 in the middle region.

[0052] For example, if three conductive structures 2 are set, the horizontal length of the edge conductive structures on both sides is 50% to 95% of the horizontal length of the middle conductive structure.

[0053] It should be understood that the above are merely examples and not limitations.

[0054] It is understandable that, due to the small size of the conductive structure 2 at the edge, the number of light-emitting holes in the light-emitting area 1 at the edge is small, resulting in a low total current carrying capacity. The size of the Pad at the edge is reduced, and its "low inductance advantage" is offset by "small Pad → high injection resistance", which forces the current to be diverted to the middle section (the Pad in the middle section has low resistance and attracts more current).

[0055] In one possible embodiment, the number of light-emitting holes in the light-emitting region 1 is positively correlated with the length of the conductive structure 2 in the horizontal direction.

[0056] It is understood that the longer the conductive structure 2 is in the horizontal direction, the more light-emitting holes there are in the light-emitting area 1 on the lower side of the conductive structure 2.

[0057] For example, if the length of the conductive structure 2 increases by 10μm in the horizontal direction, the number of light-emitting holes in the corresponding light-emitting area 1 increases by 5 to 20. The specific number ratio can be customized according to the rated current and light-emitting power requirements of the VCSEL chip, and no specific limit is made here.

[0058] It should be understood that the above are merely examples and not limitations.

[0059] In one possible embodiment, the conductive structure 2 can also be 4, 5, 6, etc., without being specifically limited here.

[0060] For example, when the number of conductive structures 2 exceeds 3, the spacing between adjacent conductive structures 2 remains equal, and the size of conductive structures 2 decreases in a gradient from the center of the chip to the edge, and the number of corresponding light-emitting holes also decreases in a gradient, so as to adapt to the current uniform shunting requirements of multiple regions.

[0061] It should be understood that the above are merely examples and not limitations.

[0062] In one possible embodiment, the spacing between two adjacent light-emitting regions 1 is equal.

[0063] It should be noted that the spacing design must take into account both the independence of the light-emitting area and the integration of the chip, to avoid the chip power density being reduced due to excessive spacing, or the light crosstalk and current crosstalk between adjacent light-emitting areas being caused by excessive spacing.

[0064] Optionally, the spacing is 5μm. This spacing design can ensure that the oxide confinement layer between adjacent light-emitting areas is completely closed, effectively isolating the current and light signals in adjacent areas, while reserving enough process windows for photolithography, avoiding the failure of photoresist in non-electroplated areas, and improving the yield of chip manufacturing.

[0065] It should be noted that each light-emitting region consists of a substrate, a bottom reflector structure, an active layer, and a top reflector structure. The layered structure of each light-emitting region is formed by stacked growth, and electrical independence is achieved only through vias and electrodes. The specific formation process can be found in the description of the VCSEL chip manufacturing method below. It will not be repeated here.

[0066] Secondly, such as Figure 5 As shown, this application also provides a method for manufacturing a VCSEL chip, which includes:

[0067] Step S201: Provide a VCSEL chip.

[0068] The VCSEL chip includes a substrate, a bottom mirror structure, an active layer, and a top mirror structure stacked sequentially.

[0069] For example, the substrate material includes, but is not limited to, GaAs, InP, Si, etc.

[0070] The top reflector structure contains several oxide confinement layers.

[0071] For example, the oxide confinement layer can be made of AlGaAs material with an Al content of more than 90%, and oxide pores are formed by a wet oxidation process. The size of the oxide pores can be 5~20μm, which is used to confine the current and light field and improve the luminous efficiency.

[0072] It should be understood that the above are merely examples and not limitations.

[0073] In this embodiment, the bottom and top reflector structures may include films with periodically varying refractive indices to achieve efficient reflection or transmission of light within a specific wavelength range. The films with periodically varying refractive indices can be made of semiconductor materials, dielectric materials, metal-dielectric hybrid materials, etc. For example, the bottom reflector structure can be an N-type semiconductor layer, and the top reflector structure can be a P-type semiconductor layer. Alternatively, the bottom reflector structure can be a P-type semiconductor layer, and the top reflector structure can be an N-type semiconductor layer. Optionally, the materials of the N-type and P-type semiconductor layers can be, but are not limited to, GaAs, AlGaAs, etc. This is not a limitation; as long as the resonant cavity can be defined, it falls within the scope of this embodiment.

[0074] For example, the substrate can be a single-crystal GaAs substrate with a crystal orientation of (100) and a thickness of 100~300μm, which has good semiconductor epitaxial growth characteristics; both the bottom and top mirror structures adopt distributed Bragg reflectors (DBRs) made of AlGaAs material, wherein the bottom DBR has 20~35 pairs of layers and the top DBR has 15~25 pairs of layers, and high reflectivity for specific laser wavelengths is achieved through periodic changes in Al composition, with a reflectivity of over 99%; the active layer adopts a multi-quantum well structure, which is composed of alternating InGaAs potential wells and AlGaAs potential barriers, with 3~8 potential well layers.

[0075] It should be understood that the above are merely examples and not limitations.

[0076] Step S202: A plurality of vias are formed on the VCSEL chip to form a plurality of light-emitting regions in the VCSEL chip.

[0077] Each of the light-emitting regions is provided with the same or different number of light-emitting holes.

[0078] For example, vias can be created using deep ultraviolet lithography (DUV) combined with inductively coupled plasma etching (ICP). Positive photoresist is used, with a spin-coating thickness of 1~3μm and an exposure dose of 50~200mJ / cm². After development, an etching mask is formed. The etching gas for ICP etching is a Cl2 / BCl3 mixture with a gas flow ratio of 3:1~5:1, an etching power of 200~500W, and an etching depth of 2~5μm.

[0079] It should be understood that the above are merely examples and not limitations.

[0080] It should be noted that each of the vias exposes a portion of the bottom reflector structure. In other words, the via does not penetrate the VCSEL chip.

[0081] For example, such as Figure 6As shown, the via 170 passes through the top reflector structure 140 and the active layer 130 in sequence until it exposes part of the bottom reflector structure 120, that is, the bottom of the via 170 terminates at the upper half of the bottom reflector structure 120.

[0082] In other words, the via 170 does not penetrate the bottom reflector structure 120 and the substrate 110.

[0083] Step S203: An electrode is formed in the via.

[0084] Step S204: A plurality of conductive structures are formed on the top reflector structure, and each of the conductive structures is connected to the electrode.

[0085] The number of light-emitting holes in each light-emitting region is related to the length of the conductive structure in the horizontal direction.

[0086] In one possible embodiment, the number of the conductive structures is multiple.

[0087] Optionally, the number of conductive structures is three.

[0088] In one possible embodiment, the conductive structures are of the same size.

[0089] In one possible embodiment, the conductive structures have different dimensions.

[0090] In one possible embodiment, the size of the conductive structure located on the edge of the light-emitting area is smaller than the size of the conductive structure located on the middle region of the light-emitting area.

[0091] In one possible embodiment, the number of light-emitting holes in the light-emitting region is positively correlated with the length of the conductive structure in the horizontal direction.

[0092] For example, such as Figure 3 As shown, metal can be deposited inside the via to form an electrode 150 by electrode evaporation process, and then a conductive structure 160 can be formed on the electrode.

[0093] Optionally, the electrode 150 and the conductive structure 160 can be integrally formed or formed in stages; no specific limitation is made here.

[0094] Optionally, the conductive structure 160 is a pad.

[0095] In one possible embodiment, the spacing between two adjacent light-emitting regions is equal.

[0096] Optionally, the spacing is 5 μm.

[0097] It is understandable that the spacing between adjacent conductive structures 160 is 5µm. That is, the isolation region is set to 5µm. This isolation region forms a complete oxide layer through a wet oxidation process, which can completely isolate the current and light signals of adjacent light-emitting regions, so as to ensure that the oxide layer in this region is completely closed, and to reserve a process window for photoresist to block non-electroplated areas.

[0098] It is understood that the VCSEL chip and its manufacturing method provided in this embodiment, by setting the VCSEL chip as multiple light-emitting regions, each light-emitting region having the same or different number of light-emitting holes; and setting at least two conductive structures on one side of the light-emitting region; and the number of light-emitting holes in each light-emitting region being related to the horizontal length of the conductive structure, this application achieves uniform current injection across multiple regions through the differentiated design of multiple conductive structures, effectively suppressing the problems of current accumulation at the metal layer edges and current congestion at the edge emitter, effectively reducing edge effects, and improving current injection uniformity. Simultaneously, through the positive correlation design between the number of light-emitting holes and the length of the conductive structure, precise matching of current injection capability and light-emitting load is achieved, further improving the chip's luminous efficiency and power stability.

[0099] The foregoing disclosure provides illustrations and descriptions, but is not intended to be exhaustive or to limit the embodiments to the precise forms disclosed. Modifications and variations may be made in light of the foregoing disclosure or may be derived from practice of the embodiments. Furthermore, any embodiments described herein may be combined unless the foregoing disclosure expressly provides for reasons why one or more embodiments may not be combined.

Claims

1. A VCSEL chip, characterized in that, include: Multiple light-emitting areas, each of which has the same or different number of light-emitting holes; At least two conductive structures are located on one side of the light-emitting region; The number of light-emitting holes in each of the light-emitting regions is related to the length of the conductive structure in the horizontal direction.

2. The VCSEL chip according to claim 1, characterized in that, The number of the conductive structures is multiple.

3. The VCSEL chip according to claim 2, characterized in that, The number of conductive structures is three.

4. The VCSEL chip according to any one of claims 1-3, characterized in that, The conductive structures are all the same size.

5. The VCSEL chip according to any one of claims 1-3, characterized in that, The conductive structures have different dimensions.

6. The VCSEL chip according to claim 5, characterized in that, The size of the conductive structure on the side of the light-emitting region near the edge of the plurality of light-emitting regions is smaller than the size of the conductive structure on the side of the light-emitting region located in the middle region.

7. The VCSEL chip according to claim 1, characterized in that, The number of light-emitting holes in the light-emitting region is positively correlated with the length of the conductive structure in the horizontal direction.

8. The VCSEL chip according to claim 1 or 7, characterized in that, The spacing between two adjacent light-emitting regions is equal.

9. The VCSEL chip according to claim 8, characterized in that, The spacing is 5 μm.

10. A method for manufacturing a VCSEL chip, characterized in that, The method includes: A VCSEL chip is provided, the VCSEL chip comprising a substrate, a bottom mirror structure, an active layer and a top mirror structure stacked sequentially. Multiple vias are formed on the VCSEL chip to create multiple light-emitting regions in the VCSEL chip; wherein each light-emitting region has the same or different number of light-emitting vias; An electrode is formed within each of the aforementioned vias; Multiple conductive structures are formed on the top reflector structure, and each conductive structure is connected to the electrode; wherein the number of light-emitting holes in each light-emitting region is related to the length of the conductive structure in the horizontal direction.

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