Variable sampling rate interpolation filter based on FPGA

Abstract

The invention provides a variable sampling rate interpolation filter based on an FPGA, and the filter comprises an interpolation signal generation module which correspondingly generates an interpolation signal based on an obtained original signal and an interpolation factor L; the multiplication and addition unit generator correspondingly generates a filtering module based on the obtained filter order O, the filtering module comprises N cascaded multiplication and addition units, each multiplication and addition unit comprises an M-bit interpolation signal storage unit and a filtering coefficient storage unit, and N * M is greater than or equal to O; the filtering module receives one interpolation signal in every M clock periods, and enables each multiply-add unit to respectively and sequentially perform M times of cyclic multiply-add processing to correspondingly generate N intermediate signals; and the filtering output module is used for accumulating the N intermediate signals, correspondingly generating a filtering signal and outputting the filtering signal. According to the scheme, by arranging the multiply-add unit generator, the sampling rate can be automatically adjusted based on the actual application requirement, the sampling rate can meet the signal processing requirement, and sampling data redundancy caused by the too high sampling rate is avoided.

Description

Technical Field

[0001] This application relates to the field of electrical data processing technology, and in particular to a variable sampling rate interpolation filter based on FPGA. Background Technology

[0002] The sampling rate refers to the number of times a continuous-time signal (such as an analog signal) is sampled per unit of time, usually expressed as samples per second. The sampling rate determines the degree of time discretization of the signal, that is, the time resolution when discretizing a continuous signal into a digital signal. A higher sampling rate results in denser sampling points and higher approximate accuracy after discretization. If the sampling rate is insufficient, high-frequency signals may be distorted or cannot be recovered. According to the Nyquist sampling theorem, the sampling rate must be twice the highest frequency of the sampled signal to recover the original signal without distortion. Insufficient sampling rate leads to aliasing, causing high-frequency components to be incorrectly mapped to low-frequency regions. Conversely, an excessively high sampling rate results in redundant sampled data. Therefore, it is necessary to select an appropriate sampling rate based on different application scenarios.

[0003] In practical applications, sampling rate conversion is frequently encountered, requiring a digital system to operate at multiple sampling rates. For example, when transmitting a digital signal between two digital systems with independent clocks, the sampling frequency of the digital signal must be able to change according to the different clocks. Alternatively, when performing spectral analysis or encoding on non-stationary random signals, different sampling rates can be used for different signal segments based on their frequency components, thereby satisfying the Nyquist sampling theorem while minimizing the amount of data.

[0004] Increasing the sampling rate is generally achieved through interpolation, also known as digital upsampling, a common digital signal processing technique. Interpolation increases the sampling rate, making discrete signals closer to the original waveform of continuous signals. Interpolation can improve the performance of digital systems. The most common interpolation method is zero-point interpolation. As the name suggests, it involves inserting several zeros between every two original sample values ​​to increase the sampling rate of the digital signal. If the sampling rate is increased to L times the original signal sampling rate, L-1 zeros should be added between each pair of original samples, where L is called the interpolation factor. For example, for an interpolation operation with an interpolation factor of L=4, three times the number of zeros should be evenly inserted into the original signal. The signal spectrum after zero-placing will repeat at multiples of L in the frequency domain, producing high-frequency image components. Therefore, a low-pass filter is needed to eliminate image components outside the original signal spectrum, retaining only the effective frequency range of the original signal.

[0005] Filters used to increase the signal sampling rate are called interpolation filters. Interpolation filters typically employ an FIR (Finite Impulse Response) structure, providing accurate linear phase, avoiding signal distortion, and effectively suppressing high-frequency components in the interpolated signal. Traditional interpolation filters have a fixed hardware structure; once the circuit is designed, it can only increase the sampling rate by a fixed factor. Changing the sampling rate requires redesigning the entire interpolation filter circuit, resulting in poor flexibility, a cumbersome design process, and low efficiency. This is a significant problem, especially in applications requiring frequent changes to the signal sampling rate.

[0006] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0007] The purpose of this invention is to provide a variable sampling rate interpolation filter based on FPGA to meet the application requirements that require frequent changes in signal sampling rate.

[0008] To address the aforementioned problems, an FPGA-based variable sampling rate interpolation filter is provided, characterized by comprising: The interpolation signal generation module generates an interpolation signal based on the acquired original signal and the interpolation factor L. A multiply-accumulate unit generator generates a corresponding filtering module based on the obtained filter order O. The filtering module includes N cascaded multiply-accumulate units, each of which includes an interpolation signal storage unit with M storage bits and a filter coefficient storage unit with M storage bits, wherein N*M≥O. The filtering module is used to receive one interpolation signal every M clock cycles, and to make each multiply-accumulate unit perform M cyclic multiply-accumulate processes in sequence to generate N intermediate signals. The filtering output module is used to accumulate the N intermediate signals, generate a corresponding filtered signal, and output it.

[0009] In this technical solution, by setting up a multiply-accumulate unit generator, the sampling rate can be automatically adjusted based on actual application requirements. This ensures that the sampling rate meets the signal processing requirements without causing data redundancy due to excessively high sampling rates. A variable sampling rate interpolation filter on an FPGA is provided, which can achieve adaptive changes in the sampling rate without redesigning the filter structure.

[0010] Based on the obtained interpolation factor L and filter order O, a corresponding filtering module is generated. The generated filtering module includes N cascaded multiply-accumulate units. Each multiply-accumulate unit includes an interpolation signal storage unit with M storage bits and a filter coefficient storage unit with M storage bits, where M=L, N=ceil[O / L], and ceil[] represents rounding up. By making the number of cyclic multiply-accumulate operations of each multiply-accumulate unit equal to the sampling amplification factor, an optimal balance can be achieved between resource consumption and computational efficiency.

[0011] In the filtering module, the interpolation signal storage circuits of the N multiply-accumulate units are cascaded sequentially. Through this cascading arrangement, combined with the storage locations of the filter coefficients, the interpolation signal can be filtered to generate the desired filtered signal.

[0012] The difference signal generation module includes a raw signal module, an interpolation module, and a signal selection module. The raw signal module sequentially provides the raw signals, the interpolation module provides zero-value signals, and the input of the signal selection module is connected to the outputs of the raw signal module and the interpolation module, respectively. The signal selection module generates L interpolated signals by first selecting one raw signal and then selecting L-1 zero-value signals. By using the selective output of the selector to generate interpolated signals, a large amount of storage space can be avoided, saving FPGA device resources.

[0013] In the filtering module, the acquired filter coefficients are sequentially stored in each filter coefficient storage unit, and the remaining filter coefficient storage units are set to zero values; the number of filter coefficients is equal to the filter order 0. This specific coefficient storage method, combined with the zero-value design, allows this interpolation filter to automatically perform filtering processing on the interpolated signal using the zero-value interpolation method without the need for complex techniques.

[0014] The filtering module receives one interpolation signal every M clock cycles and stores them sequentially in the interpolation signal storage unit. After every M clock cycles, it shifts the interpolation signals in all the interpolation signal storage units one position to the right; the interpolation signal storage units that do not store any interpolation signals are set to zero. By employing a specific structure of the interpolation signal storage unit and data storage method, this interpolation filter can automatically perform filtering of the interpolation signals using the zero-value interpolation method without the need for complex methods. Each multiply-accumulate unit includes an interpolation signal storage unit with M storage bits, a filter coefficient storage unit with M storage bits, a multiplier, and an adder. In each multiply-accumulate unit, the multiplier is used to sequentially multiply one bit in the interpolation signal storage unit with the corresponding bit in the filter coefficient storage unit, and the adder is used to accumulate the result of each multiplication calculation to generate an intermediate signal.

[0015] The multiply-accumulate unit generator, based on the acquired interpolation factor L and the filter order O, activates the multiplier, adder, and storage unit within the FPGA to generate the corresponding filtering module. It can adaptively adjust the sampling rate of the interpolation filter based on user requirements.

[0016] The filter coefficients are generated using MATLAB or Python functions based on the interpolation factor L and the filter order O.

[0017] The signal selection module inputs an interpolation signal to the filtering module every M clock cycles.

[0018] Compared with the prior art, the beneficial effects of the present invention mainly include the following: It provides an interpolation filter on an FPGA that supports variable sampling rates. The filter structure supports variable sampling rate multiples and can automatically generate interpolation signals and multiply-accumulate units with specific structures, achieving adaptive changes in the sampling rate without redesigning the filter structure. In this technical solution, by setting a multiply-accumulate unit generator, the sampling rate can be automatically adjusted based on actual application requirements, ensuring that the sampling rate meets the signal processing requirements without causing excessive sampling rate redundancy. The structure is flexible and can meet the needs of complex application scenarios. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a block diagram of an interpolation filter (L=4, O=12) provided in this embodiment.

[0021] Figure 2 This is a block diagram of an interpolation signal generation module provided in this embodiment.

[0022] Figure 3 This is a block diagram of the multiply-accumulate unit structure provided in this embodiment.

[0023] Figure 4 This is a schematic diagram of the interpolation filter used in this embodiment to calculate the filtered signal y0.

[0024] Figure 5 The interpolation filter provided in this embodiment calculates the filtered signal y. 11 A schematic diagram.

[0025] Figure 6 This is a block diagram of an interpolation filter (L=6, O=12) provided in this embodiment 2.

[0026] Figure 7 This is a block diagram of an interpolation filter structure provided in Embodiment 3. Detailed Implementation

[0027] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the accompanying drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front, or back, are merely for reference to the accompanying drawings. Therefore, the directional terms used are for illustrative purposes and not for limiting the present invention.

[0028] The embodiments of this application will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this application to facilitate a better understanding of the application. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0029] The steps in the following embodiments do not correspond one-to-one with the contents of the invention.

[0030] Example 1 like Figure 1 The diagram shown is a block diagram of an interpolation filter structure provided in Embodiment 1 of the present invention. (Reference) Figure 1 This invention provides a variable sampling rate interpolation filter based on FPGA, comprising: The interpolation signal generation module generates an interpolation signal based on the acquired original signal and the interpolation factor L. The multiply-accumulate unit generator generates a corresponding filtering module based on the obtained filter order O. The filtering module includes N cascaded multiply-accumulate units. Each multiply-accumulate unit includes an interpolation signal storage unit with M storage bits and a filter coefficient storage unit with M storage bits, where N*M≥O. The filtering module is used to receive an interpolation signal every M clock cycles and make each multiply-accumulate unit perform M cyclic multiply-accumulate processes in sequence to generate N intermediate signals. The filter output module is used to accumulate N intermediate signals, generate a corresponding filtered signal, and output it.

[0031] Figure 2 This is a block diagram of an interpolation signal generation module provided in this embodiment. Figure 3 This is a block diagram of the multiply-accumulate unit structure provided in Embodiment 1. For details, refer to the reference... Figures 1 to 3 The interpolation filter consists of an interpolation signal generation module, a multiply-accumulate unit generator, a filter output module, and several multiply-accumulate units. The interpolation signal generation module comprises a raw signal module, an interpolation module, and a signal selection module, as detailed below. Figure 2 As shown; the original signal module is used to sequentially provide the original signals (i.e., x). （n） The interpolation module provides zero-value signals, and the input of the signal selection module is connected to the outputs of the original signal module and the interpolation module, respectively. The signal selection module generates L interpolation signals by first selecting one original signal and then selecting L-1 zero-value signals. The signal selection module inputs one interpolation signal to the filtering module every M clock cycles.

[0032] The multiply-accumulate unit generator, based on a preset or externally input sampling factor L and filter order O, can generate several multiply-accumulate units with a specific structure to form a filtering module. Specifically, the filtering module includes N cascaded multiply-accumulate units capable of performing M cyclic multiplications and additions, such that N*M≥O, meaning the product of the number of cyclic multiplications and additions for each multiply-accumulate unit and the number of multiply-accumulate units is greater than or equal to the filter order O (the filter order O equals the number of filter coefficients). This ensures that all filter coefficients are fully accommodated to satisfy the filtering formula: In the formula, Original signal, L represents the filtered signal, and L represents the interpolation factor.

[0033] The multiply-accumulate unit consists of an interpolation signal storage unit, a filter coefficient storage unit, a multiplier, and an adder, specifically as follows: Figure 3As shown. The interpolation signal storage unit stores the interpolation signal (set to 0 when not stored), and the filter coefficient storage unit stores the filter coefficients (set to 0 when not stored). The signal storage circuits of multiple multiply-accumulate units are connected end-to-end. The filtering module receives one interpolation signal every M clock cycles and stores it sequentially into the interpolation signal storage unit. After every M clock cycles, it shifts the interpolation signals in all interpolation signal storage units one position to the right. When an interpolation signal is shifted out of the interpolation signal storage unit of one multiply-accumulate unit, it is shifted into the interpolation signal storage unit of the next multiply-accumulate unit within the same clock cycle. The filter coefficient storage unit of the multiply-accumulate unit stores the interpolation filter coefficients. Different sampling factors L correspond to different filter coefficients, which are generally generated by MATLAB or Python functions. The acquired filter coefficients are stored sequentially in each filter coefficient storage unit, and the remaining filter coefficient storage units are set to zero.

[0034] In this first embodiment, a sampling factor L=4 and an interpolation filter order O=12 are set as an example. Once the sampling factor L and filter order O are selected, the multiply-accumulate unit generator of this interpolation filter will automatically generate several corresponding multiply-accumulate units to form the filtering module. It can be understood that the function of the multiply-accumulate unit generator in this invention can be implemented by developing RTL code (generally Verilog or System Verilog). After the RTL code is synthesized into a bitstream file using an EDA tool, it is downloaded to the FPGA. Based on the content of the bitstream file, the FPGA selects and activates the multipliers, adders, memory, and other structures within the FPGA, thus forming the multiply-accumulate unit generator described in this invention.

[0035] Preferably, in this embodiment, based on the principle that "the number of cyclic multiplication-accumulation units M equals L, and the number of multiplication-accumulation units N = ceil[O / L]", the multiplication-accumulation unit generator generates three multiplication-accumulation units with a cyclic multiplication-accumulation count of 4. This generation strategy can balance resource consumption and processing efficiency.

[0036] In this first embodiment, 12th-order interpolation filter coefficients, {h0,h1,h2,...,h10,h11}, were generated using MATLAB, while the original signal was {x0,x1,x2,...,xn-1,xn}. The original signal was stored in the original signal module. The user wrote the sampling factor (L=4) and filter order (O=12) into the interpolation filter register. Since this embodiment uses zero-value interpolation, the output of the interpolation module was 0. Therefore, the signal selection module inserted three zeros between every two original signals to obtain the interpolated signal, as shown below. Figure 3 As shown.

[0037] In this first embodiment, the multiply-accumulate unit generator generates three multiply-accumulate units with a cycle multiply-accumulate count of 4. Therefore, the interpolation filter coefficients are also divided into three groups and sequentially loaded into the corresponding multiply-accumulate units, such as... Figure 1 As shown.

[0038] After filtering begins, the signal selection module inputs the first interpolated signal x0 into the interpolated signal storage unit of the first multiply-accumulate unit (multiply-accumulate unit 1). After 4 clock cycles (M=L=4), each multiply-accumulate unit performs 4 sequential cyclic multiply-accumulate processes, generating N intermediate signals. These N intermediate signals are then accumulated to generate a filtered signal, as shown below. Figure 4 As shown. Specifically, the calculation process of the first filtered result y0 is illustrated as an example: In the first multiply-accumulate unit (multiply-accumulate unit 1), in the first clock cycle: calculate h(3)*0, and accumulate the value to h(3)*0; in the second clock cycle: calculate h(2)*0, and accumulate the value to h(2)*0+h(3)*0; in the third clock cycle: calculate h(1)*0, and accumulate the value to h(1)*0+h(2)*0+h(3)*0; in the fourth clock cycle: calculate h(0)*x(0), and accumulate the value (i.e., the intermediate signal) to h(0)*x(0)+h(1)*0+h(2)*0+h(3)*0; The above describes the four-cycle multiply-accumulate process in the first multiply-accumulate unit. It can be understood that in the other two multiply-accumulate units, the same four-cycle multiply-accumulate calculation will be performed over four clock cycles. However, in the other two multiply-accumulate units, all interpolated signal storage units are 0, so the final calculation result is always 0. Finally, the cumulative result of the three multiply-accumulate units, Y0 = h(0)*x(0) + h(1)*0 + h(2)*0 + h(3)*0, is the corresponding filtered signal.

[0039] Next, the signal selection module inputs the second interpolated signal (i.e., 0) into the interpolated signal storage unit of the first multiply-accumulate unit. After 4 clock cycles, the second filtered result y1 is obtained (refer to the calculation process of y0, which will not be elaborated here); similarly, y2 and y3 are obtained. The signal selection module inputs the 5th interpolated signal x1 into the interpolated signal storage unit of the first multiply-accumulate unit. After 4 clock cycles, y4 is obtained. Every 4 clock cycles, the signal selection module inputs an interpolated signal into the interpolated signal storage unit of the first multiply-accumulate unit, and at the same time, the filtering output module outputs a filtered signal. When the signal selection module inputs the "12th" interpolated signal (i.e., 0) into the interpolated signal storage unit of the first multiply-accumulate unit, as follows... Figure 5As shown, at this point, all interpolation signal storage units of the multiply-accumulate units are filled with interpolation signals, resulting in the filtered result y11. When the signal selection module inputs a new interpolation signal into the interpolation signal storage unit of the first multiply-accumulate unit, the initial x0 is shifted out of the interpolation signal storage unit. This process continues, and the interpolation filter can perform filtering operations on all interpolation signals, resulting in filtered signals that represent sampled data with a sampling rate increased by four times.

[0040] Example 2 like Figure 6 The diagram shown is a block diagram of an interpolation filter structure provided in Embodiment 2 of the present invention. (Reference) Figure 6 This invention provides a variable sampling rate interpolation filter based on FPGA, comprising: The interpolation signal generation module generates an interpolation signal based on the acquired original signal and the interpolation factor L. The multiply-accumulate unit generator generates a corresponding filtering module based on the obtained filter order O. The filtering module includes N cascaded multiply-accumulate units. Each multiply-accumulate unit includes an interpolation signal storage unit with M storage bits and a filter coefficient storage unit with M storage bits, where N*M≥O. The filtering module is used to receive an interpolation signal every M clock cycles and make each multiply-accumulate unit perform M cyclic multiply-accumulate processes in sequence to generate N intermediate signals. The filter output module is used to accumulate N intermediate signals, generate a corresponding filtered signal, and output it.

[0041] The technical solution of this embodiment is basically the same as that of embodiment one. The main difference is that in this embodiment two, the sampling factor L=6 and the interpolation filter order O=12 are set as an example.

[0042] Once the sampling factor L and filter order O are selected, the multiply-accumulate unit generator of this interpolation filter will automatically generate several corresponding multiply-accumulate units to form the filter module. Preferably, in this embodiment two, according to "the number of cyclic multiply-accumulate units M equals L, and the number of multiply-accumulate units N = ceil[O / L]", the multiply-accumulate unit generator generates two multiply-accumulate units with a cyclic multiply-accumulate count of 6. This generation strategy can balance resource consumption and processing efficiency.

[0043] In this second embodiment, 12th-order interpolation filter coefficients, {h0,h1,h2,...,h10,h11}, were generated using MATLAB, while the original signal was {x0,x1,x2,...,xn-1,xn}. The original signal was stored in the original signal module. The user wrote the sampling factor (L=6) and filter order (O=12) into the interpolation filter register. Since this embodiment uses zero-value interpolation, the output of the interpolation module was 0. Therefore, the signal selection module inserted five zeros between every two original signals to obtain the interpolated signal, as shown below. Figure 6 As shown.

[0044] In this first embodiment, the multiply-accumulate unit generator generates two multiply-accumulate units with a cycle multiply-accumulate count of 6. Therefore, the interpolation filter coefficients are also divided into two groups and sequentially loaded into the corresponding multiply-accumulate units, such as... Figure 6 As shown.

[0045] After filtering begins, the signal selection module inputs the first interpolation signal x0 into the interpolation signal storage unit of the first multiply-accumulate unit (multiply-accumulate unit 1). After 6 clock cycles (M=L=6), each multiply-accumulate unit performs 6 cyclic multiply-accumulate processes in sequence to generate N intermediate signals. The N intermediate signals are then accumulated to generate a filter signal.

[0046] Next, the signal selection module inputs the second interpolated signal (i.e., 0) into the interpolated signal storage unit of the first multiply-accumulate unit, obtaining the second filtered result y1 after 6 clock cycles; similarly, y2, y3, y4, and y5 are obtained. The signal selection module inputs the 7th interpolated signal x1 into the interpolated signal storage unit of the first multiply-accumulate unit, obtaining y6 after 6 clock cycles. Every 6 clock cycles, the signal selection module inputs an interpolated signal into the interpolated signal storage unit of the first multiply-accumulate unit, while the filtering output module outputs a filtered signal. When the signal selection module inputs the "12th" interpolated signal (i.e., 0) into the interpolated signal storage unit of the first multiply-accumulate unit, as follows... Figure 6 As shown, at this point, all interpolation signal storage units of the multiply-accumulate units are filled with interpolation signals, resulting in the filtered result y11. When the signal selection module inputs a new interpolation signal into the interpolation signal storage unit of the first multiply-accumulate unit, the initial x0 is shifted out of the interpolation signal storage unit. This process continues, and the interpolation filter can perform filtering operations on all interpolation signals, resulting in filtered signals that represent sampled data with a sampling rate increased by 6 times.

[0047] Example 3 like Figure 7 The diagram shown is a block diagram of an interpolation filter structure provided in Embodiment 3 of the present invention. (Reference) Figure 7This invention provides a variable sampling rate interpolation filter based on FPGA, comprising: The interpolation signal generation module generates an interpolation signal based on the acquired original signal and the interpolation factor L. The multiply-accumulate unit generator generates a corresponding filtering module based on the obtained filter order O. The filtering module includes N cascaded multiply-accumulate units. Each multiply-accumulate unit includes an interpolation signal storage unit with M storage bits and a filter coefficient storage unit with M storage bits, where N*M≥O. The filtering module is used to receive an interpolation signal every M clock cycles and make each multiply-accumulate unit perform M cyclic multiply-accumulate processes in sequence to generate N intermediate signals. The filter output module is used to accumulate N intermediate signals, generate a corresponding filtered signal, and output it.

[0048] Specifically, refer to the following: Figure 1 , Figure 2 and Figure 7 The interpolation filter consists of an interpolation signal generation module, a multiply-accumulate unit generator, a filtering module, and several multiply-accumulate units.

[0049] The interpolation signal generation module consists of a raw signal module, an interpolation module, and a signal selection module, as detailed below. Figure 2 As shown. The original signal module is used to sequentially provide the original signals (i.e., x). （n） The interpolation module provides zero-value signals, and the input of the signal selection module is connected to the outputs of the original signal module and the interpolation module, respectively. The signal selection module generates L interpolation signals by first selecting one original signal and then selecting L-1 zero-value signals. The signal selection module inputs one interpolation signal to the filtering module every M clock cycles.

[0050] The multiply-accumulate unit generator generates several multiply-accumulate units with a specific structure to form a filtering module based on a preset or externally input sampling factor L and filter order O. Specifically, the filtering module includes N cascaded multiply-accumulate units that can perform cyclic multiplication and accumulation M times, such that N*M≥O, that is, the product of the number of cyclic multiplication and accumulation times of each multiply-accumulate unit and the number of multiply-accumulate units is greater than or equal to the filter order O (the filter order O is equal to the number of filter coefficients). This ensures that all filter coefficients are fully accommodated to satisfy the filtering formula: In the formula, Original signal, L represents the filtered signal, and L represents the interpolation factor.

[0051] The multiply-accumulate unit consists of an interpolation signal storage unit, a filter coefficient storage unit, a multiplier, and an adder, specifically as follows: Figure 3As shown. The interpolation signal storage unit is used to store the interpolation signal (set to 0 when not stored), and the filter coefficient storage unit is used to store the filter coefficients (set to 0 when not stored). In this interpolation filter, the interpolation signal storage units of N multiply-accumulate units are cascaded sequentially. Each multiply-accumulate unit performs a cyclic multiplication and accumulation operation on the stored digital signal and the corresponding filter coefficient. The number of cyclic multiplication and accumulation operations is M, which is equal to the number of storage bits M of the interpolation signal storage unit and the filter coefficient storage unit in each multiply-accumulate unit. It can be understood that the multiply-accumulate unit performs a multiplication and accumulation operation once in each clock cycle. After that, the result of each multiplication and accumulation operation is accumulated with the result of the previous multiplication and accumulation operation. The accumulated result is temporarily stored in the FPGA storage circuit. After M clock cycles, the cyclic multiplication and accumulation operation inside each multiply-accumulate unit is completed, and an intermediate signal is generated accordingly. Then, the accumulated results of all multiply-accumulate units (i.e., the intermediate signals) are added together to obtain a filter signal, which is finally output through the filter output module.

[0052] The specific implementation process is as follows: First, the original signal {x0,x1,x2,...,xn-1,xn} is acquired and stored in the original signal module. The user can determine the sampling factor L and filter order O based on actual needs and write them into the FPGA register. The outputs of both the original signal module and the interpolation module are connected to the input of the signal selection module. The original signal module outputs the original signal without interpolation, and the interpolation module outputs interpolated 0 (i.e., zero value). Thus, the signal selection module can insert L-1 interpolations between every two original signals according to the preset sampling factor L, resulting in an interpolated signal expanded by a factor of L. Then, every M clock cycles, one interpolated signal can be output to the interpolated signal storage unit of the first multiply-accumulate unit.

[0053] The interpolation signal storage unit of the multiply-accumulate unit is used to store the interpolation signal. The signal storage circuits of multiple multiply-accumulate units are connected end-to-end. The filtering module receives one interpolation signal every M clock cycles and stores it sequentially in the interpolation signal storage unit. After every M clock cycles, it shifts the interpolation signals in all interpolation signal storage units one position to the right. When an interpolation signal is shifted out of the interpolation signal storage unit of one multiply-accumulate unit, it is shifted into the interpolation signal storage unit of the next multiply-accumulate unit within the same clock cycle. The filter coefficient storage unit of the multiply-accumulate unit stores the interpolation filter coefficients. Different sampling factors L correspond to different filter coefficients, which are generally generated by MATLAB or Python functions. The acquired filter coefficients are stored sequentially in each filter coefficient storage unit, and the remaining filter coefficient storage units are set to zero.

[0054] After filtering begins, the signal selection module inputs the first interpolated signal x0 into the interpolated signal storage unit of the first multiply-accumulate unit. All multiply-accumulate units perform one multiply-accumulate operation per clock cycle, accumulating the results of each unit. After M clock cycles, the accumulated results of all units are summed to obtain the first filtered result y0. Then, the signal selection module inputs the second interpolated signal x0 into the signal storage circuit of the first multiply-accumulate unit. After L clock cycles, the second filtered result y1 is obtained, and so on for y2, y3, ..., yL-1. The signal selection module then inputs the (L+1)th interpolated signal x1 into the signal storage circuit of the first multiply-accumulate unit, obtaining yL after L clock cycles. Every L clock cycles, the signal selection module inputs an interpolated signal into the signal storage circuit of the first multiply-accumulate unit, while the filtering output module outputs a filtered signal. When the signal selection module inputs the last interpolated signal into the signal storage circuit of the first multiply-accumulate unit, the filtered result yn is obtained. When the signal selection module inputs the new interpolated signal into the signal storage circuit of the first multiply-accumulate unit, x0 is shifted out of the filter. Following this process, filtering operations can be performed on all interpolated signals, resulting in sampled data with a sampling rate increased by L times.

[0055] If the sampling rate multiplier needs to be changed, the user writes the new sampling rate multiplier M and the new filter order into the register of the circuit device. The interpolation filter will generate a specific number of multiply-accumulate units with a specific number of cycles based on the newly written sampling factor L2 and the new filter order O2. Multiple multiply-accumulate units are connected end to end to form an interpolation filter, which filters the original signal after the interpolation operation. The filtering result is sampled data with the sampling rate increased by a factor of L2.

[0056] The common English terms or letters used in this invention for clarity of description are for illustrative purposes only and are not limiting interpretations or specific uses. They should not be used to limit the scope of protection of this invention based on their possible Chinese translations or specific letters.

[0057] It should also be noted that in this article, relational terms such as “first” and “second” are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

Claims

1. A variable sampling rate interpolation filter based on FPGA, characterized in that, include: The interpolation signal generation module generates an interpolation signal based on the acquired original signal and the interpolation factor L. A multiply-accumulate unit generator generates a corresponding filtering module based on the obtained filter order O. The filtering module includes N cascaded multiply-accumulate units, each of which includes an interpolation signal storage unit with M storage bits and a filter coefficient storage unit with M storage bits, wherein N*M≥O. The filtering module is used to receive one interpolation signal every M clock cycles, and to make each multiply-accumulate unit perform M cyclic multiply-accumulate processes in sequence to generate N intermediate signals. The filtering output module is used to accumulate the N intermediate signals, generate a corresponding filtered signal, and output it.

2. The FPGA-based variable sampling rate interpolation filter according to claim 1, characterized in that, Based on the obtained interpolation factor L and filter order O, a corresponding filtering module is generated. The generated filtering module includes N cascaded multiply-accumulate units. Each multiply-accumulate unit includes an interpolation signal storage unit with M storage bits and a filter coefficient storage unit with M storage bits, where M=L, N=ceil[O / L], and ceil[] represents rounding up.

3. A variable sampling rate interpolation filter based on FPGA according to claim 1 or 2, characterized in that, In the filtering module, the interpolation signal storage circuits of the N multiply-accumulate units are cascaded in sequence.

4. The FPGA-based variable sampling rate interpolation filter according to claim 1, characterized in that, The difference signal generation module includes a raw signal module, an interpolation module, and a signal selection module; The original signal module is used to provide the original signals sequentially, the interpolation module is used to provide zero-value signals, and the input terminal of the signal selection module is connected to the output terminal of the original signal module and the interpolation module respectively. The signal selection module generates L interpolated signals by first selecting and outputting one original signal, and then selecting and outputting L-1 zero-value signals.

5. A variable sampling rate interpolation filter based on FPGA according to claim 3, characterized in that, In the filtering module, the acquired filtering coefficients are stored sequentially in each of the filtering coefficient storage units, and the remaining filtering coefficient storage units are set to zero. The number of filter coefficients is equal to the filter order O.

6. The FPGA-based variable sampling rate interpolation filter according to claim 5, characterized in that, The filtering module receives one interpolation signal every M clock cycles and stores them sequentially in the interpolation signal storage unit, and shifts the interpolation signals in all the interpolation signal storage units one position to the right after every M clock cycles. The interpolation signal storage unit that does not store the interpolation signal is set to zero.

7. A variable sampling rate interpolation filter based on FPGA according to claim 1, characterized in that, Each of the multiply-accumulate units includes an interpolation signal storage unit with M storage bits, a filter coefficient storage unit with M storage bits, a multiplier, and an adder. In each of the multiply-accumulate units, the multiplier is used to sequentially multiply one bit in the interpolation signal storage unit and the corresponding one bit in the filter coefficient storage unit, and the adder is used to accumulate the result of each multiplication calculation to generate an intermediate signal.

8. A variable sampling rate interpolation filter based on FPGA according to claim 2, characterized in that, The multiply-add unit generator, based on the acquired interpolation factor L and the filter order O, activates the multiplier, the adder, and the storage unit inside the FPGA to generate the corresponding filtering module.

9. A variable sampling rate interpolation filter based on FPGA according to claim 5, characterized in that, The filter coefficients are generated using MATLAB or Python functions based on the interpolation factor L and the filter order O.

10. A variable sampling rate interpolation filter based on FPGA according to claim 4, characterized in that, The signal selection module inputs an interpolation signal to the filtering module every M clock cycles.

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