High-voltage-resistant level conversion circuit based on voltage-limited transistor and chip

Abstract

The invention discloses a high-voltage-resistant level conversion circuit and chip based on a voltage-limited transistor, and the circuit comprises an input control module, a first same-level control module, a second same-level control module, a first stacking voltage control module, a second stacking voltage control module, and a positive feedback module which are connected in sequence. The input control module is used for accessing an input voltage and providing the input voltage to the first same-level control module, and the first stacking voltage control module and the second stacking voltage control module respectively comprise at least one stacked NMOS (N-channel Metal Oxide Semiconductor) tube and at least one stacked PMOS (P-channel Metal Oxide Semiconductor) tube so as to realize voltage drop through the stacked MOS tubes; the first same-level control module and the second same-level control module respectively adopt the same-level control to carry out input voltage transmission, and the positive feedback module is used for outputting converted voltage. The invention can realize high power supply voltage resistant conversion of the low-voltage tube, and has the advantages of simple and compact structure, low cost and power consumption, small required circuit area, safety, reliability and the like, and is not limited by process transistors.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to a high-voltage level conversion circuit and chip based on a voltage-limited transistor. Background Technology

[0002] Level shifting circuits are widely used in integrated circuit design, such as in analog-to-digital converters and large-scale integrated circuits with multiple voltage domains. Traditional level shifting circuits include... Figure 1 As shown, the circuit includes two NMOS transistors, MN1 and MN2, and two PMOS transistors, MP1 and MP2. During operation, when the input voltage is low, MN1 in the left path is off, and the gate of MN2 in the right path is at a logic high level (VDDL). MN2 then enables its pull-down current capability. At this time, the drain of MP2 is pulled low by the pull-down transistor, transmitting the signal to the positive feedback circuit, which pulls the drain of MP1 high. Therefore, the OUT terminal outputs a logic low level. Conversely, when the input voltage is VDDL high, the output voltage is VDDH high. This level-shifting circuit is only suitable for integrated circuits with low power supply voltages and is not suitable for high power supply voltage conversion scenarios. For transistor types with limited operating voltages, implementing a level-shifting circuit to convert to a high voltage may result in transistor breakdown.

[0003] Taking a transistor type with an operating voltage of 1.8V as an example, when the high voltage to be converted by the level conversion circuit is 3.3V, most existing 1.8V transistors cannot achieve a high voltage withstand of 3.3V. Therefore, a method such as... Figure 1 The level conversion circuit shown may have a risk of transistor breakdown. Summary of the Invention

[0004] The technical problem to be solved by the present invention is as follows: In view of the above-mentioned problems existing in the prior art, the present invention provides a high voltage level conversion circuit and chip based on voltage-limited transistors that is simple and compact in structure, low in cost and power consumption, requires a small circuit area, is not limited by process transistors, and is safe and reliable. It can realize the conversion of low voltage transistors to withstand high power supply voltages and solve the problem of insufficient operating voltage of process transistors.

[0005] To solve the above-mentioned technical problems, the technical solution proposed by this invention is as follows: A high-voltage level conversion circuit based on a voltage-limited transistor includes an input control module, a first same-level control module, a second same-level control module, a first stacked voltage control module, a second stacked voltage control module, and a positive feedback module connected in sequence. The input terminal of the input control module is connected to an input voltage, and the output terminal is connected to the first stacked voltage control module and the second stacked voltage control module through the first same-level control module and the second same-level control module, respectively. The first stacked voltage control module and the second stacked voltage control module are respectively connected to one end of the positive feedback module. The output terminal of the positive feedback module outputs the converted voltage. The input voltage is a low voltage below a preset standard voltage threshold, and the converted voltage is higher than the input voltage. The input control module is used to receive the input voltage and provide it to the first same-level control module. The first stacked voltage control module and the second stacked voltage control module each include at least one stacked NMOS transistor and at least one PMOS transistor to achieve voltage drop through the stacked MOS transistors. The first same-level control module and the second same-level control module are used to transmit the input voltage using the same level control. The positive feedback module is used to output the converted voltage through the positive feedback circuit. The operating voltage of the switching transistors used in each module is lower than the preset standard voltage threshold.

[0006] Furthermore, the input control module includes an inverter, a thirteenth NMOS transistor gate MN13, a fourteenth NMOS transistor MN14, and a fifteenth NMOS transistor gate MN15. The input terminal of the inverter is connected to the gates of the thirteenth NMOS transistor MN13 and the fifteenth NMOS transistor, respectively, and the output terminal is connected to the gate of the fourteenth NMOS transistor. The drain terminals of the thirteenth NMOS transistor MN13, the fourteenth NMOS transistor MN14, and the fifteenth NMOS transistor gate MN15 are respectively connected to the first level control module. The gate of the thirteenth NMOS transistor MN13 is connected to the input voltage.

[0007] Furthermore, the first level control module includes a ninth NMOS transistor MN9, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, and a twelfth NMOS transistor MN12, and the gates of each NMOS transistor are controlled by the same voltage. The source of the ninth NMOS transistor MN9 is connected to the drain of the thirteenth NMOS transistor MN13, the sources of the tenth NMOS transistor MN10 and the eleventh NMOS transistor MN11 are connected to the drain of the fourteenth NMOS transistor MN14, and the source of the twelfth NMOS transistor MN12 is connected to the drain of the fifteenth NMOS transistor MN15.

[0008] Furthermore, the second level control module includes a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, and an eighth NMOS transistor MN8, with the gates of each NMOS transistor controlled by the same voltage. The source of the third NMOS transistor MN13 is connected to the drain of the thirteenth NMOS transistor MN13, the drain of the third NMOS transistor MN3 is connected to the source of the first NMOS transistor MN1, the source of the fourth NMOS transistor MN4 is connected to the drain of the ninth NMOS transistor MN9, and the drain of the fourth NMOS transistor is connected to the... In the positive feedback module, the source of the fifth NMOS transistor MN5 is connected to the drain of the tenth NMOS transistor MN10, and the drain of the fifth NMOS transistor MN5 is connected to the positive feedback module. The source of the sixth NMOS transistor MN6 is connected to the source of the tenth NMOS transistor MN10, and the drain of the sixth NMOS transistor MN6 is connected to the second stacked voltage-controlled module. The source of the seventh NMOS transistor MN7 is connected to the drain of the eleventh NMOS transistor MN11, and the drain of the seventh NMOS transistor MN7 is connected to the gate of the ninth PMOS transistor MN9. The source of the eighth NMOS transistor MN8 is connected to the drain of the twelfth NMOS transistor MN12.

[0009] Furthermore, the first stacked voltage control module includes a seventh PMOS transistor MN7 and a first NMOS transistor MN1, wherein the source of the seventh PMOS transistor MP7 is connected to the gate of the first NMOS transistor MN1, the gate of the first NMOS transistor MN1 is connected to the source of the seventh PMOS transistor MP7, and the sources of the first NMOS transistor MN1 and the seventh NMOS transistor MN7 are respectively connected to one end of the positive feedback module. Furthermore, the second stacked voltage control module includes an eighth PMOS transistor MP8 and a second NMOS transistor MN2, wherein the source of the eighth PMOS transistor MP8 is connected to the gate of the second NMOS transistor MN2, the gate of the eighth PMOS transistor MP8 is connected to the source of the second NMOS transistor MN2, and the sources of the second NMOS transistor MN2 and the eighth PMOS transistor MP8 are connected to the other end of the positive feedback module. Furthermore, the positive feedback module includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, and a sixth PMOS transistor MP6. The gates of the third PMOS transistor MP3, the fourth PMOS transistor MP4, the fifth PMOS transistor MP5, and the sixth PMOS transistor MP6 are provided with VBIAS voltage by an external bias module. The gate of the second PMOS transistor MP2 is connected to the drain of the fifth PMOS transistor MP5, and the gate of the first PMOS transistor MP1 is connected to the drain of the sixth PMOS transistor MP6.

[0010] Furthermore, a ninth PMOS transistor is also provided at the output terminal of the positive feedback module. The drain of the ninth PMOS transistor is connected to the drain of the eighth NMOS transistor MN8 in the second same-level control module. The ninth PMOS transistor MP9, the eighth NMOS transistor MN8 in the second same-level control module, the twelfth NMOS transistor MN12 in the first same-level control module, and the fifteenth NMOS transistor MN15 in the input control module constitute the voltage drop control of the output voltage. The switching transistors are stacked and connected in sequence.

[0011] Furthermore, the operating voltage of the switching transistors used in each module is 1.8V, the input voltage is 1.8V, and the converted voltage is 3.3V.

[0012] A chip includes a chip body, and the chip body further includes a high-voltage level conversion circuit based on a voltage-limited transistor as described above.

[0013] Compared with the prior art, the beneficial effects of the present invention are as follows: The present invention constructs a high-voltage-resistant level conversion circuit by means of an input control module, a first same-level control module, a second same-level control module, a first stacked voltage control module, a second stacked voltage control module, and a positive feedback module. The voltage drop is achieved by stacking MOS transistors, resulting in a small area, low power consumption, and simple structure. It can not only achieve operation in multiple voltage domains and realize the level conversion of low-voltage transistors operating in high power supply voltage domains, but is also not limited by process transistors. It can solve the problems of traditional low-operating voltage transistors being unable to operate in high power supply voltage domains exceeding process limitations and insufficient operating voltage of process transistors. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of a traditional level conversion circuit.

[0015] Figure 2 This is a schematic diagram of the high-voltage level conversion circuit based on a voltage-limited transistor in this embodiment.

[0016] Legend: 1. Input control module; 2. First same-level control module; 3. Second same-level control module; 4. First stacked voltage control module; 5. Second stacked voltage control module; 6. Positive feedback module. Detailed Implementation

[0017] The present invention will be further described below with reference to the accompanying drawings and specific preferred embodiments, but this does not limit the scope of protection of the present invention.

[0018] As disclosed in this invention, unless the context clearly indicates otherwise, words such as "a," "an," "an," and / or "the" do not specifically refer to the singular and may also include the plural. The terms "first," "second," and similar terms used in this invention disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, words such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connected" or "linked" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0019] like Figure 2 As shown, this embodiment uses a voltage-limited transistor-based high-voltage level conversion circuit, including an input control module 1, a first same-level control module 2, a second same-level control module 3, a first stacked voltage control module 4, a second stacked voltage control module 5, and a positive feedback module 6 connected in sequence. The input terminal of the input control module 1 is connected to the input voltage, and its output terminal is connected to the first stacked voltage control module 4 and the second stacked voltage control module 5 through the first same-level control module 2 and the second same-level control module 3, respectively. The first stacked voltage control module 4 and the second stacked voltage control module 5 are respectively connected to one end of the positive feedback module 6. The converted voltage is output from the output terminal of the positive feedback module 6, and the input voltage is lower than a preset standard voltage. The threshold voltage is low, and the converted voltage is higher than the input voltage. Input control module 1 receives the input voltage and provides it to the first same-level control module 2. The first stacked voltage control module 4 and the second stacked voltage control module 5 each include at least one stacked NMOS transistor and at least one stacked PMOS transistor to achieve voltage drop through the stacked MOS transistors. The first same-level control module 2 and the second same-level control module 3 are used to transmit the input voltage using the same level control. The positive feedback module 6 outputs the converted voltage through a positive feedback circuit. The operating voltage of the switching transistors used in each module is lower than the preset standard voltage threshold, meaning the operating voltage of the switching transistors used in each module is low. It is understandable that high-voltage switching transistors can be used for some switching transistors in the circuit according to actual needs.

[0020] The level conversion circuit described in this embodiment achieves voltage drop through MOSFET stacking, resulting in a level conversion circuit with small area, low power consumption, and simple structure. It can not only operate in multiple voltage domains, enabling low-voltage transistors to operate in high power supply voltage domains, but is also not limited by process transistors. This solves the problem that traditional low-operating-voltage transistors cannot operate in high power supply voltage domains exceeding process limitations, and that process transistors have insufficient operating voltage.

[0021] In this embodiment, low voltage refers to a voltage below a preset standard voltage threshold, and high voltage refers to a voltage above a preset standard voltage threshold. The preset standard voltage threshold can be determined according to actual needs. For example, low voltage can be 1.8V and high voltage can be 3.3V.

[0022] In this embodiment, the input control module 1 specifically includes an inverter, a thirteenth NMOS transistor gate MN13, a fourteenth NMOS transistor MN14, and a fifteenth NMOS transistor gate MN15. The input terminal of the inverter is connected to the gates of the thirteenth NMOS transistor MN13 and the fifteenth NMOS transistor, respectively, and the output terminal is connected to the gate of the fourteenth NMOS transistor. The drains of the thirteenth NMOS transistor MN13, the drains of the fourteenth NMOS transistor MN14, and the gate of the fifteenth NMOS transistor MN15 are respectively connected to the first level control module 2. The gate of the thirteenth NMOS transistor MN13 is connected to the input voltage. Specifically, the source of the aforementioned NMOS transistors is grounded, and the drain of the thirteenth NMOS transistor is connected to the source of the ninth NMOS transistor.

[0023] Understandably, inverters can also be implemented using other types of logic circuit combinations depending on actual needs.

[0024] In this embodiment, the first level control module 2 includes a ninth NMOS transistor MN9, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, and a twelfth NMOS transistor MN12, and the gates of each NMOS transistor are controlled by the same voltage. The source of the ninth NMOS transistor MN9 is connected to the drain of the thirteenth NMOS transistor MN13, the sources of the tenth NMOS transistor MN10 and the eleventh NMOS transistor MN11 are connected to the drain of the fourteenth NMOS transistor MN14, and the source of the twelfth NMOS transistor MN12 is connected to the drain of the fifteenth NMOS transistor MN15.

[0025] Furthermore, the gate levels of each NMOS transistor in the first level control module 2 are controlled by logic. VDDH may support not only 3.3V, but also 1.8V. In this embodiment, by pulling the gate voltage to the logic high level of VDDL, the output logic high and low levels for 1.8V can be achieved.

[0026] In this embodiment, the second level control module 3 includes a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, and an eighth NMOS transistor MN8. The gates of each NMOS transistor are controlled by the same voltage. The source of the third NMOS transistor MN13 is connected to the drain of the thirteenth NMOS transistor MN13. The drain of the third NMOS transistor MN3 is connected to the source of the first NMOS transistor MN1. The source of the fourth NMOS transistor MN4 is connected to the drain of the ninth NMOS transistor MN9. The drain of the fourth NMOS transistor is connected to the positive voltage. Feedback module 6: The source of the fifth NMOS transistor MN5 is connected to the drain of the tenth NMOS transistor MN10; the drain of the fifth NMOS transistor MN5 is connected to the positive feedback module 6; the source of the sixth NMOS transistor MN6 is connected to the source of the tenth NMOS transistor MN10; the drain of the sixth NMOS transistor MN6 is connected to the second stacked voltage control module 5; the source of the seventh NMOS transistor MN7 is connected to the drain of the eleventh NMOS transistor MN11; the drain of the seventh NMOS transistor MN7 is connected to the gate of the ninth PMOS transistor MN9; and the source of the eighth NMOS transistor MN8 is connected to the drain of the twelfth NMOS transistor MN12.

[0027] Specifically, the drain of the fourth NMOS transistor is connected to the drain of the fifth PMOS transistor MP5 in the positive feedback module 6, the drain of the fifth NMOS transistor MN5 is connected to the drain of the sixth PMOS transistor MP6 in the positive feedback module 6, and the drain of the sixth NMOS transistor MN6 is connected to the source of the second NMOS transistor MN2 in the second stacked voltage control module 5.

[0028] In this embodiment, a ninth PMOS transistor is also provided at the output terminal of the positive feedback module 6, and the drain of the eighth NMOS transistor is connected to the drain of the ninth PMOS transistor.

[0029] In this embodiment, the first stacked voltage control module 4 includes a seventh PMOS transistor MN7 and a first NMOS transistor MN1. The source of the seventh PMOS transistor MP7 is connected to the gate of the first NMOS transistor MN1, and the gate of the first NMOS transistor MN1 is connected to the source of the seventh PMOS transistor MP7. The sources of the first NMOS transistor MN1 and the seventh NMOS transistor MN7 are respectively connected to one end of the positive feedback module 6. Specifically, the source of the first NMOS transistor MN1 is connected to the drain of the third NMOS transistor MN3 in the positive feedback module 6, and the source of the seventh NMOS transistor MN7 is connected to the drain of the fifth PMOS transistor MP5 in the positive feedback module 6. In this embodiment, the second stacked voltage control module 5 includes an eighth PMOS transistor MP8 and a second NMOS transistor MN2. The source of the eighth PMOS transistor MP8 is connected to the gate of the second NMOS transistor MN2, and the gate of the eighth PMOS transistor MP8 is connected to the source of the second NMOS transistor MN2. The sources of the second NMOS transistor MN2 and the eighth PMOS transistor MP8 are connected to the other end of the positive feedback module 6. Specifically, the second NMOS transistor MN2 is connected to the drain of the sixth PMOS transistor MP6 in the positive feedback module 6, and the source of the eighth PMOS transistor MP8 is connected to the drain of the fourth PMOS transistor MP4 in the positive feedback module 6. In this embodiment, the positive feedback module 6 includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, and a sixth PMOS transistor MP6. The gates of the third PMOS transistor MP3, the fourth PMOS transistor MP4, the fifth PMOS transistor MP5, and the sixth PMOS transistor MP6 are provided with VBIAS voltage by an external bias module. The gate of the second PMOS transistor MP2 is connected to the drain of the fifth PMOS transistor MP5, and the gate of the first PMOS transistor MP1 is connected to the drain of the sixth PMOS transistor MP6.

[0030] In this embodiment, the output voltage drop control is achieved by the ninth PMOS transistor MP9 at the output of the positive feedback module 6, the eighth NMOS transistor MN8 in the second same-level control module 3, the twelfth NMOS transistor MN12 in the first same-level control module 2, and the fifteenth NMOS transistor MN15 in the input control module 1. These switching transistors are stacked sequentially. This embodiment achieves voltage-bearing separation by using stacked switching transistors at the output stage, avoiding the risk of breakdown of a single NMOS transistor. It further ensures that the low-voltage transistor can perform level switching in the high power supply voltage domain. Furthermore, each NMOS switching transistor is controlled by the first same-level control module 2, the second same-level control module 3, and the input voltage, respectively, without requiring additional level control circuitry.

[0031] Taking an example where the operating voltage of the switching transistors used in each module is 1.8V, the input voltage is 1.8V, and the converted voltage is 3.3V. See [link / reference]. Figure 2This circuit enables a level shifting circuit that supports a 3.3V power supply voltage from a 1.8V operating voltage transistor. It is used to achieve a level shifting circuit supporting higher power supply voltages under process limitations. The circuit includes an inverter control logic section (corresponding to input control module 1) and a PMOS stacked NMOS voltage-controlled section (corresponding to first same-level control module 2, second same-level control module 3, first stacked voltage-controlled module 4, and second stacked voltage-controlled module 5). The gate of the intermediate PMOS is connected to the source of the next NMOS, and the gate of the NMOS is connected to the source of the PMOS, ensuring that the Vgs of the two transistors are the same. This achieves a voltage reduction effect without the need for an additional bias voltage module. Furthermore, the path to ground is composed of multiple stacked NMOS transistors, further enhancing the voltage drop process. The inverter's logic control can incorporate various combination control methods to achieve the desired logic control.

[0032] Specifically, the above conversion circuit can be applied to three different voltage domains: VDDH, VDDM, and VDDL. During operation, by applying a low-level input voltage, the fourteenth NMOS transistor MN14 is turned on, and the gate voltages of each NMOS switch in the second same-level control module 3 can be controlled by a logic low level. The gate voltages of each NMOS in the first same-level control module 2 can be directly controlled by a logic high level of VDDM. Since this circuit supports multiple power supply voltages, and the voltage relationship is VDDH > VDDM > VDDL, the gates of each NMOS switch in the first same-level control module 2 do not require additional bias circuit control, which greatly saves chip area.

[0033] In the above conversion circuit, to achieve the stacking of MOS transistors, the source of the seventh PMOS transistor MP7 is connected to the gate of the first NMOS transistor MN1, the gate of the first NMOS transistor MN1 is connected to the source of the seventh PMOS transistor MP7, and the drain of the seventh PMOS transistor MP7 is connected to the drain of the first NMOS transistor MN1. This stacking method ensures that the Vgs of the two stacked switching transistors are identical during circuit operation, thus saving one Vth voltage when setting the operating voltage. Therefore, the output voltage OUT is approximately VBIAS + Vth, which is a logic low level. The voltage of OUT is connected to the ninth NMOS transistor MN9. Through the voltage drop across the four stacked transistors, the output of OUT1 is ultimately made to be a logic high level VCCO. Conversely, if the input voltage VDDL is logic high, the output OUT is the opposite of OUT1.

[0034] This embodiment also provides a chip, including a chip body, in which a high-voltage level conversion circuit based on a voltage-limited transistor as described above is further provided.

[0035] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Therefore, any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention should fall within the protection scope of the present invention.

Claims

1. A high-voltage level conversion circuit based on a voltage-limited transistor, characterized in that, The system includes an input control module (1), a first same-level control module (2), a second same-level control module (3), a first stacked voltage control module (4), a second stacked voltage control module (5), and a positive feedback module (6) connected in sequence. The input terminal of the input control module (1) is connected to the input voltage, and the output terminal is connected to the first stacked voltage control module (4) and the second stacked voltage control module (5) through the first same-level control module (2) and the second same-level control module (3), respectively. The first stacked voltage control module (4) and the second stacked voltage control module (5) are respectively connected to one end of the positive feedback module (6), and the output terminal of the positive feedback module (6) outputs the converted voltage. The input voltage is a low voltage lower than the preset standard voltage threshold, and the converted voltage is higher than the input voltage. The input control module (1) is used to receive the input voltage and provide it to the first same-level control module (2). The first stacked voltage control module (4) and the second stacked voltage control module (5) each include at least one stacked NMOS transistor and at least one PMOS transistor to achieve voltage drop through the stacked MOS transistors. The first same-level control module (2) and the second same-level control module (3) are used to transmit the input voltage using the same level control. The positive feedback module (6) is used to output the converted voltage through the positive feedback circuit. The operating voltage of the switching transistors used in each module is lower than the preset standard voltage threshold.

2. The high-voltage level conversion circuit based on a voltage-limited transistor according to claim 1, characterized in that, The input control module (1) includes an inverter, a thirteenth NMOS transistor gate MN13, a fourteenth NMOS transistor MN14, and a fifteenth NMOS transistor gate MN15. The input terminal of the inverter is connected to the gates of the thirteenth NMOS transistor MN13 and the fifteenth NMOS transistor, respectively, and the output terminal is connected to the gate of the fourteenth NMOS transistor. The drains of the thirteenth NMOS transistor MN13, the drains of the fourteenth NMOS transistor MN14, and the gate of the fifteenth NMOS transistor MN15 are respectively connected to the first level control module (2). The gate of the thirteenth NMOS transistor MN13 is connected to the input voltage.

3. The high-voltage level conversion circuit based on a voltage-limited transistor according to claim 2, characterized in that, The first level control module (2) includes a ninth NMOS transistor MN9, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, and a twelfth NMOS transistor MN12. The gates of each NMOS transistor are controlled by the same voltage. The source of the ninth NMOS transistor MN9 is connected to the drain of the thirteenth NMOS transistor MN13. The sources of the tenth NMOS transistor MN10 and the eleventh NMOS transistor MN11 are connected to the drain of the fourteenth NMOS transistor MN14. The source of the twelfth NMOS transistor MN12 is connected to the drain of the fifteenth NMOS transistor MN15.

4. The high-voltage level conversion circuit based on a voltage-limited transistor according to claim 3, characterized in that, The second level control module (3) includes a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, and an eighth NMOS transistor MN8. The gates of each NMOS transistor are controlled by the same voltage. The source of the third NMOS transistor MN13 is connected to the drain of the thirteenth NMOS transistor MN13. The drain of the third NMOS transistor MN3 is connected to the source of the first NMOS transistor MN1. The source of the fourth NMOS transistor MN4 is connected to the drain of the ninth NMOS transistor MN9. The drain of the fourth NMOS transistor is connected to the positive feedback module (…). 6) The source of the fifth NMOS transistor MN5 is connected to the drain of the tenth NMOS transistor MN10, and the drain of the fifth NMOS transistor MN5 is connected to the positive feedback module (6). The source of the sixth NMOS transistor MN6 is connected to the source of the tenth NMOS transistor MN10, and the drain of the sixth NMOS transistor MN6 is connected to the second stacked voltage control module (5). The source of the seventh NMOS transistor MN7 is connected to the drain of the eleventh NMOS transistor MN11, and the drain of the seventh NMOS transistor MN7 is connected to the gate of the ninth PMOS transistor MN9. The source of the eighth NMOS transistor MN8 is connected to the drain of the twelfth NMOS transistor MN12.

5. The high-voltage level conversion circuit based on a voltage-limited transistor according to claim 1, characterized in that, The first stacked voltage control module (4) includes a seventh PMOS transistor MN7 and a first NMOS transistor MN1, wherein the source of the seventh PMOS transistor MP7 is connected to the gate of the first NMOS transistor MN1, the gate of the first NMOS transistor MN1 is connected to the source of the seventh PMOS transistor MP7, and the source of the first NMOS transistor MN1 and the source of the seventh NMOS transistor MN7 are respectively connected to one end of the positive feedback module (6).

6. The high-voltage level conversion circuit based on a voltage-limited transistor according to claim 5, characterized in that, The second stacked voltage control module (5) includes an eighth PMOS transistor MP8 and a second NMOS transistor MN2, wherein the source of the eighth PMOS transistor MP8 is connected to the gate of the second NMOS transistor MN2, the gate of the eighth PMOS transistor MP8 is connected to the source of the second NMOS transistor MN2, and the sources of the second NMOS transistor MN2 and the eighth PMOS transistor MP8 are connected to the other end of the positive feedback module (6).

7. The high-voltage level conversion circuit based on a voltage-limited transistor according to any one of claims 1 to 6, characterized in that, The positive feedback module (6) includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, and a sixth PMOS transistor MP6. The gates of the third PMOS transistor MP3, the fourth PMOS transistor MP4, the fifth PMOS transistor MP5, and the sixth PMOS transistor MP6 are provided with VBIAS voltage by an external bias module. The gate of the second PMOS transistor MP2 is connected to the drain of the fifth PMOS transistor MP5, and the gate of the first PMOS transistor MP1 is connected to the drain of the sixth PMOS transistor MP6.

8. The high-voltage level conversion circuit based on a voltage-limited transistor according to any one of claims 1 to 6, characterized in that, A ninth PMOS transistor is also provided at the output terminal of the positive feedback module (6). The drain of the ninth PMOS transistor is connected to the drain of the eighth NMOS transistor MN8 in the second same level control module (3). The ninth PMOS transistor MP9, the eighth NMOS transistor MN8 in the second same level control module (3), the twelfth NMOS transistor MN12 in the first same level control module (2) and the fifteenth NMOS transistor MN15 in the input control module (1) constitute the voltage drop control of the output voltage. The switching transistors are stacked and connected in sequence.

9. The high-voltage level conversion circuit based on a voltage-limited transistor according to any one of claims 1 to 6, characterized in that, The operating voltage of the switching transistors used in each module is 1.8V, the input voltage is 1.8V, and the converted voltage is 3.3V.

10. A chip, comprising a chip body, characterized in that, The chip body also includes a high-voltage level conversion circuit based on a voltage-limited transistor as described in any one of claims 1 to 9.

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