NORD type flash memory manufacturing method and NORD type flash memory device

Abstract

The invention provides a manufacturing method of an NORD type flash memory and an NORD type flash memory device. The method comprises the following steps: providing a semiconductor substrate and forming a floating gate structure with a top sharp corner and a side wall; depositing and back-etching a first dielectric layer on the surface of the floating gate to form a dielectric side wall; cleaning and removing the medium side wall at the sharp corner to expose the sharp corner; depositing a second dielectric layer to form a tunneling oxide layer, so that the thickness at the top sharp corner is smaller than the thickness at the side wall; and finally depositing a conductive material to form a word line. According to the invention, the gradual change type tunneling oxide layer is constructed, the thin oxide layer at the sharp corner is used for improving the erasing efficiency, and the thick oxide layer at the side wall is used for inhibiting the leakage current from the substrate to the word line, so that the contradiction between the erasing efficiency and the device reliability in the NORD type flash memory is effectively solved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing, and in particular to a method for manufacturing NORD-type flash memory and a NORD-type flash memory device. Background Technology

[0002] With the rapid development and widespread adoption of embedded devices, a wide variety of embedded devices have been designed and developed. Flash memory, with its advantages of high performance, low power consumption, and non-volatility, has become an important data storage medium for various embedded devices. However, Flash technology is unique and complex, and its fabrication is challenging. In typical NOR Flash structures, especially those involving trench or stacked gate structures, the tunnel oxide structure between the word line (WL) and the floating gate (FG) is crucial for achieving high-efficiency Flash memory performance.

[0003] In traditional Flash memory structures, the tunneling oxide layer between the winding layer (WL) and the flash gate (FG) serves not only as a transport channel for electrons tunneling from the FG to the WL, but also as an insulator between the WL and the substrate (or the FG and the sidewalls) to prevent unintended leakage current. On the one hand, a thinner tunneling oxide layer can improve electron tunneling efficiency and enhance the device's erase performance by utilizing the tip discharge effect; however, on the other hand, an excessively thin tunneling oxide layer can significantly increase the leakage path from the substrate to the WL, or cause non-erasing leakage from the FG to the WL, especially when the WL is subjected to high voltage for erasing operations, this leakage phenomenon is particularly severe.

[0004] Current manufacturing processes typically employ the growth or deposition of oxide layers of uniform thickness, making it difficult to simultaneously achieve the requirements of "high tunneling efficiency at sharp corners" and "low leakage current at sidewalls / bottoms." Therefore, designing a structure to balance the trade-off between the erase efficiency and device leakage current of NORD-type flash memory—that is, effectively suppressing leakage current under high voltage while ensuring high erase efficiency at the FG sharp corners—is a pressing technical problem in the current semiconductor manufacturing field. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a method and device for manufacturing NORD type flash memory, so as to solve the contradiction between high erasure efficiency and low device leakage current in the prior art, and the problem that it is impossible to ensure device reliability under high voltage while improving erasure speed.

[0006] This invention provides a method for manufacturing NORD-type flash memory, the method comprising the following steps:

[0007] Step 1: Provide a semiconductor substrate and form a floating gate structure on the semiconductor substrate. The floating gate structure is formed by an etching process and has a top sharp corner and sidewalls.

[0008] Step 2: Deposit a first dielectric layer on the surface of the floating grid structure and etch the first dielectric layer to retain a portion of the first dielectric layer on the sidewall of the floating grid structure to form a dielectric sidewall;

[0009] Step 3: Perform a cleaning process to remove the medium sidewall located at the top sharp corner, exposing the top sharp corner of the floating grid structure;

[0010] Step 4: Deposit a second dielectric layer on the surface of the floating gate structure and the dielectric sidewall that expose the top sharp corner. The second dielectric layer covers the top sharp corner and the dielectric sidewall to form a tunneling oxide layer structure, wherein the thickness of the tunneling oxide layer structure located at the top sharp corner is less than the thickness of the tunneling oxide layer structure located at the sidewall. Step 5: Deposit a conductive material on the tunneling oxide layer structure to form word lines.

[0011] Preferably, in step one, forming the floating gate structure includes: sequentially stacking a floating gate material layer, an inter-electrode dielectric layer, and a control gate material layer on the semiconductor substrate; etching the control gate material layer and the inter-electrode dielectric layer to form an opening; forming a mask sidewall on the inner wall of the opening; using the mask sidewall as a mask, etching the floating gate material layer to form the floating gate structure, wherein the dielectric sidewall is formed on the sidewall of the floating gate structure exposed within the opening.

[0012] Preferably, in step two, the first dielectric layer is made of a high-temperature oxide material.

[0013] Preferably, in step two, the thickness of the deposited first dielectric layer ranges from 80 angstroms to 120 angstroms.

[0014] Preferably, in step two, the etching employs a full-area back etching process to remove the first dielectric layer located on top of the floating gate structure and on the surface of the semiconductor substrate, retaining the dielectric sidewall only on the sidewall.

[0015] Preferably, in step three, the cleaning process uses hydrofluoric acid solution for wet cleaning.

[0016] Preferably, in step three, the ratio of the hydrofluoric acid solution to water is in the range of 1:100 to 1:300.

[0017] Preferably, in step three, the thickness removed by the cleaning process ranges from 5 angstroms to 15 angstroms.

[0018] Preferably, in step four, the second dielectric layer is made of silicon oxide.

[0019] Preferably, in step four, the tunneling oxide layer structure formed is a gradient structure, which includes a thin oxide layer region located at the top corner and a thick oxide layer region located at the sidewall.

[0020] Preferably, in step four, the thickness of the thin oxide layer region ranges from 60 angstroms to 90 angstroms.

[0021] Preferably, in step four, the thickness of the thick oxide layer region ranges from 120 angstroms to 240 angstroms.

[0022] The present invention also provides a NORD type flash memory device, the device comprising a tunneling oxide layer structure manufactured according to any one of the preceding methods, the tunneling oxide layer structure being located between a floating gate structure and a word line, and the thickness of the tunneling oxide layer structure at the top corner of the floating gate structure being less than the thickness at the sidewall of the floating gate structure.

[0023] As described above, the method for manufacturing NORD-type flash memory of the present invention has the following beneficial effects:

[0024] By constructing a composite structure of "dielectric sidewall + capping layer" on the surface of the floating gate structure, a tunneling oxide layer with gradient thickness characteristics is formed. At the sharp corner of the floating gate, only the second dielectric layer constitutes a thin oxide layer (e.g., 60 Å to 90 Å). When an erase voltage is applied to the word line, the thin dielectric at this location enhances the FN tunneling effect or tip discharge effect, thereby significantly improving the erase efficiency of NORD flash memory. Simultaneously, at the sidewalls of the floating gate, the retained dielectric sidewalls and the second dielectric layer together constitute a thicker oxide layer (e.g., 120 Å to 240 Å). The thick dielectric at this location effectively increases the barrier width, blocking the leakage current path from the semiconductor substrate to the word line under high voltage. This invention cleverly decouples the constraint between erase speed and leakage current suppression, improving the overall performance and reliability of the device without sacrificing data retention characteristics. Attached Figure Description

[0025] Figure 1 The diagram shows a process flow diagram of the manufacturing method of the NORD type flash memory of the present invention.

[0026] Figure 2 The diagram shown is a schematic diagram of the structure after the floating gate material layer is patterned to form a floating gate structure in the manufacturing method of the NORD type flash memory of the present invention.

[0027] Figure 3 The diagram shows a schematic of the structure after the first dielectric layer is deposited on the surface of the floating gate structure in the manufacturing method of the NORD type flash memory of the present invention;

[0028] Figure 4The diagram shows a structural schematic after etching the first dielectric layer to form dielectric sidewalls in the manufacturing method of the NORD type flash memory of the present invention.

[0029] Figure 5 The diagram shows a structural schematic after the top sharp corner of the floating gate structure is exposed during the cleaning process in the manufacturing method of the NORD type flash memory of the present invention;

[0030] Figure 6 The diagram shows the structure after the tunneling oxide layer structure is formed in the manufacturing method of the NORD type flash memory of the present invention;

[0031] Figure 7 The diagram shown is a schematic representation of the device structure after word lines are formed in the manufacturing method of the NORD-type flash memory of the present invention. Detailed Implementation

[0032] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0033] like Figures 1 to 7 As shown, this invention provides a method for manufacturing a NORD-type flash memory. This method, through an optimized process flow, constructs a tunneling oxide layer with a gradient thickness on the surface of the floating gate structure. This achieves the beneficial effects of a thin oxide layer at the floating gate tip to improve erase efficiency, and a thick oxide layer on the sidewalls and bottom to suppress leakage current, all within the same device.

[0034] The manufacturing method includes step one: providing a semiconductor substrate 101, and forming a floating gate structure 103 on the semiconductor substrate 101. The floating gate structure 103 is formed by an etching process and has a sharp top corner and sidewalls. Figure 2 As shown, the semiconductor substrate 101 may include, but is not limited to, a silicon substrate, a germanium substrate, a silicon-germanium substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate. In other embodiments, the semiconductor substrate 101 may also be a III-V compound semiconductor (such as gallium arsenide, indium phosphide, gallium nitride, etc.) or a II-VI compound semiconductor. The semiconductor substrate 101 may be doped (e.g., p-type or n-type doped), and a dielectric layer 102 (e.g., gate oxide or tunnel oxide), as well as various isolation structures (e.g., shallow trench isolation, STI) and active regions (e.g., P-type wells or N-type wells) may be formed on or within the semiconductor substrate 101 to provide a basic electrical environment for the formation of subsequent devices. Figure 2As shown, the dielectric layer 102 is located on the surface of the semiconductor substrate 101, and the floating gate structure 103 is formed on the dielectric layer 102.

[0035] In some embodiments, forming the floating gate structure 103 in step one includes: sequentially stacking a floating gate material layer 103, an inter-electrode dielectric layer 104, and a control gate material layer 105 on a semiconductor substrate 101; etching the control gate material layer 105 and the inter-electrode dielectric layer 104 to form an opening; forming a mask sidewall 106 on the inner wall of the opening; using the mask sidewall 106 as a mask, etching the floating gate material layer 103 to form the floating gate structure 103, wherein the dielectric sidewall 107 is formed on the sidewall of the floating gate structure 103 exposed in the opening.

[0036] Specific reference Figure 2 First, a stacked structure is formed on a semiconductor substrate 101. This stacked structure includes a floating gate material layer 103 at the bottom, an inter-electrode dielectric layer 104 in the middle, and a control gate material layer 105 at the top. The floating gate material layer 103 can be formed by chemical vapor deposition (CVD), and the material can be doped polycrystalline silicon, amorphous silicon, a metallic material, or a conductive metal compound. The inter-electrode dielectric layer 104 can be a silicon oxide-silicon nitride-silicon oxide (ONO) stacked structure, or other high-k dielectric materials, such as hafnium oxide (HfO2), zirconium oxide (ZrO2), or combinations thereof, to isolate the control gate material layer 105 from the floating gate material layer 103. The control gate material layer 105 can be made of doped polycrystalline silicon. Subsequently, openings (trenches) are formed through the control gate material layer 105 and the inter-electrode dielectric layer 104 using photolithography and etching processes. Next, a mask sidewall 106 is formed on the sidewall of the opening. The mask sidewall 106 is typically made of silicon nitride or silicon oxynitride, and it acts as a hard mask to define the morphology of the subsequent floating gate structure 103. Using the mask sidewall 106 as a mask, the bottom floating gate material layer 103 is anisotropically etched to form a floating gate structure 103 with sharp top corners and steep sidewalls.

[0037] The manufacturing method includes step two: depositing a first dielectric layer on the surface of the floating gate structure 103 and etching the first dielectric layer to retain a portion of the first dielectric layer on the sidewall of the floating gate structure 103 to form a dielectric sidewall 107. The formation of this dielectric sidewall 107 forms the basis for constructing a gradient thickness, physically increasing the distance between the sidewall of the floating gate structure 103 and the subsequent word lines 109. Figure 3 As shown, a first dielectric layer is first conformally deposited on the surface of the structure containing the floating gate structure 103 and the interpolar dielectric layer 104. Figure 3 The outermost layer of the inner wall of the trench); then, the first dielectric layer is etched (e.g., full back etching) to form a layer like... Figure 4The structure shown is such that the first dielectric layer is removed at the bottom and top of the trench, but retained at the sidewalls; subsequently, etching (or cleaning) is performed to form a structure like... Figure 5 The structure shown allows for the final stable formation of a medium sidewall 107 on the sidewall of the floating grid structure 103.

[0038] In some embodiments, the first dielectric layer in step two is a high-temperature oxide (HTO) material. High-temperature oxides are typically generated by low-pressure chemical vapor deposition (LPCVD) at relatively high process temperatures (e.g., greater than 700 degrees Celsius) using a reaction of dichlorosilane (DCS) and nitrous oxide (N₂O). HTO films exhibit excellent step coverage and a dense film texture, enabling them to uniformly cover the sidewall surface of the floating gate structure 103. In other alternative embodiments, the first dielectric layer may also be an oxide deposited using tetraethyl orthosilicate (TEOS) as a precursor, a medium-temperature oxide (MTO), or a dielectric material such as silicon oxide or silicon oxynitride formed by atomic layer deposition (ALD), provided that it possesses good insulating properties and adhesion to the floating gate structure 103.

[0039] In some embodiments, the thickness of the first dielectric layer deposited in step two ranges from 80 angstroms to 120 angstroms. For example, the nominal thickness of the first dielectric layer can be set to 100 angstroms. This thickness range is chosen to balance the requirements of device miniaturization and breakdown voltage. An excessively thick first dielectric layer may lead to an increase in device size, while an excessively thin layer may not be able to effectively block electron tunneling under high fields.

[0040] In some embodiments, the etching in step two employs a full back etching process to remove the first dielectric layer located on top of the floating gate structure 103 and on the surface of the semiconductor substrate 101, retaining only the dielectric sidewalls 107 on the sidewalls. Full back etching (BlankEtch) refers to etching the entire wafer surface directly without using a photoresist mask. This process typically employs dry plasma etching with high anisotropy, utilizing the characteristic that the ion bombardment rate in the vertical direction is much greater than the chemical reaction rate in the horizontal direction to preferentially remove the first dielectric layer on the horizontal surface (top of the floating gate structure 103 and bottom of the trench), thereby achieving etching from the top of the floating gate structure 103 and the bottom of the trench. Figures 3 to 4 The structural transformation retains the medium sidewall 107 on the vertical sidewall.

[0041] The manufacturing method includes step three: performing a cleaning process to remove the dielectric sidewall 107 located at the top sharp corner, exposing the top sharp corner of the floating grid structure 103. This step corresponds to... Figure 5 Further processing of the structure shown. For example... Figure 5As shown, after the re-etching, the upper end of the dielectric sidewall 107 may remain and cover the sharp corners of the floating gate material layer 103, or a natural oxide layer may form on the surface, which can hinder the concentration of the electric field. The cleaning process in step three, through precisely controlled wet etching, not only removes the natural oxide layer and etching residues from the surface, but more importantly, performs a slight retraction trimming on the top of the dielectric sidewall 107, ensuring that the sharpest geometric feature points of the floating gate structure 103 are fully exposed to the subsequent deposition environment, preventing the sharp corners from being blunted.

[0042] In some embodiments, the cleaning process in step three uses a hydrofluoric acid solution for wet cleaning. Wet cleaning can be performed using a single-wafer cleaning machine or a tank cleaning machine. In addition to hydrofluoric acid (HF), the cleaning solution may also include a buffered oxide etchant (BOE), or a standard cleaning solution (SC-1) containing ammonia and hydrogen peroxide to remove particles, followed by HF treatment.

[0043] In some embodiments, the ratio of hydrofluoric acid solution to water in step three ranges from 1:100 to 1:300. For example, dilute hydrofluoric acid (DHF) with a dilution ratio of 1:200 is used. A high dilution ratio helps to reduce the etching rate, thereby enabling precise control over the removal thickness at the angstrom level.

[0044] In some embodiments, the thickness removed by the cleaning process in step three ranges from 5 to 15 angstroms. For example, the target removal amount is set to 10 angstroms. This cleaning amount has been experimentally verified to be sufficient to open the cover layer at sharp corners while keeping the loss of thickness of the main body of the media sidewall 107 within an acceptable range.

[0045] The manufacturing method includes step four, depositing a second dielectric layer 108 on the surface of the floating gate structure 103 and dielectric sidewall 107 that expose the top sharp corner, the second dielectric layer 108 covering the top sharp corner and dielectric sidewall 107 to form a tunneling oxide layer structure, wherein the thickness of the tunneling oxide layer structure located at the top sharp corner is less than the thickness of the tunneling oxide layer structure located at the sidewall.

[0046] like Figure 6As shown, the second dielectric layer 108 conformally covers the entire surface of the structure. Through this step-by-step formation, the final tunneling oxide layer structure is actually a composite layer structure: at the sharp corners of the floating gate structure 103, the insulating layer consists only of the newly deposited second dielectric layer 108, resulting in a thinner layer; while at the sidewalls of the floating gate structure 103, the insulating layer is formed by the combined superposition of the retained dielectric sidewalls 107 and the newly deposited second dielectric layer 108, resulting in a thicker layer. This structural design cleverly resolves the contradiction between erase efficiency and leakage current in NOR flash memory. The thinner sharp-corner oxide layer allows electrons to tunnel more easily from the floating gate structure 103 to the word line 109 during erase operations via FN tunneling or tip discharge effects, significantly improving the erase speed; while the thicker sidewall oxide layer effectively increases the barrier width between the semiconductor substrate 101 and the word line 109, preventing unexpected leakage or breakdown from the semiconductor substrate 101 to the word line 109 when a high voltage is applied to the word line 109, thereby enhancing the high-voltage reliability of the device.

[0047] In some embodiments, the second dielectric layer 108 in step four is made of silicon oxide. The second dielectric layer 108 can be formed using atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition (PECVD), high-density plasma-enhanced chemical vapor deposition (HDP-CVD), or in-situ water vapor generation (ISSG) oxidation processes. Preferably, the second dielectric layer 108 is made of the same material as the first dielectric layer (dielectric sidewall 107) (such as silicon oxide) to ensure good interface fusion and reduce interface defects. In some embodiments, the second dielectric layer 108 can also be annealed after deposition (e.g., annealed in a nitrogen, nitric oxide, or nitrous oxide atmosphere) to densify the film and repair defects.

[0048] In some embodiments, the tunneling oxide layer structure formed in step four is a gradient structure, which includes a thin oxide layer region at the top corner and a thick oxide layer region at the sidewall.

[0049] In some embodiments, the thickness of the thin oxide layer region in step four ranges from 60 angstroms to 90 angstroms. This thickness range is the optimal range for ensuring efficient erasure performance; if the thickness is too thick, the erasure speed will be reduced, and if it is too thin, the data retention characteristics will be affected.

[0050] In some embodiments, the thickness of the thick oxide layer region in step four ranges from 120 angstroms to 240 angstroms. This thickness is significantly greater than that of a conventional uniform tunneling oxide layer, providing a superior high-voltage insulation protection barrier for the device, capable of withstanding the high voltage on word line 109 during erase operations, and keeping the leakage current of the device at an extremely low level.

[0051] The manufacturing method includes step five: depositing conductive material on the tunneling oxide layer structure to form word lines 109. For example... Figure 7 As shown, conductive material fills the trenches between the floating gate structures 103 and covers the second dielectric layer 108 to form word lines 109. Word lines 109 serve as the control terminals of the memory cells. The conductive material may include doped polysilicon, metallic materials (such as tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), metal nitrides (such as titanium nitride (TiN), tantalum nitride (TaN), or metal silicides (such as tungsten silicide (WSix), cobalt silicide (CoSi), nickel silicide (NiSi)). The deposition method may employ chemical vapor deposition (CVD), physical vapor deposition (PVD), or electroplating. After forming the conductive material, a chemical mechanical planarization (CMP) process is typically performed to planarize the surface of the word lines 109, facilitating subsequent metal interconnect processes.

[0052] The present invention also provides a NOR flash memory device. This device includes a tunneling oxide layer structure manufactured according to any of the above embodiments, the tunneling oxide layer structure being located between the floating gate structure 103 and the word line 109, and the thickness of the tunneling oxide layer structure at the top corner of the floating gate structure 103 being less than the thickness at the sidewalls of the floating gate structure 103. Specifically, as... Figure 7 As shown, the device includes a semiconductor substrate 101, a floating gate structure 103 on the semiconductor substrate 101, and a word line 109 located on one side of the floating gate structure 103. A composite tunneling oxide layer is sandwiched between the floating gate structure 103 and the word line 109. This tunneling oxide layer is composed of dielectric sidewalls 107 and a second dielectric layer 108, exhibiting a gradient characteristic of thin corners and thick sidewalls. Due to its unique tunneling oxide layer configuration, this NOR flash memory device successfully decouples the long-standing conflicting performance indicators of erase speed and leakage current suppression while maintaining high storage density, demonstrating excellent durability and data retention characteristics. It is particularly suitable for embedded storage applications with high reliability requirements.

[0053] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0054] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a NORD-type flash memory, characterized in that, At least including: Step 1: Provide a semiconductor substrate and form a floating gate structure on the semiconductor substrate. The floating gate structure is formed by an etching process and has a top sharp corner and sidewalls. Step 2: Deposit a first dielectric layer on the surface of the floating grid structure and etch the first dielectric layer to retain a portion of the first dielectric layer on the sidewall of the floating grid structure to form a dielectric sidewall; Step 3: Perform a cleaning process to remove the medium sidewall located at the top sharp corner, exposing the top sharp corner of the floating grid structure; Step 4: Deposit a second dielectric layer on the surface of the floating gate structure and the dielectric sidewall that expose the top sharp corner. The second dielectric layer covers the top sharp corner and the dielectric sidewall to form a tunneling oxide layer structure, wherein the thickness of the tunneling oxide layer structure located at the top sharp corner is less than the thickness of the tunneling oxide layer structure located at the sidewall. Step 5: Deposit conductive material on the tunnel oxide layer structure to form word lines.

2. The method for manufacturing NORD-type flash memory according to claim 1, characterized in that: In step one, forming the floating gate structure includes: A floating gate material layer, an inter-electrode dielectric layer, and a control gate material layer are sequentially stacked on the semiconductor substrate. The control gate material layer and the inter-electrode dielectric layer are etched to form an opening; A mask sidewall is formed on the inner wall of the opening; Using the mask sidewall as a mask, the floating grid material layer is etched to form the floating grid structure, wherein the dielectric sidewall is formed on the sidewall exposed in the opening of the floating grid structure.

3. The method for manufacturing NORD-type flash memory according to claim 1, characterized in that: In step two, the first dielectric layer is made of a high-temperature oxide material.

4. The method for manufacturing NORD-type flash memory according to claim 1, characterized in that: In step two, the thickness of the first deposited dielectric layer ranges from 80 angstroms to 120 angstroms.

5. The method for manufacturing NORD-type flash memory according to claim 1, characterized in that: In step two, the etching employs a full-coverage etch-back process to remove the first dielectric layer located on top of the floating gate structure and on the surface of the semiconductor substrate, leaving only the dielectric sidewalls on the sidewalls.

6. The method for manufacturing NORD-type flash memory according to claim 1, characterized in that: In step three, the cleaning process uses hydrofluoric acid solution for wet cleaning.

7. The method for manufacturing NORD-type flash memory according to claim 6, characterized in that: In step three, the ratio of the hydrofluoric acid solution to water is in the range of 1:100 to 1:

300.

8. The method for manufacturing NORD-type flash memory according to claim 6, characterized in that: In step three, the thickness removed by the cleaning process ranges from 5 angstroms to 15 angstroms.

9. The method for manufacturing NORD-type flash memory according to claim 1, characterized in that: In step four, the second dielectric layer is made of silicon oxide.

10. The method for manufacturing NORD-type flash memory according to claim 1, characterized in that: In step four, the tunneling oxide layer structure formed is a gradient structure, which includes a thin oxide layer region located at the top corner and a thick oxide layer region located at the sidewall.

11. The method for manufacturing NORD-type flash memory according to claim 10, characterized in that: In step four, the thickness of the thin oxide layer region ranges from 60 angstroms to 90 angstroms.

12. The method for manufacturing NORD-type flash memory according to claim 10, characterized in that: In step four, the thickness of the thick oxide layer region ranges from 120 angstroms to 240 angstroms.

13. A NORD-type flash memory device, characterized in that, The device includes a tunneling oxide layer structure manufactured by the method according to any one of claims 1 to 12, the tunneling oxide layer structure being located between the floating gate structure and the word line, and the thickness of the tunneling oxide layer structure at the top corner of the floating gate structure being less than the thickness at the sidewall of the floating gate structure.

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