RRAM memory calculation array simulation model
By constructing a simulation model of an RRAM in-memory computing array, including PMOS turn-on transistors and RRAM cells in Verilog A models, the problem of inaccurate simulation and verification in existing technologies is solved, achieving accurate simulation and multi-bit storage of RRAM arrays, and supporting simulation and verification of in-memory computing chips.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- 58TH RES INST OF CETC
- Filing Date
- 2026-02-06
- Publication Date
- 2026-05-19
AI Technical Summary
The lack of existing technology for in-memory array simulation models based on RRAM devices makes it difficult to accurately and conveniently perform simulation verification of circuit designs.
A simulation model of an RRAM memory array is provided, comprising i rows and j columns of RRAM memory cells. Each cell consists of a PMOS turn-on transistor and an RRAM model described by Verilog A. Programming, reset, and readout operations are performed by controlling the voltages BL, WL, and SL. Current is collected by a subsequent current readout module to achieve accurate simulation.
It achieves accurate simulation of RRAM arrays, supports multi-configuration weight storage, and can accurately simulate the resistance state changes and read operations after programming and reset, and is used for simulation verification of in-memory computing chips.
Smart Images
Figure CN122065743A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and in particular to a simulation model of an RRAM (Real-Time RAM) storage array. Background Technology
[0002] The core of in-memory computing chips is to break through the "memory wall" and "power wall" under the von Neumann architecture, while adapting to the high parallelism and low latency requirements of AI and other scenarios, achieving a disruptive improvement in energy efficiency and bandwidth.
[0003] As a core device for in-memory computing, RRAM (Resistive Random Access Memory) has significant advantages over SRAM, DRAM, Flash and emerging PCM (Phase Change Memory) in terms of in-memory computing capabilities, energy efficiency, integration density and cost, and is especially suitable for core in-memory computing scenarios such as AI large model inference and edge computing.
[0004] However, there is still a lack of in-memory array simulation models based on RRAM devices, making it impossible to perform accurate and convenient simulation verification during circuit design. Summary of the Invention
[0005] The purpose of this invention is to provide an RRAM in-memory array simulation model to solve the problems in the background art.
[0006] To address the aforementioned technical problems, this invention provides an RRAM memory array simulation model, comprising i rows and j columns of RRAM memory units; where i and j are both integers not less than 1; Each RRAM memory unit consists of a PMOS gate and an RRAM model described in Verilog A. In each RRAM memory cell, the gate of the PMOS turn signal is connected to the WL potential, the source is connected to the BL potential, the substrate and drain are connected to the AN terminal of the RRAM model, and the CA terminal of the RRAM model is connected to the SL potential. The inputs of each RRAM storage unit are the voltages of BL, WL, and SL, and the output is the current flowing out of SL.
[0007] In one embodiment, the BL, WL, and SL terminals of the RRAM storage unit are powered by the front-end drive circuit, and the output current on SL is collected and read by the back-end current readout module.
[0008] In one implementation, the workflow of the RRAM in-memory array simulation model includes: Step 1: Change BLx to set the programming voltage of the RRAM memory cell in this column, where x = 0, 1, ..., j; Step 2: Lower the RRAM memory cell selected by WLy for a specific row, and perform programming operations on the RRAM memory cells selected by both BLx and WLy, where y = 0, 1, ..., i; Step 3: Change the BLx voltage to the reading voltage, read the current on SLy, and observe whether the read current meets expectations; Step 4: If the read current matches the expectation, switch to the next RRAM storage unit for programming; if it does not match the expectation, reset the unit, and then repeat steps 1 to 3. Step 5: Once all RRAM cells involved in the calculation have been programmed, a read operation is performed, and the data is processed by the subsequent circuitry.
[0009] In one implementation, the RRAM memory cell has a maximum resistance state and a minimum resistance state, with corresponding maximum and minimum read currents.
[0010] In one implementation, the RRAM storage array simulation model supports multi-configuration weighted storage, which is reflected in different readout currents to characterize multi-bit stored data.
[0011] In one implementation, the current, voltage states, and resistance weights of each terminal of the RRAM model in the RRAM storage unit are stored in a text document for simulation debugging, or the target resistance weights can be quickly set using the text document.
[0012] The present invention provides an RRAM in-memory computing array simulation model, which, based on simulation test stimuli, can accurately simulate the resistance changes of the RRAM array after programming and resetting, as well as the output current during read and storage operations. It can be used for simulation verification of in-memory computing chips based on RRAM arrays. Attached Figure Description
[0013] Figure 1 This is a schematic diagram of the structure of a single RRAM storage unit in Embodiment 1 of the present invention.
[0014] Figure 2 This is a schematic diagram of the RRAM in-memory array simulation model in Embodiment 2 of the present invention.
[0015] Figure 3 This is a schematic diagram of the simulation waveform of a single RRAM memory unit in Embodiment 1 of the present invention.
[0016] Figure 4 This is a schematic diagram of the simulation waveform of the first row array in Embodiment 2 of the present invention.
[0017] Figure 5 This is a schematic diagram of the simulation waveform of the second row array in Embodiment 2 of the present invention.
[0018] Figure 6 This is a flowchart of the array operation in an embodiment of the present invention. Detailed Implementation
[0019] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of the RRAM in-memory array simulation model proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, and are only used to facilitate and clarify the illustration of the embodiments of this invention.
[0020] Example 1: RRAM Memory Unit like Figure 1 As shown, this invention provides an RRAM memory cell, which can also be viewed as a 1×1 RRAM memory array simulation model. The memory cell includes a PMOS transistor and an RRAM model. The gate of the PMOS transistor is connected to the WL potential, the source is connected to the BL potential, and the substrate and drain are connected to the AN terminal of the RRAM model; the CA terminal of the RRAM model is connected to the SL potential.
[0021] The inputs to this memory-based computing unit are the voltages of BL, WL, and SL, and the output is the current flowing out of SL. The BL, WL, and SL terminals of this memory-based computing unit need to be powered by the preceding driver circuit, and the output current on SL is acquired and read by the subsequent current readout module.
[0022] like Figure 6 As shown, the workflow of the in-memory computing unit is as follows: Step 1: Change BL to set the programming voltage of the RRAM memory unit; Step 2: Lower WL to select the RRAM memory cell, and perform programming operations on the cell selected by both BL and WL; Step 3: Change the BL voltage to the reading voltage, read the current on SL, and observe whether the read current meets expectations; Step 4: If the read current matches the expectation, the read current is passed to the subsequent circuit for processing; if it does not match the expectation, the unit is reset, and then steps 1 to 3 are repeated. This memory cell has a maximum resistance state and a minimum resistance state, and therefore also has a corresponding maximum and minimum read current; Simulation results are as follows Figure 3 As shown.
[0023] Example 2: RRAM In-Memory Array Simulation Model like Figure 2 As shown, the present invention provides an RRAM in-memory computing array simulation model that can accurately adapt to the programming and reset storage data of a real RRAM array and can be used for simulation verification of in-memory computing chips.
[0024] The simulation model of the RRAM memory array consists of 2 rows and 3 columns of RRAM memory cells. Each RRAM memory cell consists of a PMOS turn-on transistor and an RRAM model described by Verilog A. In each RRAM memory cell: the gate of the PMOS turn signal is connected to the WL potential, the source is connected to the BL potential, and the substrate and drain are connected to the AN terminal of the RRAM model; the CA terminal of the RRAM model is connected to the SL potential.
[0025] Each RRAM storage unit receives the voltages of BL, WL, and SL as inputs and receives the current flowing out of SL as output. The BL, WL, and SL terminals of the array are powered by the preceding driver circuit, and the current output on SL is acquired and read by the subsequent current readout module.
[0026] like Figure 6 As shown, the workflow of the RRAM in-memory array simulation model is as follows: Step 1: Change BLx to set the programming voltage of the RRAM memory cell in this column, where x = 0, 1, ..., j; Step 2: Lower the RRAM memory cell selected by WLy for a specific row, and perform programming operations on the RRAM memory cells selected by both BLx and WLy, where y = 0, 1, ..., i; Step 3: Change the BLx voltage to the reading voltage, read the current on SLy, and observe whether the read current meets expectations; Step 4: If the read current matches the expectation, switch to the next RRAM memory cell for programming; if it does not match the expectation, reset the RRAM memory cell, and then repeat steps 1 to 3. Step 5: Once all RRAM memory units involved in the calculation have been programmed, a read operation is performed, and the subsequent circuitry processes the data. Each RRAM storage unit has a maximum resistance state and a minimum resistance state, and therefore also has a corresponding maximum and minimum read current; Each RRAM storage unit in the array can support multi-configuration weighted storage, which is reflected in different readout currents and can be used to characterize multi-bit stored data. The current, voltage states, and resistance weights of each terminal of the Verilog A module in the RRAM memory unit are stored in a text document for simulation debugging. The text document can also be used to quickly set the target resistance weights.
[0027] The array simulation waveforms in the first and second rows are as follows: Figure 4 and Figure 5 As shown.
[0028] The simulation model of this invention is based on simulation test stimuli and can accurately simulate the resistance changes of the RRAM in-memory array after programming and resetting. It can also accurately simulate the output current during read and in-memory operations and can be used for simulation verification of in-memory computing chips based on RRAM arrays.
[0029] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.
Claims
1. A simulation model for an RRAM (Real-Time RAM) computing array, characterized in that, It includes i rows and j columns of RRAM storage units; where i and j are both integers not less than 1; Each RRAM memory unit consists of a PMOS gate and an RRAM model described in Verilog A. In each RRAM memory cell, the gate of the PMOS turn signal is connected to the WL potential, the source is connected to the BL potential, the substrate and drain are connected to the AN terminal of the RRAM model, and the CA terminal of the RRAM model is connected to the SL potential. The inputs of each RRAM storage unit are the voltages of BL, WL, and SL, and the output is the current flowing out of SL.
2. The RRAM in-memory array simulation model as described in claim 1, characterized in that, The BL, WL, and SL terminals of the RRAM storage unit are powered by the front-end drive circuit, and the output current on SL is collected and read by the back-end current readout module.
3. The RRAM in-memory array simulation model as described in claim 1, characterized in that, The workflow of the RRAM in-memory array simulation model includes: Step 1: Change BLx to set the programming voltage of the RRAM memory cell in this column, where x = 0, 1, ..., j; Step 2: Lower the RRAM memory cell selected by WLy for a specific row, and perform programming operations on the RRAM memory cells selected by both BLx and WLy, where y = 0, 1, ..., i; Step 3: Change the BLx voltage to the reading voltage, read the current on SLy, and observe whether the read current meets expectations; Step 4: If the read current matches the expectation, switch to the next RRAM storage unit for programming; if it does not match the expectation, reset the unit, and then repeat steps 1 to 3. Step 5: Once all RRAM cells involved in the calculation have been programmed, a read operation is performed, and the data is processed by the subsequent circuitry.
4. The RRAM in-memory array simulation model as described in claim 1, characterized in that, The RRAM storage unit has a maximum resistance state and a minimum resistance state, with corresponding maximum and minimum read currents.
5. The RRAM in-memory array simulation model as described in claim 1, characterized in that, The RRAM storage array simulation model supports multi-configuration weighted storage, which is reflected in different readout currents, used to characterize multi-bit stored data.
6. The RRAM in-memory array simulation model as described in claim 1, characterized in that, The current, voltage states, and resistance weights of each terminal of the RRAM model in the RRAM storage unit are stored in a text document for simulation debugging, or the target resistance weights can be quickly set using this text document.