Artificial neural network processing method and system for providing semiconductor device parameters

Abstract

The embodiment of the invention relates to an artificial neural network processing method and system for providing semiconductor device parameters. A method includes providing a set of measured characteristic curve values for a semiconductor device having a control node and a current flow path through between a first current node and a second current node, the values including a measured current value through the current flow path, the current value is a function of a voltage value across the first and second current nodes, a set of control voltage levels is applied at the control node, an artificial neural network processing pipeline is applied to the set of measured characteristic curve values to obtain a set of reconstructed physical parameter values for the semiconductor device, a reconstructed characteristic curve value of the semiconductor device is calculated based on the reconstructed physical parameter value and the set of device modeling equations, a comparison of the reconstructed characteristic curve value and the measured characteristic curve value is performed, and an indicator of a variation of the physical value of the semiconductor device is provided.

Description

Cross-references to related applications

[0001] This application claims the benefit of Italian Application No. 102024000026370, filed on 22 November 2024, which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a method for calculating parameters of a known model of a physical system, such as an integrated circuit or a semiconductor device.

[0003] One or more embodiments can be applied to track the evolution of integrated circuit parameters over time, thereby facilitating the evaluation of device reliability. Background Technology

[0004] The performance of transistors in integrated circuits and electronic devices may vary during their lifetime, and this can affect the overall performance of the systems in which they are embedded.

[0005] Therefore, it is necessary to be able to detect the drift of transistor parameters with respect to design parameters.

[0006] One method for theoretically retrieving physical parameter values ​​from observations of system behavior is currently known as "inverse modeling." Existing methods for transistor inverse modeling are discussed in the following documents:

[0007] T. Patel: “Comparison of Class 1, Class 2 and Class 3 MOSFETs”, Course: Advanced Electronics, Department of Electrical Engineering, University of Texas at Arlington, 2014. Discusses existing models of transistors;

[0008] K. Jepson, “Learning Tool MOSFET Model: A Stepping Stone from Square-Law Model to BSIM4,” 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Karlsruhe, Germany, 2013, pp. 39-44, doi: 10.1109 / PATMOS.2013.6662153. This paper discusses a physics-based learning tool MOSFET model, which is presented based on three model parameters in each of two regions of a strongly inverted operation. The model is applicable to both small-signal parameter calculations in the analog bias region and large-signal current calculations during logic gate transients.

[0009] A. Lakhlef and A. Benfdila: “Drain Current Modeling in Silicon MOSFETs”, Proceedings of the 29th International Conference on Microelectronics - MIEL 2014, Belgrade, Serbia, 2014, pp. 213–216, doi: 10.1109 / MIEL.2014.6842124. This paper discusses the modeling of silicon MOSFETs across a wide channel range from submicron to nanometer MOSFETs, aiming to study the degradation and aging of MOSFET transistors used in VLSI integrated circuits. The model is expressed as current versus voltage over the full range of possible gate voltages and implies conformance to a unified current model.

[0010] C. Leonardi et al.: “A New Power MOSFET Model Including Parameter Variation with Temperature” Proceedings of the Second IEEE International Conference on Devices, Circuits and Systems in Caracas, 1998, 98, MOSFET 70th Anniversary and BJT 50th Anniversary, Margarita Island, Venezuela, 1998, pp. 261-266, doi: 10.1109 / ICCDCS.1998.705845. This paper discusses a new PSpice model designed to illustrate parameter variation with temperature, and reports static and dynamic verification tests on real-world devices at various operating temperatures ranging from 25 to 150 °C.

[0011] Massimo Spata et al. "Deep Learning Algorithms for Advanced Level 3 Inverse Modeling of Silicon Carbide Power MOSFET Devices." Seminar on Electronic and Communications Engineering (2023) discusses deep learning algorithms involving training deep architectures to predict device parameters based on the static behavior of the device, and in particular, deep learning methods for training physical parameters for retrieving a level 3 model of a power silicon carbide MOSFET (SiC power MOS).

[0012] JE Suseno et al., “Artificial Intelligence Techniques for SPICE Optimization of MOSFET Modeling,” Innovative Technologies in Intelligent Systems and Industrial Applications, Kuala Lumpur, Malaysia, 2009, pp. 76-80, doi: 10.1109 / CITISIA.2009.5224238. This paper discusses a new method for optimizing and verifying MOSFET electrical characteristic maps using artificial neural networks, comparing current-voltage (I-V) characteristic maps as desired data control model parameters between TCAD simulation and TSPICE modeling.

[0013] US2024 / 0119274A1 discusses a method for selecting initial weight vectors for convex optimization subproblems associated with neural networks having loss surfaces with non-convex network architectures.

[0014] Existing methods may suffer from one or more of the following drawbacks: they represent general-purpose systems and therefore cannot capture the complex behavior of modern transistor devices, such as transistors based on silicon carbide (SiC) technology; they suffer from reduced performance in terms of computational burden; and they have limited adaptability to various environments. Summary of the Invention

[0015] The purpose of one or more embodiments is to help overcome the above-mentioned disadvantages.

[0016] According to one or more embodiments, this objective can be achieved via a method having the features set forth in the following claims.

[0017] One or more embodiments may relate to a corresponding system, such as a microcontroller.

[0018] One or more embodiments may include a computer program product that can be loaded into the memory of at least one processing circuit (e.g., a computer) and includes software code portions for performing steps of a method when the product is run on at least one processing circuit. As used herein, references to such computer program products should be understood to be equivalent to references to computer-readable media including instructions for controlling a processing system to coordinate the implementation of the method according to one or more embodiments. The reference to “at least one computer” is intended to emphasize the possibility of implementing one or more embodiments in a modular and / or distributed manner.

[0019] The claims form an integral part of the technical teachings provided herein with reference to the embodiments.

[0020] One or more embodiments utilize a Siamese-like architecture of artificial neural networks to facilitate the computation of various parameters of complex transistor devices.

[0021] One or more embodiments facilitate in-operation diagnostics of electronic components, for example, via a microcontroller configured to perform methods according to this disclosure.

[0022] One or more embodiments demonstrate the ability to solve a specific problem even without time-consuming training.

[0023] One or more embodiments exhibit high adaptability due to the structure of the underlying artificial neural network. Attached Figure Description

[0024] One or more embodiments will now be described by way of non-limiting example only, with reference to the accompanying drawings, in which:

[0025] Figure 1 This is an example diagram illustrating a method for measuring the characteristic curves of electronic devices;

[0026] Figure 2 It is through Figure 1 Example graph illustrating the evolution of characteristic curves obtained by the method shown in the example;

[0027] Figure 3 This is a diagram illustrating the method according to this disclosure;

[0028] Figure 4 This is an example diagram of a fully connected artificial neural network (ANN);

[0029] Figures 5 to 11 It is the training and testing signal and based on the signal generated by the training and testing signal. Figure 3 An example diagram comparing the signals calculated using the parameters provided by the method illustrated in the example.

[0030] Unless otherwise stated, corresponding reference numerals and symbols in different figures usually refer to the corresponding parts.

[0031] The accompanying drawings are drawn to clearly illustrate relevant aspects of the embodiments and are not necessarily drawn to scale.

[0032] The edges of features drawn in the accompanying figures do not necessarily indicate the end of the feature's range. Detailed Implementation

[0033] In the following description, one or more specific details are shown to provide a thorough understanding of examples of embodiments described herein. Embodiments may be obtained without one or more specific details, or by utilizing other methods, components, materials, etc. In other instances, known structures, materials, or operations are not shown or described in detail so that certain aspects of the embodiments are not obscured.

[0034] The reference to "embodiment" or "an embodiment" within the framework of this specification is intended to indicate that a particular configuration, structure, or feature described with respect to an embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in one embodiment" that may appear in one or more places in this specification do not necessarily refer to one and the same embodiment.

[0035] Furthermore, in one or more embodiments, a particular conformation, structure, or feature may be combined in any suitable manner.

[0036] The references used herein are provided for convenience only and are not intended to limit the extent of protection or the scope of the embodiments.

[0037] For simplicity, the same reference numerals may be used in the following detailed description to designate nodes / lines in the circuit and signals that may appear at those nodes or lines.

[0038] Figure 1 This is an example diagram of a method for measuring the characteristic curves of electronic device 10;

[0039] like Figure 1 As shown, the example MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) includes: a substrate 20, which includes a base layer that may be n-type or p-type; a source channel 12 and a drain channel 14, which include two heavily doped regions (n-type or p-type, depending on the type of MOSFET) forming nodes through which current flows in the transistor; and a gate node G separated from the current flow channel (the region between the source and drain) by a thin insulating layer 18.

[0040] As mentioned above, the region between the source and drain where conduction occurs is called the channel, and the type of channel (n-channel or p-channel) depends on the doping of the source and drain regions. The channel can be reversed by applying a voltage to the gate. An insulating layer provides electrical isolation between the gate and the channel, allowing the gate voltage to control the channel conductivity without direct electrical contact.

[0041] like Figure 1 As illustrated, when a voltage is applied to gate 16 (e.g., via gate node G), it generates an electric field that modifies the charge carrier concentration in the channel, thereby allowing or preventing current from flowing between source node S and drain node D. This operating principle enables MOSFETs to be used as switches or amplifiers in a variety of electronic circuits in ways known per se.

[0042] Silicon carbide (SiC) is a wide-bandgap semiconductor suitable for operation at higher voltages, temperatures, and frequencies than silicon. This facilitates improved efficiency and reduced heat generation. Compared to conventional silicon MOSFETs, MOSFETs are becoming increasingly popular in advanced power electronics due to their enhanced performance in high-voltage, high-temperature, and high-frequency applications.

[0043] like Figure 1 As shown, the measuring device includes: a first adjustable voltage source 22 coupled to a node of transistor 10, which applies an adjustable voltage V across the gate and source nodes. GS And change the voltage drop V across the drain-source node. DS Detector 24, which is coupled across the drain node D and source node S of transistor 10, is configured to sense the drain current I. D The system 100, coupled to an adjustable voltage source 22 and a detector 24, is configured to drive the adjustable voltage source 22 to scan a finite number of values ​​of the adjustable voltage source 22 within a range of values ​​of interest for the performance of the transistor 10. The system 100 is also configured to store (e.g., in a digital file MC) the drain current value sensed via the current detector 24 and the corresponding applied voltage value V. GS V DS .

[0044] Figure 2 It is to complete the adjustment of voltage value V within a given range GS V DS A graph of the characteristic curves (drain-source voltage V on the vertical axis) of the data stored by system 100 (e.g., on a digital file MC) after a scan is applied to transistor device 10. DS The drain current I on the horizontal axis is expressed in volts. D In amperes, each curve indicates the gate-source voltage V. GS (Fixed level).

[0045] The evolution of this characteristic curve can be modeled using various specialized functions of the device's physical parameters. Simulation tools, such as those sold by Cadence Design Systems, Inc. under the trademark PSpice, utilize such functions to simulate the behavior of real transistor devices. The models used by the PSpice tool are called Level-1, Level-2, and Level-3 PSpice models, and they differ in terms of complexity and accuracy.

[0046] For simplicity, one or more embodiments are discussed below primarily with reference to the PSPICE Level-3 model; otherwise, it should be understood that this model selection is purely exemplary and not restrictive. One or more embodiments can conceptually operate with any Pspice model of a transistor device or any other simulator model.

[0047] The P-Spice level-3 model for transistors (e.g., MOSFETs) includes several parameters that define the characteristics and behavior of the device, including, for example: threshold voltage VT, which is the minimum gate-to-source voltage required to activate the conductive path between the source and drain terminals; saturation voltage VDSat, which is the voltage drop across the drain-source when the transistor enters saturation; transconductance KP: representing the change in drain current relative to the gate-to-source voltage, indicating how effectively the transistor can amplify; drain current Id: the drain-to-source current affected by the gate voltage and transistor characteristics; channel length L and width W, which define the dimensions of the transistor channel, where the aspect ratio W / L affects current drive capability and transconductance; bulk effect parameter γ: describing the effect of substrate bias on the threshold voltage, especially in bulk CMOS technology; current gain β: the product of transconductance KP and the channel aspect ratio W / L; surface potential. : The height of the potential barrier that causes the reverse charge in the channel.

[0048] As will be understood by those skilled in the art, the above list of parameters is non-exhaustive and covers some of the parameters that have the most impact on the behavior of transistor device 10.

[0049] For example, the parameters mentioned above enable the PSpice Level-3 model to accurately predict the electrical behavior of transistors under various operating conditions, making it suitable for circuit design and analysis in analog and digital applications.

[0050] The inventors have observed that by applying artificial neural network (ANN) processing to the measured characteristic curve MS, the values ​​of at least some of the PSPICE level-3 parameters (e.g., those listed above or others) of a particular transistor device under test 10 can be measured (indirectly).

[0051] like Figure 3 As illustrated, the system 30 for inverse modeling of transistor device 10 includes: providing a gate-source voltage V GS and drain-source voltage V DS The drain current I is a function of D The measurement set MS; preferably, preprocessing 31 is applied to the measurement set MS, for example, to generate a sample similar to... Figure 2 The example image 32 or reducing the number of feature curves in the data MS; applying artificial neural network (ANN) processing 34 to the measurement set MS to provide the transistor device 10 with a (e.g., level-3) set of model parameter values ​​VDsat, VT, γ, KP, W, L, measurement data MS sensed from transistor device 10; preferably, post-processing 36 is applied to the model parameter value set VDsat, VT, γ, KP, W, L, calculate the characteristic curve of transistor device 10 via a given transistor model (e.g., level-3), and perform a comparison between the calculated curve and the measured curve. Based on this comparison, provide a drift indicator D to user circuit U (e.g., a diagnostic circuit embedded in an integrated circuit or memory for storage). The drift indicator D indicates the evolution of the physical parameters of device 10 (over time).

[0052] For example, post-processing stage 36 can calculate the characteristic curve by interpolating the calculated model parameter values ​​VD, ..., VT into the following PSPICE level-3 equation:

[0053] For example, System 30 can reconstruct the model and parameters in approximately 60 milliseconds. Figure 3 As illustrated, the user circuit U can be configured to monitor parameters over time and issue an alarm signal if it detects degradation, thus allowing for timely intervention. This feature can be useful, for example, in the automotive sector or other safety-focused applications.

[0054] like Figure 3As illustrated, the applied ANN processing 34 includes an applied ANN processing pipeline comprising multiple ANN processing stages 340, 342, 343, 344, 346, 347, and 348, each configured to compute a parameter from a parameter set based on a daisy-chain topology. In the daisy-chain topology, the output of stage i 340 is provided as input to subsequent stages (i+1) along with training data TD (which includes measurement data MS and / or known physical parameter values ​​of the device under test).

[0055] As illustrated in this paper, ANN processing stages 340, 342, 343, 344, 346, 347, and 348 of the ANN processing chain 34 are also configured to perform “weight sharing”, which means that for each stage, the weights for training the i-th stage are initialized to the same values ​​reached at the end of the (i-1)-th previous stage in the training daisy chain.

[0056] As illustrated in this paper, the training phase of an ANN can advantageously employ a technique currently known as Jacobi regularization (which is known in itself) and has been discussed, for example, in the literature Hoffman, Judy et al., “Robust learning with Jacobi regularization” (2019), ArXiv, abs 1908.02729 and Cui, C. et al., “Generalization and improvement of Jacobi and Hessian regularizations” (2022), ArXiv, abs / 2212.00311.

[0057] As illustrated in this paper, the training dataset for the ANN processing stage 34 can even include a single set of measurements performed on a single transistor device 10, thereby reducing computational complexity and facilitating implementation on microcontrollers or other edge processing devices.

[0058] As illustrated herein, each of the plurality of ANN processing stages 340, 342, 343, 344, 346, 347, and 348 preferably includes a feedforward or convolutional neural network architecture.

[0059] like Figure 4As illustrated, the feedforward ANN processing stage 800 includes: an input layer 810 including input nodes x1, x2, ..., xK corresponding to input values ​​x1, x2, ..., xK; at least one hidden layer 820 including a hidden layer summation node Σ, which provides a weighted sum of input values ​​with respective weights w11, w22, ..., wk1, wk2, and hidden output nodes g(n11), g(n21), and g(n31); and an output layer 830 including a summation node Σ with corresponding weights from the previous layer and output nodes y1 and y2.

[0060] like Figure 3 and Figure 4 As illustrated, during the training phase, the first processing phase 340 receives the measurement set MS and applies ANN processing to it, such as regression using a feedforward network 800 or pattern recognition using a convolutional neural network; the weights w11, w22, ..., wk1, wk2 of the neurons in network 800 can be varied to minimize a loss function with respect to the training data TD, which can be expressed as: in Indicates predicted value and ground true value Differences between

[0061] In the example under consideration, still during the training phase, once the loss function is minimized, the first weight set W1 of the first processing phase 340 reaches a stable set of values ​​and provides an estimate of the first model parameter values ​​(e.g., the saturation voltage VDsat).

[0062] like Figure 3 As illustrated, still during the training phase, the second ANN processing phase 342 receives both the measurement data MS and the first model parameter estimate VDsat as input data and applies the second ANN processing to them. Preferably, the values ​​of the second weight set W2 in the second ANN processing phase 342 are set to be equal to the stable values ​​reached by the first weight set W1. After this, training is performed again to minimize the loss function (e.g., equal to the same aforementioned loss function in each of the ANN processing phases 34) until the second ANN processing phase provides the second model parameter estimate, such as the threshold voltage value Vt.

[0063] like Figure 3As illustrated, for each i-th ANN processing stage among the multiple ANN processing stages 340, 342, 343, 344, 346, 348, and 349, the training process discussed above regarding the first processing stage 340 and the second processing stage 342 is iterated. Therefore, the amount of input data provided to the first ANN processing stage 340 is minimal (including the measured data MS), while the amount of input data provided to the final ANN processing stage 349 is maximum (including the measured data and all estimated parameter values ​​VDsat, Vt, γ). KP, W, except for the last one L). Instead, each processing stage receives the same amount of data for initializing the weight values.

[0064] Given the aforementioned processing layers, the input layer of the final processing stage of the processing chain (e.g., 348) can have an input layer with a greater number of input nodes than the first layer of processing chain 34 (e.g., 340). Therefore, reshaping can be used to adapt the output of each i-th layer to become the input of each (i+1)-th layer of processing chain 34. Reshaping involves changing the shape of the tensor without altering the corresponding data, and is known from the documentation of software tools known, for example, under the name PyTorch 2.5 (e.g., see the function torch.reshape).

[0065] like Figure 3 As illustrated, at the end of the training phase, the final values ​​reached by the weights W1, W2, W3, W4, W5, W6, and W7 of each of the multiple ANN phases 340, 342, 343, 344, 346, 347, and 348 are stored (e.g., in memory as stored weights WG) for later use during the inference phase.

[0066] As illustrated in this paper, during the inference phase, the daisy-chain ANN processing structure is maintained such that each i-th layer receives the input measured data MS and the outputs of the previous (i-1) ANN processing stages, while weights are no longer shared, because each of the multiple ANN stages 340, 342, 343, 344, 346, 347, and 348 has a corresponding weight value loaded from memory equal to the stable weight values ​​W1, W2, W3, W4, W5, W6, and W7 acquired during the training phase.

[0067] In one or more embodiments, the method includes interrupting the application of Jacobi regularization during the inference phase, for example, because the weight values ​​are stable and no longer change.

[0068] In a first example, the method includes providing a set of measured characteristic curve values ​​for a semiconductor device having a control node and a current flow path between a first current node and a second current node, the measured characteristic curve values ​​including measured current values ​​through the current flow path, the measured current values ​​being a function of the voltage values ​​of the first and second current nodes; applying a set of control voltage levels at the control node of the semiconductor device; and applying an artificial neural network (ANN) processing pipeline to the set of measured characteristic curve values ​​to obtain a set of reconstructed physical parameter values ​​for the semiconductor device.

[0069] In the first example under consideration, the ANN processing pipeline includes multiple ANN processing stages, each having at least one corresponding ANN processing weight set, and the method further includes calculating the reconstruction characteristic curve values ​​of the semiconductor device based on the set of reconstruction physical parameter values ​​and the device modeling equation set; performing a comparison between the reconstruction characteristic curve values ​​and the measured characteristic curve values; and providing an indicator of the variation of the physical values ​​of the semiconductor device based on the performed comparison.

[0070] In the second example, each of the multiple ANN processing stages is trained to reconstruct different parameters in the set of physical parameter values.

[0071] In the third example, the method includes adjusting the weight values ​​of multiple corresponding ANN weight sets during a training phase, in which the weight values ​​of the multiple corresponding ANN weight sets are iteratively adjusted to minimize the loss function with respect to the training data provided thereto.

[0072] For example, during the training phase, multiple ANN processing phases are coupled according to a daisy chain topology, where the output of the i-th phase is provided as input along with the training data to the subsequent (i+1)-th phase.

[0073] In the fourth example, during the training phase, the i-th multiple weights of the corresponding i-th ANN processing phase are initialized to the (i-1)-th multiple weights of the (i-1)-th ANN phase in the daisy chain configuration, which have been adjusted as a result of training with the training data.

[0074] In the fifth example, the training data includes known values ​​of the measurement characteristic curves of semiconductor devices and their physical parameter values.

[0075] In the sixth example, the method includes applying a Jacobi regularization scheme during the training phase of the ANN processing phase in multiple ANN processing phases.

[0076] In the seventh example, the set of reconstructed physical parameter values ​​and the set of device modeling equations include P-spice parameters and equations, preferably P-SPICE level-3 parameters, including threshold voltage, saturation voltage, transconductance, drain current, channel length and width, bulk effect parameters, current gain and surface potential.

[0077] In the eighth example, applying ANN processing includes applying at least one fully connected (FC) artificial neural network processing stage to the measured set of characteristic curve values, and / or applying image representation processing to the measured set of characteristic curve values, thereby obtaining at least one image of the characteristic curve, and applying convolutional neural network (CNN) processing to the obtained at least one image.

[0078] In the ninth example, the computer program product includes instructions that, when the program is executed by a computer, cause the computer to perform the methods of the examples in this article.

[0079] In the tenth example, the adjusted weight values ​​of multiple ANN processing stages obtained using the methods illustrated herein are stored in a computer-readable medium.

[0080] In the eleventh example, a method of operating a processing device (e.g., a microcontroller), wherein the processing device is configured to perform artificial neural network (ANN) processing as a function of multiple ANN weight values, includes: accessing adjusted weight values ​​of multiple corresponding ANN weight value sets obtained using the methods illustrated herein, and performing artificial neural network (ANN) processing as weight values ​​of the accessed multiple corresponding ANN weight value sets.

[0081] In the twelfth example, the computer program product includes instructions that, when the program is executed by a processing device, cause the processing device to perform the methods of the examples herein.

[0082] In the thirteenth example, a computer-readable medium includes instructions that, when executed by a processing device, cause the processing device to perform the methods illustrated herein.

[0083] In the fourteenth example, a processing device includes memory circuitry storing: adjusted values ​​of a plurality of corresponding ANN weight value sets obtained using the methods illustrated herein, and instructions that, when executed in the processing device, cause the processing device to access the adjusted weight values ​​of the plurality of corresponding ANN weight value sets obtained using the methods illustrated herein, and to perform ANN processing as the adjusted values ​​of the plurality of corresponding ANN weight value sets.

[0084] For example, processing devices include microcontroller devices.

[0085] The inventors have tested various topologies for different ANN processing stages in the ANN processing pipeline 34, which are summarized in Tables I, II and III below, which can be found at the end of the specification.

[0086] Figures 5 to 11 It involves comparing the known parameter values ​​with the model parameter set VDsat, Vt, γ, A graph comparing the corresponding estimates of each model parameter in KP, W, and L.

[0087] Specifically:

[0088] Figure 5 The measured surface potential (Dashed line) A graph relative to the estimated values ​​of the same model parameters provided by the corresponding ANN processing stage 344 (in terms of the number of test datasets on the y-axis in any cell and the absolute values ​​of the parameters on the x-axis in any cell).

[0089] Figure 6 It is a graph of the measured volume threshold parameter γ (dashed line) relative to the estimated value of the same model parameter provided by the corresponding ANN processing stage 343 (in terms of the number of test datasets on the y-axis in any cell and the absolute value of the parameter on the x-axis in any cell).

[0090] Figure 7 It is a graph of the measured geometric factor β (dashed line) relative to the estimates of the same model parameters provided by the corresponding ANN processing stage (e.g., 342) (in terms of the number of test datasets on the y-axis in any cell and the absolute value of the parameters on the x-axis in any cell).

[0091] Figure 8 It is a graph of the measured transconductance KP (dashed line) relative to the estimated values ​​of the same model parameters provided by the corresponding ANN processing stage 346 (in terms of the number of test datasets on the ordinate axis in any cell and the absolute values ​​of the parameters on the abscissa axis in any cell).

[0092] Figure 9 It is a graph of the measured channel width W (dashed line) relative to the estimated values ​​of the same model parameters provided by the corresponding ANN processing stage 347 at different processing periods (in terms of the number of test datasets on the vertical axis in any cell and the absolute values ​​of the parameters on the horizontal axis in any cell).

[0093] Figure 10It is a graph of the measured channel length L (dashed line) relative to the estimated values ​​of the same model parameters provided by the corresponding ANN processing stage 348 (in terms of the number of test datasets on the ordinate axis in any cell and the absolute values ​​of the parameters on the abscissa axis in any cell).

[0094] Figure 11 It is a graph of the measured saturation voltage VDsat (dashed line) relative to the estimated values ​​of the same model parameters provided by the corresponding ANN processing stage 340 (in terms of the number of test datasets on the vertical axis in any cell, and the absolute values ​​of the parameters on the horizontal axis in any cell).

[0095] Table IV at the end of the description summarizes the experimental results of running the ANN processing pipeline using various configurations of the structure used for the ANN processing stage in the ANN processing pipeline.

[0096] In addition to the loss functions discussed earlier, different loss functions can be used. Table V at the end of the description summarizes the lower error values ​​achieved by estimating different parameter values ​​using different loss functions.

[0097] It should also be understood that the various individual implementation options illustrated throughout the accompanying drawings are not necessarily intended to be used in the same combinations illustrated in the drawings. Therefore, one or more embodiments may employ these (further non-mandatory) options individually and / or in different combinations relative to the combinations shown in the drawings.

[0098] Details and embodiments may be changed, even significantly changed, relative to what has been described by way of example only, without departing from the scope of protection, provided that the basic principles are not departed. The scope of protection is defined by the appended claims.

[0099] Table I: Architecture of the ANN processing pipeline when configured to apply regression processing to the input measurement data MS

[0100] Table II: The number of ANN processing stages is reduced relative to those listed in Table I when the ANN processing pipeline architecture is configured to apply regression processing to the input measurement data MS.

[0101] Table III: Architectures when an ANN processing pipeline is configured to apply convolutional neural network (CNN) processing to the input measurement data MS, where s = size, p = padding, and d = dilation.

[0102] Table IV

[0103] Table V

Claims

1. A method comprising: A set of measurement characteristic curve values ​​is provided for a semiconductor device having a control node and a current flow path between a first current node and a second current node. The measurement characteristic curve values ​​include measured current values ​​through the current flow path, the measured current values ​​being a function of voltage values ​​across the first current node and the second current node. A set of control voltage levels is applied at the control node of the semiconductor device. An artificial neural network (ANN) processing pipeline is applied to the measurement characteristic curve value set to obtain the reconstructed physical parameter value set of the semiconductor device. The ANN processing pipeline includes multiple ANN processing stages, each of which has at least one corresponding ANN processing weight set. The reconstruction characteristic curve value of the semiconductor device is calculated based on the set of reconstructed physical parameter values ​​and the set of device modeling equations. Compare the reconstructed characteristic curve value with the measured characteristic curve value; as well as Based on the comparison, an indicator of the variation of the physical values ​​of the semiconductor device is provided.

2. The method according to claim 1, wherein each of the plurality of ANN processing stages is trained to reconstruct different parameters in the reconstructed physical parameter value set.

3. The method according to claim 2, comprising: During the training phase, the weight values ​​of multiple corresponding ANN weight sets in the multiple ANN processing phases are adjusted iteratively to minimize the loss function with respect to the training data provided thereto. as well as During the training phase, each of the plurality of ANN processing phases is coupled according to a daisy-chain topology, in which the output of the i-th phase is provided as input along with the training data to the subsequent (i+1)-th phase.

4. The method of claim 3, wherein during the training phase, the i-th plurality of weights of the corresponding i-th ANN processing phase are initialized to the values ​​that the (i-1)-th plurality of weights of the (i-1)-th ANN phase in the daisy chain topology have been adjusted as a result of training using the training data.

5. The method of claim 3, wherein the training data includes known values ​​of the measurement characteristic curves of the semiconductor device and its physical parameter values.

6. The method according to claim 3, comprising: Jacobi regularization is applied during the training phase of the ANN processing phase in the plurality of ANN processing phases.

7. The method of claim 3, wherein the set of reconstructed physical parameter values ​​and the set of device modeling equations include P-spice parameters and equations.

8. The method of claim 7, wherein the P-spice parameters are P-spice level 3 parameters, including threshold voltage, saturation voltage, transconductance, drain current, channel length and width, bulk effect parameters, current gain and surface potential.

9. The method of claim 1, wherein applying the ANN processing pipeline comprises: At least one fully connected ANN processing stage is applied to the set of measured characteristic curve values; and / or Image representation processing is applied to the set of measured characteristic curve values ​​to obtain at least one image of the characteristic curve, and convolutional neural network processing is applied to the obtained at least one image.

10. A computer program product comprising instructions that, when executed by a computer, cause the computer to perform the following methods: A set of measurement characteristic curve values ​​is provided for a semiconductor device having a control node and a current flow path between a first current node and a second current node. The measurement characteristic curve values ​​include measured current values ​​through the current flow path, the measured current values ​​being a function of voltage values ​​across the first current node and the second current node. A set of control voltage levels is applied at the control node of the semiconductor device. An artificial neural network (ANN) processing pipeline is applied to the measurement characteristic curve value set to obtain the reconstructed physical parameter value set of the semiconductor device. The ANN processing pipeline includes multiple ANN processing stages, each of which has at least one corresponding ANN processing weight set. The reconstruction characteristic curve value of the semiconductor device is calculated based on the set of reconstructed physical parameter values ​​and the set of device modeling equations. Compare the reconstructed characteristic curve value with the measured characteristic curve value; as well as Based on the comparison, an indicator of the variation of the physical values ​​of the semiconductor device is provided.

11. The computer program product of claim 10, wherein each of the plurality of ANN processing stages is trained to reconstruct different parameters in the set of reconstructed physical parameter values.

12. The computer program product of claim 11, wherein the method comprises: During the training phase, the weight values ​​of multiple corresponding ANN weight sets in the multiple ANN processing phases are adjusted iteratively to minimize the loss function with respect to the training data provided thereto. as well as During the training phase, each of the plurality of ANN processing phases is coupled according to a daisy-chain topology, in which the output of the i-th phase is provided as input along with the training data to the subsequent (i+1)-th phase.

13. The computer program product of claim 11, wherein during the training phase, the i-th plurality of weights of the corresponding i-th ANN processing phase are initialized to values ​​that the (i-1)-th plurality of weights of the (i-1)-th ANN phase in the daisy chain topology have been adjusted as a result of training using the training data.

14. The computer program product of claim 11, wherein the training data includes known values ​​of the measurement characteristic curves of the semiconductor device and its physical parameter values.

15. The computer program product of claim 11, wherein the method comprises: Jacobi regularization is applied during the training phase of the ANN processing phase in the plurality of ANN processing phases.

16. The computer program product of claim 11, wherein the set of reconstructed physical parameter values ​​and the set of device modeling equations include P-spice parameters and equations.

17. The computer program product of claim 16, wherein the P-spice parameters are P-spice level 3 parameters, including threshold voltage, saturation voltage, transconductance, drain current, channel length and width, bulk effect parameters, current gain and surface potential.

18. The computer program product of claim 10, wherein the ANN processing pipeline comprises: Apply at least one fully connected ANN processing stage to the set of measured characteristic curve values; and / or Image representation processing is applied to the set of measured characteristic curve values ​​to obtain at least one image of the characteristic curve, and convolutional neural network processing is applied to the obtained at least one image.

19. A method comprising: A set of measurement characteristic curve values ​​is provided for a semiconductor device having a control node and a current flow path between a first current node and a second current node. The measurement characteristic curve values ​​include measured current values ​​through the current flow path, the measured current values ​​being a function of voltage values ​​across the first current node and the second current node. A set of control voltage levels is applied at the control node of the semiconductor device. An artificial neural network (ANN) processing pipeline is applied to the measurement characteristic curve value set to obtain the reconstructed physical parameter value set of the semiconductor device. The ANN processing pipeline includes multiple ANN processing stages, each of which has at least one corresponding ANN processing weight set. Each of the multiple ANN processing stages is trained to reconstruct different parameters in the reconstructed physical parameter value set. The reconstruction characteristic curve value of the semiconductor device is calculated based on the set of reconstructed physical parameter values ​​and the set of device modeling equations. Compare the reconstructed characteristic curve value with the measured characteristic curve value; Based on the comparison, an indicator of the variation of the physical values ​​of the semiconductor device is provided; During the training phase, the weight values ​​of multiple corresponding ANN weight sets in the multiple ANN processing phases are adjusted iteratively to minimize the loss function with respect to the training data provided thereto. Access the adjusted weight values ​​of the plurality of corresponding ANN weight value sets; as well as Perform ANN processing as a function of the accessed weight values ​​of the plurality of corresponding ANN weight value sets.

20. The method of claim 19, further comprising: During the training phase, each of the plurality of ANN processing phases is coupled according to a daisy-chain topology, in which the output of the i-th phase is provided as input along with the training data to the subsequent (i+1)-th phase.

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