Chip problem positioning method and device, equipment, storage medium and product

Abstract

The invention discloses a chip problem positioning method and device, equipment, a storage medium and a product. The method comprises the steps that a JTAG debugger is controlled to send a first preset instruction to a JTAG interface of a PCB where a to-be-tested chip is located so as to conduct a target test scan chain related to a suspected fault module in the to-be-tested chip; under the condition that the target test scan chain is conducted, the JTAG debugger is controlled to send a second preset instruction to a JTAG interface of a PCB where the to-be-tested chip is located, so that a preset controller in the to-be-tested chip is triggered to conduct self-testing on the suspected fault module, and a self-testing result is fed back to the JTAG debugger through the JTAG interface; and receiving a self-test result forwarded by the JTAG debugger, and carrying out fault positioning on the suspected fault module according to the self-test result. According to the invention, the fault module in the chip can be directly positioned on the printed circuit board, the chip does not need to be desoldered, and the positioning efficiency of the chip fault in the application field is greatly improved.

Description

Technical Field

[0001] This invention relates to the field of chip functional verification technology, and in particular to chip problem localization methods, apparatus, equipment, storage media and products. Background Technology

[0002] If a suspected problem is found in the chip during the mass production and delivery process, it is necessary to desolder the chip on the printed circuit board and re-ball it. After the chip is restored, a final test is conducted using a relevant testing system to identify the area of ​​failure within the chip and thus locate the problem.

[0003] However, the above methods require steps such as desoldering, ball repositioning, and final testing, resulting in a long positioning cycle and potentially damaging the failure site of the printed circuit board. Therefore, there is an urgent need for a more efficient and accurate method for locating chip problems. Summary of the Invention

[0004] This invention provides a chip problem localization method, apparatus, device, storage medium, and product to solve the problems in the prior art that require chip desoldering, ball repositioning, and final testing when locating problematic modules within a chip, resulting in long localization cycles and damage to the failure site.

[0005] According to one aspect of the present invention, a chip problem localization method is provided, applied to electronic devices, wherein the Joint Test Action Group (JTAG) interface of the printed circuit board (PCB) containing the chip under test is in an exposed state; the method includes: The JTAG debugger is controlled to send a first preset command to the JTAG interface of the PCB where the chip under test is located, so as to activate the target test scan chain related to the suspected fault module in the chip under test. When the target test scan chain is active, the JTAG debugger is controlled to send a second preset command to the JTAG interface of the PCB where the chip under test is located, so as to trigger the preset controller inside the chip under test to perform a self-test on the suspected fault module, and to feed back the self-test result to the JTAG debugger through the JTAG interface. Receive the self-test results forwarded by the JTAG debugger, and locate the suspected faulty module based on the self-test results.

[0006] According to another aspect of the present invention, a chip problem localization device is provided, characterized in that it is applied to an electronic device, wherein the Joint Test Action Group (JTAG) interface of the printed circuit board (PCB) where the chip under test is located is in an exposed state; the device includes: The first preset instruction sending module is used to control the JTAG debugger to send a first preset instruction to the JTAG interface of the PCB where the chip under test is located, so as to activate the target test scan chain related to the suspected fault module in the chip under test. The second preset instruction sending module is used to control the JTAG debugger to send a second preset instruction to the JTAG interface of the PCB where the chip under test is located when the target test scan chain is on, so as to trigger the preset controller inside the chip under test to perform a self-test on the suspected fault module, and to feed back the self-test result to the JTAG debugger through the JTAG interface. The fault location module is used to receive the self-test results forwarded by the JTAG debugger and locate the fault in the suspected fault module based on the self-test results.

[0007] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the chip problem localization method according to any embodiment of the present invention.

[0008] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions for causing a processor to execute and implement the chip problem localization method according to any embodiment of the present invention.

[0009] According to another aspect of the present invention, a computer program product is provided, the computer program product comprising a computer program that, when executed by a processor, implements the chip problem localization method according to any embodiment of the present invention.

[0010] The technical solution of this invention brings out the JTAG interface of the Joint Test Action Group on the printed circuit board (PCB) where the chip under test (DUT) is located, allowing the JTAG debugger to be directly connected to the PCB, providing a foundation for subsequent testing. By controlling the JTAG debugger to send a first preset command to the JTAG interface of the DUT PCB, the target test scan chain is activated, providing a basis for targeted testing of suspected faulty modules and avoiding the cost increase caused by comprehensive testing. With the target test scan chain activated, the JTAG debugger sends a second preset command to the JTAG interface of the DUT PCB, causing a preset controller within the DUT to perform a self-test on the suspected faulty module to obtain its internal state. Finally, the self-test results are received, and the suspected faulty module is located based on these results. This invention achieves direct location of suspected faulty modules within the DUT on the printed circuit board without desoldering the chip, protecting the failure scene and significantly improving the efficiency of fault location within the DUT in the application environment.

[0011] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a flowchart of a chip problem localization method provided in Embodiment 1 of the present invention; Figure 2 This is a hardware architecture diagram applicable to embodiments of the present invention; Figure 3 This is a flowchart of a chip problem localization method provided in Embodiment 2 of the present invention; Figure 4 This is a schematic diagram of a chip problem localization device according to Embodiment 3 of the present invention; Figure 5 This is a schematic diagram of the structure of an electronic device that implements the chip problem localization method of Embodiment 4 of the present invention. Detailed Implementation

[0014] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0015] It should be noted that the terms "first," "second," and "target," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0016] Example 1 Figure 1 This is a flowchart illustrating a chip problem localization method according to Embodiment 1 of the present invention. This embodiment is applicable to the localization of chip problems. The method can be executed by a chip problem localization device, which can be implemented in hardware and / or software and can be configured in an electronic device. Figure 1 As shown, the method includes: S101. Control the JTAG debugger to send a first preset command to the JTAG interface of the PCB where the chip under test is located, so as to activate the target test scan chain related to the suspected fault module in the chip under test.

[0017] In this embodiment, the chip under test (DUT) can be a chip already packaged on a printed circuit board (PCB), such as a PCB delivered by the customer. The Joint Test Action Group (JTAG) interface of the PCB containing the DUT is designed to be exposed, ensuring that the JTAG debugger can establish a connection with the PCB through the JTAG interface and trigger the DUT packaged on the PCB to open its internal test scan chain through relevant JTAG commands.

[0018] For example, such as Figure 2As shown, multiple pins conforming to the Joint Test Action Group Test Access Port (JTAG TAP) standard can be brought out on the PCB, putting the JTAG interface on the PCB in an exposed state. For example, the JTAG interface may include the phy_jtag_clk pin, phy_jtag_trst pin, phy_jtag_tms pin, phy_jtag_tdi pin, phy_jtag_tdo pin, and phy_jtag_oe pin; where the phy_jtag_clk pin is the clock pin, the phy_jtag_trst pin is the reset pin, the phy_jtag_tms pin is the test mode selection pin, the phy_jtag_tdi pin is the test data input pin, the phy_jtag_tdo pin is the test data output pin, and the phy_jtag_oe pin is the test data output enable pin.

[0019] In this embodiment, the electronic device configured with the chip problem localization device can serve as the host computer of the JTAG debugger. The electronic device can communicate with the JTAG debugger to control the JTAG debugger to send instructions to the JTAG interface of the PCB where the chip under test is located. The JTAG debugger can establish a JTAG bus connection with the chip under test packaged on the PCB through the JTAG interface, thereby transmitting instructions to the chip under test.

[0020] The first preset instruction can carry unique identification information of the target test scan chain, such as the segment number or address code of the target test scan chain, to activate the target test scan chain related to the suspected faulty module within the chip under test. The suspected faulty module can be any one of the storage module, communication module, or computing module within the chip under test; the suspected faulty module can be a module within the chip under test that is suspected of having a fault, as pre-identified by relevant personnel or a test platform. Different modules correspond to their own dedicated test scan chains, which are serial shift hardware links reserved by the chip during the design phase for Design for Test (DFT). The target test scan chain can be understood as the serial shift hardware link reserved by the chip under test during the design phase for DFT testing of the suspected faulty module.

[0021] S102. When the target test scan chain is on, control the JTAG debugger to send a second preset command to the JTAG interface of the PCB where the chip under test is located, so as to trigger the preset controller inside the chip under test to perform self-test on the suspected faulty module, and feed back the self-test result to the JTAG debugger through the JTAG interface.

[0022] In this embodiment, the second preset instruction may carry identification information that triggers the preset controller to perform self-testing on the suspected faulty module, as well as relevant configuration parameters (e.g., test algorithm selection code) to guide the preset controller to perform self-testing. The preset controller can be understood as a controller integrated during the chip design phase for performing self-testing on the suspected faulty module; generally, different modules within the chip correspond to different self-test controllers; the preset controller can automatically generate test data for testing the suspected faulty module and perform tests on the suspected faulty module according to the test algorithm to obtain the self-test results within the suspected faulty module. The test data can specifically be applied to… Figure 2 The DataSlice in the data path, after completing the self-test, allows the default controller to feed back the self-test results to the JTAG debugger via the JTAG interface on the PCB. The self-test results can include test results for suspected faulty modules and information such as the location of the fault.

[0023] S103. Receive the self-test results forwarded by the JTAG debugger, and locate the fault in the suspected faulty module based on the self-test results.

[0024] In this embodiment, the JTAG debugger forwards the self-test results to its host computer, which then determines whether the suspected faulty module has failed based on the self-test results, and, if a fault has occurred, accurately locates the fault location.

[0025] This invention provides a chip problem localization method. By bringing out the JTAG interface of the Joint Test Action Group (JTAG) on the printed circuit board (PCB) where the chip under test (DUT) is located, a JTAG debugger can be directly connected to the PCB, providing a foundation for subsequent testing. By controlling the JTAG debugger to send a first preset command to the JTAG interface of the DUT PCB, the target test scan chain is activated, providing a basis for targeted testing of suspected faulty modules and avoiding the cost increase caused by comprehensive testing. With the target test scan chain activated, the JTAG debugger sends a second preset command to the JTAG interface of the DUT PCB, causing a preset controller within the DUT to perform a self-test on the suspected faulty module to obtain its internal state. Finally, the self-test results are received, and the suspected faulty module is located based on these results. This invention enables the direct location of suspected faulty modules within the DUT on the printed circuit board without desoldering the chip, protecting the failure scene and significantly improving the efficiency of fault location within the DUT in the application field.

[0026] Example 2 Figure 3This is a flowchart of a chip problem localization method provided in Embodiment 2 of the present invention. This embodiment further refines the above embodiment. Figure 3 As shown, the method includes: S301. Set the preset pin of the chip under test to a preset level state; wherein, the preset pin is an enable pin related to the target test scan chain.

[0027] In this embodiment, the suspected faulty module is taken as a storage module (e.g., static random access memory). The target test scan chain can be a memory built-in self-test (MBIST) test chain related to static random access memory (SRAM). The preset pin can be an enable pin related to the target test scan chain, such as the TEST_EN pin, SCAN_ENABLE pin, and MBIST_MODE pin. For example, setting the preset pin to a high level switches the chip under test from the working mode to the test mode, providing a hardware foundation for subsequent testing; and changes the DFT test logic of the chip under test from silicon-etched but power-off to power-on and controllable, greatly improving the testing efficiency of problems within the chip under test at the user's site.

[0028] S302: Control the JTAG debugger to send a first preset command to the JTAG interface of the PCB where the chip under test is located, so as to switch the target segment insertion bit SIB in the chip under test to the preset state.

[0029] The Segment Insertion Bit (SIB) is a configuration bit that controls the on / off state of the target test scan chain corresponding to the suspected fault module in the chip under test; when the target SIB is in a preset state, the target test scan chain is turned on.

[0030] In this embodiment, the target SIB can control the on and off of the target test scan chain. For example, by switching the target SIB to the ON state (i.e., the preset state) through a first preset instruction, the target test scan chain is turned on.

[0031] S303. When the target test scan chain is on, control the JTAG debugger to send a second preset command to the JTAG interface of the PCB where the chip under test is located, so as to trigger the TMB controller inside the chip under test to perform a self-test on the suspected faulty module, and feed back the self-test result to the JTAG debugger through the JTAG interface.

[0032] In this embodiment, the suspected faulty module is a storage module, so the preset controller can be a Time- and Magnitude Bounded (TMB) controller. The TMB controller can use the generated test vectors to perform self-tests on each storage cell in the suspected faulty module (e.g., SRAM) and send back the self-test results.

[0033] Optionally, this step specifically involves: with the target test scan chain active, using the JTAG debugger to send a second preset instruction to the JTAG interface of the PCB where the chip under test is located, triggering the TMB controller to generate a test vector through its internal state machine; wherein, the test vector includes test data and expected data; based on the test data, using the TMB controller to perform self-tests on each memory unit within the suspected faulty module to obtain test result data; performing a bit-level comparison between the test result data and the expected data, determining the self-test result based on the comparison result, and transmitting the self-test result back.

[0034] In this embodiment, the second preset instruction can be the MBIST start instruction, such as the MBIST_RUN instruction. This instruction can wake up the TMB controller inside the chip under test to perform self-tests on each memory cell in the SRAM. The test vector can include test data and expected data. The test data can be written to each memory cell in the SRAM, and the expected data is the expected data corresponding to the test data, which can be used as verification data for self-testing. The test result data can be understood as the response value of the memory cell to the test data. For example, if the test data is 1, 1 is first written to a memory cell, and then the stored value of that memory cell is read. The read result is the test result data.

[0035] For example, by controlling the JTAG debugger to send an MBIST_RUN instruction to the JTAG interface of the PCB, the TMB controller receives the instruction and its internal state machine generates test data, addresses of various memory cells in the SRAM, and read / write enable data according to the test algorithm. Then, it performs read and / or write operations on each memory cell of the SRAM according to the addresses based on the corresponding read / write enable data, thereby obtaining test result data. The test result data is compared with the expected data at the bit level to obtain the comparison result, and the self-test result is determined based on the comparison result. The self-test result can be serially shifted to... Figure 2 The phy_jtag_tdo pin in the JTAG is then sent back to the JTAG debugger.

[0036] Optionally, the self-test results include fault flag information, fault address information, and fault bit information. The fault flag information can be identification information that reflects whether the suspected faulty module is faulty; the fault address information can be the address information where the fault occurred within the suspected faulty module (i.e., the test result data is inconsistent with the expected data); and the fault bit can be the failure bit where the fault occurred within the suspected faulty module.

[0037] S304: Receive the self-test results forwarded by the JTAG debugger, and locate the faulty module based on the self-test results.

[0038] Based on the self-test results, fault location is performed on the suspected faulty module. Specifically, this may include determining the suspected faulty module as a fault-free module in response to the fault flag information in the self-test results being a first preset flag information; determining the suspected faulty module as a faulty module in response to the fault flag information in the self-test results being a second preset flag information; and determining the location of the fault in the faulty module based on the fault address information and fault position information in the self-test results.

[0039] For example, a mapping table between addresses and modules within the chip under test can be pre-built in the host computer. This mapping table records the correspondence between address ranges and modules. Therefore, in the event of a suspected faulty module malfunction, the fault location within the suspected faulty module can be quickly and accurately located based on the self-test results forwarded by the JTAG debugger, according to the mapping table. For instance, the mapping table can record information such as the base address, storage capacity, and function or identifier of each module. When the fault flag information is a second preset standard information, the corresponding target address range can be found in the mapping table based on the fault address information in the self-test results. The identifier information corresponding to the target address range in the mapping table can then be used to determine which module is faulty. Furthermore, the fault bit information in the self-test results can be used to further determine which register and data line within the module is faulty, thus achieving precise location of the problem within the chip under test.

[0040] This invention first sets a preset pin of the chip under test (DUT) to a preset level state. Then, by controlling a JTAG debugger to send a first preset command to the JTAG interface of the PCB containing the DUT, the target SIB within the DUT is switched to the preset state. This enables direct activation of the target test scan chain within the DUT on the PCB, eliminating the need for desoldering the DUT. Next, by controlling the JTAG debugger to send a second preset command to the JTAG interface of the PCB containing the DUT, a self-test of the suspected faulty module is triggered by the internal TMB controller of the DUT. This allows for external triggering of the TMB controller without direct contact with the internal circuitry of the DUT, further ensuring the authenticity and accuracy of the test results. This invention transforms the traditional built-in self-test, which is only applicable to screening qualified chips, into fault location of modules within the packaged chip, achieving hourly-level location of faulty modules within the DUT and significantly shortening the location time.

[0041] Example 3 Figure 4 This is a schematic diagram of a chip problem localization device provided in Embodiment 3 of the present invention. The device is applied to electronic devices, and the Joint Test Action Group (JTAG) interface of the printed circuit board (PCB) where the chip under test is located is in an exposed state; for example... Figure 4 As shown, the device includes: a first preset command sending module 401, a second preset command sending module 402, and a fault location module 403.

[0042] The first preset instruction sending module is used to control the JTAG debugger to send a first preset instruction to the JTAG interface of the PCB where the chip under test is located, so as to activate the target test scan chain related to the suspected fault module in the chip under test. The second preset instruction sending module is used to control the JTAG debugger to send a second preset instruction to the JTAG interface of the PCB where the chip under test is located when the target test scan chain is on, so as to trigger the preset controller inside the chip under test to perform a self-test on the suspected fault module, and to feed back the self-test result to the JTAG debugger through the JTAG interface. The fault location module is used to receive the self-test results forwarded by the JTAG debugger and locate the fault in the suspected fault module based on the self-test results.

[0043] This invention provides a chip problem localization device. By bringing out the JTAG interface of the Joint Test Action Group (JTAG) on the printed circuit board (PCB) where the chip under test (DUT) is located, a JTAG debugger can be directly connected to the PCB, providing a foundation for subsequent testing. By controlling the JTAG debugger to send a first preset command to the JTAG interface of the DUT PCB, the target test scan chain is activated, providing a basis for targeted testing of suspected faulty modules and avoiding the cost increase caused by comprehensive testing. With the target test scan chain activated, the JTAG debugger sends a second preset command to the JTAG interface of the DUT PCB, causing a preset controller within the DUT to perform a self-test on the suspected faulty module to obtain its internal state. Finally, the self-test results are received, and the suspected faulty module is located based on these results. This invention achieves direct localization of suspected faulty modules within the DUT on the printed circuit board without desoldering the chip, protecting the failure scene and significantly improving the efficiency of fault localization within the DUT in the application field.

[0044] Optionally, the device further includes: The level setting module is used to set a preset pin of the chip under test to a preset level state before controlling the JTAG debugger to send the first preset instruction to the JTAG interface of the PCB where the chip under test is located; wherein, the preset pin is an enable pin related to the target test scan chain.

[0045] Optionally, the first preset instruction sending module is specifically used to: control the JTAG debugger to send a first preset instruction to the JTAG interface of the PCB where the chip under test is located, so as to switch the target segment insertion bit (SIB) in the chip under test to a preset state; wherein, the target SIB is a configuration bit that controls the on / off state of the target test scan chain corresponding to the suspected fault module in the chip under test; when the target SIB is in the preset state, the target test scan chain is turned on.

[0046] Optionally, the preset controller is a time- and amplitude-limited TMB controller; the second preset instruction sending module is specifically used to: when the target test scan chain is on, control the JTAG debugger to send a second preset instruction to the JTAG interface of the PCB where the chip under test is located, so as to trigger the TMB controller inside the chip under test to perform a self-test on the suspected faulty module, and to feed back the self-test result to the JTAG debugger through the JTAG interface; wherein, the TMB controller is used to perform a self-test on each memory unit in the suspected faulty module using the generated test vector, and to send back the self-test result.

[0047] Optionally, the second preset instruction sending module is specifically used for: when the target test scan chain is active, using the JTAG debugger to send a second preset instruction to the JTAG interface of the PCB where the chip under test is located, triggering the TMB controller to generate a test vector through its internal state machine; wherein, the test vector includes test data and expected data; based on the test data, using the TMB controller to perform self-tests on each memory unit in the suspected fault module to obtain test result data; performing a bit-level comparison between the test result data and the expected data, and determining the self-test result based on the comparison result.

[0048] Optionally, the self-test results include fault flag information, fault address information, and fault location information; the fault location module includes: The test result receiving unit is used to receive the self-test results forwarded by the JTAG debugger; The first positioning unit is used to determine the suspected fault module as a fault-free module in response to the fault flag information in the self-test result being the first preset flag information. The second positioning unit is used to determine the suspected fault module as a fault module in response to the fault flag information in the self-test result being the second preset flag information, and to determine the location of the fault in the fault module based on the fault address information and fault position information in the self-test result.

[0049] The chip problem localization device provided in the embodiments of the present invention can execute the chip problem localization method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the method execution.

[0050] Example 4 Figure 5 A schematic diagram of an electronic device 500 that can be used to implement embodiments of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0051] like Figure 5As shown, the electronic device 500 includes at least one processor 501 and a memory, such as a read-only memory (ROM) 502 and a random access memory (RAM) 503, communicatively connected to the at least one processor 501. The memory stores computer programs executable by the at least one processor. The processor 501 can perform various appropriate actions and processes based on the computer program stored in the ROM 502 or loaded into the RAM 503 from storage unit 508. The RAM 503 can also store various programs and data required for the operation of the electronic device 500. The processor 501, ROM 502, and RAM 503 are interconnected via a bus 504. An input / output (I / O) interface 505 is also connected to the bus 504.

[0052] Multiple components in electronic device 500 are connected to I / O interface 505, including: input unit 506, such as keyboard, mouse, etc.; output unit 507, such as various types of monitors, speakers, etc.; storage unit 508, such as disk, optical disk, etc.; and communication unit 509, such as network card, modem, wireless transceiver, etc. Communication unit 509 allows electronic device 500 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0053] Processor 501 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 501 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, digital signal processors (DSPs), and any suitable processor, controller, microcontroller, etc. Processor 501 performs the various methods and processes described above, such as chip problem localization methods.

[0054] In some embodiments, the chip problem localization method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 508. In some embodiments, part or all of the computer program may be loaded and / or installed on electronic device 500 via ROM 502 and / or communication unit 509. When the computer program is loaded into RAM 503 and executed by processor 501, one or more steps of the chip problem localization method described above may be performed. Alternatively, in other embodiments, processor 501 may be configured to perform the chip problem localization method by any other suitable means (e.g., by means of firmware).

[0055] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0056] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0057] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0058] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0059] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0060] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0061] This disclosure provides a computer program product, including a computer program that, when executed by a processor, implements the chip problem localization method provided in the above embodiments.

[0062] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0063] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method for locating chip problems, characterized in that, Applied to electronic devices, the Joint Test Action Group (JTAG) interface of the printed circuit board (PCB) containing the chip under test is in an exposed state; the method includes: The JTAG debugger is controlled to send a first preset command to the JTAG interface of the PCB where the chip under test is located, so as to activate the target test scan chain related to the suspected fault module in the chip under test. When the target test scan chain is active, the JTAG debugger is controlled to send a second preset command to the JTAG interface of the PCB where the chip under test is located, so as to trigger the preset controller inside the chip under test to perform a self-test on the suspected fault module, and to feed back the self-test result to the JTAG debugger through the JTAG interface. Receive the self-test results forwarded by the JTAG debugger, and locate the suspected faulty module based on the self-test results.

2. The chip problem localization method according to claim 1, characterized in that, Before controlling the JTAG debugger to send the first preset command to the JTAG interface of the PCB where the chip under test is located, the following steps are also included: Set a preset pin of the chip under test to a preset level state; wherein the preset pin is an enable pin associated with the target test scan chain.

3. The chip problem localization method according to claim 1, characterized in that, The control JTAG debugger sends a first preset command to the JTAG interface of the PCB where the chip under test is located, to activate the target test scan chain related to the suspected faulty module within the chip under test, including: The JTAG debugger is controlled to send a first preset command to the JTAG interface of the PCB where the chip under test is located, so as to switch the target segment insertion bit SIB in the chip under test to a preset state; wherein, the target segment insertion bit SIB is a configuration bit that controls the on / off state of the target test scan chain corresponding to the suspected fault module in the chip under test; when the target segment insertion bit SIB is in the preset state, the target test scan chain is turned on.

4. The chip problem localization method according to claim 1, characterized in that, The preset controller is a time- and amplitude-limited TMB controller; Specifically, the step of controlling the JTAG debugger to send a second preset command to the JTAG interface of the PCB where the chip under test is located, thereby triggering a preset controller inside the chip under test to perform a self-test on the suspected faulty module, including: The JTAG debugger is controlled to send a second preset command to the JTAG interface of the PCB where the chip under test is located, so as to trigger the TMB controller inside the chip under test to perform a self-test on the suspected faulty module; wherein, the TMB controller is used to perform a self-test on each memory unit in the suspected faulty module using the generated test vector, and to send back the self-test results.

5. The chip problem localization method according to claim 4, characterized in that, The step of controlling the JTAG debugger to send a second preset command to the JTAG interface of the PCB where the chip under test is located, to trigger the TMB controller inside the chip under test to perform a self-test on the suspected faulty module, including: The JTAG debugger sends a second preset instruction to the JTAG interface of the PCB where the chip under test is located, triggering the TMB controller to generate a test vector through its internal state machine; wherein, the test vector includes test data and expected data; Based on the test data, the TMB controller is used to perform self-tests on each storage unit in the suspected faulty module to obtain test result data. The test result data is compared with the expected data at the bit level, and the self-test result is determined based on the comparison result.

6. The chip problem localization method according to claim 5, characterized in that, The self-test results include fault flag information, fault address information, and fault bit information; The step of locating the suspected faulty module based on the self-test results includes: In response to the fault flag information in the self-test result being the first preset flag information, the suspected fault module is determined to be a fault-free module; In response to the fault flag information in the self-test result being the second preset flag information, the suspected fault module is identified as a fault module, and the location of the fault in the fault module is determined according to the fault address information and fault position information in the self-test result.

7. A chip problem location device, characterized in that, Applied to electronic devices, the Joint Test Action Group (JTAG) interface of the printed circuit board (PCB) containing the chip under test is in an exposed state; the device includes: The first preset instruction sending module is used to control the JTAG debugger to send a first preset instruction to the JTAG interface of the PCB where the chip under test is located, so as to activate the target test scan chain related to the suspected fault module in the chip under test. The second preset instruction sending module is used to control the JTAG debugger to send a second preset instruction to the JTAG interface of the PCB where the chip under test is located when the target test scan chain is on, so as to trigger the preset controller inside the chip under test to perform a self-test on the suspected fault module, and to feed back the self-test result to the JTAG debugger through the JTAG interface. The fault location module is used to receive the self-test results forwarded by the JTAG debugger and locate the fault in the suspected fault module based on the self-test results.

8. An electronic device, characterized in that, The electronic device includes: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the chip problem localization method according to any one of claims 1-6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that cause a processor to execute the chip problem localization method according to any one of claims 1-6.

10. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the chip problem localization method according to any one of claims 1-6.

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