Reference voltage generation circuit and microcontroller

Abstract

This application provides a reference voltage generation circuit and a microcontroller. The circuit includes a startup circuit, a power supply circuit, a bias circuit, and an output circuit. The startup circuit starts the reference voltage generation circuit; the power supply circuit is connected to the power supply voltage and provides a bias voltage to the bias circuit; the bias circuit provides a bias current independent of the power supply voltage to the output circuit. The bias circuit includes first and second NMOS transistors and a first resistor. The gates of the first and second NMOS transistors are connected, the source of the first NMOS transistor is grounded, and the source of the second NMOS transistor is connected to ground through the first resistor. Both the first and second NMOS transistors operate in the subthreshold region, and their drain-source voltages are higher than a predetermined voltage threshold. The bias current is equal to the current flowing through the first resistor; the output circuit generates a reference voltage based on the bias current. This application can provide a reference voltage independent of the power supply voltage, has a small size, and low power consumption.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design technology, and in particular to a reference voltage generation circuit and a microcontroller. Background Technology

[0002] Voltage references are used in most MCUs (Micro Controller Units) to provide a stable reference voltage to ensure circuit accuracy and consistency. MCUs typically require a low-power reference voltage that is independent of supply voltage and temperature.

[0003] A common solution is to create a bandgap reference, which utilizes the base-emitter voltage Vo of a transistor. BE The negative temperature coefficient, and the difference ΔV between the base-emitter voltages of two different transistors. BE The positive temperature coefficient, then, V BE With △V BE By adding them together with different weights, a voltage reference independent of temperature can be obtained.

[0004] The circuit structure of classic bandgap references is usually quite complex with many branches, resulting in high power consumption, making them unsuitable for low-power applications. They also require multiple transistors, consuming a large amount of circuit area. Furthermore, due to process limitations, transistors are not suitable for advanced processes, further increasing area and cost, and failing to meet the requirements for smaller size and lower power consumption. Summary of the Invention

[0005] The purpose of this application is to provide a reference voltage generation circuit and microcontroller that can provide a reference voltage independent of the power supply voltage, and has a small size and low power consumption.

[0006] One aspect of this application provides a reference voltage generation circuit. The reference voltage generation circuit includes a startup circuit, a power supply circuit connected to the startup circuit, a bias circuit connected to the output terminal of the power supply circuit, and an output circuit connected to the output terminal of the bias circuit. The startup circuit is used to start the reference voltage generation circuit; the power supply circuit is connected to a power supply voltage and is used to provide a bias voltage to the bias circuit; the bias circuit is used to provide a bias current to the output circuit that is independent of the power supply voltage; the bias circuit includes a first NMOS transistor, a second NMOS transistor, and a first resistor; the gate of the first NMOS transistor is connected to the gate of the second NMOS transistor; the source of the first NMOS transistor is grounded; the source of the second NMOS transistor is connected to ground through the first resistor; both the first and second NMOS transistors operate in the subthreshold region, and the drain-source voltages of the first and second NMOS transistors are higher than a predetermined voltage threshold; the bias current is equal to the current flowing through the first resistor; the output circuit is used to generate a reference voltage based on the bias current.

[0007] Furthermore, the width-to-length ratio of the channel of the second NMOS transistor is greater than that of the channel of the first NMOS transistor.

[0008] Furthermore, the bias circuit also includes a first PMOS transistor and a second PMOS transistor. The gate of the first PMOS transistor is connected to the gate of the second PMOS transistor. The sources of the first PMOS transistor and the second PMOS transistor are both connected to the output terminal of the power supply circuit. The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, and the gate of the first NMOS transistor is shorted to its drain. The drain of the second PMOS transistor is connected to the drain of the second NMOS transistor, and the gate of the second PMOS transistor is shorted to its drain.

[0009] Furthermore, the bias circuit also includes a seventh NMOS transistor, the gate of which is connected to the output terminal of the power supply circuit, and the source and drain of which are both connected to ground.

[0010] Furthermore, the output circuit includes a third PMOS transistor and a third NMOS transistor. The third PMOS transistor and the second PMOS transistor form a current mirror. The gate of the third PMOS transistor is connected to the gate of the second PMOS transistor. The source of the third PMOS transistor is connected to the output terminal of the power supply circuit. The drain of the third PMOS transistor is connected to the drain of the third NMOS transistor and serves as the output terminal of the output circuit for outputting the reference voltage. The gate and drain of the third NMOS transistor are shorted, and the source of the third NMOS transistor is grounded.

[0011] Furthermore, the bias circuit is configured to adjust the magnitude of the bias current generated by the bias circuit to be equal to the zero temperature coefficient current of the third NMOS transistor, so that the third NMOS transistor operates at the zero temperature coefficient operating point.

[0012] Furthermore, the startup circuit includes a fourth PMOS transistor, a fourth NMOS transistor, a fifth PMOS transistor, and a fifth NMOS transistor. The gate of the fourth PMOS transistor is connected to the gate of the fifth PMOS transistor. The sources of both the fourth and fifth PMOS transistors are connected to the power supply voltage. The drain of the fourth PMOS transistor is connected to the drain of the fourth NMOS transistor, and the gate and drain of the fourth PMOS transistor are shorted. The drain of the fifth PMOS transistor is connected to the drain of the fifth NMOS transistor. The gate of the fourth NMOS transistor is connected to the gate of the fifth NMOS transistor, and the sources of both the fourth and fifth NMOS transistors are connected to ground.

[0013] Furthermore, the power supply circuit includes a sixth PMOS transistor, a sixth NMOS transistor, and a seventh PMOS transistor. The gate of the sixth PMOS transistor is connected to the gate of the fifth PMOS transistor, the source of the sixth PMOS transistor is connected to the power supply voltage, and the drain of the sixth PMOS transistor is connected to the drain of the sixth NMOS transistor and serves as the output terminal of the power supply circuit. The gate and drain of the sixth NMOS transistor are shorted, and the source of the sixth NMOS transistor is grounded. The gate of the seventh PMOS transistor is connected to the drain of the fifth PMOS transistor, the source of the seventh PMOS transistor is connected to the power supply voltage, and the drain of the seventh PMOS transistor is connected to the drain of the sixth PMOS transistor.

[0014] Furthermore, the substrates of the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor are all connected to the bias voltage; the substrates of the fourth PMOS transistor, the fifth PMOS transistor, and the sixth PMOS transistor are all connected to the power supply voltage.

[0015] The reference voltage generation circuit of this application can provide a bias current independent of the power supply voltage by utilizing the difference between the gate-source voltages of the first NMOS transistor and the second NMOS transistor and the first resistor. When applied to the voltage reference of an MCU, it can operate within a sufficiently wide power supply voltage range of 1.8-5.5V, meeting the voltage reference design requirements of general-purpose MCUs.

[0016] The reference voltage generation circuit of this application reduces overall power consumption by operating the first NMOS transistor and the second NMOS transistor in the subthreshold region and using subthreshold bias current.

[0017] The reference voltage generation circuit of this application is implemented using a MOSFET instead of a transistor. Its simple structure saves circuit area, reduces cost, is applicable to advanced processes, and can meet the requirements of smaller size and lower power consumption.

[0018] Another aspect of this application provides a microcontroller. The microcontroller includes a reference voltage generation circuit as described above. Attached Figure Description

[0019] Figure 1 This is a partial structural schematic diagram of a reference voltage generation circuit according to an embodiment of this application.

[0020] Figure 2 This is a graph showing the relationship between the drain current and gate-source voltage of a MOSFET.

[0021] Figure 3 This is a schematic diagram of a reference voltage compensation circuit.

[0022] Figure 4 This is a schematic diagram of the overall structure of a reference voltage generation circuit according to an embodiment of this application.

[0023] Figure 5 The curves of the reference voltage output by the reference voltage generation circuit of one embodiment of this application at different temperatures are shown.

[0024] Figure 6 This is a schematic diagram showing the overall power consumption of a reference voltage generation circuit according to an embodiment of this application at different temperatures. Detailed Implementation

[0025] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses consistent with some aspects of this application as detailed in the appended claims.

[0026] The reference voltage generation circuit and microcontroller of this application will now be described in detail with reference to the accompanying drawings. Unless otherwise specified, the features of the following embodiments and implementations can be combined with each other.

[0027] Figure 1 A partial structural schematic diagram of a reference voltage generation circuit 100 according to one embodiment of this application is shown. Figure 1As shown, a reference voltage generating circuit 100 of one embodiment of this application includes a startup circuit 110, a power supply circuit 120 connected to the startup circuit 110, and a bias circuit 130 connected to the output terminal of the power supply circuit 120.

[0028] The startup circuit 110 can be used to start the reference voltage generation circuit 100. The power supply circuit 120 is connected to the power supply voltage VDD and can provide a bias voltage VDD1 to the bias circuit 130. The bias circuit 130 of this application can provide a bias current I independent of the power supply voltage VDD. bias .

[0029] The bias circuit 130 includes a first NMOS transistor MN1, a second NMOS transistor MN2, and a first resistor R1. The gate of the first NMOS transistor MN1 is connected to the gate of the second NMOS transistor MN2. The source of the first NMOS transistor MN1 is grounded to GND, and the source of the second NMOS transistor MN2 is connected to ground GND through the first resistor R1. Both the first NMOS transistor MN1 and the second NMOS transistor MN2 operate in the subthreshold region, and the bias current I... bias It is equal to the current I1 flowing through the first resistor R1, that is, I bias =I1.

[0030] The main working principle of the bias circuit 130 of this application will be described in detail below.

[0031] like Figure 1 As shown, based on the voltage at node A, the following relationship can be obtained:

[0032] V GS1 =V GS2 +I1×R1 (1)

[0033] Among them, V GS1 V represents the gate-source voltage of the first NMOS transistor MN1. GS2 R1 represents the gate-source voltage of the second NMOS transistor MN2, R1 represents the resistance value of the first resistor R1, and I1 represents the current flowing through the first resistor R1.

[0034] In addition, it is known that when the gate-source voltage V of the MOSFET... GS Below the turn-on threshold voltage V of the MOSFET TH V GS <V TH At this time, the MOSFET operates in the subthreshold region. When the MOSFET operates in the subthreshold region, there is still a small leakage current between the source and drain of the MOSFET. When the drain-source voltage V of the MOSFET... DS Above a predetermined voltage threshold, for example, V DS When the voltage is greater than 0.2V, there is an exponential relationship between the gate-source voltage and the leakage current of the MOSFET, as shown in the following formula:

[0035]

[0036] Among them, I D This represents the leakage current between the source and drain of the MOSFET (i.e., the drain current of the MOSFET). The aspect ratio of the channel of a MOSFET; I t This is a current that is related to temperature and process parameters, and is called the subthreshold current density; V T For thermal voltage; k is the Boltzmann constant; T is the absolute temperature; n is the subthreshold slope; μ is the carrier mobility; C ox q is the gate oxide capacitance of the MOSFET, and q is the amount of electron charge.

[0037] Transforming the above formula (2), we can obtain the following:

[0038]

[0039] Therefore, combining formulas (1) and (3), the voltage drop across the first resistor R1 can be obtained as follows:

[0040]

[0041] Therefore, the current I1 flowing through the first resistor R1 can be obtained as follows:

[0042]

[0043] The width-to-length ratio of the channel of the second NMOS transistor MN2 It must be greater than the width-to-length ratio of the channel of the first NMOS transistor MN1.

[0044] From formula (4), it can be clearly seen that the current I1 flowing through the first resistor R1 is a current independent of the power supply voltage VDD, and exhibits a positive temperature characteristic as the temperature increases. This current I1 flowing through the first resistor R1 serves as the bias current I generated by the bias circuit 130. bias .

[0045] The reference voltage generation circuit 100 of this application can generate a bias current I independent of the power supply voltage VDD by utilizing the difference between the gate-source voltages of the first NMOS transistor MN1 and the second NMOS transistor MN2 and the first resistor R1. bias .

[0046] Furthermore, the reference voltage generation circuit 100 of this application utilizes the first NMOS transistor MN1 and the second NMOS transistor MN2 to operate in the subthreshold region. Since the current in the subthreshold region is very small, the power consumption of the first NMOS transistor MN1 and the second NMOS transistor MN2 when operating in the subthreshold region is extremely low, thereby reducing the overall power consumption of the reference voltage generation circuit 100.

[0047] In some embodiments, the bias circuit 130 of this application further includes a first PMOS transistor MP1 and a second PMOS transistor MP2. The gate of the first PMOS transistor MP1 is connected to the gate of the second PMOS transistor MP2. The sources of the first PMOS transistor MP1 and the second PMOS transistor MP2 are both connected to the output terminal of the power supply circuit 120. The drain of the first PMOS transistor MP1 is connected to the drain of the first NMOS transistor MN1, and the gate and drain of the first NMOS transistor MN1 are short-circuited. The drain of the second PMOS transistor MP2 is connected to the drain of the second NMOS transistor MN2, and the gate and drain of the second PMOS transistor MP2 are short-circuited.

[0048] In some embodiments, the bias circuit 130 further includes a seventh NMOS transistor MN7. The gate of the seventh NMOS transistor MN7 is connected to the output terminal of the power supply circuit 120, and both the source and drain of the seventh NMOS transistor MN7 are connected to ground GND. The seventh NMOS transistor MN7 can act as a filter capacitor to filter the bias voltage VDD1 provided by the power supply circuit.

[0049] It is known that a MOSFET has a zero temperature coefficient (ZTC) operating point. By scanning the gate-source voltage of the MOSFET at different temperatures, the drain current can be obtained. Figure 2 This reveals the drain current I of an NMOS transistor. D With gate-source voltage V GS A diagram showing the relationship between changes. For example... Figure 2 As shown, for a MOSFET, there exists a gate-source voltage V corresponding to a zero temperature coefficient (ZTC) operating point. GS-ZTC When the gate-source voltage of a MOSFET is lower than its ZTC operating point gate-source voltage, i.e., V GS <V GS-ZTC At that time, the drain current I of the MOSFET D The MOSFET exhibits a proportional-to-temperature (PTAT) characteristic as its temperature changes; when the gate-source voltage V of the MOSFET changes... GS Gate-source voltage V higher than its ZTC operating point GS-ZTC V GS >V GS-ZTC The drain current I of the MOSFET DThe MOSFET exhibits complementary temperature absolute temperature (CTAT) characteristics with temperature variations. Therefore, at the gate-source voltage V0 of the MOSFET... GS Equal to its ZTC operating point gate-source voltage V GS-ZTC V GS =V GS-ZTC At this point, a zero-temperature-coefficient current can be obtained. When a MOSFET operates at its zero-temperature-coefficient operating point, the temperature coefficient of its voltage is 0, and the temperature coefficient of its current is also 0. For example, from... Figure 2 The graph shows the relationship between the gate-source voltage V at the ZTC operating point of the NMOS transistor. GS-ZTC It is approximately 1.24V.

[0050] Due to the bias current I provided by the bias circuit 130 bias It exhibits positive temperature characteristics; therefore, in order to reference voltage V ref Compensation is performed to generate a temperature-independent reference voltage V. ref This can provide a reference voltage compensation circuit. Figure 3 A schematic diagram of a reference voltage compensation circuit is shown. Figure 3 As shown, the reference voltage compensation circuit includes a current source and an NMOS transistor M1. The drain of the NMOS transistor M1 is connected to the current source, which provides an appropriate PATA current I to the drain of the NMOS transistor M1. PTAT As a bias current, thus causing the reference voltage V ref First-order temperature compensation can be achieved. The gate and drain of NMOS transistor M1 are shorted, the source of NMOS transistor M1 is grounded to GND, and the drain of NMOS transistor M1 is used to output the reference voltage V. ref .

[0051] It is known that the UICM (Unified Current Control Model) model can be used to understand... Figure 3 The condition for the bias ZTC operating point is given by the following expression:

[0052]

[0053] In the above formula, T represents absolute temperature; V ref (T) is Figure 3 Output temperature-dependent reference voltage; V refZ for Figure 3 The NMOS transistor M1 operates at the ZTC operating point, outputting a zero temperature coefficient voltage; I SQ The normalized current; β zThe ZTC slope is negatively correlated with temperature; ΔI d =I D -I DZ , among which, I D Let I be the drain current of NMOS transistor M1 at the current temperature. D That is, equal to the current I provided by the current source. PTAT ;I DZ It is the zero temperature coefficient current of NMOS transistor M1. This represents the width-to-length ratio of the NMOS transistor M1.

[0054] From formula (5) above, we can obtain the zero temperature coefficient voltage V at the ZTC operating point. refZ nearby, Figure 3 The reference voltage V output by the reference voltage compensation circuit ref It exhibits an approximately linear temperature dependence, and this dependence can be positive or negative, depending on the chosen ΔI. d .

[0055] If ΔI d >0, meaning the current I supplied by the current source PTAT If the bias current is located "after" the ZTC operating point, its derivative is positive or exhibits PTAT. If ΔI is chosen... d =0, meaning the current I supplied by the current source is... PTAT If the bias current is at the ZTC operating point, then the change is zero. If ΔI d <0, meaning the current I supplied by the current source PTAT If the bias current (i.e., the bias current) is located "before" the ZTC operating point, its derivative is negative or exhibits CTAT (temperature-dependent bias). Therefore, it can be concluded that MOSFETs operating near the ZTC operating point exhibit temperature-dependent behavior, showing either PTAT (temperature-dependent bias) or CTAT (temperature-dependent bias) characteristics. Thus, a suitable current I can be selected. PTAT Adjust the magnitude of (i.e., bias current) to achieve the desired effect. Figure 3 The reference voltage V output by the reference voltage compensation circuit in the middle ref (T) Dependence on temperature.

[0056] Based on the above conclusions, it is possible to base on Figure 3 The reference voltage compensation circuit is used to construct the output circuit of the reference voltage generation circuit 100 of this application.

[0057] Figure 4 A schematic diagram of the overall structure of a reference voltage generation circuit 100 according to one embodiment of this application is shown. Figure 4As shown, the reference voltage generating circuit 100 of one embodiment of this application further includes an output circuit 140. The output circuit 140 is connected to the output terminal of the bias circuit 130, and the bias circuit 130 can provide the output circuit 140 with a bias current I independent of the power supply voltage VDD. bias The output circuit 140 can be based on this bias current I. bias Generates a temperature-independent reference voltage V ref .

[0058] In some embodiments, the output circuit 140 includes a third PMOS transistor MP3 and a third NMOS transistor MN3.

[0059] The third PMOS transistor MP3 and the second PMOS transistor MP2 form a current mirror. The third PMOS transistor MP3 is used to replicate the current in the branch where the second PMOS transistor MP2 is located, that is, to replicate the bias current I provided by the bias circuit. bias The gate of the third PMOS transistor MP3 is connected to the gate of the second PMOS transistor MP2. The source of the third PMOS transistor MP3 is connected to the output terminal of the power supply circuit 120. The drain of the third PMOS transistor MP3 is connected to the drain of the third NMOS transistor MN3 and serves as the output terminal of the output circuit 140, used to output the reference voltage V. ref The gate and drain of the third NMOS transistor MN3 are shorted, and the source of the third NMOS transistor MN3 is grounded to GND.

[0060] Therefore, based on the above conclusion, the bias current I generated by the bias circuit 130 can be adjusted. bias The magnitude of the voltage is equal to the current at the zero-temperature coefficient operating point of the third NMOS transistor MN3, thus enabling the third NMOS transistor MN3 to operate at the zero-temperature coefficient operating point, thereby allowing the output circuit 140 to output a temperature-independent reference voltage V. ref .

[0061] Optionally, the substrates of the first PMOS transistor MP1, the second PMOS transistor MP2, and the third PMOS transistor MP3 are all connected to a bias voltage VDD1, thereby preventing current from directly conducting to ground from the source and drain terminals.

[0062] In some embodiments, the startup circuit 110 includes a fourth PMOS transistor MP4, a fourth NMOS transistor MN4, a fifth PMOS transistor MP5, and a fifth NMOS transistor MN5. The gate of the fourth PMOS transistor MP4 is connected to the gate of the fifth PMOS transistor MP5. The sources of both the fourth PMOS transistor MP4 and the fifth PMOS transistor MP5 are connected to the power supply voltage VDD. The drain of the fourth PMOS transistor MP4 is connected to the drain of the fourth NMOS transistor MN4, and the gate and drain of the fourth PMOS transistor MP4 are shorted. The drain of the fifth PMOS transistor MP5 is connected to the drain of the fifth NMOS transistor MN5. The gate of the fourth NMOS transistor MN4 is connected to the gate of the fifth NMOS transistor MN5, and the sources of both the fourth NMOS transistor MN4 and the fifth NMOS transistor MN5 are connected to ground GND.

[0063] In some embodiments, the power supply circuit 120 includes a sixth PMOS transistor MP6, a sixth NMOS transistor MN6, and a seventh PMOS transistor MP7. The gate of the sixth PMOS transistor MP6 is connected to the gate of the fifth PMOS transistor MP5, the source of the sixth PMOS transistor MP6 is connected to the power supply voltage VDD, and the drain of the sixth PMOS transistor MP6 is connected to the drain of the sixth NMOS transistor and serves as the output terminal of the power supply circuit 120. The gate and drain of the sixth NMOS transistor MN6 are shorted, and the source of the sixth NMOS transistor MN6 is grounded to GND. The gate of the seventh PMOS transistor MP7 is connected to the drain of the fifth PMOS transistor MP5, the source of the seventh PMOS transistor MP7 is connected to the power supply voltage VDD, and the drain of the seventh PMOS transistor MP7 is connected to the drain of the sixth PMOS transistor MP6.

[0064] Optionally, the substrates of the fourth PMOS transistor MP4, the fifth PMOS transistor MP5, and the sixth PMOS transistor MP6 are all connected to the power supply voltage VDD, thereby preventing current from directly conducting to ground from the source and drain terminals.

[0065] like Figure 4 As shown, when the bias circuit 130 starts working, the bias circuit 130 uses the first resistor R1 to change the bias current I. bias Simultaneously, the current mirror formed by the third PMOS transistor MP3 and the second PMOS transistor MP2, and the current mirror formed by the fourth NMOS transistor MN4 and the third NMOS transistor MN3, will bias the current I. bias The signal is replicated from node A to startup circuit 110. Due to the large resistance of the fifth NMOS transistor MN5, node B is gradually pulled up to the power supply voltage VDD, completing the startup process. The bias current I provided by bias circuit 130... bias Independent of the supply voltage VDD, the bias circuit 130 can provide a stable bias current I. biasTherefore, the bias voltage VDD1 generated by the power supply circuit 120 is stabilized at, for example, 1.6V. Subsequently, this bias voltage VDD1 is used as the power supply instead of the power supply voltage VDD to power the bias circuit 130, thus making the bias circuit 130 essentially unaffected by the power supply voltage VDD. Furthermore, by adjusting the bias current I generated by the bias circuit 130... bias The size of the value allows the third NMOS transistor MN3 to operate at its zero-temperature coefficient operating point, thus enabling the final output circuit 140 to output a reference voltage V that is independent of temperature and power supply voltage VDD. ref .

[0066] The reference voltage generation circuit 100 of this application can be used as a voltage reference for MCUs, and it features a wide operating voltage range and low power consumption.

[0067] Figure 5 This application discloses a reference voltage generation circuit 100 according to an embodiment of the present application, which outputs a reference voltage V at different temperatures. ref The curve is shown. Using the Cadence Spectre simulation tool, the reference voltage generation circuit 100 of this application was simulated, and the reference voltage V of the reference voltage generation circuit 100 of this application was obtained. ref The output results are as follows Figure 5 As shown. By Figure 5 This can indicate the reference voltage V ref There is first-order temperature compensation, therefore, the output reference voltage V can be reduced. ref Temperature coefficient.

[0068] Figure 6 A schematic diagram showing the overall power consumption of a reference voltage generation circuit 100 according to an embodiment of this application at different temperatures is provided. Figure 6 This refers to the power consumption generated when operating at a power supply voltage of 5V (VDD). Figure 6 It can be seen that, at room temperature, the overall power consumption of the reference voltage generation circuit 100 of this application is approximately 5μW; when operating at the lowest power supply voltage VDD of 1.8V, the overall power consumption of the reference voltage generation circuit 100 of this application is approximately 1.8μW. Therefore, it can be seen that the reference voltage generation circuit 100 of this application, compared to... Figure 1 and Figure 2 The related technologies exhibit low power consumption characteristics.

[0069] The reference voltage generation circuit 100 of this application can provide a bias current I independent of the power supply voltage VDD by utilizing the difference between the gate-source voltages of the first NMOS transistor MN1 and the second NMOS transistor MN2 and the first resistor R1. biasIn voltage references used in MCUs, it can operate within a sufficiently wide power supply voltage range of 1.8-5.5V (VDD), meeting the voltage reference design requirements of general-purpose MCUs.

[0070] The reference voltage generation circuit 100 of this application reduces overall power consumption by operating the first NMOS transistor MN1 and the second NMOS transistor MN2 in the subthreshold region and using a subthreshold bias current to provide a very small bias current for the zero temperature coefficient voltage. This is in contrast to... Figure 1 and Figure 2 Compared with related technologies, the power consumption of the reference voltage generation circuit 100 of this application is much smaller.

[0071] The reference voltage generation circuit 100 of this application is implemented by a MOSFET instead of a transistor. Its structure is simple, which can save circuit area, reduce cost, and make it applicable to advanced processes, thus meeting the requirements of smaller size and lower power consumption.

[0072] This application also provides a microcontroller. The microcontroller includes the reference voltage generation circuit 100 as described above.

[0073] The microcontroller of this application has beneficial technical effects that are substantially similar to those of the reference voltage generation circuit 100 described above, so it will not be repeated here.

[0074] The reference voltage generating circuit and microcontroller provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the reference voltage generating circuit and microcontroller in the embodiments of this application. The descriptions of the embodiments above are only for helping to understand the core ideas of this application and are not intended to limit this application. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the spirit and principles of this application, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A reference voltage generating circuit, characterized in that, It includes a startup circuit, a power supply circuit connected to the startup circuit, a bias circuit connected to the output terminal of the power supply circuit, and an output circuit connected to the output terminal of the bias circuit, wherein, The startup circuit is used to start the reference voltage generating circuit; The power supply circuit is connected to the power supply voltage and is used to provide bias voltage for the bias circuit; The bias circuit is used to provide a bias current to the output circuit that is independent of the power supply voltage. The bias circuit includes a first NMOS transistor, a second NMOS transistor, and a first resistor. The gate of the first NMOS transistor is connected to the gate of the second NMOS transistor. The source of the first NMOS transistor is grounded. The source of the second NMOS transistor is connected to ground through the first resistor. Both the first NMOS transistor and the second NMOS transistor operate in the subthreshold region, and the drain-source voltage of the first NMOS transistor and the second NMOS transistor is higher than a predetermined voltage threshold. The bias current is equal to the current flowing through the first resistor. The output circuit is used to generate a reference voltage based on the bias current.

2. The reference voltage generating circuit as described in claim 1, characterized in that, The width-to-length ratio of the channel of the second NMOS transistor is greater than that of the channel of the first NMOS transistor.

3. The reference voltage generating circuit as described in claim 1, characterized in that, The bias circuit further includes a first PMOS transistor and a second PMOS transistor. The gate of the first PMOS transistor is connected to the gate of the second PMOS transistor. The sources of the first PMOS transistor and the second PMOS transistor are both connected to the output terminal of the power supply circuit. The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, and the gate and drain of the first NMOS transistor are shorted. The drain of the second PMOS transistor is connected to the drain of the second NMOS transistor, and the gate and drain of the second PMOS transistor are shorted.

4. The reference voltage generating circuit as described in claim 3, characterized in that, The bias circuit also includes a seventh NMOS transistor, the gate of which is connected to the output terminal of the power supply circuit, and the source and drain of which are both connected to ground.

5. The reference voltage generating circuit as described in claim 3, characterized in that, The output circuit includes a third PMOS transistor and a third NMOS transistor. The third PMOS transistor and the second PMOS transistor form a current mirror. The gate of the third PMOS transistor is connected to the gate of the second PMOS transistor. The source of the third PMOS transistor is connected to the output terminal of the power supply circuit. The drain of the third PMOS transistor is connected to the drain of the third NMOS transistor and serves as the output terminal of the output circuit for outputting the reference voltage. The gate and drain of the third NMOS transistor are shorted, and the source of the third NMOS transistor is grounded.

6. The reference voltage generating circuit as described in claim 5, characterized in that, The bias circuit is configured to adjust the magnitude of the bias current generated by the bias circuit to be equal to the zero temperature coefficient current of the third NMOS transistor, so that the third NMOS transistor operates at the zero temperature coefficient operating point.

7. The reference voltage generating circuit as described in claim 5, characterized in that, The startup circuit includes a fourth PMOS transistor, a fourth NMOS transistor, a fifth PMOS transistor, and a fifth NMOS transistor. The gate of the fourth PMOS transistor is connected to the gate of the fifth PMOS transistor. The sources of both the fourth and fifth PMOS transistors are connected to the power supply voltage. The drain of the fourth PMOS transistor is connected to the drain of the fourth NMOS transistor, and the gate and drain of the fourth PMOS transistor are shorted. The drain of the fifth PMOS transistor is connected to the drain of the fifth NMOS transistor. The gate of the fourth NMOS transistor is connected to the gate of the fifth NMOS transistor, and the sources of both the fourth and fifth NMOS transistors are connected to ground.

8. The reference voltage generating circuit as described in claim 7, characterized in that, The power supply circuit includes a sixth PMOS transistor, a sixth NMOS transistor, and a seventh PMOS transistor. The gate of the sixth PMOS transistor is connected to the gate of the fifth PMOS transistor, the source of the sixth PMOS transistor is connected to the power supply voltage, and the drain of the sixth PMOS transistor is connected to the drain of the sixth NMOS transistor and serves as the output terminal of the power supply circuit. The gate and drain of the sixth NMOS transistor are shorted, and the source of the sixth NMOS transistor is grounded. The gate of the seventh PMOS transistor is connected to the drain of the fifth PMOS transistor, the source of the seventh PMOS transistor is connected to the power supply voltage, and the drain of the seventh PMOS transistor is connected to the drain of the sixth PMOS transistor.

9. The reference voltage generating circuit as described in claim 8, characterized in that, The substrates of the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor are all connected to the bias voltage; the substrates of the fourth PMOS transistor, the fifth PMOS transistor, and the sixth PMOS transistor are all connected to the power supply voltage.

10. A microcontroller, characterized in that, Includes a reference voltage generating circuit as described in any one of claims 1 to 9.

Images