Pixel circuit and display panel

Abstract

This invention discloses a pixel circuit and a display panel, including a pre-write unit and a driving unit. The driving unit includes a second transistor, a holding capacitor, and a pixel electrode. The second transistor is a dual-gate transistor, with its top gate coupled to a transfer signal line and its bottom gate connected to a control signal line. The first source and drain of the second transistor are coupled to the pre-write unit, and its second source and drain are coupled to one end of the holding capacitor and the pixel electrode. The ends of the holding capacitor and the pixel electrode furthest from the transistor are both coupled to a common signal line. The beneficial effects achieved by this invention are: by adjusting the adjustment signal voltage of the bottom gate of the second transistor, leakage current is suppressed, ensuring uniform screen brightness and extending product lifespan.

Description

Technical Field

[0001] This invention relates to the field of pixel display technology, and more specifically to a pixel circuit and display panel suitable for field sequence display. Background Technology

[0002] Field-sequential display technology uses time-division multiplexing to sequentially illuminate red, green, and blue backlights, utilizing the persistence of vision to achieve color display. Compared to traditional solutions using color filters, field-sequential display has the potential for higher light utilization, simpler structure, and lower cost.

[0003] However, field-sequence displays have extremely stringent requirements for driving timing. Traditional 1T1C or 1T2C pixel circuits can only turn on the backlight for display after all rows of data have been written and the liquid crystal molecules are fully deflected; otherwise, the image will become distorted. This results in the actual backlight illumination time being much shorter than one frame, leading to low time utilization and limiting the improvement of display brightness. To achieve sufficient brightness, it is necessary to increase the backlight power, which in turn affects the lifespan of the components and increases costs.

[0004] Furthermore, to meet the demands of high refresh rates, LTPS (Low Temperature Polycrystalline Silicon) TFTs, which have higher mobility, are often used as switching elements. However, LTPS TFTs have an inherent drawback of large off-state leakage current, which can cause changes in the voltage maintained on the pixel electrode, leading to problems such as flickering, crosstalk, and uneven brightness. Conventional leakage current solutions, such as adding an LDD (Lightly Doped Drain Region) structure, require additional photomasks and process steps, increasing manufacturing costs and affecting the pixel aperture ratio.

[0005] Therefore, there is an urgent need in the field for a pixel circuit solution that can effectively improve backlight time utilization and effectively suppress TFT leakage current in a simple and low-cost manner. Summary of the Invention

[0006] The purpose of this invention is to provide a pixel circuit and a display panel to solve the problems of low backlight time utilization and poor display uniformity caused by TFT off-state leakage current in existing field sequence display technology.

[0007] In a first aspect, the present invention provides a pixel circuit, including a pre-write unit and a driving unit. The driving unit includes: a second transistor, a holding capacitor, and a pixel electrode; The second transistor is a dual-gate transistor. The top gate of the second transistor is coupled to the transfer signal line, and the bottom gate of the second transistor is connected to the bottom gate adjustment signal. The bottom gate adjustment signal is input from the control signal line or the back gate adjustment signal line. The first source and drain of the second transistor are coupled to the pre-write cell, and the second source and drain of the second transistor are coupled to one end of the holding capacitor and the pixel electrode. The end of the holding capacitor and the pixel electrode away from the transistor are both coupled to a common signal line.

[0008] The core of the driving unit lies in the use of a dual-gate transistor. The top gate of this dual-gate transistor is controlled by a global transfer signal for data sharing and transfer; its bottom gate is connected to an independent control signal. By dynamically adjusting the voltage of this control signal, the threshold voltage of the dual-gate transistor can be changed, thereby achieving precise time-division and zone-division control of the device leakage current.

[0009] Furthermore, the pre-write unit includes: a first transistor and a pre-storage capacitor; The gate of the first transistor is coupled to the row gate signal line, the first source and drain of the first transistor are coupled to the data signal line, the second source and drain of the first transistor are coupled to one end of the pre-storage capacitor, and the other end of the pre-storage capacitor is coupled to the common signal line. Controlled by the row gate signal line, it is responsible for pre-storing the data signal into the pre-storage capacitor.

[0010] Furthermore, the pixel circuit also includes a back gate control unit, which includes a third transistor; The gate of the third transistor is coupled to the row gate signal line, the first source and drain of the third transistor are coupled to the bottom gate of the second transistor, and the second source and drain of the third transistor are coupled to the back gate control signal line.

[0011] Furthermore, the back gate control unit further includes: a first sustaining capacitor; One end of the third holding capacitor is coupled to the connection node between the first source / drain of the third transistor and the bottom gate of the second transistor, and the other end of the third holding capacitor away from the transistor is coupled to a common signal line.

[0012] Furthermore, the pixel circuit also includes a second back gate control unit, which further includes a fourth transistor; The gate of the fourth transistor is coupled to the second row gate signal line, the first source and drain of the fourth transistor are coupled to the data signal line, and the second source and drain of the fourth transistor are coupled to the bottom gate of the second transistor.

[0013] Furthermore, the second back-gate control unit also includes a second sustaining capacitor; One end of the second sustaining capacitor is coupled to the connection node between the second source / drain of the fourth transistor and the bottom gate of the second transistor, and the other end of the second sustaining capacitor is coupled to a common signal line.

[0014] Furthermore, the second back gate control unit also includes a third sustaining capacitor, the upper plate of which is the lower plate of the pre-storage capacitor, and the lower plate of the third sustaining capacitor is connected to the second source and drain of the fourth transistor.

[0015] Furthermore, the driving timing of the pixel circuit is configured as follows: During the backlight activation phase of frame N: When the row gate signal line switches to a low level, the first transistor is turned on, and the data signal line writes the data signal voltage of the N+1th frame to the pre-storage capacitor through the first transistor. The voltage of the first node is the data signal voltage. At this time, the control signal line is a first voltage, used to raise the threshold voltage of the second transistor to suppress leakage current; the row gate signal line jumps to a high level, the first transistor is turned off, and the backlight off stage of the Nth frame is entered; During the backlight off phase of frame N: When the control signal line switches to the second voltage, the transfer signal line switches to a low level, and the second transistor is turned on; The pre-storage capacitor transfers the data signal voltage of the N+1th frame to the holding capacitor and the pixel capacitor through the second transistor; after the transfer is completed, the transfer signal line jumps to a low level, the second transistor is turned off, and the backlight on stage of the N+1th frame is entered, and the pixel capacitor displays the display screen corresponding to the data signal voltage of the N+1th frame. During the backlight-on phase of the (N+1)th frame, the control signal line switches to the first voltage, the row gate signal line switches to a high level, the first transistor is turned on, and the data signal line writes the (N+2)th frame data signal voltage into the pre-storage capacitor through the first transistor.

[0016] The core timing sequence of the pixel circuit driving method described in this invention is as follows: while the backlight is lit up for display in the Nth frame, the data signal of the N+1th frame is written to the pre-storage capacitor through the pre-writing unit; in the dark field stage when the backlight is off, the pre-stored data signal is transferred to the pixel electrode through the driving unit. This "parallel" processing method achieves "full-field illumination", greatly improving the backlight time utilization rate.

[0017] In a second aspect, the present invention also provides a display panel including pixel circuitry as described in the first aspect. Control signal lines VC can be configured only in 1 / 2 or 1 / 3 rows of pixel circuitry across the entire panel.

[0018] The present invention has the following advantages: First, by using a driving timing of "parallel display and current frame writing", the present invention achieves full-field illumination, increasing the backlight time utilization rate from less than 50% in traditional solutions to nearly 100%. Under the same backlight power, it can significantly improve display brightness, or effectively reduce power consumption and cost under the same brightness.

[0019] Secondly, the present invention can also achieve efficient suppression of leakage current. By dynamically adjusting the voltage of the bottom gate of the second transistor, its threshold voltage can be actively and precisely controlled, thereby suppressing the leakage current to an extremely low level (such as reducing it from the level of 10^-12A to the level of 10^-14A) during the turn-off phase, ensuring the stability of pixel voltage and improving display uniformity.

[0020] Simultaneously, the control signal line level changes can be partitioned or adjusted pixel by pixel, which can effectively compensate for the TFT performance difference between the screen edge and center areas caused by the inherent characteristics of LTPS process, thereby eliminating the Mura phenomenon and obtaining a more uniform display.

[0021] Furthermore, this leakage current suppression scheme does not require changing the semiconductor layer doping structure of the TFT (such as adding LDD), nor does it require additional photomasks and complex processes, which helps to control manufacturing costs and improve pixel aperture ratio. Attached Figure Description

[0022] Figure 1 This is a circuit diagram of the present invention (Embodiment 1); Figure 2 This is a timing diagram of the present invention (Embodiment 1); Figure 3 This is a circuit diagram of the present invention (Embodiment 2); Figure 4 This is a circuit diagram of the present invention (Embodiment 3); Figure 5 This is a circuit diagram of the present invention (Embodiment 4); Figure 6 This is a timing diagram of the present invention (Example 3). Detailed Implementation

[0023] The present invention will be further described below with reference to the accompanying drawings, but the scope of protection of the present invention is not limited to the following description.

[0024] It should be noted that the orientation or positional relationship indicated by terms such as "left" and "right" is based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of the invention is usually placed during use, or the orientation or positional relationship in which those skilled in the art would conventionally understand it. Such terms are only for the convenience of describing the invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention.

[0025] It should be noted that, unless otherwise specified, the embodiments and features and technical solutions in the present invention can be combined with each other. Example 1

[0026] See Figure 1 This embodiment provides a pixel circuit, including a pre-write unit and a driving unit. The pre-write unit includes a first transistor M1 and a pre-storage capacitor Cst1. The gate of the first transistor M1 is coupled to the row gate signal line Scan, the source is coupled to the data signal line Data, and the drain is coupled to the first node A and one end of the pre-storage capacitor Cst1.

[0027] The driving unit includes a second transistor M2, a holding capacitor Cst2, and a liquid crystal capacitor Clc. The top gate of the second transistor M2 is connected to the transfer signal line Tran, and the bottom gate is connected to the control signal line VC. The source of the second transistor M2 is connected to the first node A, and the drain is connected to the second node B; the holding capacitor Cst2 and the pixel capacitor Clc are connected in parallel between the first node B and the common signal line Com.

[0028] See Figure 2 The driving timing of the pixel circuit is configured as follows: During the backlight activation phase of frame N: When the row gate signal line Scan switches to a low level, the first transistor M1 is turned on, and the data signal line Data writes the data signal voltage of the N+1th frame to the pre-storage capacitor Cst1 through the first transistor M1. The voltage of the first node A is the data signal voltage. At this time, the control signal line VC is a first voltage, and the configuration voltage range of the first voltage is -3V to -1V, which is used to raise the threshold voltage Vth of the second transistor M2 to suppress leakage current. Low level < 0V < high level.

[0029] During the backlight off phase of frame N: When the control signal line VC jumps to the second voltage, i.e., 0V, the transfer signal line Tran jumps to a low level, and the second transistor M2 is turned on. The pre-storage capacitor Cst1 transfers the data signal voltage of the N+1th frame to the holding capacitor Cst2 and the pixel capacitor Clc through the second transistor M2; after the transfer is completed, the transfer signal line Tran jumps to a low level, the second transistor M2 is turned off, and the backlight on stage of the N+1th frame is entered, and the pixel capacitor Clc displays the display screen corresponding to the data signal voltage of the N+1th frame. At this point, the voltage of the second node B is refreshed to the target voltage of the N+1th frame. VC=0V, and the threshold voltage Vth of the second transistor M2 returns to normal, without affecting its on-state performance.

[0030] During the backlight activation phase of the Nth frame, the Scan signal line transitions, turning on the first transistor M1. The data voltage of the N+1th frame is written from the Data signal line to the pre-storage capacitor Cst1, refreshing the potential of the first node A. At this time, the voltage signal of the control signal line VC is at a low potential (e.g., -2V), causing the threshold voltage Vth of the second transistor M2 to be forward biased, shifting the output characteristic curve to the right. Its off-state leakage current Ioff is significantly suppressed, thereby stabilizing the potentials of the first node A and the second node B to prevent leakage and ensuring stable display of the Nth frame.

[0031] During the backlight-on phase of the (N+1)th frame, the control signal line VC switches to the first voltage, the row gate signal line Scan switches to a high level, the first transistor M1 is turned on, and the data signal line Data writes the (N+2)th frame data signal voltage into the pre-storage capacitor Cst1 through the first transistor M1. The liquid crystal displays the (N+1)th frame under the voltage drive of the second node B.

[0032] This embodiment achieves effective control over the leakage current of the second transistor M2 by dynamically switching the control signal line VC. Example 2

[0033] See Figure 3 This embodiment adds a back grid control unit to the first embodiment to achieve pixel-level fine compensation.

[0034] The back-gate control unit includes a third transistor M3 and a first sustaining capacitor Cst3. The gate of the third transistor M3 is connected to the row gate signal line Scan, the source is connected to the back-gate control signal line i-Data, and the drain is connected to the bottom gate of the second transistor M2 and one end of the first sustaining capacitor Cst3. The other end of the first sustaining capacitor Cst3 is coupled to the common signal line Com.

[0035] Its driving timing is similar to that of Embodiment 1. The key difference is that during the backlight-on stage of the Nth frame: the row gate signal line Scan jumps to a low level, the first transistor M1 and the third transistor M3 are turned on, and the back gate control signal line i-Data writes the back gate control voltage to the first sustaining capacitor Cst3 through the third transistor M3. The back gate control voltage is the back gate voltage that needs to be compensated under different gray level voltages input to the row pixel circuit. The i-Data signal on the back gate control line synchronously writes a specific back gate control voltage into the bottom gate of the second transistor M2 through the third transistor M3, and it is maintained by the first sustaining capacitor Cst3. This back gate control voltage can be calculated based on the data relationship between the previous and next frames of the pixel, or through Demura data, thereby "tailor-making" the most suitable bottom gate voltage for each second transistor M2, achieving optimal leakage current suppression and greatly improving display uniformity. Example 3

[0036] See Figure 4 This embodiment adds a second back-gate control unit based on the first embodiment.

[0037] The second back-gate control unit also includes: a fourth transistor M4 and a second sustaining capacitor Cst4; The gate of the fourth transistor M4 is coupled to the second row gate signal line ScanB, the first source and drain of the fourth transistor M4 are coupled to the data signal line Data, and the second source and drain of the fourth transistor M4 are coupled to the bottom gate of the second transistor M2; one end of the second sustaining capacitor Cst4 is coupled to the connection node between the second source and drain of the fourth transistor M4 and the bottom gate of the second transistor M2, and the other end of the second sustaining capacitor Cst4 is coupled to the common signal line Com.

[0038] See Figure 6 Its driving timing is similar to that of Embodiment 1. The key difference is that during the backlight-on stage of the Nth frame, both the row gate signal line Scan and the second row gate signal line ScanB jump to a low level, the first transistor M1 and the third transistor M3 are turned on, and the data signal line Data writes voltage to the second sustaining capacitor Cst3 through the third transistor M3, so that the bottom gate of the second transistor M2 obtains voltage. This embodiment can save signal lines compared to Embodiment 2. Example 4

[0039] See Figure 5 This embodiment is based on embodiment three, but with adjustments to the structural configuration of the sustaining capacitor; The gate of the fourth transistor M4 is coupled to the second row gate signal line ScanB, the first source and drain of the fourth transistor M4 are coupled to the data signal line Data, and the second source and drain of the fourth transistor M4 are coupled to the bottom gate of the second transistor M2; the third sustaining capacitor Cst5 has its upper plate being the lower plate of the pre-storage capacitor Cst1, and its lower plate being connected to the second source and drain of the fourth transistor M4.

[0040] The third sustaining capacitor Cst5 and the pre-storage capacitor Cst1 share the same capacitor plate. In the light emission direction, the third sustaining capacitor Cst5 and the pre-storage capacitor Cst1 partially overlap, which can improve the aperture ratio.

[0041] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

[0042] The above embodiments only illustrate preferred implementation methods, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of this invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from this invention, and these all fall within the protection scope of this invention.

Claims

1. A pixel circuit, characterized in that, include: Pre-write unit and drive unit; The driving unit includes: a second transistor (M2), a holding capacitor (Cst2), and a pixel electrode (Clc). The second transistor (M2) is a dual-gate transistor. The top gate of the second transistor (M2) is coupled to the transfer signal line (Tran), and the bottom gate of the second transistor (M2) is connected to the bottom gate adjustment signal. The first source and drain of the second transistor (M2) are coupled to the pre-write cell, and the second source and drain of the second transistor (M2) are coupled to one end of the holding capacitor (Cst2) and the pixel electrode (Clc). The ends of the holding capacitor (Cst2) and the pixel electrode (Clc) away from the transistor are both coupled to the common signal line (Com).

2. The pixel circuit according to claim 1, characterized in that, The pre-write unit includes: a first transistor (M1) and a pre-storage capacitor (Cst1). The gate of the first transistor (M1) is coupled to the row gate signal line (Scan), the first source and drain of the first transistor (M1) are coupled to the data signal line (Data), the second source and drain of the first transistor (M1) are coupled to one end of the pre-storage capacitor (Cst1), and the other end of the pre-storage capacitor (Cst1) is coupled to the common signal line (Com).

3. The pixel circuit according to claim 2, characterized in that, The pixel circuit also includes a back gate control unit, which includes a third transistor (M3). The gate of the third transistor (M3) is coupled to the row gate signal line (Scan), the first source and drain of the third transistor (M3) are coupled to the bottom gate of the second transistor (M2), and the second source and drain of the third transistor (M3) are coupled to the back gate control signal line (i-Data).

4. The pixel circuit and display panel according to claim 3, characterized in that, The back gate control unit also includes: a first sustaining capacitor (Cst3). One end of the third holding capacitor (Cst3) is coupled to the connection node between the first source and drain of the third transistor (M3) and the bottom gate of the second transistor (M2), and the other end of the third holding capacitor (Cst3) away from the transistor is coupled to the common signal line (Com).

5. The pixel circuit and display panel according to claim 2, characterized in that, The pixel circuit further includes a second back gate control unit, which further includes a fourth transistor (M4). The gate of the fourth transistor (M4) is coupled to the second row gate signal line (ScanB), the first source and drain of the fourth transistor (M4) are coupled to the data signal line (Data), and the second source and drain of the fourth transistor (M4) are coupled to the bottom gate of the second transistor (M2).

6. The pixel circuit and display panel according to claim 5, characterized in that, The second back gate control unit also includes a second sustaining capacitor (Cst4). One end of the second sustaining capacitor (Cst4) is coupled to the connection node between the second source / drain of the fourth transistor (M4) and the bottom gate of the second transistor (M2), and the other end of the second sustaining capacitor (Cst4) is coupled to the common signal line (Com).

7. The pixel circuit and display panel according to claim 5, characterized in that, The second back gate control unit also includes a third sustaining capacitor (Cst5), the upper plate of which is the lower plate of the pre-storage capacitor (Cst1), and the lower plate of which is connected to the second source and drain of the fourth transistor (M4).

8. The pixel circuit according to claim 3, characterized in that, The driving timing of the pixel circuit is configured as follows: During the backlight activation phase of frame N: When the row gate signal line (Scan) switches to a low level, the first transistor (M1) is turned on, and the data signal line (Data) writes the data signal voltage of the N+1th frame to the pre-storage capacitor (Cst1) through the first transistor (M1). The voltage of the first node (A) is the data signal voltage. At this time, the control signal line (Vc) is a first voltage, used to raise the threshold voltage of the second transistor (M2) to suppress leakage current; the row gate signal line (Scan) jumps to a high level, the first transistor (M1) is turned off, and the backlight off stage of the Nth frame is entered; During the backlight off phase of frame N: When the control signal line (Vc) switches to the second voltage, the transfer signal line (Tran) switches to a low level, and the second transistor (M2) turns on. The pre-storage capacitor (Cst1) transfers the data signal voltage of the N+1th frame to the holding capacitor (Cst2) and the pixel capacitor (Clc) through the second transistor (M2); after the transfer is completed, the transfer signal line (Tran) jumps to a low level, the second transistor (M2) is turned off, and the backlight on stage of the N+1th frame is entered, and the pixel capacitor (Clc) displays the display screen corresponding to the data signal voltage of the N+1th frame; During the backlight-on phase of the N+1th frame, the control signal line (Vc) switches to the first voltage, the row gate signal line (Scan) switches to a high level, the first transistor (M1) is turned on, and the data signal line (Data) writes the N+2th frame data signal voltage into the pre-storage capacitor (Cst1) through the first transistor (M1).

9. The pixel circuit according to claim 5, characterized in that, The driving timing of the field-sequence display circuit is configured to include: During the backlight activation phase of frame N: When the row gate signal line (Scan) switches to a low level, the first transistor (M1) and the third transistor (M3) are turned on. The data signal line (Data) writes the data signal voltage of the N+1th frame to the pre-storage capacitor (Cst1) through the first transistor (M1). The voltage of the first node (A) is the data signal voltage. The back gate control signal line (i-Data) writes the back gate control voltage to the first sustaining capacitor (Cst3) through the third transistor (M3); At this time, the back gate control voltage is used to raise the threshold voltage of the second transistor (M2) to suppress leakage current; the row gate signal line (Scan) jumps to a high level, the first transistor (M1) is turned off, and the backlight off stage of the Nth frame is entered; During the backlight off phase of frame N: When the control signal line (Vc) switches to the second voltage, the transfer signal line (Tran) switches to a low level, and the second transistor (M2) turns on. The pre-storage capacitor (Cst1) transfers the data signal voltage of the N+1th frame to the holding capacitor (Cst2) and the pixel capacitor (Clc) through the second transistor (M2); after the transfer is completed, the transfer signal line (Tran) jumps to a low level, the second transistor (M2) is turned off, and the backlight on stage of the N+1th frame begins. During the backlight-on phase of the N+1th frame, the control signal line (Vc) switches to the first voltage, the row gate signal line (Scan) switches to a high level, the first transistor (M1) is turned on, and the data signal line (Data) writes the N+2th frame data signal voltage into the pre-storage capacitor (Cst1) through the first transistor (M1).

10. A display panel, characterized in that, Includes the pixel circuit as described in any one of claims 1 to 9.

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