Storage arrays, memories and their reading methods and electronic devices

Abstract

A storage array, a memory, a reading method thereof, and an electronic device are disclosed. The storage array includes multiple storage cell subarrays, a reference cell column, and a set of reference voltage generation circuits, reference cell switching circuits, and read word line control circuits. The storage cell subarrays and reference cell column in two storage arrays are electrically connected via read bit lines and symmetrically distributed around a read decision unit. The transistors of the reference cells and storage cells are isomorphic and have the same circuit structure. The memory includes at least one pair of open storage arrays, each pair comprising a first storage array, a second storage array, and a set of read decision units. Each storage array is electrically connected to one of the two input terminals of the read decision unit. During reading, the two storage arrays provide a read voltage and a reference voltage, respectively. The two input terminals of the read decision unit have similar RC parameters, and the drift generated by the voltages at the two input terminals is also matched. This application improves storage density and data reading reliability.

Description

Technical Field

[0001] This invention relates to the field of electrical components technology, and in particular to a storage array, a memory, a method for reading the memory, and an electronic device. Background Technology

[0002] With the rise and rapid development of IoT applications, artificial intelligence technologies, and cloud computing technologies, the traditional von Neumann architecture faces the memory wall problem. High-performance computer systems have an increasingly urgent need for high-speed, large-capacity non-volatile memory.

[0003] As an alternative to SRAM, eDRAM has evolved into various cell structures, mainly divided into two categories: traditional single-transistor single-capacitor (1T1C) cells and gain cells based on standard CMOS processes. However, the 1T1C structure faces significant challenges: its manufacturing process requires the integration of complex deep trench capacitors or stacked capacitors, increasing process complexity and cost; more importantly, its inherent destructive read characteristics limit performance and require additional recovery operations. On the other hand, while gain cells have advantages in CMOS compatibility, they present a key bottleneck when used as memory: significant subthreshold leakage current leads to a substantial reduction in cell data retention time, necessitating high refresh rates to maintain data integrity, which not only increases dynamic power consumption but also exacerbates static power consumption issues. Furthermore, the area overhead of gain cells is generally higher than that of the 1T1C structure, further limiting its integration density.

[0004] For 2T0C high-density memory design, the core challenge lies in the inherent contradiction between coordinating and optimizing cell area density, dynamic power consumption, and data reliability: the increase in cell density under continuous process miniaturization is the cornerstone of achieving high storage capacity, but the accompanying short-channel effects exacerbate the design difficulty; dynamic power consumption accounts for a significant proportion of the total system power consumption, among which refresh power consumption increases sharply with process miniaturization; charge tolerance decay caused by process deviations and signal interference introduced by wiring continuously threaten data integrity.

[0005] Based on this, the industry has proposed using novel amorphous oxide semiconductor field-effect transistors (AOSFETs) to replace traditional silicon-based devices in constructing 2T0C gain cells, leveraging their ultra-low leakage characteristics to significantly extend data retention time. However, existing research focuses on performance optimization at the cell level (such as reducing write voltage and improving on / off ratio), but lacks effective solutions for array-level optimization.

[0006] In related technologies, the 2T0C gain unit storage array structure is as follows: Figure 15 As shown, the following performance limitations exist: 1. Typically, an array is connected to a read decision circuit of a sensitive amplifier. The more sensitive amplifiers there are, the more the total area of ​​the memory increases, which reduces the data storage density per unit area.

[0007] 2. To ensure that all sensitive amplifiers can obtain a stable and accurate reference voltage, the reference voltage generation circuit must have sufficient driving capability, which increases power consumption. Furthermore, since multiple sensitive amplifiers share the same reference voltage generation circuit, if the reference voltage generation circuit is disturbed, the input terminals of the sensitive amplifiers will also be disturbed.

[0008] 3. The two input terminals of the sensitive amplifier are connected to completely different loads: one end is the storage cell and the other end is the reference voltage generation circuit. During reading, this load asymmetry causes the two ends to respond inconsistently to common-mode noise, which in turn causes abnormal drift of the reference voltage and the reading voltage, resulting in data reading errors.

[0009] 4. As a global reference source, the reference voltage generation circuit cannot sense or adapt to the local drift of device characteristics (such as threshold voltage) caused by process deviations, power supply voltage fluctuations, or temperature gradients in different areas of the chip. When the local PVT conditions of the memory cell and its reference source are inconsistent, the read voltage and the reference voltage may drift out of match, which may lead to the closure of the read window or misjudgment, affecting the reliability of data reading and the robustness of read decision. Summary of the Invention

[0010] This invention provides a storage array, a memory, a method for reading the memory, and an electronic device thereof, solving the problem of how to improve the performance of a storage array.

[0011] To achieve the above objectives, this application adopts the following technical solution: In a first aspect, a storage array is provided, comprising: A first preset number of storage cell subarrays; each storage cell subarray includes multiple array-distributed storage cells; wherein each column of storage cells is electrically connected to a write word line and a read word line arranged along a first direction, and each row of storage cells is electrically connected to a write bit line and a read bit line arranged along a second direction; A second preset number of reference cell columns; each reference cell column includes multiple arrayed reference cells, the reference cell columns are divided into a fifth preset number of reference cell groups, each reference cell group includes at least one reference cell; wherein, each column of reference cells is electrically connected to the same reference write word line and the same reference read word line; each row of reference cells is electrically connected to a reference read bit line; each reference cell group is electrically connected to a fourth preset number of reference write bit lines, and reference cells in different rows within the same group can be configured to be electrically connected to the same or different reference write bit lines; The read bit line of each row of storage cells and the reference read bit line of each row of reference cells are electrically connected sequentially along a first direction; The other end of a read word line electrically connected to each column of the memory cells, and the other end of a reference read word line electrically connected to each column of the reference cells, are both electrically connected to a read word line control circuit along a first direction; the read word line control circuit is used to control the voltage state of the read word line and the reference read word line.

[0012] Secondly, a memory is provided, comprising: At least one pair of open storage arrays based on the storage arrays described in the first aspect; The open storage array pair includes a first storage array, a second storage array, and a set of read decision units; The read decision device includes a first input terminal, a second input terminal, and a first output terminal. The read bit line of the first storage array is electrically connected to the first input terminal, and the read bit line of the second storage array is electrically connected to the second input terminal. The storage cell subarrays and reference cell columns in the first and second storage arrays are symmetrically distributed with the read decision unit as the center of symmetry. When one of the first input terminal and the second input terminal is a data input terminal, the other is a reference input terminal; The first output terminal is used to output the corresponding logic decision result of the voltage at the first input terminal and the voltage at the second input terminal of the read decision unit. The first output terminal is a single-ended output or a double-ended output.

[0013] Thirdly, a method for reading a memory is provided for reading the memory as described in the second aspect, comprising: Perform the following on the memory array in reference mode: S11: Pre-charge, configure the read bit line, read word line and reference read word line of the memory array in reference mode to the first voltage, and configure the reference write word line of all reference cell columns to the fifth voltage; S12: Write a reference voltage, configure the reference write word line of at least one target reference cell column in the memory array of the reference mode to a fourth voltage, so as to turn on the first transistor of the reference cell column and write the reference voltage set to the gate of the second transistor of the reference cell. S13: Generate a reference voltage, configure the reference read word line of the target reference cell column to a third voltage, turn on the second transistor of the reference cell, and after a first preset time, generate a set of reference voltages on the read bit line electrically connected to the second transistor. Perform the following on the memory array in read mode: S21: Pre-charge, configuring the read bit lines and all read word lines of the memory array in read mode to the first voltage; S22: Gating configuration, configuring the read word line of the selected target memory cell column to a second voltage to turn on the second transistor of the target memory cell column; S23: Generate a read voltage. After a second preset time, generate a set of read voltages on the read bit lines of the memory array in the read mode. S24: Sensing decision, activating the read decision unit, comparing the reference voltage set with the read voltage set, and outputting the decision result; to read the corresponding stored data in the gate of the second transistor of the memory cell in the target memory cell column.

[0014] Fourthly, an electronic device is provided, including a memory as described in the second aspect.

[0015] This application firstly reduces the number of read decision units in the memory, thereby increasing its data storage density per unit area. Secondly, it isolates the read decision unit from the reference voltage generation circuit during reading, thus reducing the driving capability requirements of the reference voltage generation circuit. Furthermore, the reference cell array is closer to the read decision unit compared to traditional reference sources, thus avoiding voltage drop losses caused by large parasitic resistances on long transmission lines. The distributed placement of the reference cell array allows for the selection of suitable arrays to achieve structural symmetry, reducing common-mode noise interference at the read decision unit input. Since the reference cells use the same device parameters and circuit structure as the memory cells, their PVT responses are identical, enabling the reference voltage to approximately follow the read voltage drift, improving the robustness and reliability of data reading. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a storage array circuit topology provided in an embodiment of this application; Figure 2 A circuit diagram of a memory array for write layer configuration is provided in an embodiment of this application; Figure 3 Schematic diagrams illustrating several planar structures of memory array circuits provided in the embodiments of this application; Figure 4 Schematic diagrams illustrating several memory array circuit topologies provided in the embodiments of this application; Figure 5 This application provides a schematic diagram of an open memory array circuit topology. Figure 6 A circuit diagram of an open memory array for write layer configuration provided in an embodiment of this application; Figure 7This application provides a schematic diagram of an example of an open memory array for configuring the read layer circuit topology. Figure 8 This application provides a schematic diagram of a specific circuit example of an open memory array. Figure 9 A schematic diagram of a 2T0C gain unit structure provided in an embodiment of this application; Figure 10 This is a schematic diagram illustrating an example of an open memory array reference voltage generation scheme provided in an embodiment of this application. Figure 11 This is a schematic diagram illustrating another example of an open memory array reference voltage generation scheme provided in an embodiment of this application. Figure 12 A schematic diagram illustrating another example of an open memory array reference voltage generation scheme provided in this application embodiment; Figure 13 A schematic diagram of a specific circuit example of an open memory array based on a 2T0C gain unit provided in this application embodiment; Figure 14 A timing diagram illustrating the reading method of an open memory array pair based on 2T0C gain units provided in an embodiment of this application; Figure 15 This is a schematic diagram of a traditional open-array memory.

[0017] Figure label: Storage array 100; Storage cell subarray 1011; read word lines 1071-107m; read bit lines 1051-105n; Reference cell column 1021; Reference read line 1101; Reference write line 1061-106x; Reference write line 1111; Reading line control circuit 103; reference voltage generation circuit 104; reference unit switching circuit 106; First transistor 702; Second transistor 701; Unit write word line 704; Unit write bit line 706; Unit read word line 703; Unit read bit line 705; First storage array 400; First storage cell subarray 4011; First storage cell subarray read bit lines 4051-405n; First storage cell subarray read word lines 4071-407m; First storage cell subarray write word lines 4091-4091m; First storage cell subarray write bit lines 4081-408n; First reference cell column 4021; First reference cell column reference read word line 4101; First reference write word line 4111; First reference write bit lines 4061-406; First read word line control circuit 403; Second storage array 400'; Second storage cell subarray 4011'; Second storage cell subarray read bit lines 4051'-405n'; Second storage cell subarray read word lines 4071'-407m'; Second storage cell subarray write word lines 4091'-409m'; Second storage cell subarray write bit lines 081'-408n'; Second reference cell column 4021'; Second reference cell column reference read word lines 4101'; Second reference write word lines 4111'; Second reference write bit lines 4061'-406x'; Second read word line control circuit 403' Read the decision unit 405; Sensitive Amplifier Group 605; Storage unit column 912. Detailed Implementation

[0018] To further illustrate the technical means and effects adopted by the present invention to achieve its intended purpose, the technical solutions in the embodiments of this application are clearly described. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art are within the scope of protection of this application.

[0019] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0020] The steps described in this application and the flowcharts in the accompanying drawings are not necessarily strictly executed according to the step numbers; the execution order of the steps can be changed. Furthermore, certain steps can be omitted, multiple steps can be combined into one step, and / or one step can be broken down into multiple steps.

[0021] This specification provides a storage array, a memory, a method for reading the memory, and an electronic device thereof, which will be described in detail below with reference to the accompanying drawings and preferred embodiments.

[0022] This application provides a storage array 100, including: A first preset number of storage cell subarrays 1011; each storage cell subarray 1011 includes multiple array-distributed storage cells; wherein each column of storage cells is electrically connected to a write word line and a read word line arranged along a first direction, and each row of storage cells is electrically connected to a write bit line and a read bit line arranged along a second direction; A second preset number of reference cell columns 1021; each reference cell column 1021 includes a plurality of arrayed reference cells, the reference cell columns are divided into a fifth preset number of reference cell groups, each reference cell group includes at least one reference cell; wherein, each column of reference cells is electrically connected to the same reference write word line and the same reference read word line 1101; each row of reference cells is electrically connected to a reference read bit line; each reference cell group is electrically connected to a fourth preset number of reference write bit lines, and reference cells in different rows within the same group can be configured to be electrically connected to the same or different reference write bit lines; The read bit line of each row of storage cells and the reference read bit line of each row of reference cells are electrically connected sequentially along a first direction; The other end of a read word line electrically connected to each column of the storage cells, and the other end of a reference read word line electrically connected to each column of the reference cells, are electrically connected to the read word line control circuit 103 along the first direction; the read word line control circuit 103 is used to control the voltage state of the read word line and the reference read word line 1101.

[0023] Furthermore, the storage array 100 also includes a set of reference voltage generation circuits and a set of reference cell switching circuits to form a reference write layer configuration; The reference voltage generation circuit is used to generate an adjustable set of reference voltages; the reference voltage generation circuit is electrically connected to each of the reference cell groups through the reference write bit line to output different or the same reference voltage to the gate of the second transistor in the reference cell of different reference cell groups. The reference unit switching circuit is electrically connected to each of the reference unit groups through the reference writing line, and is used to control the conduction and cutoff of the first transistor in the reference unit within the reference unit group.

[0024] Specifically, such as Figure 1 The first preset number N of storage cell subarrays 1011 and the second preset number M of reference cell columns 1021 can be arranged sequentially along the second direction in any order. The storage array includes a fourth preset number of read bit lines and a fourth preset number of write bit lines arranged parallel to the second direction. The read bit lines of the storage array are electrically connected sequentially along the first direction to the read bit lines of the storage cell subarrays and the read bit lines of the reference cell columns.

[0025] The storage cell subarray 1011 includes multiple storage cells, a third preset number m of write word lines arranged parallel to a first direction, a third preset number m of read word lines 1071-107m arranged parallel to the first direction, a fourth preset number n of write bit lines arranged parallel to a second direction, and a fourth preset number n of read bit lines 1051-105n arranged parallel to the second direction. The values ​​of n and m can be the same or different.

[0026] Each row of storage cells in the first direction is electrically connected to a corresponding write bit line and a read bit line.

[0027] Each column of storage cells in the second direction is electrically connected to a corresponding write line and a read line.

[0028] The other end of the third preset number of read lines 1071-107m of the storage unit is electrically connected to the read line control circuit 103.

[0029] Each reference unit column 1021 includes multiple reference units, a reference writing line and a reference reading line 1101 arranged in parallel along the first direction, a sixth preset number of reference writing lines arranged in parallel along the first direction, and a fourth preset number of reference reading lines arranged in parallel along the second direction.

[0030] Each row of reference cells in the first direction is electrically connected to a corresponding read line 1051-105n.

[0031] Each column of reference units in the second direction is electrically connected to a reference reading line 1101, and the other end of the reference reading line 1101 is electrically connected to the reading line control circuit 103.

[0032] like Figure 2 One reference write layer configuration of the storage array includes at least one reference cell column 1021, a set of reference cell switching circuits 106, and a set of reference voltage generation circuits 104.

[0033] The reference cell column is divided into a fifth preset number of reference cell groups, each reference cell group containing one or more reference cells; each reference cell group is electrically connected to the reference voltage generation circuit through at least one reference write bit line 1061-106x. The reference cell column is electrically connected to the reference cell switching circuit 106 through the reference write word line 1111.

[0034] The reference unit switching circuit 106 is used to control the on and off states of the first transistor of the reference unit in the reference unit column 1021.

[0035] The reference voltage generation circuit 104 can be used to output an adjustable set of reference voltages to the gates of the second transistors of the reference cells in the reference cell group. The reference voltages output to different reference cell groups can be the same or different.

[0036] The storage unit is a gain unit.

[0037] For example, such as Figure 9 As shown, it can be a 2T0C gain unit containing two transistors. The gain unit includes a first transistor 702, a second transistor 701, a unit write word line 704, a unit write bit line 706, a unit read word line 703, and a unit read bit line 705.

[0038] The first and second transistors are thin-film transistors with vertical channel characteristics and / or amorphous oxide semiconductor channel materials. These transistors are compatible with low-temperature back-end processes. The vertical channel characteristic refers to the transistor having a vertical annular channel (CAA) structure, which allows for three-dimensional multilayer stacking, enabling a cell area of ​​[missing information - likely a specific area]. Amorphous oxide semiconductors (AOS) have become a core material for next-generation thin-film transistors (TFTs) due to their excellent electrical properties, high optical transparency, and low-temperature fabrication capabilities. Compared to traditional amorphous silicon (a-Si), amorphous oxide semiconductors such as amorphous indium gallium zinc oxide (a-IGZO) exhibit higher electron mobility, lower off-state current, and superior uniformity, meeting the demands of high-resolution displays and flexible electronic devices. In the embodiments of this application, both the first and second transistors are n-type transistors.

[0039] In the gain unit: the gate of the first transistor is electrically connected to the write word line, the first electrode of the first transistor is electrically connected to the write bit line, and the second electrode is electrically connected to the gate of the second transistor; The first electrode of the second transistor is electrically connected to the read bit line and the second electrode is electrically connected to the read word line, or the second electrode is electrically connected to the read bit line and the first electrode is electrically connected to the read word line.

[0040] The working principle of the 2T0C gain unit is as follows: The storage node (SN) capacitors in the aforementioned gain cell structure are all composed of the gate capacitance, junction capacitance, metal lines, and sidewalls of vias, as well as planar capacitance. The "gain cell" originates from the transconductance gain of the read transistor, which converts the voltage level on the storage node, or equivalently converts the gate voltage of the read transistor, thereby generating a read current related to the magnitude of the storage node voltage.

[0041] The first transistor 702 is turned on by the write word line 704 of the control unit, and then the storage data is written to the storage node SN by the cell write bit line 706. The writing of the storage data is completed when the potential of the storage data is the same as that of the cell write bit line 706. If amorphous oxide semiconductor (AOS) is used as the transistor channel material, due to its ultra-low off-state current, the retention time of the stored data in the storage node can reach [a certain value]. It significantly exceeds the data retention time of 2T0C gain cells that use traditional silicon as the transistor channel material.

[0042] The stored data can be represented as a high-level data "1" or a low-level data "0". By using the read word line 703 of the control unit to generate a voltage difference between the first and second electrodes of the second transistor 701, the second transistor 701 determines the conduction level of the second transistor according to the stored data of the storage node, thereby generating different magnitudes of read current, and can be used to determine whether the data of the storage node is "1" or "0".

[0043] It should be noted that the reference cell and the memory cell are isomorphic. That is, the transistors contained in the reference cell and the memory cell have the same transistor structure and device parameters, including width, length, channel doping concentration, etc.; the memory cell and the reference cell can use the same read word line, read bit line, write word line, and write bit line electrical connection method.

[0044] For example, Figure 3 Several examples of planar structures for memory array circuits provided in embodiments of this application are illustrated. Figure 4 Examples of several memory array circuit topologies provided in embodiments of this application are illustrated. One or more reference cell columns can be located on the side of the memory array closer to the read decision device, on the side farther from the read decision device, or distributed within the memory cell subarray, and the reference cell columns can be arranged adjacent to each other.

[0045] Corresponding to the above-described storage array embodiments, this application provides a memory, including: At least one open storage array pair based on the above-mentioned storage arrays; The open storage array pair includes a first storage array 400, a second storage array 400', and a set of read decision units; The read decision device includes a first input terminal, a second input terminal, and a first output terminal. The read bit line of the first storage array 400 is electrically connected to the first input terminal, and the read bit line of the second storage array is electrically connected to the second input terminal. The storage cell subarrays and reference cell columns in the first storage array 400 and the second storage array 400' are symmetrically distributed with the read decision unit as the center of symmetry. When one of the first input terminal and the second input terminal is a data input terminal, the other is a reference input terminal; The first output terminal is used to output the corresponding logic decision result of the voltage at the first input terminal and the voltage at the second input terminal of the read decision unit. It can be a single-ended output or a double-ended output.

[0046] Furthermore, multiple open memory arrays are integrated in a multi-layer stack on a single wafer.

[0047] Specifically, an open storage array pair can be constructed based on the above-mentioned storage array. For example... Figure 5 As shown, the open storage array pair includes: a set of read decision units 405, a first storage array 400, and a second storage array 400'.

[0048] The first storage array 400 and the second storage array 400' are the storage array 100 described above. Both the first storage array 400 and the second storage array 400' have a first preset number of storage cell subarrays (4011 / 4011'), a second preset number of reference cell columns (4021 / 4021'), a fourth preset number of read bit lines (4051-405n / 4051'-405n'), a second preset number of reference read word lines (4101 / 4101'), and a set of read word line control circuits (403 / 403').

[0049] The first storage array 400 and the second storage array 400' are arranged symmetrically with the read decision unit 405 as the center. That is, the distribution of the reference cell columns and storage cell subarrays in the first storage array 400 and the second storage array 400' located at both ends of the read decision unit 405 is symmetrically distributed with the read decision unit 405 as the center of symmetry.

[0050] The read decision device 405 has three port sets: the first port set is located on the first side of the read decision device and has a fourth preset number of first input terminals; the second port set is located on the second side of the read decision device and has a fourth preset number of second input terminals; and the third port set is located on the third side of the read decision device and has a fourth preset number of first output terminals.

[0051] The first storage array 400 is located on the side where the first port set of the read decision unit 405 is located, and is electrically connected to each first input terminal on the first side of the read decision unit via a fourth preset number of read bit lines (4051-405n) along the second direction. The second storage array is located on the side where the second port set of the read decision unit 405 is located, and is electrically connected to each second input terminal on the second side of the read decision unit via a fourth preset number of read bit lines (4051'-405n') along the second direction.

[0052] When one of the first input terminal and the second input terminal is a data input terminal, the other is a reference input terminal. The first output terminal is used to output the logical decision result of the voltage at the first input terminal and the voltage at the second input terminal of the read decision unit. In specific implementations, the first output terminal can be a single-ended output or a double-ended output.

[0053] For example, Figure 6 This is a circuit diagram illustrating the write layer configuration of an open memory array pair provided in an embodiment of this application. The write layer configuration of the open memory array pair includes reference cell columns of a first memory array 400 and a second memory array 400', a set of reference voltage generation circuitry, and a set of reference cell switching circuitry.

[0054] The reference unit switching circuit is electrically connected to the reference write lines (4111, 4111') of the reference unit column.

[0055] The reference voltage generation circuit is electrically connected to the reference write lines (4061-406x, 4061'-406x') of the reference cell column, and is used to output a reference voltage set to it. The reference voltage set is the collection of reference voltages output by the reference voltage generation circuit, and is used to drive the reference cell group in the reference cell column.

[0056] This write layer configuration is primarily used to write the corresponding reference voltage to the gate of the second transistor in each reference cell within the target reference cell column. The setting of the reference voltage input to each reference cell requires comprehensive consideration of factors such as the preset generation time of the reference voltage (if the preset time is long, the reference voltage at the gate of the second transistor can be smaller, and vice versa), voltage drop losses on long transmission lines, and the performance degradation of local devices due to different PVT conditions in certain regions. Therefore, the reference voltage input to different reference cell groups within different reference cell columns can be different.

[0057] In the open storage array pair, when one storage array is in read mode, the other storage array is in reference mode. That is, one storage array is used for reading, generating a read voltage on all read bit lines electrically connected to the read decision unit; the other storage array is used to generate a reference voltage on all read bit lines electrically connected to the read decision unit, so that the read decision unit can make a decision on the read voltage and read the relevant data from the read storage array.

[0058] Figure 7 This is a circuit diagram illustrating an open memory array pair for read layer configuration, provided as an embodiment of this application. The read layer configuration of the open memory array pair includes a first memory array 400, a second memory array 400', and a set of read decision units; used to select reference cell columns and memory cell subarrays in the memory array pair during read operations.

[0059] In practical implementation, the read decision group, first memory array, second memory array, reference cell switching circuit group, and reference voltage generation circuit group of the open memory array pair can be integrated on a single wafer (die). Multiple read decision groups, first memory array, second memory array, reference cell switching circuit group, and reference voltage generation circuit group of the open memory array pair can be integrated in multiple layers on a single wafer (die). Compared to traditional memory array architectures, this open memory array pair adopts an open bitline architecture scheme, where two memory arrays share a set of read decision groups, which directly reduces the area occupied by the read decision groups and increases the data storage density per unit area.

[0060] Figure 8 This illustration shows a specific circuit example of a memory provided in an embodiment of this application. The memory includes: a first memory array 400, a second memory array 400', a set of reference voltage generation circuits, a set of sensitive amplifier groups 605, a set of reference cell switching circuits, and peripheral circuits. Each memory array includes a memory cell subarray comprising m memory cells arranged sequentially along a second direction, n memory cells arranged sequentially along a first direction, and a column of reference cells (4021 / 4021') positioned near the sensitive amplifiers, totaling... Each reference cell has one reference cell group, which is electrically connected to the reference voltage generation circuit via a reference write bit line (4061 / 4061') and to the reference cell switching circuit via a reference write word line (4111 / 4111').

[0061] More specifically, each memory array also includes a third preset number m of read word lines (4071-407m / 4071'-407m') and write word lines (4091-4091m / 4091-4091m') along the first direction, a fourth preset number n of read bit lines (4051-405n / 4051'-405n') and write bit lines (4081-408n / 4081'-408n') along the second direction, a reference read word line (4101 / 4101'), and a set of read word line control circuits.

[0062] The sensitive amplifier group 605 can be an example of the read decision unit 405. Each sensitive amplifier includes two input terminals; the two input terminals are respectively electrically connected to the read bit lines (4051-405n / 4051'-405n') in the first memory array 400 and the second memory array 400' along a first direction, and the two adjacent memory arrays share one sensitive amplifier, so this structure can reduce the need for... Figure 15 The area occupied by the sensitive amplifier in the traditional memory structure.

[0063] The reference voltage generation circuit is electrically connected to the reference write lines (4061 / 4061') of the first reference cell column 4021 and the second reference cell column 4021'. It outputs a reference voltage to each reference cell group in the memory array in reference mode and writes the reference voltage to the gate of the corresponding reference cell's second transistor. Thus, when a voltage difference is generated between the first and second electrodes of the second transistor, each second transistor indirectly generates a reference voltage on all read lines of the reference cell column based on the gate reference voltage. This indirect reference voltage generation method isolates the reference voltage generation circuit from the sensitive amplifier group 605, avoiding the reference voltage generation circuit directly driving multiple sensitive amplifiers and significantly reducing the driving capability requirements of the reference voltage generation circuit.

[0064] Corresponding to the above-described memory embodiments, this application provides a memory reading method for reading the aforementioned memory, including: Perform the following on the memory array in reference mode: S11: Pre-charge, configure the read bit line, read word line and reference read word line of the memory array in reference mode to the first voltage, and configure the reference write word line of all reference cell columns to the fifth voltage; S12: Write a reference voltage, configure the reference write word line of at least one target reference cell column in the memory array of the reference mode to a fourth voltage, so as to turn on the first transistor of the reference cell column and write the reference voltage set to the gate of the second transistor of the reference cell. S13: Generate a reference voltage, configure the reference read word line of the target reference cell column to a third voltage, turn on the second transistor of the reference cell, and after a first preset time, generate a set of reference voltages on the read bit line electrically connected to the second transistor. Perform the following on the memory array in read mode: S21: Pre-charge, configuring the read bit lines and all read word lines of the memory array in read mode to the first voltage; S22: Gating configuration, configuring the read word line of the selected target memory cell column to a second voltage to turn on the second transistor of the target memory cell column; S23: Generate a read voltage. After a second preset time, generate a set of read voltages on the read bit lines of the memory array in the read mode. S24: Sensing decision, activating the read decision unit, comparing the reference voltage set with the read voltage set, and outputting the decision result; to read the corresponding stored data in the gate of the second transistor of the memory cell in the target memory cell column.

[0065] Furthermore, during the reference voltage generation stage, the read word lines of all memory cell subarrays of the memory array in reference mode are maintained at the first voltage to turn off the second transistors of all their memory cells; During the sensing decision phase, the reference write word lines of all reference cell columns of the memory array in read mode are configured to the fifth voltage, and the reference read word lines are configured to the first voltage, so as to turn off all reference cell columns.

[0066] Specifically, the reading method includes a reference voltage generation operation and a reading operation.

[0067] In an open storage array pair, when one storage array is in read mode, the other storage array is in reference mode.

[0068] The reference voltage generation operation is performed on a memory array in reference mode.

[0069] Before performing the reference voltage generation operation: First, pre-charging is performed. In all memory arrays, the read bit lines of the memory array are configured to a first voltage. The read word line control circuit configures the read word lines of all memory cell subarrays and the reference read word lines of the reference cell columns to the first voltage (belonging to the reference read layer operation). The reference cell switching circuit configures the reference write word lines of all reference cell columns to a fifth voltage (belonging to the write layer operation). A reference voltage generation circuit is configured to generate a target reference voltage set.

[0070] The reference voltage generation operation is as follows: The first step involves configuring the reference write word lines of the second preset number of reference cell columns to be activated to a fourth voltage via a reference cell switching circuit, thereby turning on the first transistor of the reference cell in the reference cell column and configuring the target reference voltage set on the gate of the second transistor of the reference cell.

[0071] The second step involves configuring the eighth preset number of reference read word lines to the third voltage via a read word line control circuit. This causes the second transistor of the corresponding reference cell in the reference cell column to conduct, thereby generating a conduction current between its first and second electrodes. After a first preset time, a reference voltage is generated on the read bit line electrically connected to the second transistor of the reference cell. The reference voltages generated on a set of read bit lines in each reference cell group within the reference cell column constitute a subset of reference voltages, and the subsets of reference voltages from all reference cell groups constitute a set of reference voltages.

[0072] It is worth noting that the third voltage is the electrode voltage applied to the read word line of the second transistor of the reference cell, and the third voltage is less than the first voltage (pre-charge voltage). In some possible implementations, the third voltage may be the ground voltage of the memory array. The fourth voltage is the voltage applied to the gate of the first transistor of the reference cell, and enables the first transistor of the reference cell to conduct; the fifth voltage is the voltage applied to the gate of the first transistor of the reference cell, and enables the first transistor of the reference cell to turn off. Any reference voltage in the set of reference voltages is greater than the third voltage and less than the first voltage.

[0073] All memory cell subarrays of the memory array in reference mode are configured with a first voltage by a read word line control circuit to turn off the second transistors of all memory cells in the memory cell subarray.

[0074] When the memory array is in reference mode for a long time, the reference voltage generation operation only needs to be performed once. Subsequent read and write operations can be performed repeatedly on the memory array in read mode to reduce the power consumption caused by the repeated switching of transistors during the reference voltage generation operation and the complexity of the operation timing design.

[0075] For example, Figure 10-12 Examples of several possible reference voltage generation schemes in embodiments of this application are provided. The reference voltage for each row of read bits can be generated by the combined action of reference cells in the same row of multiple reference cell columns, or it can be generated by reference cells in only one reference cell column. The advantage of generating the reference voltage by multiple reference cell columns is that if a row of reference cells in one reference cell column fails or is affected by noise, thus disturbing the reference voltage on that row of read bits, while the reference cells in other reference cell columns are working normally, the disturbance will not directly cause the reference voltage to fail. This scheme has stronger anti-interference capability than the scheme of generating the reference voltage by a single reference cell column, but it will reduce the data storage density in the memory array and increase the area occupied by the reference voltage generation circuit.

[0076] The read operation is performed on a storage array that is in read-only mode.

[0077] The storage array in read mode selects a column of storage cells in the storage cell subarray and performs a read operation on it in the read layer through its read word line control circuit.

[0078] The read operation is as follows: First, pre-charging is performed by configuring the read bit lines of the memory array to the first voltage, and the read word line control circuit configures the read word lines of all memory cell subarrays in the memory array to the first voltage.

[0079] Next, a gating operation is performed, configuring the read word lines of the selected memory cell column to the second voltage, thus turning on the second transistor of the corresponding memory cell. The read word lines of the remaining unselected memory cell columns remain at the first voltage. At any given time, only one column of memory cells in the memory cell subarray is selected for a read operation.

[0080] Next, in the read voltage generation phase, within the selected memory cell column, after a second preset time, the second transistor in the on-state generates a set of read voltages on the read bit lines electrically connected to it. More specifically, when a memory cell stores the first stored data, a first read voltage is generated on the read bit line; when a memory cell stores the second stored data, a second read voltage is generated on the read bit line. The set of read voltages is the combination of the first and second read voltages that may be generated on each read bit line of the read array's memory cell subarray. Any read voltage in the set is greater than the second voltage and less than the first voltage.

[0081] During the sensing phase, a ninth preset number of read decision units in the read decision unit group are activated to sense the ninth preset number of reference voltage subset inputs and the read voltage set on the corresponding read bit lines of the ninth preset number of bars. Each read decision unit compares the read voltage at its two input terminals with the corresponding reference voltage within the reference voltage subset output by the corresponding reference unit group. When the read voltage is greater than the reference voltage, the first stored data is read out; when the read voltage is less than the reference voltage, the second stored data is read out.

[0082] It is worth noting that the second voltage is lower than the first voltage. In some possible implementations, the second voltage may be the ground voltage of the storage array; the first stored data is data "0", and the second stored data is data "1".

[0083] In the read-mode memory array, all reference cell columns have their reference write word lines configured to the fifth voltage by a reference cell switching circuit and their reference read word lines configured to the first voltage by a read word line control circuit. All reference cell columns are then turned off.

[0084] For example, Figure 13 This is a specific circuit example of an open memory array pair based on a 2T0C gain unit provided in the embodiments of this application. The open memory array pair based on the 2T0C gain unit includes a first memory array 400, a second memory array 400', a set of sensitive amplifiers, a set of reference voltage generation circuits, a set of reference cell switching circuits, and a set of peripheral circuits (907 / 907') for pre-charging.

[0085] Each memory array includes a memory cell subarray consisting of m memory cells arranged sequentially along the second direction, n memory cells arranged sequentially along the first direction, and a column of reference cells (4021 / 4021') positioned near the sensitive amplifier, totaling... Each reference cell has a 2T0C gain unit, and only one reference cell group in this reference cell column is electrically connected to the reference voltage generation circuit through a reference write bit line (4061 / 4061') and electrically connected to the reference cell switching circuit through a reference write word line (4111 / 4111').

[0086] Each memory array also includes a third preset number of read word lines (4071-407m / 4071'-407m') and write word lines (4091-4091m / 4091'-409m') along the first direction, a fourth preset number of read bit lines (4051-405n / 4051'-405n') and write bit lines (4081-408n / 4081'-408n') along the second direction, a reference read word line (4101 / 4101'), and a set of read word line control circuits (403 / 403').

[0087] It adopts a method of electrically connecting a set of reference voltage generation circuits to a reference write bit line (4061 / 4061') of a reference cell group in the reference cell column. This connection method can minimize the size of the reference voltage generation circuit while meeting the driving capability of the reference voltage generation circuit. It can also avoid the voltage drop loss of the reference voltage generated by the reference cell column far away from the sensitive amplifier on the long transmission line, thus avoiding the disturbance to the reference voltage.

[0088] In this design, both the storage cell and the reference cell are 2T0C gain cells with identical structures. Their transistors are n-type amorphous oxide thin-film transistors, and the device parameters of the storage cell and the reference cell are identical, including but not limited to width, length, and channel doping concentration. This ensures that during data reading, the load at each input terminal of the read decision unit consists of a reference cell and a storage cell with identical structures and device parameters, guaranteeing the symmetry of the load at both ends. This helps reduce common-mode interference noise at the input terminal of the read decision unit and improves the robustness of the read decision.

[0089] Furthermore, the reference cell can track the PVT conditions of the region where the memory cell is located. Since it adopts the same 2T0C gain cell structure as the memory cell, when the device performance (such as threshold voltage) caused by local PVT drifts, the impact on the reference cell and the memory cell in that region is also consistent. This allows the reference voltage generated by the reference cell to automatically follow the read voltage on the corresponding read bit line of the read memory cell and make adaptive adjustments in the same direction, thereby improving the reliability of data reading.

[0090] In this open memory array pair based on 2T0C gain units, exemplarily, the first stored data can be a low-level logic "0", and the second stored data can be a high-level logic "1". The first voltage can be the pre-charge voltage VDD, the second and third voltages are the array ground voltage GND, and the fourth voltage can be the turn-on voltage. The fifth voltage can be the shutdown voltage. In a memory array operating in reference mode, the reference voltage on the read bit line of the reference cell column can be... The reference voltage output by the reference voltage generation circuit can be .

[0091] The following description uses the reading of memory cell column 912 in memory cell subarray 4011 of the first memory array as an example, and the control signals in the figure can all be generated by an external memory controller. At this time, the first memory array is in read mode, and the second memory array is in reference mode.

[0092] First, before the reference voltage of the second memory array is generated, pre-charging is performed: In all memory arrays, PCH2 controls the conduction of T2, configuring the read bit lines (4051'-405n') of the second memory array as VDD. The second read word line control circuit 403' configures the read word lines (4071'-407m') of the second memory cell subarray 4011' and the reference read word lines of the second reference cell column 4021' as VDD (belonging to the reference read layer operation); the reference cell switching circuit configures the reference write word lines of all reference cell columns of the two memory arrays as VDD. (This belongs to the write layer operation). A reference voltage generation circuit is configured to generate a target reference voltage to drive the corresponding reference cell group.

[0093] The reference voltage generation operation begins at this point: First, the reference write line of the second reference cell column 4021' to be activated is configured using the reference cell switching circuit. To enable the first transistor of the reference cell in the second reference cell column 4021', and to set the target reference voltage. The gate of the second transistor configured in the reference cell.

[0094] The second step involves configuring the reference read word line 4101' as GND via the read word line control circuit. This turns on the second transistor of the reference unit corresponding to the second reference unit column 4021', thereby generating a conduction current between its first and second electrodes. After a first preset time, a reference voltage is generated on the read bit line electrically connected to the second transistor of the reference unit. A subset of reference voltages is generated on a set of read bit lines in the reference unit group of the second reference unit column 4021'. Since this reference unit column has only one reference unit group, the subset of reference voltages generated on the corresponding set of read bit lines constitutes the reference voltage set, and all reference voltages within it are... .

[0095] For the first storage array in read mode, the first read word line control circuit 403 in the read layer selects a column of storage cells 912 in the first storage cell subarray 4011 and performs a read operation on it.

[0096] The specific read operation is as follows: First, pre-charging is performed. Signal PCH1 controls the conduction of transistor T1, configuring the read bit lines (4051-405n) of the memory array as VDD. The first read word line control circuit 403 configures the read word lines of the first memory cell subarray 4011 in the memory array as VDD.

[0097] Next, a gating operation is performed. Specifically, the read word line of the selected memory cell column is configured to GND, turning on the second transistor of the corresponding memory cell. The read word lines of the remaining unselected memory cell columns remain VDD. At the same time, only memory cell column 912 in the first memory cell subarray 4011 is selected for read operation.

[0098] Next, in the read voltage generation stage, in the selected memory cell column 912, after a second preset time, the second transistor in the on state generates a read voltage on the read bit line (4051-405n) electrically connected to it. Specifically, when the memory cell stores "0", its second transistor has a lower conduction degree, generating a larger read voltage on the read bit line, which is the first read voltage; when the memory cell stores "1", its second transistor has a higher conduction degree, generating a smaller read voltage on the read bit line, which is the second read voltage. The set of all possible first and second read voltages generated on all read bit lines (4051-405n) of the read array memory cell subarray is the read voltage set.

[0099] During the sensing phase, all sensitive amplifiers in the sensitive amplifier group are activated to sense the reference voltage subset of one reference cell group in the second reference cell column 4021' and the read voltage subset on all read bit lines of the first memory cell subarray 4011. Each sensitive amplifier compares the read voltage at its two input terminals with the corresponding reference voltage within the reference voltage subset output by the corresponding reference cell group. When the read voltage is greater than the reference voltage, it reads "0"; when the read voltage is less than the reference voltage, it reads "1".

[0100] The first reference cell column 4021 of the memory array in read mode has its reference write word lines configured by the reference cell switching circuit. The first read word line control circuit 403 configures its reference read word line 4101 to VDD. The first reference cell column 4021 is turned off.

[0101] At this point, the first storage array is equivalent to only the storage cell column 912 being electrically connected to the sensitive amplifier, and the second storage array is equivalent to only the second reference cell column 4021' being electrically connected to the sensitive amplifier. Since the performance parameters (such as threshold voltage) of the devices in the reference cell column and the storage cell column are identical, the loads at the two input terminals of the sensitive amplifier are highly symmetrical. If common-mode noise interferes, the input voltages at both terminals can change in the same direction and amount, canceling out the common-mode noise and improving the reliability of data reading. Furthermore, the change in PVT conditions has the same effect on the reference cell and the storage cell, causing the drift of the read voltage and the reference voltage to change in the same direction and amount.

[0102] Figure 14 The timing diagram for reading a specific circuit of an open memory array based on a 2T0C gain unit shows that when reading the same array multiple times, the reference voltage generation operation only needs to be performed once. At the end of a read operation cycle, the read bit lines and read word lines of the first array are pre-charged to a high level VDD, while the reference voltage on the read bit lines in the memory array in reference mode remains unchanged.

[0103] The present invention has the following beneficial effects: 1. The adoption of an open bitline architecture reduces the number of read decision units, thereby improving the data storage density per unit area of ​​the array.

[0104] 2. During data reading, the reference unit isolates the read decision unit from the reference source, avoiding the reference source from directly driving the read decision unit and reducing the requirements for the reference source's driving capability.

[0105] 3. By integrating the reference cell array into the memory array, the loads at the two inputs of the read decision unit during data reading are a reference cell and a memory cell with identical structure and device parameters. This ensures the symmetry of the loads at both ends, helps reduce common-mode interference noise at the input of the read decision unit, and improves the accuracy of data reading.

[0106] 4. Compared with traditional reference sources, the reference cell array is closer to the readout decision unit, thus avoiding the voltage drop loss caused by the large parasitic resistance on long transmission lines, which affects the amplitude of the reference voltage disturbance.

[0107] 5. By employing a distributed reference cell column scheme, appropriate reference cell columns can be selected, enabling the reference cells to track the PVT conditions of the region where the memory cell is located. Furthermore, since the reference cell structure is identical to that of the memory cell, when device performance (such as threshold voltage) drifts due to local PVT, the impact on the local reference cell and memory cell is consistent. This allows the reference voltage generated by the reference cell to automatically and adaptively adjust in the same direction to follow the read voltage on the corresponding read bit line of the read memory cell, improving the reliability of data reading and the robustness of read decisions.

[0108] Corresponding to the above-described memory embodiments, this application provides an electronic device that includes the aforementioned memory. It achieves the same technical effects, and to avoid repetition, it will not be described again here. In some possible implementations, the memory is a GC-eDRAM type memory.

[0109] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0110] It is understood that the embodiments of this application have been described above in conjunction with the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. As those skilled in the art will know, various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of the invention. Furthermore, those skilled in the art, under the guidance or instruction of this application, can modify these features and embodiments to adapt to specific situations and materials without departing from the spirit and scope of the invention. Therefore, this invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the protection scope of this invention.

Claims

1. A storage array, characterized in that, include: A first preset number of storage cell subarrays; each storage cell subarray includes multiple array-distributed storage cells; wherein each column of storage cells is electrically connected to a write word line and a read word line arranged along a first direction, and each row of storage cells is electrically connected to a write bit line and a read bit line arranged along a second direction; A second preset number of reference cell columns; each reference cell column includes multiple arrayed reference cells, the reference cell columns are divided into a fifth preset number of reference cell groups, each reference cell group includes at least one reference cell; wherein, each column of reference cells is electrically connected to the same reference write word line and the same reference read word line; each row of reference cells is electrically connected to a reference read bit line; each reference cell group is electrically connected to a fourth preset number of reference write bit lines, and reference cells in different rows within the same group can be configured to be electrically connected to the same or different reference write bit lines; The read bit line of each row of storage cells and the reference read bit line of each row of reference cells are electrically connected sequentially along a first direction; The other end of a read word line electrically connected to each column of the memory cells, and the other end of a reference read word line electrically connected to each column of the reference cells, are both electrically connected to a read word line control circuit along a first direction; the read word line control circuit is used to control the voltage state of the read word line and the reference read word line.

2. The storage array according to claim 1, characterized in that, The storage unit is a gain unit, comprising: First transistor and second transistor; The gate of the first transistor is electrically connected to the write word line, the first electrode of the first transistor is electrically connected to the write bit line, and the second electrode is electrically connected to the gate of the second transistor. The first electrode of the second transistor is electrically connected to the read bit line and the second electrode is electrically connected to the read word line, or the second electrode is electrically connected to the read bit line and the first electrode is electrically connected to the read word line. The first and second transistors have a vertical channel structure and are compatible with low-temperature back-end processes, and can be stacked in three dimensions.

3. The storage array according to claim 1 or 2, characterized in that, The reference unit has the same transistor structure and transistor parameters as the memory unit; the reference unit has the same read word line, read bit line, write word line, and write bit line electrical connection method as the memory unit.

4. The storage array according to claim 3, characterized in that, The memory array also includes a set of reference voltage generation circuits and a set of reference cell switching circuits to form a reference write layer configuration; The reference voltage generation circuit is used to generate an adjustable set of reference voltages; the reference voltage generation circuit is electrically connected to each of the reference cell groups through the reference write bit line to output different or the same reference voltage to the gate of the second transistor in the reference cell of different reference cell groups. The reference unit switching circuit is electrically connected to each of the reference unit groups through the reference writing line, and is used to control the conduction and cutoff of the first transistor in the reference unit within the reference unit group.

5. The storage array according to claim 4, characterized in that, The transistors in the reference voltage generation circuit have the same transistor structure as those in the memory cell.

6. A memory, characterized in that, include: At least one open storage array pair based on the storage array described in any one of claims 1-5; The open storage array pair includes a first storage array, a second storage array, and a set of read decision units; The read decision device includes a first input terminal, a second input terminal, and a first output terminal. The read bit line of the first storage array is electrically connected to the first input terminal, and the read bit line of the second storage array is electrically connected to the second input terminal. The storage cell subarrays and reference cell columns in the first and second storage arrays are symmetrically distributed with the read decision unit as the center of symmetry. When one of the first input terminal and the second input terminal is a data input terminal, the other is a reference input terminal; The first output terminal is used to output the corresponding logic decision result of the voltage at the first input terminal and the voltage at the second input terminal of the read decision unit. The first output terminal is a single-ended output or a double-ended output.

7. The memory according to claim 6, characterized in that, Multiple open memory arrays are integrated in a multi-layer stack on a single wafer.

8. A method for reading a memory, characterized in that, Reading from the memory according to any one of claims 6-7, comprising: Perform the following on the memory array in reference mode: S11: Pre-charge, configure the read bit line, read word line and reference read word line of the memory array in reference mode to the first voltage, and configure the reference write word line of all reference cell columns to the fifth voltage; S12: Write reference voltage, configure the reference write word line of at least one target reference cell column in the memory array of the reference mode to a fourth voltage, so as to turn on the first transistor of the reference cell column and write the reference voltage set to the gate of the second transistor of the reference cell. S13: Generate a reference voltage, configure the reference read word line of the target reference cell column to a third voltage, turn on the second transistor of the reference cell, and after a first preset time, generate a reference voltage set on the read bit line electrically connected to the second transistor. Perform the following on the memory array in read mode: S21: Pre-charge, configuring the read bit lines and all read word lines of the memory array in read mode to the first voltage; S22: Gating configuration, configuring the read word line of the selected target memory cell column to a second voltage to turn on the second transistor of the target memory cell column; S23: Generate a read voltage. After a second preset time, generate a set of read voltages on the read bit lines of the memory array in the read mode. S24: Sensing decision, activating the read decision unit, comparing the reference voltage set with the read voltage set, and outputting the decision result; to read the corresponding stored data in the gate of the second transistor of the memory cell in the target memory cell column.

9. The method for reading a memory according to claim 8, characterized in that, During the reference voltage generation phase, the read word lines of all memory cell subarrays of the memory array in reference mode are maintained at the first voltage to turn off the second transistors of all their memory cells.

10. The method for reading a memory according to claim 8, characterized in that, During the sensing decision phase, the reference write word lines of all reference cell columns of the memory array in read mode are configured to the fifth voltage, and the reference read word lines are configured to the first voltage, so as to turn off all reference cell columns.

11. An electronic device, characterized in that, Includes the memory as described in any one of claims 6-7.

Images