A bridgeless Cuk power factor correction topology circuit and its control strategy

Abstract

A bridgeless Cuk power factor correction topology circuit and its control strategy are disclosed. The circuit includes an AC voltage source, a filter energy storage module, a bridgeless rectifier module, a power frequency ripple coupling module, a buck filter module, and an equivalent load RL. This circuit uses transistors instead of traditional rectifier bridge diodes, reducing the number of components and solving the problem of high conduction losses in traditional diodes. It also offers advantages such as reduced power consumption and high reliability, improving the efficiency of the Cuk PFC converter. Furthermore, based on the bridgeless Cuk power factor correction topology circuit, this invention proposes a simple and easy-to-implement dead-time control strategy and a zero-crossing control strategy, ensuring the integrity of the inductor freewheeling path. Compared to traditional totem-pole bridgeless PFC converters, it has lower requirements for controller performance and better robustness.

Description

Technical Field

[0001] This invention relates to the field of switching power supply technology, specifically to a bridgeless Cuk power factor correction topology circuit and its control strategy. Background Technology

[0002] During the operation of a bridgeless PFC (Power Factor Correction) circuit, the increased number of MOSFETs introduces many new problems, such as zero-crossing distortion and the need for dead-time control, making the control method of totem-pole bridgeless PFC more complex. Traditional switching power supplies typically employ a two-stage architecture to achieve high power factor and low output ripple. First, a boost PFC stage is used to obtain a DC voltage with a frequency component twice the line voltage, and then a buck circuit is used to absorb the ripple. This process of boosting and then bucking inevitably leads to a decrease in overall efficiency and power density, which contradicts the goal of increasing power density and efficiency by reducing capacitors and inductors through increasing the switching frequency. The traditional Cuk PFC converter topology can be viewed as an integrated boost and buck circuit, possessing wide output voltage capability. However, the traditional Cuk PFC converter topology uses multiple diodes for rectification in multiple operating modes, resulting in operating losses.

[0003] Xiang Lin published "A Novel Bridgeless Cuk PFC Converter with Further Reduced Conduction Losses and Simple Circuit Structure" in the journal IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS. This paper proposes a novel bridgeless Cuk PFC converter structure, which reduces the transmission loss caused by the rectifier bridge by replacing the rectifier bridge in the traditional topology with two high-frequency MOSFETs and two power frequency diodes, while keeping the number of other components unchanged. However, its drawback is that it does not significantly reduce the number of components compared to the traditional topology. While the use of more MOSFETs increases the cost, there are still many diodes in the current loop, resulting in a less significant reduction in transmission loss. Summary of the Invention

[0004] To overcome the shortcomings of the existing technology, the present invention aims to provide a bridgeless Cuk power factor correction topology circuit and its control strategy. This circuit uses transistors to replace traditional rectifier bridge diodes, reducing the number of components and solving the problem of high conduction losses of traditional diodes. It also has the advantages of reduced power consumption and high reliability, thus improving the efficiency of the Cuk PFC converter. At the same time, based on the bridgeless Cuk power factor correction topology circuit, a simple and easy-to-implement dead-time control strategy and zero-crossing control strategy are proposed to ensure the integrity of the inductor freewheeling path. Compared with the traditional totem-pole bridgeless PFC converter, it has lower requirements for controller performance and better robustness.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows: A bridgeless Cuk power factor correction topology circuit includes an AC voltage source, a filter energy storage module, a bridgeless rectifier module, a power frequency ripple coupling module, a buck filter module, and an equivalent load RL. The AC voltage source is connected to the filter energy storage module to filter out the high-frequency switching components of the AC voltage output from the AC voltage source. The filter energy storage module is connected to the bridgeless rectifier module to synchronously rectify the AC voltage after filtering by the filter energy storage module during the positive and negative half-cycles, converting it into a DC voltage. The bridgeless rectifier module is connected to the power frequency ripple coupling module to buffer the power frequency ripple in the DC voltage converted by the bridgeless rectifier module. The power frequency ripple coupling module is connected to the buck filter module to step down and filter the DC voltage buffered by the power frequency ripple coupling module. The buck filter module is connected to the equivalent load RL to supply the DC voltage output by the buck filter module to the equivalent load RL.

[0006] Furthermore, the filtering energy storage module is an inductor L1, with the first end of the inductor L1 connected to the first end of the AC voltage source and the second end of the inductor L1 connected to the bridgeless rectifier module.

[0007] Further, the bridgeless rectifier module includes an interconnected power frequency transistor pair and a high frequency transistor pair; the power frequency transistor pair includes power frequency transistor M1, power frequency transistor M2, diode D4, and diode D5; the high frequency transistor pair includes high frequency transistor H1, high frequency transistor H2, diode D1, and diode D2; the drain of power frequency transistor M1 is connected to the cathode of diode D4, the drain of power frequency transistor M2, and the cathode of diode D5, respectively; the source of power frequency transistor M1 is connected to the anode of diode D4, the drain of high frequency transistor H1, and the cathode of diode D1, respectively; the source of power frequency transistor M1 is connected to... The connection point between the drains of high-frequency transistor H1 is connected to the second terminal of inductor L1. The source of power frequency transistor M2 is connected to the anode of diode D5, the drain of high-frequency transistor H2, and the cathode of diode D2, respectively. The connection point between the source of power frequency transistor M2 and the drain of high-frequency transistor H2 is connected to the second terminal of AC voltage source. The source of high-frequency transistor H1 is connected to the anode of diode D1, the source of high-frequency transistor H2, and the anode of diode D2, respectively. The gates of power frequency transistor M1, power frequency transistor M2, high-frequency transistor H1, and high-frequency transistor H2 are all connected to on / off control signals.

[0008] Furthermore, the power frequency ripple coupling module is a capacitor C1. The first end of the capacitor C1 is connected to the connection point between the drain of the power frequency tube M1 and the cathode of the diode D5, and the second end of the capacitor C1 is connected to the step-down filter module.

[0009] Furthermore, the step-down filter module includes a high-frequency transistor H3, a diode D3, an inductor L2, and a capacitor C2. The source of the high-frequency transistor H3 is connected to the anode of the diode D3, the second terminal of the capacitor C1, and the first terminal of the inductor L2. The drain of the high-frequency transistor H3 is connected to the cathode of the diode D3, the connection point between the source of the high-frequency transistor H1 and the anode of the diode D2, the second terminal of the capacitor C2, and the second terminal of the equivalent load RL. The source of the high-frequency transistor H1 is grounded. The first terminal of the capacitor C2 is connected to the second terminal of the inductor L2 and the first terminal of the equivalent load RL. The gate of the high-frequency transistor H3 is connected to an on / off control signal.

[0010] Furthermore, the power frequency transistor M1, power frequency transistor M2, high frequency transistor H1, high frequency transistor H2 and high frequency transistor H3 are all transistors, including but not limited to MOSFET and HEMT.

[0011] A dead-time control strategy for a bridgeless Cuk power factor correction topology circuit involves the following steps: when high-frequency transistors H1 and H2 switch from on to off, and high-frequency transistor H3 switches from off to on, H1 and H2 are first turned off, and H3 is turned on after one dead time. Conversely, when high-frequency transistors H1 and H2 switch from off to on, and H3 switches from on to off, H3 is first turned off, and H1 and H2 are turned on after one dead time. This strategy aims to prevent capacitor C1 from short-circuiting due to simultaneous conduction of high-frequency transistors H1, H2, and H3.

[0012] A zero-crossing control strategy for a bridgeless Cuk power factor correction topology circuit is provided. When the AC voltage input to the bridgeless Cuk power factor correction topology circuit is switching between positive and negative half-cycles, if high-frequency transistors H1 and H2 are simultaneously turned on, then power frequency transistors M1 and M2 are simultaneously turned on. After a dead time, the previously turned-on power frequency transistors M1 or M2 are turned off. If high-frequency transistors H1 and H2 are simultaneously turned off, then power frequency transistors M1 and M2 are simultaneously turned off. After a dead time, the previously turned-off power frequency transistors M1 or M2 are turned on again. This ensures that the switching states of power frequency transistors M1, M2, H1, and H2 are consistent when the power frequency crosses zero, and the charging and discharging states of inductors L1 and L2 will not change due to the zero crossing.

[0013] A switching power supply, comprising a bridgeless Cuk power factor correction topology circuit as described above.

[0014] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. The bridgeless rectifier module of this invention is an improvement on the traditional totem pole rectifier bridge. By replacing the diodes in the traditional totem pole rectifier bridge with transistors (i.e., power frequency transistor M1, power frequency transistor M2, high frequency transistor H1, and high frequency transistor H2), the dependence of the bridgeless Cuk PFC converter on diodes is reduced. This solves the problems of high conduction loss, high-frequency heat generation, low PFC efficiency, and complicated device layout in the traditional totem pole rectifier bridge. It features reduced power consumption, fast response, small on-state voltage drop, low switching loss, simplified structure, high reliability, and excellent high-frequency performance, thereby improving the efficiency of the bridgeless Cuk PFC converter and reducing the number of devices used.

[0015] 2. The buck filter module of the present invention solves the problems of high conduction loss and poor high-frequency performance of the output freewheeling diode in the traditional Cuk PFC topology by replacing the traditional diode with a transistor (high-frequency transistor H3). It has the characteristics of reduced power consumption, fast response, low switching loss, good high-frequency performance and simple control.

[0016] 3. The current path of the present invention under different operating modes is improved from the current path of the existing bridgeless Cuk PFC converter. By keeping the power frequency transistors M1 and M2 always on, the requirement of the bridgeless Cuk PFC converter for additional transistors is reduced. This solves the problems of the existing bridgeless Cuk PFC converter having many components, reduced overall efficiency, and complex control. It has the characteristics of cost reduction, simplified control, and improved reliability.

[0017] 4. The dead-time control strategy and zero-crossing control strategy of the present invention based on the bridgeless Cuk power factor correction topology circuit are simple and easy to implement, and the inductor freewheeling path is complete. Therefore, compared with the traditional totem pole bridgeless PFC converter, it has lower requirements for controller performance and better robustness.

[0018] In summary, the bridgeless Cuk power factor correction topology circuit of this invention uses transistors instead of traditional rectifier bridge diodes, reducing the number of components and solving the problems of high conduction losses in traditional diodes. It also has the advantages of reduced power consumption and high reliability, improving the efficiency of the Cuk PFC converter. At the same time, its control strategy and operating mode are simple and reliable, and the inductor freewheeling path is complete. Compared with traditional totem-pole bridgeless PFC converters, it has lower requirements for controller performance and better robustness. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of a traditional bridgeless Cuk PFC converter.

[0020] Figure 2 This is a schematic diagram of the bridgeless Cuk power factor correction topology circuit of the present invention. Figure 1 .

[0021] Figure 3 This is a schematic diagram of the bridgeless Cuk power factor correction topology circuit of the present invention. Figure 2 .

[0022] Figure 4 This is an analytical diagram of the bridgeless Cuk power factor correction topology circuit of the present invention.

[0023] Figure 5 The diagram shows the three operating modes of the bridgeless Cuk power factor correction topology circuit of the present invention during the positive half-AC input cycle; wherein, Figure 5 (a) in the diagram is the first mode diagram of the positive half-cycle of the bridgeless Cuk power factor correction topology; Figure 5 (b) in the diagram is the second mode diagram of the positive half-cycle of the bridgeless Cuk power factor correction topology; Figure 5 (c) in the diagram is the third mode diagram of the positive half-cycle of the bridgeless Cuk power factor correction topology.

[0024] Figure 6The diagram shows the three operating modes of the bridgeless Cuk power factor correction topology circuit of the present invention during the negative half-AC input cycle; wherein, Figure 6 (a) in the diagram is the first mode diagram of the negative half-cycle of the bridgeless Cuk power factor correction topology circuit; Figure 6 (b) in the diagram is the second mode diagram of the negative half-cycle of the bridgeless Cuk power factor correction topology; Figure 6 (c) in the diagram is the third mode diagram of the negative half-cycle of the bridgeless Cuk power factor correction topology.

[0025] Figure 7 Waveform simulation of the present invention in open-loop control mode Figure 1 ;in, Figure 7 (a) in the figure is a simulation diagram of the control signal waveform of the high-frequency tube H1; Figure 7 (b) in the figure is a simulation diagram of the current waveform of inductor L1; Figure 7 (c) in the figure is a simulation diagram of the current waveform of inductor L2.

[0026] Figure 8 Waveform simulation of the present invention in open-loop control mode Figure 2 ;in, Figure 8 In the diagram, (a) represents the AC input sinusoidal voltage V. ac Waveform simulation diagram; Figure 8 (b) in the figure is a simulation diagram of the control signal waveforms of power frequency transistors M1 and M2; Figure 8 In the equation (c), the output voltage V is... DC The waveform simulation diagram.

[0027] Where L1 and L2 are inductors, M1 and M2 are power frequency transistors, H1, H2, and H3 are high frequency transistors, D1, D2, D3, D4, and D5 are diodes, C1 and C2 are capacitors, RL is the equivalent load, and V ac For sinusoidal voltage, V DC This is the voltage output by capacitor C2. Detailed Implementation

[0028] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments: See Figure 1 and Figure 2Compared to the bridgeless Cuk PFC converter structure proposed in traditional topologies and background technologies, this invention more tightly integrates the totem-pole structure and Cuk circuit, reducing the overall number of components required. Furthermore, while ensuring simple control, it replaces diodes with transistors to the greatest extent possible. This ensures that in operating modes requiring diode freewheeling, only one diode participates in freewheeling, reducing transmission losses and overall cost. Since transistors replace diodes, dead-time control and zero-crossing control issues arise. This invention also provides complete dead-time control and zero-crossing control strategies.

[0029] See Figure 2 and Figure 3 This invention provides a bridgeless Cuk power factor correction topology circuit, comprising an AC voltage source, a filter energy storage module, a bridgeless rectifier module, a power frequency ripple coupling module, a buck filter module, and an equivalent load RL. The AC voltage source is connected to the filter energy storage module to filter out the high-frequency switching components of the AC voltage output from the AC voltage source. The filter energy storage module is connected to the bridgeless rectifier module to synchronously rectify the AC voltage after filtering by the filter energy storage module during the positive and negative half-cycles, converting it into a DC voltage. The bridgeless rectifier module is connected to the power frequency ripple coupling module to buffer the power frequency ripple in the DC voltage converted by the bridgeless rectifier module. The power frequency ripple coupling module is connected to the buck filter module to step down and filter the DC voltage buffered by the power frequency ripple coupling module. The buck filter module is connected to the equivalent load RL to supply the DC voltage output by the buck filter module to the equivalent load RL.

[0030] See Figure 4 The AC voltage source in this embodiment includes a first terminal and a second terminal. The first terminal is connected to the AC L-line voltage, and the second terminal is connected to the AC N-line voltage. A sinusoidal voltage V exists between the first terminal and the second terminal. ac It is used to provide alternating positive and negative half-cycle AC input voltages for the bridgeless Cuk power factor correction topology circuit.

[0031] The filtering energy storage module is an inductor L1. The first end of the inductor L1 is connected to the first end of the AC voltage source, and the second end of the inductor L1 is connected to the bridgeless rectifier module. In this embodiment, the inductor L1 is a single inductor or a series connection of multiple inductors, and the inductance of the inductor L1 is 120uH. The bridgeless rectifier module includes interconnected power frequency transistor pairs and high frequency transistor pairs; the power frequency transistor pairs and high frequency transistor pairs form a bridge arm, which is usually composed of switching transistors. The switching transistors are controlled by an external drive signal to achieve the rectification function.

[0032] The power frequency transistor pair includes power frequency transistor M1, power frequency transistor M2, diode D4, and diode D5; the high frequency transistor pair includes high frequency transistor H1, high frequency transistor H2, diode D1, and diode D2; the drain of power frequency transistor M1 is connected to the cathode of diode D4, the drain of power frequency transistor M2, and the cathode of diode D5, respectively; the source of power frequency transistor M1 is connected to the anode of diode D4, the drain of high frequency transistor H1, and the cathode of diode D1, respectively; the connection point between the source of power frequency transistor M1 and the drain of high frequency transistor H1 is connected to... The source of the power frequency transistor M2 is connected to the anode of diode D5, the drain of high-frequency transistor H2, and the cathode of diode D2, respectively. The connection point between the source of power frequency transistor M2 and the drain of high-frequency transistor H2 is connected to the second terminal of the AC voltage source. The source of high-frequency transistor H1 is connected to the anode of diode D1, the source of high-frequency transistor H2, and the anode of diode D2, respectively. The gates of power frequency transistor M1, power frequency transistor M2, high-frequency transistor H1, and high-frequency transistor H2 are all connected to the on / off control signal.

[0033] In this embodiment, the operating frequencies of power frequency transistors M1 and M2 are both 50Hz (the mains voltage frequency), and the gate frequencies of high frequency transistors H1 and H2 are both 50kHz with a duty cycle of 10%. Furthermore, this embodiment can employ traditional open-loop control, where the on / off control signal is controlled by a digital controller (DSP). The generated and output data is only used to achieve the switching of the working mode of this invention, so as to complete the drive control of the positive and negative half-cycles of the AC input. This invention does not specifically limit this.

[0034] The power frequency ripple coupling module is capacitor C1. The first end of capacitor C1 is connected to the connection point between the drain of power frequency tube M1 and the cathode of diode D5, and the second end of capacitor C1 is connected to the step-down filter module. In this embodiment, capacitor C1 is a 50uF metallized polypropylene film capacitor.

[0035] The step-down filter module includes a high-frequency transistor H3, a diode D3, an inductor L2, and a capacitor C2. The source of the high-frequency transistor H3 is connected to the anode of the diode D3, the second terminal of the capacitor C1, and the first terminal of the inductor L2. The drain of the high-frequency transistor H3 is connected to the cathode of the diode D3, the connection point between the source of the high-frequency transistor H1 and the anode of the diode D2, the second terminal of the capacitor C2, and the second terminal of the equivalent load RL. The source of the high-frequency transistor H1 is grounded. The first terminal of the capacitor C2 is connected to the second terminal of the inductor L2 and the first terminal of the equivalent load RL. The gate of the high-frequency transistor H3 is connected to an on / off control signal.

[0036] In this embodiment, the inductance of L1 is 1mH, the capacitor C2 is a 50uF metallized polypropylene film capacitor, the high-frequency tube H3 operates at a frequency of 50KHz and has a duty cycle of 90%, and is complementary to the high-frequency tubes H1 and H2; the equivalent load RL in this embodiment can also be LED lights or DC motors or other electrical equipment that require DC power supply.

[0037] The power frequency transistors M1, M2, H1, H2, and H3 are all transistors, including but not limited to MOSFETs (metal-oxide-semiconductor field-effect transistors) and HEMTs (high electron mobility transistors).

[0038] In this embodiment, diodes D1, D2, D3, D4, and D5 are all fast recovery diodes, thereby providing freewheeling paths for inductors L1 and L2 and ensuring reliable circuit operation.

[0039] In this embodiment, the power frequency transistors M1 and M2 are both IPB65R110CFDA, the high frequency transistors H1, H2, and H3 are all INN650D080BS, and the diodes D1, D2, D3, D4, and D5 are all FFSB0665A.

[0040] A dead-time control strategy for a bridgeless Cuk power factor correction topology circuit: When high-frequency transistors H1 and H2 switch from on to off, and high-frequency transistor H3 switches from off to on, high-frequency transistors H1 and H2 are turned off first, and after one dead time, high-frequency transistor H3 is turned on; when high-frequency transistors H1 and H2 switch from off to on, and high-frequency transistor H3 switches from on to off, high-frequency transistor H3 is turned off first, and after one dead time, high-frequency transistors H1 and H2 are turned on, to prevent high-frequency transistors H1, H2, and H3 from being turned on simultaneously, which would cause capacitor C1 to short-circuit.

[0041] A zero-crossing control strategy for a bridgeless Cuk power factor correction topology circuit: When the AC voltage input to the bridgeless Cuk power factor correction topology circuit is switching between positive and negative half-cycles, if high-frequency transistors H1 and H2 are simultaneously turned on, then power frequency transistors M1 and M2 are simultaneously turned on. After a dead time, the previously turned-on power frequency transistors M1 or M2 are turned off. If high-frequency transistors H1 and H2 are simultaneously turned off, then power frequency transistors M1 and M2 are simultaneously turned off. After a dead time, the previously turned-off power frequency transistors M1 or M2 are turned on again. This ensures that the switching states of power frequency transistors M1, M2, H1, and H2 are consistent when the power frequency crosses zero, and the charging and discharging states of inductors L1 and L2 will not change due to the zero crossing.

[0042] A switching power supply, comprising a bridgeless Cuk power factor correction topology circuit as described above.

[0043] The working principle of this invention is as follows: Before the bridgeless Cuk power factor correction topology circuit is enabled, the entire bridgeless rectifier module is turned off, the high-frequency tube H3 of the buck filter module is turned on, and capacitor C1 is charged to the peak AC voltage through inductor L1, bridgeless rectifier module and high-frequency tube H3. The operating mode of the bridgeless Cuk power factor correction topology circuit after being enabled is as follows: See Figure 5 In the (ac) mode, when both the first and second terminals of the AC voltage source are input with a positive half-cycle AC voltage, the power frequency transistor M1 is turned on and the power frequency transistor M2 is turned off, entering the first positive half-cycle mode: high frequency transistors H1 and H2 are turned on, and high frequency transistor H3 is turned off; inductor L1 is charged clockwise by the AC voltage source through high frequency transistors H1 and H2; inductor L2 is charged by capacitor C1 through power frequency transistor M1, high frequency transistor H1, and equivalent load RL; when the mode switching condition is met (for example, in the open-loop control mode where the high frequency transistor operates at a fixed frequency and a fixed duty cycle, the mode switching condition is when the conduction time of high frequency transistors H1 and H2 ends; in addition, it also includes a current control mode where the high frequency transistor determines the switching state based on the inductor current, the mode switching condition is when the current of inductor L1 reaches the target control value), the mode switching condition of the bridgeless Cuk power factor correction topology circuit of the present invention can be adjusted according to different control conditions. (The specific method is determined by the method, and this invention does not impose specific limitations), entering the second positive half-cycle mode: high-frequency transistors H1 and H2 are turned off, and high-frequency transistor H3 is turned on; inductor L1 discharges to capacitor C1 through power frequency transistor M1, high-frequency transistor H3, and diode D2; inductor L2 discharges through high-frequency transistor H3; when inductor L1 discharges to 0, entering the third positive half-cycle mode: high-frequency transistors H1 and H2 are turned off, and high-frequency transistor H3 is turned on; the current of inductor L1 remains at 0; inductor L2 discharges through high-frequency transistor H3 until the mode switching condition is met (for example, in open-loop control mode, this mode switching condition is the end of one switching cycle of high-frequency transistors H1 and H2; in current control mode where the switching state is determined based on the inductor current, this mode switching condition is after the current discharge of inductor L2 reaches the target control value), and then repeating the first positive half-cycle mode, the second positive half-cycle mode, and the third positive half-cycle mode in sequence; See Figure 6In the AC voltage source, when both the first and second terminals are input with negative half-cycle AC voltage, the power frequency transistor M2 is turned on and the power frequency transistor M1 is turned off, entering the first mode of the negative half-cycle: high frequency transistors H1 and H2 are turned on, and high frequency transistor H3 is turned off; inductor L1 is charged counterclockwise by the AC power supply through high frequency transistors H1 and H2; inductor L2 is charged by capacitor C1 through power frequency transistor M2, high frequency transistor H2, and the equivalent load RL; when the mode switching condition is met (for example, in open-loop control mode, the mode switching condition is the end of the conduction time of high frequency transistors H1 and H2; in current control mode where the switching state is determined according to the inductor current, the mode switching condition is after the current of inductor L1 reaches the target control value), the second mode of the negative half-cycle is entered: high frequency transistors H1 and H2... When the circuit is turned off, high-frequency transistor H3 is turned on; inductor L1 discharges to capacitor C1 through power frequency transistor M2, high-frequency transistor H3, and diode D1, while inductor L2 discharges through high-frequency transistor H3; when inductor L1 discharges to 0, it enters the third mode of the negative half-cycle: high-frequency transistors H1 and H2 are turned off, and high-frequency transistor H3 is turned on; the current of inductor L1 remains at 0; inductor L2 discharges through high-frequency transistor H3 until the mode switching condition is met (for example, in open-loop control mode, this mode switching condition is the end of one switching cycle of high-frequency transistors H1 and H2; in current control mode where the switching state is determined based on the inductor current, this mode switching condition is after the current discharge of inductor L2 reaches the target control value), and then the cycle repeats sequentially according to the first mode of the negative half-cycle, the second mode of the negative half-cycle, and the third mode of the negative half-cycle.

[0044] Performance simulation Open-loop simulation was performed using PSIM simulation software; results are shown below. Figure 7 (ac) and Figure 8 (ac) in Figure 7 In the figure, (ac) represents the change in current of inductors L1 and L2 during the three-mode switching process of the high-frequency transistor in the positive half-cycle at a switching frequency of 50kHz. Figure 8 In the figure, (ac) represents the switching of control signals for power frequency transistors M1 and M2 under an input 50Hz power frequency voltage, as well as the output voltage magnitude. As can be seen from the figure, after inputting an AC voltage of 35V RMS, the output voltage is -12V DC, indicating that the bridgeless Cuk power factor correction topology circuit and its control strategy of this invention can operate normally.

[0045] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications, equivalent substitutions or improvements made by those skilled in the art within the spirit and principles of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A bridgeless Cuk power factor correction topology circuit, characterized in that: The system includes an AC voltage source, a filter and energy storage module, a bridgeless rectifier module, a power frequency ripple coupling module, a step-down filter module, and an equivalent load RL. The AC voltage source is connected to the filter and energy storage module to filter out the high-frequency switching components of the AC voltage output from the AC voltage source. The filter and energy storage module is connected to the bridgeless rectifier module to synchronously rectify the AC voltage after filtering by the filter and energy storage module during the positive and negative half-cycles, converting it into a DC voltage. The bridgeless rectifier module is connected to the power frequency ripple coupling module to buffer the power frequency ripple in the DC voltage converted by the bridgeless rectifier module. The power frequency ripple coupling module is connected to the step-down filter module to step down and filter the DC voltage buffered by the power frequency ripple coupling module. The step-down filter module is connected to the equivalent load RL to supply the DC voltage output by the step-down filter module to the equivalent load RL.

2. The bridgeless Cuk power factor correction topology circuit according to claim 1, characterized in that: The filtering energy storage module is an inductor L1. The first end of the inductor L1 is connected to the first end of the AC voltage source, and the second end of the inductor L1 is connected to the bridgeless rectifier module.

3. The bridgeless Cuk power factor correction topology circuit according to claim 1, characterized in that: The bridgeless rectifier module includes interconnected power frequency transistors and high frequency transistors; the power frequency transistors include power frequency transistor M1, power frequency transistor M2, diode D4, and diode D5; the high frequency transistors include high frequency transistor H1, high frequency transistor H2, diode D1, and diode D2; the drain of power frequency transistor M1 is connected to the cathode of diode D4, the drain of power frequency transistor M2, and the cathode of diode D5, respectively; the source of power frequency transistor M1 is connected to the anode of diode D4, the drain of high frequency transistor H1, and the cathode of diode D1, respectively; the source of power frequency transistor M1 is connected to the high frequency transistor... The connection point between the drains of transistor H1 is connected to the second terminal of inductor L1. The source of power frequency transistor M2 is connected to the anode of diode D5, the drain of high frequency transistor H2, and the cathode of diode D2, respectively. The connection point between the source of power frequency transistor M2 and the drain of high frequency transistor H2 is connected to the second terminal of AC voltage source. The source of high frequency transistor H1 is connected to the anode of diode D1, the source of high frequency transistor H2, and the anode of diode D2, respectively. The gates of power frequency transistor M1, power frequency transistor M2, high frequency transistor H1, and high frequency transistor H2 are all connected to on / off control signals.

4. The bridgeless Cuk power factor correction topology circuit according to claim 1, characterized in that: The power frequency ripple coupling module is capacitor C1. The first end of capacitor C1 is connected to the connection point between the drain of power frequency tube M1 and the cathode of diode D5, and the second end of capacitor C1 is connected to the step-down filter module.

5. The bridgeless Cuk power factor correction topology circuit according to claim 1, characterized in that: The step-down filter module includes a high-frequency transistor H3, a diode D3, an inductor L2, and a capacitor C2. The source of the high-frequency transistor H3 is connected to the anode of the diode D3, the second terminal of the capacitor C1, and the first terminal of the inductor L2. The drain of the high-frequency transistor H3 is connected to the cathode of the diode D3, the connection point between the source of the high-frequency transistor H1 and the anode of the diode D2, the second terminal of the capacitor C2, and the second terminal of the equivalent load RL. The source of the high-frequency transistor H1 is grounded. The first terminal of the capacitor C2 is connected to the second terminal of the inductor L2 and the first terminal of the equivalent load RL. The gate of the high-frequency transistor H3 is connected to an on / off control signal.

6. A bridgeless Cuk power factor correction topology circuit according to claim 3 or 5, characterized in that: The power frequency transistors M1, M2, H1, H2, and H3 are all transistors, including but not limited to MOSFETs and HEMTs.

7. A dead-time control strategy for a bridgeless Cuk power factor correction topology circuit, characterized in that: When high-frequency transistors H1 and H2 switch from being on to being off, and high-frequency transistor H3 switches from being off to being on, high-frequency transistors H1 and H2 are turned off first, and after one dead time, high-frequency transistor H3 is turned on. When high-frequency transistors H1 and H2 switch from being off to being on, and high-frequency transistor H3 switches from being on to being off, high-frequency transistor H3 is turned off first, and after one dead time, high-frequency transistors H1 and H2 are turned on, to prevent high-frequency transistors H1, H2, and H3 from being turned on simultaneously and causing a short circuit in capacitor C1.

8. A zero-crossing control strategy for a bridgeless Cuk power factor correction topology circuit, characterized in that: When the AC voltage input to the bridgeless Cuk power factor correction topology circuit is switching between positive and negative half-cycles, if high-frequency transistors H1 and H2 are turned on simultaneously, then power frequency transistors M1 and M2 are turned on simultaneously. After a dead time, the previously turned-on power frequency transistor M1 or M2 is turned off. If high-frequency transistors H1 and H2 are turned off simultaneously, then power frequency transistors M1 and M2 are turned off simultaneously. After a dead time, the previously turned-off power frequency transistor M1 or M2 is turned on again. This ensures that the switching states of power frequency transistors M1, M2, H1, and H2 are consistent when the power frequency crosses zero, and that the charging and discharging states of inductors L1 and L2 do not change due to the zero crossing.

9. A switching power supply comprising any one of the bridgeless Cuk power factor correction topologies as described in claims 1-6.

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