Semiconductor packaging structure, preparation method thereof and electronic equipment

Abstract

The invention provides a semiconductor packaging structure and a preparation method thereof, and an electronic device, and the semiconductor packaging structure comprises a glass interposer which comprises a glass through hole penetrating in the thickness direction and a first conductor filling the glass through hole; a silicon bridge chip disposed on at least one side of the glass interposer; the second electric conductor and the silicon bridge chip are arranged on the same side of the glass intermediate layer; the functional chip is arranged on one side, far away from the glass intermediate layer, of the silicon bridge chip and the second conductor; wherein the functional chip is electrically connected with the first conductor through the silicon bridge chip and / or the second conductor. Through the glass intermediate layer, overall packaging warping caused by thermal stress or mismatching stress in the preparation process or the device working process can be inhibited, so that the warping risk is reduced, and the packaging flatness and the size stability are improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and in particular to a semiconductor packaging structure and its preparation method, and an electronic device. Background Technology

[0002] With the development of high-performance chips, chip integration is becoming increasingly sophisticated, and the development of multi-chip heterogeneous integration has reached a bottleneck, placing increasingly higher demands on the mechanical strength and flatness of the substrate. Summary of the Invention

[0003] In view of this, the purpose of this application is to propose a semiconductor packaging structure and its fabrication method, and an electronic device, which achieves the mechanical strength and flatness of the substrate required for multi-chip integration by using a glass interposer and combining silicon bridges and vertical interconnect structures.

[0004] In view of the above objectives, in a first aspect, this application provides a semiconductor packaging structure, comprising: A glass interlayer, including a glass via extending along the thickness direction and a first conductor filling the glass via; A silicon bridge chip is disposed on at least one side of a glass interlayer; The second conductor is located on the same side of the glass interlayer as the silicon bridge chip; The functional chip is located on the side of the silicon bridge chip and the second conductor away from the glass interlayer. The functional chip is electrically connected to the first conductor via a silicon bridge chip and / or a second conductor.

[0005] Optional, also includes: The first wiring layer is disposed on one side of the glass interposer, the silicon bridge chip and the second conductor are disposed on the side of the first wiring layer away from the glass interposer, and the silicon bridge chip and the second conductor are electrically connected to the first wiring layer respectively. The first molding layer is disposed on the side of the first interconnect layer away from the glass interlayer, and the first molding layer covers the silicon bridge chip and the second conductor; Preferably, the silicon bridge chip and the second conductor are spaced apart, and the first molding layer fills the space between the silicon bridge chip and the second conductor; Optionally, the end of the silicon bridge chip away from the glass interlayer is exposed on the surface of the first molding compound away from the glass interlayer, and the end of the second conductor away from the glass interlayer is exposed on the surface of the first molding compound away from the glass interlayer. Optionally, the thickness of the first molding layer is 30μm-150μm.

[0006] Optional, also includes: The second wiring layer is disposed on the side of the first molding layer away from the glass interlayer, and the functional chip is disposed on the side of the second wiring layer away from the glass interlayer. The second molding layer is disposed on the side of the second wiring layer away from the glass interlayer, and the second molding layer encapsulates the functional chip. Optionally, the end of the functional chip away from the glass interlayer is exposed on the surface of the second molding layer away from the glass interlayer; Optionally, the thickness of the second molding layer is 50μm-500μm.

[0007] Optionally, the functional chip includes a first chip and a second chip, the first chip and the second chip being electrically connected to the silicon bridge chip respectively, and the first chip and the second chip being electrically connected to each other through the silicon bridge chip; Optionally, the orthographic projection of the first chip on the glass interposer layer at least partially overlaps with the orthographic projection of the silicon bridge chip on the glass interposer layer; the orthographic projection of the second chip on the glass interposer layer at least partially overlaps with the orthographic projection of the silicon bridge chip on the glass interposer layer. Optionally, the number of functional chips may exceed the number of silicon bridge chips.

[0008] Optionally, the semiconductor package structure further includes a third wiring layer and conductive bumps. The third wiring layer is disposed on the side of the glass interposer away from the silicon bridge chip. The third wiring layer is electrically connected to the first wiring layer through a first conductor. The conductive bumps are disposed on the side of the third wiring layer away from the glass interposer.

[0009] Secondly, this application also provides a method for fabricating a semiconductor packaging structure, comprising: A glass substrate is provided, a glass through-hole is formed in the glass substrate along the thickness direction, and a first conductor is formed in the glass through-hole to form a glass interlayer. A first wiring layer is formed on at least one side of the glass interlayer; A silicon bridge chip and a second conductor are disposed on the side of the first wiring layer away from the glass interlayer. A functional chip is disposed on the side of the silicon bridge chip and the second conductor away from the glass interlayer; wherein the functional chip is electrically connected to the first conductor through the silicon bridge chip and / or the second conductor.

[0010] Optionally, after setting the silicon bridge chip, the following may also be included: A first seed layer is formed on the first wiring layer; A photoresist layer is formed on the first seed layer; The photoresist layer is patterned to form through holes that expose the first seed layer; A second conductor is formed by filling the through-hole with metal using an electroplating process. Remove the photoresist layer; Remove the first seed layer that is not covered by the second conductor.

[0011] Optionally, after setting the silicon bridge chip and the second conductor, the following may also be included: A first molding layer is formed to encapsulate the silicon bridge chip and the second conductor; After the first molding layer is formed and before the functional chips are installed, the process also includes: A second wiring layer is disposed on the side of the first molding layer away from the glass interlayer, and the functional chip is disposed on the side of the second wiring layer away from the glass interlayer; A second molding layer is formed on the side of the second wiring layer away from the glass interlayer, so that the second molding layer covers the functional chip.

[0012] Optionally, the first wiring layer is formed on one side of the glass interlayer; Before setting up the silicon bridge chip, the following is also included: Bond the glass interlayer to the temporary carrier plate; After setting the functional chips, the following is also included: Debond the glass interlayer to the temporary carrier plate; The side of the second molding layer away from the glass interlayer is bonded to the temporary carrier plate; A third wiring layer and conductive bumps are provided on the side of the glass interlayer away from the first wiring layer, with the conductive bumps located on the side of the third wiring layer away from the glass interlayer. Remove the temporary carrier board.

[0013] Thirdly, this application also provides an electronic device including a semiconductor package structure as described in any of the first aspects above.

[0014] The semiconductor packaging structure provided in this application, by employing a glass interposer and combining silicon bridges and vertical interconnect structures, can effectively suppress overall package warpage caused by thermal stress or mismatch stress during subsequent processes or device operation, thereby reducing the risk of warpage and improving the flatness and dimensional stability of the package. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of a semiconductor packaging structure according to an embodiment of this application; Figure 2This is a schematic diagram of a semiconductor packaging structure according to another embodiment of this application; Figure 3 This is a schematic flowchart of a method for fabricating a semiconductor packaging structure according to another embodiment of this application; Figure 4 This is a schematic diagram illustrating the structural changes of a semiconductor packaging structure during the fabrication process, according to another embodiment of this application. Figure 5 This is a schematic diagram of the semiconductor packaging structure according to another embodiment of this application during the fabrication process; Figure 6 This is a schematic diagram illustrating the structural changes of a semiconductor packaging structure during the fabrication process, according to another embodiment of this application. Figure 7 This is a schematic diagram illustrating the structural changes of a semiconductor packaging structure during the fabrication process, according to another embodiment of this application. Figure 8 This is a schematic diagram illustrating the structural changes of a semiconductor packaging structure during the fabrication process, according to another embodiment of this application. Figure 9 This is a schematic diagram illustrating the structural changes of a semiconductor packaging structure during the fabrication process, according to another embodiment of this application. Figure 10 This is a schematic diagram of the structural changes of a semiconductor packaging structure during the fabrication process, according to another embodiment of this application.

[0017] Marker explanation: 100. Semiconductor packaging structure; 10. Glass interposer; 11. Glass via; 12. First conductor; 20. Silicon bridge chip; 30. Second conductor; 31. First seed layer; 301. Photoresist layer; 302. Through-hole; 40. Functional chip; 41. First chip; 42. Second chip; 43. Third chip; 51. First redistribution layer; 52. Second redistribution layer; 53. Third redistribution layer; 61. First molding compound layer; 62. Second molding compound layer; 70. Conductive bump; 80. Temporary carrier. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0019] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in the embodiments of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0020] With the rapid development of technologies such as high-performance computing, artificial intelligence, and 5G communication, higher demands are being placed on the computing power, bandwidth, and integration of chips. Heterogeneous integration (HII) technology, which integrates multiple functional chips such as processors, memory, and radio frequency components within a single package structure, has become a key path to improve system performance.

[0021] However, with the increasing number and size of integrated chips, challenges have been placed on the packaging substrates that carry these chips. Currently, mainstream 2.5D packaging technologies typically use silicon interposers or organic substrates as interposers. While silicon interposers can achieve high-density interconnects, their manufacturing cost is high, their area is limited by the size of the silicon wafer, and warpage control and yield improvement are difficult for large-size silicon interposers. On the other hand, while traditional organic substrates are lower in cost and can be made in larger areas, their coefficient of thermal expansion differs from that of silicon chips, potentially causing warpage in multi-chip, large-size packaging. This warpage not only affects the accuracy and reliability of chip mounting but can also lead to breakage or short circuits in delicate circuits, posing a challenge to the development of advanced packaging technologies towards larger sizes and higher integration levels.

[0022] Specifically, in 2.5D packaging using silicon interposers, the silicon interposers are limited in area, expensive, and face challenges in warpage control at large sizes, making them unsuitable for large-scale heterogeneous integration. While organic substrates allow for increased area, the inherent low mechanical strength and significant difference in thermal expansion coefficients between organic materials and silicon chips lead to uncontrollable warpage during chip mounting, molding, and other processes or during operation when supporting multiple large chips. This warpage not only affects chip mounting accuracy and the reliability of microbump connections but also threatens the increasingly sophisticated wiring on the substrate. Therefore, achieving high mechanical strength, low warpage, and high-density interconnects simultaneously in large-size packaging is a pressing issue in this field.

[0023] Based on this, this application provides a semiconductor packaging structure solution that supports large-size multi-chip integration and suppresses warping through a glass interposer.

[0024] Some embodiments of this application provide a semiconductor package structure 100. For example... Figure 1 As shown, the semiconductor package structure 100 includes a glass interposer 10, a silicon bridge chip 20, a second conductor 30, and a functional chip 40.

[0025] The glass interposer 10 includes a glass via 11 extending along its thickness direction and a first conductor 12 filling the glass via 11. A silicon bridge chip 20 is disposed on at least one side of the glass interposer 10. A second conductor 30 is disposed on the same side of the glass interposer 10 as the corresponding silicon bridge chip 20. A functional chip 40 is disposed on the side of the silicon bridge chip 20 and the second conductor 30 away from the glass interposer 10. The functional chip 40 is electrically connected to the first conductor 12 through the silicon bridge chip 20 and / or the second conductor 30.

[0026] Specifically, this embodiment uses a glass interposer 10 as a carrier and interconnect platform to improve the warpage problem of large-size multi-chip packages caused by insufficient mechanical strength and mismatched coefficients of thermal expansion of traditional organic substrates. The glass interposer 10 is made of borosilicate glass, for example. Inside the glass interposer 10, multiple through-glass vias (TGVs) are formed along its thickness direction through processes such as laser-induced wet etching and plasma etching. The through-glass vias 11 form vertical interconnect channels. The through-glass vias 11 are filled with metal materials such as copper through electroplating to form first conductors 12, thereby realizing vertical electrical connections through the glass interposer 10. The first conductors 12 are the conductive metal pillars filling the through-glass vias 11.

[0027] A silicon bridge chip 20 is disposed on one side surface of the glass interposer 10. The silicon bridge chip 20 may be a silicon wafer with internally integrated high-density interconnect lines. On the same side surface of the glass interposer 10, a plurality of second conductors 30 are also disposed. The second conductors 30 are columnar metal interconnect structures, such as copper pillars, formed by processes such as electroplating, and are used to provide vertical electrical connections.

[0028] One or more functional chips 40 are disposed on the side of the silicon bridge chip 20 and the second conductor 30 away from the glass interposer 10. The functional chips 40 are, for example, logic chips or memory chips. The functional chips 40 can be electrically connected to the underlying silicon bridge chip 20 and / or the second conductor 30 via a redistribution layer. The functional chips 40 can also be electrically connected to the first conductor 12 within the glass via 11 via the second conductor 30, the redistribution layer, or other structures, thereby establishing a connection path to the outside of the package.

[0029] The semiconductor packaging structure 100 provided in this application replaces the traditional organic substrate or silicon interposer with a glass interposer 10. The glass material has a much higher elastic modulus (approximately 70 GPa) and hardness than ordinary organic substrates, providing stronger support for the integrated chip and interconnect structure. This effectively suppresses overall package warpage caused by thermal stress or mismatch stress during subsequent fabrication processes or device operation, thereby reducing the risk of warpage and improving the flatness and dimensional stability of the package.

[0030] In addition, the glass through-hole 11 enables high-density vertical electrical connections with lower dielectric loss than organic dielectric materials. It has low dielectric loss in high-frequency signal transmission and is suitable for high-performance computing and high-speed communication scenarios.

[0031] In some embodiments, the semiconductor package structure 100 further includes a first redistribution layer 51, which is disposed on one side of the glass interposer 10 where the silicon bridge chip 20 is located. The silicon bridge chip 20 and the second conductor 30 are disposed on the side of the first redistribution layer 51 away from the glass interposer 10. The silicon bridge chip 20 and the second conductor 30 are electrically connected to the first redistribution layer 51, respectively.

[0032] The semiconductor package structure 100 also includes a first molding layer 61, which is disposed on the side of the first redistribution layer 51 away from the glass interposer 10. The first molding layer 61 covers the silicon bridge chip 20 and the second conductor 30.

[0033] The silicon bridge chip 20 and the second conductor 30 are spaced apart, and the first molding layer 61 fills the space between the silicon bridge chip 20 and the second conductor 30.

[0034] Optionally, the end of the silicon bridge chip 20 away from the glass interposer 10 is exposed on the surface of the first molding compound 61 away from the glass interposer 10, and the end of the second conductor 30 away from the glass interposer 10 is exposed on the surface of the first molding compound 61 away from the glass interposer 10.

[0035] Optionally, the thickness of the first molding layer 61 is 30μm-150μm. Specifically, a first super-wiring layer 51 is first formed on the side of the glass interposer 10 where the silicon bridge chip 20 is disposed. The first super-wiring layer 51 typically includes alternating layers of dielectric layers and metal wiring. The dielectric layer can be formed by spin coating and curing, and the metal wiring can be formed by processes such as sputtering, photolithography, electroplating, and etching.

[0036] The silicon bridge chip 20 and the second conductor 30 can be formed on the surface of the first redistribution layer 51 away from the glass interposer 10. The bottom conductive structure (such as a pad) of the silicon bridge chip 20 is aligned with the corresponding conductive structure on the top layer of the first redistribution layer 51 and electrically connected.

[0037] Subsequently, a first molding compound 61 is formed. The first molding compound 61 covers the area on the first redistribution layer 51 where the silicon bridge chip 20 and the second conductor 30 are disposed, and encapsulates the silicon bridge chip 20 and the second conductor 30 within it. The molding compound is typically an epoxy molding compound, which can be formed through a molding process. After molding, the surface of the first molding compound 61 can be ground to expose the top surfaces of the silicon bridge chip 20 and the second conductor 30 and form a relatively flat plane.

[0038] Specifically, the first molding compound 61 is formed by injection molding of plastic, and completely encapsulates the sidewalls of the silicon bridge chip 20 and the sides and back of the second conductor 30. The first molding compound 61 is then polished until the top surface of the silicon bridge chip 20 and the top of the second conductor 30 are exposed, thereby obtaining a flat surface to facilitate the fabrication of subsequent interconnect structures. The thickness of the polished first molding compound 61 can be controlled within the range of 30μm-150μm, for example, 30μm, 50μm, 100μm, 130μm, 150μm, etc. This thickness range aims to balance mechanical protection with the overall package thickness. A thickness greater than 30μm ensures that the first molding compound 61 provides reliable mechanical support and stress buffering for the silicon bridge chip 20; while controlling the upper limit within 150μm helps control the overall package thickness, meeting the requirements for thinner and lighter electronic devices.

[0039] The first wiring layer 51 serves as an interconnect transition layer, effectively connecting the global interconnects on the glass interposer 10 with the local connection points on the silicon bridge chip 20 and the second conductor 30, increasing the flexibility of wiring design. The first molding layer 61 provides mechanical protection, stress buffering, and environmental isolation for the silicon bridge chip 20 and the second conductor 30, such as moisture and contamination protection. Through the first molding layer 61 and its subsequent polishing process, a globally flat surface is provided, creating the necessary process plane for high-precision fabrication of subsequent wiring layers or chip mounting on top.

[0040] In some embodiments, the semiconductor package structure 100 further includes a second redistribution layer 52, which is disposed on the side of the first molding layer 61 away from the glass interposer 10, and the functional chip 40 is disposed on the side of the second redistribution layer 52 away from the glass interposer 10.

[0041] The semiconductor package structure 100 also includes a second molding layer 62, which is disposed on the side of the second redistribution layer 52 away from the glass interposer layer 10, and the second molding layer 62 covers the functional chip 40.

[0042] Optionally, the end of the functional chip 40 away from the glass interposer 10 is exposed on the surface of the second molding layer 62 away from the glass interposer 10.

[0043] Optionally, the thickness of the second molding compound 62 is 50μm-500μm. Controlling the thickness of the second molding compound 62 within the range of 50μm to 500μm, for example, 50μm, 80μm, 100μm, 300μm, 500μm, etc. A thickness of not less than 50μm ensures sufficient mechanical strength protection for the functional chip 40 and its bump connections, effectively buffering external impacts and blocking environmental stresses such as moisture and contaminants. Simultaneously, a molding compound within this thickness range will not severely hinder heat dissipation from the back of the chip. Setting the upper limit to 500μm effectively controls the overall thickness and volume of the package.

[0044] Specifically, a second redistribution layer 52 is formed on the planarized surface of the first molding compound 61. The second redistribution layer 52 can be fabricated using deposition, photolithography, and electroplating processes similar to those used for the first redistribution layer 51. The second redistribution layer 52 defines pad patterns for connecting the functional chips 40 above it. One or more functional chips 40 can be mounted via flip-chip bonding, with the active surfaces of the functional chips 40 facing the second redistribution layer 52. The bumps on the bottom of the functional chips 40 are aligned with and connected to the corresponding pads on the upper surface of the second redistribution layer 52. After mounting, the second molding compound 62 is formed. The second molding compound 62 covers the second redistribution layer 52 and the functional chips 40 mounted on it, encapsulating the functional chips 40 and thus completing the main body of the entire package structure.

[0045] The second redistribution layer 52 and the second molding compound layer 62 integrate and protect the functional chip 40 on the top layer of the package. The glass interposer 10, silicon bridge chip 20, and functional chip 40 form a layered integrated structure, enabling the package to have system-level functionality. The first molding compound layer 61 and the second molding compound layer 62 together form the main protective structure of the package. Their symmetrical or near-symmetrical distribution helps to balance the stress between different material layers during thermal cycling and helps to control the overall package warpage.

[0046] In some embodiments, the functional chip 40 includes a first chip 41 and a second chip 42, which are electrically connected to the silicon bridge chip 20, and the first chip 41 and the second chip 42 are electrically connected to each other through the silicon bridge chip 20.

[0047] Optionally, the orthographic projection of the first chip 41 on the glass interposer 10 at least partially overlaps with the orthographic projection of the silicon bridge chip 20 on the glass interposer 10. The orthographic projection of the second chip 42 on the glass interposer 10 at least partially overlaps with the orthographic projection of the silicon bridge chip 20 on the glass interposer 10.

[0048] Optionally, the number of functional chips 40 is greater than the number of silicon bridge chips 20. Specifically, the number of functional chips 40 is at least one more than the number of silicon bridge chips 20.

[0049] The silicon bridge chip 20 can integrate complex, high-density wiring networks. Its connectivity is not limited to one-to-one connections but can simultaneously serve multiple functional chips 40. For example, a single silicon bridge chip 20 can bridge two, three, or more functional chips 40, which not only improves the utilization efficiency of the silicon bridge chip 20 and saves packaging layout space and cost, but also provides a foundation for building efficient and flexible multi-chip interconnect networks within the package.

[0050] In some embodiments, the number of functional chips 40 is two, specifically including a first chip 41 and a second chip 42. For example, one of the first chip 41 and the second chip 42 is a processor chip, and the other is a high-bandwidth memory chip. The first chip 41 and the second chip 42 are placed adjacent to each other in space. Both the first chip 41 and the second chip 42 have multiple input / output ports that need to communicate with each other at high speed. The high-speed interconnect ports among these ports can be directly connected to the corresponding interconnect areas on the upper surface of the silicon bridge chip 20 below through the bottom bumps, instead of being routed through the redistribution layer. High-density metal interconnects are pre-fabricated inside the silicon bridge chip 20, and the metal interconnects can directly connect the ports of the first chip 41 to the corresponding ports of the second chip 42.

[0051] In this system, high-speed signals between the first chip 41 and the second chip 42 are transmitted through interconnects within the silicon bridge chip 20. Compared to connections via a packaging substrate or longer rewiring paths, this shortens the signal transmission path, reduces transmission delay and power consumption, and increases the overall system bandwidth, making it particularly suitable for high-speed data exchange between the processor and high-bandwidth memory.

[0052] In other embodiments, such as Figure 2 As shown, the functional chip 40 also includes a third chip 43, meaning there are three functional chips 40: a first chip 41, a second chip 42, and a third chip 43. The number of silicon bridge chips 20 can be set to two accordingly. The first chip 41 and the second chip 42 are connected by a silicon bridge chip 20 with high density, while the second chip 42 and the third chip 43 are connected by another silicon bridge chip 20 with high density. This configuration allows for the construction of more complex point-to-point or mesh interconnect topologies, such as implementing a parallel high-speed data channel between a central processing unit and two adjacent high-bandwidth memory modules. Of course, depending on the system architecture requirements, the number of silicon bridge chips 20 can be further increased, for example, to three, four, or more. Each silicon bridge chip 20 can be specifically responsible for connecting one or more functional chips 40, thereby modularizing and distributing the interconnect network within the package. This application does not limit the specific number of silicon bridge chips 20 or their connection relationship with the functional chips 40; those skilled in the art can flexibly configure them according to actual bandwidth, latency, and power consumption parameters.

[0053] In some embodiments, the silicon bridge chip 20 is disposed on one side of the glass interposer 10. The semiconductor package structure 100 further includes a third wiring layer 53 and conductive bumps 70. The third wiring layer 53 is disposed on the side of the glass interposer 10 away from the silicon bridge chip 20, and the third wiring layer 53 is electrically connected to the first wiring layer 51 through a first conductor 12. The conductive bumps 70 are disposed on the side of the third wiring layer 53 away from the glass interposer 10.

[0054] During the fabrication process, after completing all the processes on one side of the package structure containing the functional chip 40 (i.e., the front or first side), the package structure needs to be flipped to process the other side of the glass interposer 10 (i.e., the back or second side). A third wiring layer 53 is formed on the surface of the glass interposer 10 opposite to the side where the silicon bridge chip 20 and the functional chip 40 are integrated. The material and process of the third wiring layer 53 can be similar to those of the first wiring layer 51 and the second wiring layer 52. Its main functions include power distribution networks, grounding networks, and fan-out of some low-speed control signals.

[0055] On the side of the third wiring layer 53 away from the glass interposer 10, multiple conductive bumps 70 are formed, such as solder balls, lead-free solder balls, or copper pillar bumps. These conductive bumps 70 are typically arranged in a grid array and can form the external electrical interface of the package for final soldering of the entire package structure onto a printed circuit board (PCB).

[0056] One side of the glass interposer 10 is used to integrate high-density active chips and interconnect structures, while the other side provides a standardized external mounting interface, achieving double-sided interconnection and integration of the package structure. This improves the utilization efficiency of the package's three-dimensional space and helps achieve higher input / output pin density within a limited planar area. Conductive bumps 70 facilitate the integration of the package structure onto the system board using surface mount technology.

[0057] Some embodiments of this application also provide a method for fabricating a semiconductor package structure 100.

[0058] like Figure 3 as well as Figures 4 to 10 As shown, the method for fabricating the semiconductor package structure 100 specifically includes the following steps: Step S10: Provide a glass substrate, form a glass through-hole 11 extending along the thickness direction in the glass substrate, and form a first conductor 12 in the glass through-hole 11 to form a glass interposer layer 10.

[0059] Specifically, a clean glass substrate, such as a borosilicate glass wafer, is provided as the starting material. The process of forming a through-hole 11 in the glass substrate along its thickness direction can, in a specific example, employ laser-induced wet etching, laser melting, focused discharge machining, plasma etching, electrochemical discharge machining, etc. For example, laser-induced wet etching can be performed on the glass substrate to form the through-hole 11, but this is not limited to these methods.

[0060] In a specific example, a laser beam is used to irradiate a predetermined location to modify the glass, followed by wet etching with hydrofluoric acid (HF) solution, which can efficiently form glass vias 11 with steep sidewalls and smooth surfaces. After the vias are formed, they are cleaned. Then, the step of forming a first conductor 12 within the glass via 11 is performed. First, the glass vias are electroplated and filled, and then copper is polished. Specifically, this includes: firstly, a metal seed layer is deposited on the wall of the glass via 11. The metal seed layer is usually a titanium / copper or chromium / copper stack, where the titanium or chromium layer is used to enhance adhesion, and the copper layer is used for conductivity; then, an electroplating process is used to fill the entire glass via 11 with copper as the main metal; after electroplating, the excessively thick copper layers on both sides of the glass substrate are chemically mechanically polished (CMP) to flatten the surface, exposing the glass surface and the top of the copper pillars in the glass vias. At this point, a glass interposer 10 with vertical interconnect capability is formed, and the copper pillars in it are the first conductors 12.

[0061] Step S20: A first redistribution layer 51 is formed on at least one side of the glass interposer layer 10.

[0062] Specifically, a seed layer is deposited on one side of the glass interposer 10 (e.g., the side where the silicon bridge chip 20 needs to be integrated) using a physical vapor deposition (PVD, such as sputtering) process. Then, a pattern of the first layer of metal wiring is defined on the seed layer using photolithography, followed by copper plating to thicken the wiring in the pattern. Afterward, the photoresist is removed, and excess seed layer not covered by the electroplated copper is removed by etching, thereby forming the first layer of metal wiring in the first wiring layer 51.

[0063] Subsequently, a first dielectric layer is deposited on the surface of the first metal wiring layer, and the dielectric layer is patterned to form vias that expose the areas in the first metal wiring layer that require electrical connection.

[0064] Next, the above process cycle is repeated on the first dielectric layer: "depositing a seed layer—coating and patterning photoresist—electroplated to thicken the metal lines—removing the photoresist—etching away excess seed layer", to form the second metal wiring layer. The second metal wiring layer is electrically connected to the first metal wiring layer through vias in the dielectric layer.

[0065] Similarly, by alternately stacking dielectric layers and metal wiring layers, and creating corresponding vias in each dielectric layer, a first wiring layer 51 containing multiple dielectric layers and metal wiring layers can be formed. The first wiring layer 51 realizes the planar distribution of the electrical interconnection network and the rearrangement of the chip I / O ports, and provides an electrical connection interface for the silicon bridge chip 20 and the second conductor 30 above.

[0066] Step S30: A silicon bridge chip 20 and a second conductor 30 are disposed on the side of the first redistribution layer 51 away from the glass interposer layer 10.

[0067] Specifically, first, the silicon bridge chip 20 is set up. The silicon bridge chip 20 is pre-fabricated in a wafer fab, with through-silicon vias (TSVs) and bumps already fabricated inside. Using high-precision flip-chip mounting equipment, the silicon bridge chip 20 is aligned and placed onto predetermined pad positions on the upper surface of the first multi-level wiring layer 51. Then, reflow soldering is performed to ensure a reliable bond between the solder bumps on the bottom of the silicon bridge chip 20 and the pads of the first multi-level wiring layer 51. Subsequently, underfill is performed by injecting liquid epoxy resin underfill into the gaps at the bottom of the chip, followed by heat curing to enhance the connection points' resistance to mechanical shock and thermal fatigue.

[0068] Then, a second conductor 30 is formed. For example, a metal pillar (such as a copper pillar) is patterned and electroplated on the first redistribution layer 51.

[0069] Step S40: A functional chip 40 is disposed on the side of the silicon bridge chip 20 and the second conductor 30 away from the glass interposer 10; wherein the functional chip 40 is electrically connected to the first conductor 12 through the silicon bridge chip 20 and / or the second conductor 30.

[0070] Specifically, before setting the functional chip 40, the process includes molding and planarizing the silicon bridge chip 20 and the second conductor 30 to form a flat substrate for subsequent processes. Then, a second rewiring layer 52 is fabricated on the planarized surface. One or more functional chips 40 are then mounted onto the second rewiring layer 52 using a flip-chip bonding process, followed by underfilling and molding again to complete the main structure of the package. Through the structure formed by the above process, high-speed interconnect signals between the functional chips 40 can communicate directly through the internal circuitry of the silicon bridge chip 20. Simultaneously, the power, ground, and some low-speed I / O signals of the functional chips 40 are conducted downwards through the second conductor 30, via the first rewiring layer 51 and the first conductor 12 within the glass via 11, achieving vertical electrical connection and outward fan-out.

[0071] In the fabrication method provided in this application embodiment, the high-speed interconnect signals of the functional chip 40 can communicate directly with another adjacent functional chip 40 through the internal circuitry of the silicon bridge chip 20. Simultaneously, the power supply, ground, and some I / O signals of the functional chip 40 can achieve vertical electrical connection and fan-out via the second conductor 30 downwards through the first redistribution layer 51 and the first conductor 12 within the glass via 11. A glass interposer 10 replaces the traditional organic substrate. The high hardness and excellent dimensional stability of the glass material provide stronger rigidity support for the integrated chips and interconnect structures. This helps reduce overall package warpage caused by thermal stress or mismatch stress during subsequent process steps (such as chip mounting and molding) or device operation, thereby improving the flatness and dimensional stability of the package.

[0072] In some embodiments, such as Figure 6 As shown, after setting the silicon bridge chip 20 in step S30, the method for fabricating the semiconductor package structure 100 further includes the following steps: Step S301: Form a first seed layer 31 on the first redistribution layer 51; Step S302: Form a photoresist layer 301 on the first seed layer 31; Step S303: Pattern the photoresist layer 301 to form a through hole 302 that exposes the first seed layer 31; Step S304: Fill the through hole 302 with metal using an electroplating process to form a second conductor 30; Step S305: Remove the photoresist layer 301; Step S306: Remove the first seed layer 31 that is not covered by the second conductor 30.

[0073] Specifically, on the substrate surface where the first redistribution layer 51 has been fabricated and the silicon bridge chip 20 has been mounted, a continuous first seed layer 31 is deposited. Then, a thick photoresist layer is coated on the first seed layer 31 to form a photoresist layer 301. The photoresist layer 301 is exposed and developed. Alignment exposure is performed using a photomask that defines the position pattern of the second conductor 30. After development, a through-hole 302 is formed in the photoresist layer 301, exposing the bottom of the first seed layer 31. Then, using the exposed first seed layer as a conductive substrate, metal (e.g., copper) is filled into the through-hole 302 using an electroplating process. The copper material can be deposited and grown upwards from the bottom of the through-hole 302 until the entire through-hole 302 is filled, forming a dense copper pillar, i.e., the second conductor 30. Then, the photoresist layer 301 is removed. Finally, using the second conductor 30 as a mask, the first seed layer 31 not covered by the second conductor 30 is removed by an etching process.

[0074] By using the photoresist layer 301 as a mold, the position, diameter, and height of the second conductor 30 can be precisely controlled, thereby achieving a vertical interconnect structure with a high aspect ratio.

[0075] In some embodiments, such as Figure 7 , Figure 8 As shown, after setting the silicon bridge chip 20 and the second conductor 30 in step S30, the method for fabricating the semiconductor package structure 100 further includes the following steps: Step S311: Form a first molding layer 61 to cover the silicon bridge chip 20 and the second conductor 30.

[0076] After the first molding layer 61 is formed in step S311 and before the functional chip 40 is disposed, the method for fabricating the semiconductor package structure 100 further includes the following steps: Step S312: A second wiring layer 52 is disposed on the side of the first molding layer 61 away from the glass interposer 10, and the functional chip 40 is disposed on the side of the second wiring layer 52 away from the glass interposer 10. Step S313: A second molding compound 62 is formed on the side of the second redistribution layer 52 away from the glass interposer layer 10, so that the second molding compound 62 covers the functional chip 40.

[0077] Specifically, before setting the functional chip 40, the method for fabricating the semiconductor package structure 100 includes the step of molding the already set silicon bridge chip 20 and the second conductor 30 to form a flat surface. This includes: after completing step S40, using a molding process, forming a first molding layer 61 with epoxy molding compound, the first molding layer 61 covering the silicon bridge chip 20 and the second conductor 30. Subsequently, the first molding layer 61 is ground until the upper surface of the silicon bridge chip 20 and the top of the second conductor 30 are exposed, obtaining a globally flat surface. On this flat surface, a second redistribution layer 52 is fabricated using a process similar to step S30. Then, the functional chip 40 (e.g., CPU, GPU, HBM, etc.) is flip-chip bonded to the corresponding pads on the upper surface of the second redistribution layer 52 through its bottom microbumps. After bonding, an underfill process is performed again. Finally, molding can be performed again to form the second molding layer 62, encapsulating the functional chip 40 within it, completing the main structure of the package structure.

[0078] In some embodiments, a first redistribution layer 51 is formed on one side of the glass interposer layer 10.

[0079] Before setting the silicon bridge chip 20 in step S30, the method for fabricating the semiconductor package structure 100 further includes the following steps: Step S300: Bond the glass interlayer 10 to the temporary carrier plate 80.

[0080] like Figure 9 , Figure 10 As shown, after setting the functional chip 40 in step S40, the method for fabricating the semiconductor package structure 100 further includes the following steps: Step S41: Debond the glass interlayer 10 from the temporary carrier plate 80; Step S42: Bond the side of the second molding layer 62 away from the glass interlayer 10 to the temporary carrier plate 80; Step S43: A third wiring layer 53 and a conductive bump 70 are provided on the side of the glass interposer 10 away from the first wiring layer 51. The conductive bump 70 is provided on the side of the third wiring layer 53 away from the glass interposer 10. Step S44: Remove the temporary carrier board 80.

[0081] Specifically, before step S30, the glass interlayer 10 can be bonded to a temporary carrier plate 80 with temporary bonding adhesive to provide support for subsequent processes.

[0082] Specifically, after completing step S40, i.e., forming the second molding layer 62, the glass interposer 10 is unbonded to the temporary carrier 80. Then, the entire package structure is flipped over, so that the side containing the second molding layer 62 is rebonded to a temporary carrier 80 (which can be the same carrier or another carrier) using temporary bonding adhesive. At this point, the side of the glass interposer 10 that was originally bonded to the temporary carrier 80 (i.e., the back side) is exposed. A third wiring layer 53 is fabricated on the exposed back side of the glass interposer 10. Conductive bumps 70 (such as solder balls) are fabricated on the third wiring layer 53. Finally, the temporary carrier 80 is removed, forming a complete semiconductor package structure 100 with a double-sided interconnect structure.

[0083] In some embodiments, the method for fabricating the semiconductor package structure 100 may further include integrating passive devices. For example, in step S30, while setting the silicon bridge chip 20, passive devices such as resistors and capacitors may be mounted at specific locations on the first redistribution layer 51 and encapsulated together with the first molding compound layer 61. These passive devices can be electrically connected to the functional chip 40 through the redistribution layer to optimize system performance.

[0084] Some embodiments of this application also provide an electronic device. The electronic device includes the semiconductor package structure 100 provided in any of the above embodiments.

[0085] Based on the excellent properties of the glass interposer 10, the semiconductor packaging structure of this application embodiment can be applied to a variety of high-performance electronic devices. For example, in the field of artificial intelligence (AI) computing, the semiconductor packaging structure can provide an extremely short-distance, ultra-high bandwidth interconnect between the AI ​​processor and high-bandwidth memory (HBM) through the silicon bridge chip 20, meeting its stringent requirements for computing power and data throughput. In the field of radio frequency communication, the low dielectric loss characteristics of glass make it suitable as a carrier for radio frequency front-end modules; its structure supports the integration of embedded waveguides, and the three-dimensional stacking scheme helps to integrate high-frequency chips with low-loss interconnects, providing solutions for large-scale antenna arrays to meet the challenges of data rates exceeding 100GHz in future 6G communications. In addition, the excellent insulation, thermal stability, and surface flatness of the glass substrate enable it to provide precise mechanical support and a good electrical isolation environment for microelectromechanical systems (MEMS) devices (such as miniature mass spectrometers and inertial sensors), helping to reduce parasitic effects and improve device performance.

[0086] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0087] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the inventive concept, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A semiconductor packaging structure, characterized in that, include: A glass interlayer, comprising a glass via extending along its thickness direction and a first conductor filling the glass via; A silicon bridge chip is disposed on at least one side of the glass interposer layer; The second conductor is disposed on the same side of the glass interlayer as the silicon bridge chip; The functional chip is disposed on the side of the silicon bridge chip and the second conductor away from the glass interlayer; The functional chip is electrically connected to the first conductor via the silicon bridge chip and / or the second conductor.

2. The semiconductor packaging structure according to claim 1, characterized in that, Also includes: A first wiring layer is disposed on one side of the glass interposer, and the silicon bridge chip and the second conductor are disposed on the side of the first wiring layer away from the glass interposer, and the silicon bridge chip and the second conductor are respectively electrically connected to the first wiring layer. A first molding layer is disposed on the side of the first redistribution layer away from the glass interposer, and the first molding layer covers the silicon bridge chip and the second conductor; Preferably, the silicon bridge chip and the second conductor are spaced apart, and the first molding layer fills the space between the silicon bridge chip and the second conductor; Preferably, the end of the silicon bridge chip away from the glass interposer is exposed on the surface of the first molding compound away from the glass interposer, and the end of the second conductor away from the glass interposer is exposed on the surface of the first molding compound away from the glass interposer. Preferably, the thickness of the first molding layer is 30μm-150μm.

3. The semiconductor packaging structure according to claim 2, characterized in that, Also includes: The second wiring layer is disposed on the side of the first molding layer away from the glass interposer, and the functional chip is disposed on the side of the second wiring layer away from the glass interposer. The second molding layer is disposed on the side of the second redistribution layer away from the glass interlayer, and the second molding layer covers the functional chip; Preferably, the end of the functional chip away from the glass interlayer is exposed on the surface of the second molding layer away from the glass interlayer; Preferably, the thickness of the second molding layer is 50μm-500μm.

4. The semiconductor packaging structure according to claim 1, characterized in that, The functional chip includes a first chip and a second chip, the first chip and the second chip are electrically connected to at least one of the silicon bridge chips respectively, and the first chip and the second chip are electrically connected through the silicon bridge chips. Preferably, the orthographic projection of the first chip on the glass interposer layer at least partially overlaps with the orthographic projection of the silicon bridge chip on the glass interposer layer; The orthographic projection of the second chip on the glass interposer layer at least partially overlaps with the orthographic projection of the silicon bridge chip on the glass interposer layer; Preferably, the number of the functional chips is greater than the number of the silicon bridge chips.

5. The semiconductor packaging structure according to claim 2, characterized in that, The semiconductor packaging structure further includes a third wiring layer and conductive bumps. The third wiring layer is disposed on the side of the glass interposer away from the silicon bridge chip. The third wiring layer is electrically connected to the first wiring layer through the first conductor. The conductive bumps are disposed on the side of the third wiring layer away from the glass interposer.

6. A method for fabricating a semiconductor packaging structure, characterized in that, include: A glass substrate is provided, in which a glass through-hole is formed along the thickness direction, and a first conductor is formed in the glass through-hole to form a glass interlayer. A first redistribution layer is formed on at least one side of the glass interlayer; A silicon bridge chip and a second conductor are disposed on the side of the first redistribution layer away from the glass interposer layer; A functional chip is disposed on the side of the silicon bridge chip and the second conductor away from the glass interposer; wherein the functional chip is electrically connected to the first conductor through the silicon bridge chip and / or the second conductor.

7. The method for fabricating a semiconductor packaging structure according to claim 6, characterized in that, After setting the silicon bridge chip, the following is also included: A first seed layer is formed on the first rewiring layer; A photoresist layer is formed on the first seed layer; The photoresist layer is patterned to form through holes that expose the first seed layer; The through-hole is filled with metal using an electroplating process to form the second conductor. Remove the photoresist layer; Remove the first seed layer that is not covered by the second conductor.

8. The method for preparing a semiconductor packaging structure according to claim 6, characterized in that, After setting the silicon bridge chip and the second conductor, the method further includes: A first molding layer is formed to encapsulate the silicon bridge chip and the second conductor; After the first molding compound is formed and before the functional chip is disposed, the method further includes: A second wiring layer is provided on the side of the first molding layer away from the glass interlayer, and the functional chip is disposed on the side of the second wiring layer away from the glass interlayer; A second molding layer is formed on the side of the second redistribution layer away from the glass interposer, so that the second molding layer covers the functional chip.

9. The method for preparing a semiconductor packaging structure according to claim 8, characterized in that, The first wiring layer is formed on one side of the glass interposer; Before setting the silicon bridge chip, the following is also included: The glass interlayer is bonded to a temporary carrier plate; After configuring the functional chip, the following is also included: Debond the glass interlayer to the temporary carrier plate; The side of the second molding layer away from the glass interlayer is bonded to a temporary carrier plate; A third wiring layer and conductive bumps are provided on the side of the glass interlayer away from the first wiring layer, and the conductive bumps are provided on the side of the third wiring layer away from the glass interlayer. Remove the temporary carrier plate.

10. An electronic device, characterized in that, Includes the semiconductor packaging structure as described in any one of claims 1 to 5.

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