Automatic cell and macrocell placement in vlsi layout design

Abstract

A system (101) and a method (300) for generating a very large-scale integration layout plan (400). One method includes receiving (302) inputs (322, 324, 326) for automatically placing macrocells in the layout plan (400). The method includes performing (304) an automatic macrocell placement process based on the received inputs (322, 324, 326). The method includes generating (308) the layout plan (400) according to the automatic macrocell placement process. The layout plan (400) can then be used to generate a physical layout, and can subsequently be used to manufacture physical chips based on the generated physical layout.

Description

Technical Field

[0001] This disclosure generally relates to the design of physical layouts for very-large-scale-integration (VLSI) integrated circuits (ICs), and specifically to an improved method for automatically placing macrocells and standard cells on a VLSI physical layout design (or “layout planning”). Background Technology

[0002] The design and fabrication of integrated circuits has become increasingly complex. Modern integrated circuits can include: millions of standard “cells,” each composed of transistors and interconnect structures to implement one or more logic functions; and numerous arrays of microcells or “macrocells,” which are pre-designed structures of multiple cells to implement specific functions, such as flip-flops, arithmetic logic unit (ALU) functions, registers, memory cells, or other functions. The physical layout of the design includes the physical location of each cell and macrocell on the IC chip, as well as the interconnects (“lines”) between them. The physical chip can then be fabricated based on this layout.

[0003] Traditionally, in the physical design phase of the IC design flow, macrocells are manually placed into the floorplan by layout designers, a process that typically takes weeks to months to generate. Designers then must place standard cells and perform other steps in the physical design flow to generate a physical layout that can be manufactured without errors or interference between various components and interconnects, and that operates efficiently. The industry needs systems capable of automating or assisting in the design of VLSI floorplans. Summary of the Invention

[0004] Various disclosed embodiments include systems and methods for generating very large-scale integration (VLSI) layout plans. One method includes receiving input for automatically placing macrocells in the layout plan. The method includes performing an automatic macrocell placement process based on the received input. The method includes generating the layout plan based on the automatic macrocell placement process. The layout plan can then be used to generate a physical layout, and a physical chip can then be manufactured based on the generated physical layout.

[0005] In various embodiments, the automatic macrocell placement process is time-driven to place macrocells within the same level module close to each other in the layout plan, and macrocells with the same library are grouped together. In various embodiments, the automatic macrocell placement process includes: performing global macrocell placement of multiple macrocells in the layout plan; performing a validation process for the global macrocell placement; constructing macrocell groups, each macrocell group having multiple macrocells from the multiple macrocells; performing global macrocell group placement of the macrocell groups; and performing a validation process for the global macrocell group placement.

[0006] In various embodiments, the global macrocell placement is based on repulsive core forces and attractive line forces modeled between the plurality of macrocells in the layout plan. In various embodiments, the global macrocell group placement is based on repulsive core forces and attractive line forces modeled between the macrocell groups. In various embodiments, the legalization process for the global macrocell placement and / or the global macrocell group placement is an iterative simulated annealing-based legalization using modification techniques. In various embodiments, the legalization process for the global macrocell group placement includes performing a regrouping process to form new macrocell groups.

[0007] In various embodiments, constructing macrocell groups includes: assigning macrocell groups to each macrocell according to the layout planning bins, grouping macrocells with cells from the same standard cell library together, and grouping macrocells at the same logical level together.

[0008] In various embodiments, constructing macrocell groups includes: assigning macrocell groups to each macrocell according to an instance name-based hierarchy, grouping macrocells with cells from the same standard cell library together, and grouping macrocells together according to physical proximity-based clustering.

[0009] Some embodiments also include placing the standard cell in the layout based on repulsive core forces and attractive line forces modeled between the standard cell and multiple macrocells in the layout plan.

[0010] Other embodiments include a computer system having a processor and accessible memory, configured to perform the processes described herein. Other embodiments include a non-transitory computer-readable medium encoded with executable instructions that, when executed, cause one or more computer systems to perform the processes as described herein.

[0011] The features and technical advantages of this disclosure have been outlined rather broadly above to enable those skilled in the art to better understand the detailed description that follows. Additional features and advantages of this disclosure, which form the subject matter of the claims, will be described below. Those skilled in the art will understand that they can readily use the disclosed concepts and specific embodiments as a basis for modifying or designing other structures for performing the same purposes of this disclosure. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure as presented in its broadest form.

[0012] Before proceeding with the detailed implementation below, it may be advantageous to define certain words or phrases used in this patent document: the terms “include” and “comprise” and their derivatives mean including but not limited to; the term “or” is inclusive, meaning and / or; the phrases “associated with” and “associated with” and their derivatives may mean including, being included, interconnected with, containing, contained within, connected to or connected to, coupled to or coupled to, able to communicate with, cooperate with, interleaved, parallel, proximate, combined with or combined with, having, having the properties of, etc.; and the term “controller” means any device, system or part thereof that controls at least one operation, whether such device is implemented in hardware, firmware, software or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller can be centralized or distributed, local or remote. Definitions of certain words and phrases are provided in this patent document, and those skilled in the art will understand that such definitions apply in many (if not most) cases to the prior and future use of such defined words and phrases. While some terms may encompass a wide variety of embodiments, the appended claims may expressly limit these terms to the specific embodiments. Attached Figure Description

[0013] To gain a more complete understanding of this disclosure and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, wherein the same numerals denote the same objects, and in the drawings:

[0014] Figure 1 and Figure 2 Components of a computer system that can be used to implement various embodiments of the disclosed technology are shown;

[0015] Figure 3 A high-level view of a process for automatically generating a layout plan according to a disclosed embodiment is shown;

[0016] Figure 4 An example of a layout plan generated according to the disclosed embodiments is shown;

[0017] Figure 5A An example of a layout plan according to the disclosed embodiments is shown;

[0018] Figure 5B A more detailed view of the macrocells of a selected portion of the layout plan according to the disclosed embodiments is shown;

[0019] Figure 5C A more detailed view of the macrocells of a selected portion of the layout planning after manual repackaging according to the disclosed embodiments is shown;

[0020] Figure 6 A high-level view of a process for automatically placing macro cells in a layout plan, according to a disclosed embodiment, is shown.

[0021] Figure 7 A process for globally placing nodes in a layout plan according to a disclosed embodiment is illustrated;

[0022] Figure 8 The legalization process based on simulated annealing (SA) according to the disclosed embodiments is illustrated; and

[0023] Figure 9A and Figure 9B A process for constructing a macrocell group according to a disclosed embodiment is shown. Detailed Implementation

[0024] The following discussion Figures 1 to 9B The various embodiments used to describe the principles of this disclosure in this patent document are merely illustrative and should not be construed as limiting the scope of this disclosure in any way. Those skilled in the art will understand that the principles of this disclosure can be implemented in any suitably arranged device. Numerous innovative teachings of this application will be described with reference to exemplary, non-limiting embodiments.

[0025] There are several objectives in designing a successful layout plan, which may include thousands of cells, either individually standard or custom cells, or grouped into macrocells. One important objective is manufacturability, requiring that the placement of cells, macrocells, and lines ensures they can be successfully manufactured without interfering with each other. Another important objective is operability, which includes ensuring that cells, macrocells, and lines do not electrically or electromagnetically interfere with each other during operation. Yet another important objective is efficiency, enabling the manufactured chip to perform its functions as quickly and efficiently as possible, which may include designing interconnects to be as short as possible without sacrificing other objectives. The "quality of results" (QoR) of the layout plan is repeatedly evaluated during the legitimization process to ensure correct and efficient operation.

[0026] The disclosed embodiments include systems and methods for automatically placing macrocells and other units in layout planning. Various embodiments may include techniques for locally refining the placement (“legitimization”) of individual units or macrocells to eliminate structural overlaps, ensure proper connections between components, and, if necessary, perform modifications such as translating or transforming the shape of units or macrocells (e.g., sliding, shifting, flipping, or rotating the shape). While the techniques described herein can be applied at the unit and macrocell levels, the various embodiments are particularly useful for automated macrocell placement in layout planning.

[0027] As described in more detail below, the disclosed embodiments use kernel-force-based modeling and time-driven global placement for individual nodes (including cells, macrocells, and groups of macrocells). The disclosed embodiments may use simulated annealing-based legitimization for individual macrocells and groups of macrocells.

[0028] Explanatory operating environment

[0029] The various processes described herein can be implemented using computer-executable software instructions that are executed by one or more programmable computing devices. Because these processes can be implemented using software instructions, the components and operation of a general-purpose programmable computer system that can employ various embodiments of these processes will be described first. Furthermore, due to the complexity of some electronic design and testing processes and the large size of many circuit designs, various electronic design and testing tools are configured to operate on computing systems capable of running multiple processing threads simultaneously. Therefore, reference will be made to… Figure 1 This describes the components and operation of a computer system having a host or master computer and one or more remote or slave computers. However, this operating environment is merely an example of a suitable operating environment and is not intended to impose any limitation on the scope or functionality of any implementation of the invention.

[0030] exist Figure 1 In this embodiment, computer system 101 includes a host computer 103. In the illustrated example, host computer 103 is a multiprocessor computer that includes multiple input and output devices 105 and memory 107. Input and output devices 105 may include any device for receiving input data from a user or providing output data to a user. Input devices may include, for example, a keyboard, microphone, scanner, or indicating device for receiving input from a user. Output devices may include a display monitor, speaker, printer, or haptic feedback device. These devices and their connections are well known in the art and will not be discussed in detail here.

[0031] The memory 107 may also be implemented using any combination of computer-readable media accessible by the host computer 103. Computer-readable media may include, for example, microcircuit storage devices such as read-write memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or flash microcircuit devices, CD-ROM discs, digital video discs (DVDs), or other optical storage devices. Computer-readable media may also include magnetic cassettes, magnetic tapes, disks or other magnetic storage devices, punched media, holographic storage devices, or any other non-transitory storage medium that can be used to store desired information. As used herein, the term "non-transitory" refers to the ability to store information for subsequent retrieval at a desired time, rather than to propagate electromagnetic signals.

[0032] As will be discussed in detail below, the host computer 103 runs a software application for performing one or more operations according to various examples of the present invention. Therefore, memory 107 stores software instructions 109A, which, when executed, implement the software application for performing one or more operations. Memory 107 also stores data 109B to be used by the software application. In the illustrated embodiment, data 109B contains process data used by the software application to perform operations, wherein at least some operations may be performed in parallel.

[0033] The host computer 103 also includes multiple processor units 111 and interface devices 113. Processor units 111 can be any type of processor device that can be programmed to execute software instructions 109A, but will conventionally be microprocessor devices. For example, one or more of the processor units 111 can be commercially available general-purpose programmable microprocessors, such as Intel® Pentium® or Xeon™ microprocessors, Advanced Micro Devices Athlon™ microprocessors, or Motorola 68K / Coldfire® microprocessors. Alternatively or additionally, one or more of the processor units 111 can be custom-made processors, such as microprocessors designed to optimally perform specific types of mathematical operations. Interface devices 113, processor units 111, memory 107, and input / output devices 105 are connected together via bus 115.

[0034] In some implementations of the present invention, the host computer 103 may employ one or more processing units 111 having more than one processor core. Therefore, Figure 2An example of a multi-core processor unit 111 that can be used in conjunction with various embodiments of the present invention is shown. As shown in the figure, the processor unit 111 includes a plurality of processor cores 201. Each processor core 201 includes a computing engine 203 and a memory cache 205. As is known to those skilled in the art, the computing engine includes logic devices for performing various computational functions, such as fetching software instructions and then performing actions specified in the fetched instructions. These actions may include, for example, addition, subtraction, multiplication, and comparing numbers, performing logical operations (e.g., AND, OR, NOR, and XOR), and retrieving data. Each computing engine 203 can then use its corresponding memory cache 205 to quickly store and retrieve data and / or instructions for execution.

[0035] Each processor core 201 is connected to an interconnect 207. The specific configuration of the interconnect 207 can vary depending on the architecture of the processor unit 201. For some processor cores 201, such as the Cell microprocessors created by Sony, Toshiba, and IBM, the interconnect 207 can be implemented as an interconnect bus. However, for other processor units 201, such as the Opteron™ and Athlon™ dual-core processors available from Advanced Micro Devices in Sunnyvale, California, the interconnect 207 can be implemented as a system request interface device. In any case, the processor core 201 communicates with the input / output interface 209 and the memory controller 211 via the interconnect 207. The input / output interface 209 provides a communication interface between the processor unit 201 and the bus 115. Similarly, the memory controller 211 controls the exchange of information between the processor unit 201 and the system memory 107. In some implementations of the invention, the processor unit 201 may include additional components, such as an advanced cache memory that can be shared and accessed by the processor cores 201.

[0036] Although Figure 2 A diagram of a processor unit 201 that may be employed by some embodiments of the present invention is shown, but it should be understood that the diagram is merely representative and not intended to be limiting. It should also be understood that, for some implementations, a multi-core processor unit 111 may be used instead of multiple individual processor units 111. For example, alternative implementations of the computing system 101 may employ a single processor unit 111 with six cores, two multi-core processor units each with three cores, a multi-core processor unit 111 with four cores along with two individual single-core processor units 111, etc., instead of six individual processor units 111.

[0037] Return now Figure 1Interface device 113 allows host computer 103 to communicate with slave computers 117A, 117B, 117C...117x via a communication interface. The communication interface can be any suitable type, including, for example, a conventional wired network connection or a light-transmitting wired network connection. The communication interface can also be a wireless connection, such as a wireless optical connection, a radio frequency connection, an infrared connection, or even an acoustic connection. Interface device 113 converts data and control signals from the autonomous computer 103 and each slave computer 117 into network messages according to one or more communication protocols (e.g., Transmission Control Protocol (TCP), User Datagram Protocol (UDP), and Internet Protocol (IP)). These and other conventional communication protocols are well known in the art and will not be discussed in detail here.

[0038] Each slave computer 117 may include a memory 119, a processor unit 121, an interface device 123, and one or more input / output devices 125 optionally connected together via a system bus 127. Similar to the host computer 103, the optional input / output devices 125 for the slave computer 117 may include any conventional input or output devices, such as a keyboard, indicating device, microphone, display monitor, speaker, and printer. Similarly, the processor unit 121 may be any type of conventional or custom-made programmable processor device. For example, one or more of the processor units 121 may be commercially available general-purpose programmable microprocessors, such as Intel® Pentium® or Xeon™ microprocessors, Advanced MicroDevices Athlon™ microprocessors, or Motorola 68K / Coldfire® microprocessors. Alternatively, one or more of the processor units 121 may be custom-made processors, such as microprocessors designed to optimally perform specific types of mathematical operations. Furthermore, one or more of the processor units 121 may have more than one core, as referenced above. Figure 2 The memory 119 can then be implemented using any combination of the aforementioned computer-readable media. Similar to interface device 113, interface device 123 allows slave computer 117 to communicate with host computer 103 via a communication interface.

[0039] In the illustrated example, the host computer 103 is a multiprocessor unit computer with multiple processor units 111, while each slave computer 117 has a single processor unit 121. However, it should be noted that an alternative implementation of this technology may employ a host computer with a single processor unit 111. Furthermore, depending on its intended use, one or more slave computers 117 may have multiple processor units 121, as previously described. Additionally, although only a single interface device 113 or 123 is illustrated for both the host computer 103 and the slave computers, it should be noted that for alternative embodiments of the invention, computer 103, one or more slave computers 117, or some combination thereof may use two or more different interface devices 113 or 123 to communicate through multiple communication interfaces.

[0040] For various examples of computer system 101, host computer 103 may be connected to one or more external data storage devices. These external data storage devices may be implemented using any combination of non-transitory computer-readable media accessible by host computer 103. Computer-readable media may include, for example, microcircuit storage devices such as read-write memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or flash microcircuit devices, CD-ROM discs, digital video discs (DVDs), or other optical storage devices. Computer-readable media may also include magnetic cassettes, magnetic tapes, disks or other magnetic storage devices, punched media, holographic storage devices, or any other media that can be used to store desired information. Depending on some implementations of computer system 101, one or more slave computers 117 may be alternatively or additionally connected to one or more external non-transitory data storage devices. Typically, these external non-transitory data storage devices will include data storage devices also connected to host computer 103, but they may also differ from any data storage device accessible by host computer 103.

[0041] It should also be understood that Figure 1 and Figure 2 The description of the computer system 101 shown is provided by way of example only and is not intended to imply any limitation on the scope or functionality of the various embodiments of the invention.

[0042] Figure 3 A high-level view of a process 300 for automatically generating VLSI design layout / layout planning (including automatic placement of macro cells) is shown, which can be performed, for example, by a computer system such as computer system 101 (hereinafter referred to as the “system”).

[0043] At 302, the system receives input for automatically placing macrocells in the layout plan. This input describes, among other things, the cells and / or macrocells to be placed in the layout plan. This input may include, for example, VLSI input 322, which describes information such as the cells and macrocells to be included in the layout plan, their interconnections, the hierarchical module to which each cell and macrocell belongs, and the macrocell library associated with each macrocell. VLSI input 322 may include a netlist describing some or all of this information. As used herein, “receive” may include loading from a storage device, receiving from another device or process, receiving through interaction with a user, and other means.

[0044] Inputs may include adjustment parameters 324. Adjustment parameters may include any parameters described herein, and may include such parameters as the maximum distance between cells / macrocells, the minimum “gap” distance between cells / macrocells, timing requirements, routing requirements, uniform density requirements, and other such parameters that will be used by the automated macrocell placement process.

[0045] Inputs may include large macrocell placement 326. For example, the system may receive a user selection to "fix" a specific large macrocell on the chip boundary and allow the automatic macrocell placement process to find the optimal location for smaller macrocells (e.g., in the middle of the chip).

[0046] At 304, the system performs an automatic macrocell placement process as described herein based on the received input. According to various embodiments, the system can perform timing-driven macrocell placement to place macrocells in the same hierarchical module close to each other. The system can place some macrocells in the middle of the chip to achieve optimal timing results. The system can group macrocells with the same library together to ensure proper alignment.

[0047] At point 306, the system can optionally perform manual repackaging of some or all macrocells in the layout plan. This process can be executed in response to receiving a user selection of macrocells to be manually repackaged, and the manual repackaging can then include performing an automatic macrocell placement process only on the selected macrocells. This process can more efficiently place the selected macrocells within the layout plan to eliminate bottlenecks.

[0048] At point 308, the system generates a layout plan based on the automatic macrocell placement process and (if performed) manual repackaging. The system can display, store, or transmit the layout plan as part of this step.

[0049] Designers can use this layout plan to run subsequent physical design steps (such as placement and routing) to generate a complete physical layout. The physical chip can then be manufactured based on the layout plan and placement.

[0050] Figure 4 An example of a layout plan 400 generated according to the disclosed embodiments is shown. The layout plan 400 includes a plurality of macrocells 402. As described herein, the plurality of macrocells 402 may be grouped into macrocell groups 404. In this figure, filled graphics are used to identify macrocell groups for illustrative purposes. Note that the individual macrocells 404 may have different sizes, and multiple identical macrocells 404 may be used in the layout plan. The size and shape of each macrocell and macrocell group can be used for an automated macrocell placement process, which may include translating or transforming the macrocell or macrocell group by rotation or flipping. While this example of a layout plan 400 does not include interconnects / lines between individual cells, macrocells, and chip connections, other layout plans may include this information.

[0051] Figure 5A An example of a layout plan 500 according to a disclosed embodiment is shown, including a selected portion 502 for illustrating manual repackaging 306. The layout plan 500 can represent a layout plan 500 after a global automatic macrocell placement process is performed on the layout plan 500, where all macrocells are placed and validated, but the user believes that the selected portion 502 is inefficiently or unattractively laid out in the layout plan 500, and desires to perform an automatic macrocell placement process locally on the selected portion 502 after the global process. Consider macrocells in the selected portion 502 being selected for manual repackaging.

[0052] Figure 5B A more detailed view of the macrocell of selected section 502 is shown before manual repackaging.

[0053] The system can perform a local automatic macrocell placement process only on the selected portion 502. Figure 5C A more detailed view of the macrocells in selected portion 502 after manual repackaging using the local automated macrocell placement process is shown. Note that the selected macrocells are placed more efficiently and aesthetically relative to each other.

[0054] Figure 6 A high-level process 600 for automatically placing macrocells in VLSI design layout / layout planning is shown, which can be executed, for example, by a computer system such as computer system 101 (hereinafter referred to as "the system"). This process can be used, for example, for... Figure 3 The automatic macrocell placement 306 is described. It is assumed here that the system has received the necessary data, such as VLSI input 322, adjustment parameters 324, and large macrocell placement 326.

[0055] At 602, the system performs global placement of macrocells (excluding any manually placed macrocells, such as large macrocell placement 326).

[0056] There are several different approaches to macrocell placement (and macrocell group placement below), and a variety of adjustment parameters can be used, as understood by those skilled in the art. For example, one approach is to first place larger macrocells on the boundaries or edges of the chip, and then fill the interior with smaller macrocells (and eventually other cells), taking into account required wiring, spacing, and other adjustment considerations. Another approach is to first place larger macrocells in specific areas of the chip, and then fill the unused portions of the layout plan with smaller macrocells (and eventually other cells), taking into account required wiring, spacing, and other adjustment considerations.

[0057] Any of these techniques can lead to electromagnetic interference, crosstalk, and noise between macrocells or networks of a particular circuit that are placed too close together. One approach to addressing these issues is to use a technique known as “ePlace,” such as that described in: ePlace: Electrostatics-Based Placement Using FastFourier Transform and Nesterov's Method (Lu et al., ACM Transactions on Design Automation of Electronic Systems, Vol. 20, No. 2, 2015), which is incorporated herein by reference. The ePlace technique models each object as a positive charge and the density cost as the potential energy of the electrostatic system to aid placement. However, this technique can yield less than ideal results by weighting large, distant VLSI objects so that their influence on local placement exceeds what is necessary.

[0058] The disclosed embodiments improve upon known techniques by using an “N-Place” global placement process for placing macrocells and standard cells in a VLSI layout plan.

[0059] Figure 7 A process 700 for globally placing nodes in VLSI layout planning according to a disclosed embodiment is illustrated. A “node” refers to any VLSI object to be placed as described herein, whether it is a cell, macrocell, or group of macrocells. In various embodiments, this global placement method can be used to place a mixture of macrocells and standard cells during layout planning creation, and can be used to place standard cells during the physical IC design phase.

[0060] At position 702, the system models each of the multiple nodes as a nuclear charge proportional to the area of ​​the node in the layout plan.

[0061] At point 704, the system models the repulsive potential of each of the plurality of nodes relative to each of the other nodes. According to the disclosed embodiment, this can be performed by modeling the repulsive potential using the anti-Yukawa potential (nuclear force), which is calculated by the following formula:

[0062]

[0063] Where φ is the repulsive nuclear force, r is the radial distance between a pair of nodes, q is the assigned nuclear charge, e is the Euler number, and r0 is an optional adjustable parameter used to adjust the range of the repulsive potential model. An example of an acceptable value for r0 is 0.5 (chip width / height). Note that as r0→∞, the equation simplifies to the calculation of the potential.

[0064] At point 706, the system determines the attractive linear force between each pair of nodes, as is known to those skilled in the art.

[0065] At position 708, the system determines the core field (N field) of each node based on the charge density of each node. To do this, the system can compute the layout plan and the density grid for each node, and then use the Fast Fourier Transform (FFT) of the charge density of each node to compute the N field for each node.

[0066] At 710, the system places each node within a layout plan based on the core field of each node and the attractive line forces between each pair of nodes. When placing each node, the system attempts to balance the attractive line forces acting on each node with the repulsive N-field forces acting on each node. This process may include initial placement of some nodes as described herein (e.g., by placing large macrocells on chip boundaries or specific regions), and then placing each subsequent node based on the core field of each node and the attractive line forces between the current node and already placed nodes. Furthermore, after the initial placement, the system may move each node as needed to optimize placement to balance the repulsive core field forces and attractive line forces, including by using Nesterov methods known to those skilled in the art.

[0067] return Figure 6 At position 604, the system performs a legalization process for global macrocell placement. In this context, "legalization" means ensuring that the placement of all objects does not violate any design rules, such as object overlap, exceeding chip edges, or other rules known to those skilled in the art.

[0068] In various embodiments, the system can perform legalization based on simulated annealing (SA). Simulated annealing is a probabilistic technique for approximating the global optimum of a given function. Specifically, it is a metaheuristic algorithm used to approximate the global optimum for an optimization problem in a large search space. For a large number of local optima, SA can find the global optimum.

[0069] Figure 8 An SA legalization process 800 according to a disclosed embodiment is shown.

[0070] At position 802, the system performs an SA iteration on the existing layout plan (including any node), including moving any node to meet the legitimacy requirements.

[0071] At point 804, the system performs a Quality of Results (QoR) analysis based on the current state of SA iterations and layout planning. This can be performed, for example, once every 1000 SA iterations. In addition to physical legitimacy requirements (e.g., avoiding design rules), the QoR analysis may include timing requirements, dead zones, bottlenecks, routing issues, etc. The QoR analysis may include determining whether node modifications as described below should be performed. The QoR analysis may include determining whether regrouping is necessary or recommended (if regrouping has already been performed).

[0072] At point 806, the system can apply modification techniques. In this step, the system can perform post-processing to determine which modification techniques to include, and can determine the weights, probabilities, or other adjustment factors for these techniques as determined by QoR analysis. These modification techniques can be used in the next SA operation (at point 802). In this context, modification techniques do not refer to changing the structure of nodes and their components, but rather to performing certain modifications to the placement or arrangement of nodes. Modification techniques can include, for example, sliding or shifting nodes, flipping, reversing, or mirroring nodes, swapping the positions of two nodes, reshaping macrocell groups, and other such modifications.

[0073] When implementing any modification techniques, the system can apply a cost function to the macrocell distribution in order to comply with higher-level hierarchical constraints.

[0074] At point 808, the system can optionally roll back the state of the layout planning and associated SA iterations. That is, the SA legitimization process can continue in the current state, modifying it until legitimization is complete, but if the QoR analysis indicates that QoR is actually deteriorating, the system can roll back to a previous state and attempt modifications to other nodes. For example, in some cases, the system can roll back the layout planning state to a previous number (e.g., 1000 or 2000) SA iterations.

[0075] At 810, when legitimizing a group, the system can perform a regrouping process as described herein, such as the process described for step 610 below. The system can determine whether to perform the regrouping process based on QoR analysis.

[0076] The process loops back to the SA iteration at 802 until the layout program (or a selected portion of the layout program) has been successfully validated.

[0077] return Figure 6 During the process, at positions 606 and 610, the system constructs macrocell groups and globally places them within the layout plan. These two processes—constructing macrocell groups at position 610 and globally placing macrocell groups at position 606—can be performed simultaneously, allowing the system to place each macrocell group as it is constructed.

[0078] At position 606, the system performs a global placement of the macrocell group (excluding any manually placed macrocells, such as large macrocell placement 326). This can be described as above regarding... Figure 7 The process is performed as described. Note that since some macrocells may have been globally placed before grouping in step 602, these macrocells can be removed from their current placement when the macrocell group is constructed, and then repositioned as part of step 606.

[0079] At 610, the system constructs macrocell groups, each group comprising multiple macrocells. In the simplest case, the system can simply construct macrocell groups based on the logical hierarchy of each macrocell, such that multiple macrocells with the same logical hierarchy (e.g., according to a hierarchical netlist) are placed together in a single macrocell group. However, various embodiments can also perform more complex macrocell grouping as described below, both of which can be considered timing-driven macrocell grouping to place macrocells within the same hierarchical module together and can further ensure that macrocells with the same library units are grouped together for proper alignment.

[0080] Figure 9A A process 900 for constructing a macrocell group according to a disclosed embodiment is shown.

[0081] At point 902, the system assigns a macrocell group to each macrocell based on its "grid" in the layout plan. The layout plan (or a selected portion of it) can be divided into grid areas called "grids" or "buckets". At point 902, the system can initially assign all macrocells in a grid or a group of grids to a single macrocell group.

[0082] At 904, from these initial groups, the system can construct subgroups by grouping any macrocells in the macrocell group that have cells from the same standard cell library together.

[0083] At 906, from the subgroup, the system can construct further subgroups by grouping any macrocells at the same logical level within the macrocell subgroup together, and then return the macrocell subgroups (as macrocell groups) to the calling procedure.

[0084] Figure 9B Another process 950 for constructing a macrocell group according to a disclosed embodiment is shown.

[0085] At position 952, the system initially assigns a macrocell group to each macrocell based on the instance name-based hierarchy (e.g., based on a hierarchical netlist).

[0086] At 954, from these initial groups, the system can construct subgroups by grouping any macrocells in the macrocell group that have cells from the same standard cell library together.

[0087] At 956, from the subgroup, the system can build further subgroups by grouping the macrocell subgroups together according to physical proximity-based clustering (using algorithms such as Density-Based Spatial Clustering of Applications with Noise (DBSCAN)), and then return the macrocell subgroups (as macrocell groups) to the calling procedure.

[0088] return Figure 6 In the process at 608, the system places a validation procedure for the global macrocell group. This can be performed on the macrocell group in the same way as the validation for other layout planning nodes at 604 described above. This validation procedure can be used... Figure 8 The process includes, if necessary, constructing a new group at 610 for the regrouping process at 810.

[0089] Of course, those skilled in the art will recognize that, unless specifically indicated or required by the order of operations, certain steps in the above process may be omitted, performed concurrently or sequentially, or performed in a different order.

[0090] Those skilled in the art will recognize that, for simplicity and clarity, the complete structure and operation of all data processing systems suitable for use with this disclosure are not depicted or described herein. Rather, only those parts of the data processing systems unique to or necessary for understanding this disclosure are depicted and described. The remaining construction and operation of the computer systems disclosed herein may conform to various current implementations and practices known in the art.

[0091] It is important to note that although this disclosure is described in the context of a fully functional system, those skilled in the art will understand that at least part of the mechanisms of this disclosure can be distributed in various forms as instructions contained in machine-usable, computer-usable, or computer-readable media, and this disclosure applies equally regardless of the particular type of instruction or signal-bearing medium or storage medium used to actually perform the distribution. Examples of machine-usable / readable or computer-usable / readable media include: non-volatile, hard-coded media, such as read-only memory (ROM) or erasable electrically programmable read-only memory (EEPROM); and user-recordable media, such as floppy disks, hard disk drives, and optical disc read-only memory (CD-ROM) or digital universal disc (DVD).

[0092] Although exemplary embodiments of this disclosure have been described in detail, those skilled in the art will understand that various changes, substitutions, variations, and modifications can be made to this disclosure without departing from the spirit and scope of this disclosure as presented in its broadest form.

[0093] Nothing described in this application should be construed as implying that any particular element, step, or function is a necessary element to be included in the scope of the claims: the scope of the patent subject matter is defined only by the granted claims. Furthermore, none of these claims are intended to invoke 35 USC §112(f) unless the exact phrase “means for…” is followed by a participle. The use of terms such as (but not limited to) “mechanism,” “module,” “device,” “unit,” “component,” “element,” “building,” “device,” “machine,” “system,” “processor,” or “controller” in the claims is understood and intended to refer to structures known to a person skilled in the art, as further modified or enhanced by the features of the claims themselves, and is not intended to invoke 35 U.SC §112(f).

Claims

1. A method (300) for generating a large-scale integrated layout plan (400), the method comprising: Receive (302) inputs (322, 324, 326) for automatically placing macro cells in the layout planning (400); Based on the received inputs (322, 324, 326), execute the (304) automatic macrocell placement process; as well as The layout plan (400) is generated (308) according to the automatic macrocell placement process, wherein the layout plan (400) can then be used to generate a physical layout and can then be used to manufacture a physical chip based on the generated physical layout.

2. The method as described in claim 1, wherein, The automatic macrocell placement process (304) is time-driven to place macrocells (402) within the same level module close to each other in the layout plan (400), and macrocells (402) with the same library are grouped together.

3. The method as described in claim 1, wherein, The automatic macrocell placement process (304) includes: In the layout planning (400), the global macrocell placement of multiple macrocells (402) is performed (602); For the global macrocell, place (602) and execute (604) the legalization process; Construct (610) macrocell groups (404), each macrocell group (404) having multiple macrocells from the plurality of macrocells (402); Perform (606) the global macrocell group placement of the macrocell group (404); and The legalization process (608) is performed for the global macrocell group (606).

4. The method of claim 3, wherein, The global macrocell placement (602) is based on the repulsive core field force and attractive line force modeled between the plurality of macrocells (402) in the layout plan (400).

5. The method of claim 3, wherein, The global macrocell group placement (606) is based on the repulsive nuclear field force and attractive line force modeled between the macrocell groups (404).

6. The method of claim 3, wherein, The legalization process (604) for the global macrocell placement (602) is an iterative, simulated annealing-based legalization using modification techniques.

7. The method of claim 3, wherein, The legalization process (608) for the global macrocell group placement (606) is an iterative, simulated annealing-based legalization using modification techniques.

8. The method of claim 3, wherein, The legitimation process (608) for the placement of the global macrocell group (606) includes performing a regrouping process to form a new macrocell group (404).

9. The method of claim 3, wherein, Constructing the (610) macrounit group (404) includes: According to the layout plan, each macro cell (402) is assigned a macro cell group (404). Group macrocells (402) that have cells from the same standard cell library together; and Group macrocells (402) that are at the same logical level together.

10. The method of claim 3, wherein, Constructing the (610) macrounit group (404) includes: Macrocell group (404) is assigned to each macrocell (402) according to the instance name-based hierarchy. Group macrocells (402) that have cells from the same standard cell library together; and Macrocells (402) are grouped together based on physical proximity clustering.

11. The method of claim 3, further comprising: The standard unit (710) is placed in the layout plan (400) based on the repulsive core field force and attractive line force modeled between the standard unit (710) and the plurality of macro units (402) in the layout plan (400).

12. A computer system (101), comprising: Processor (111); as well as Accessible memory (107), the computer system (101) is specifically configured to perform the method as described in any one of claims 1-11.

13. A non-transitory computer-readable medium (107) encoded with executable instructions that, when executed, cause one or more computer systems (101) to perform the method as claimed in any one of claims 1 to 11.

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