Vertical parasitic npn triode device and method of manufacturing the same

Abstract

The application discloses a vertical parasitic NPN triode device and a manufacturing method thereof, and the vertical parasitic NPN triode device comprises the following steps: an N-type deep well is arranged on a P-type substrate, the N-type deep well is formed into a segmented structure on both sides of the P-type substrate at a corresponding position of an emission area, both ends of the segmented N-type deep well are connected to each other, and the N-type deep well serves as a collector area; a shallow trench isolation is arranged on an N well and a P well, the N well is arranged in the N-type deep well; the P well is arranged on an inner side of the segmented N-type deep well between the N wells, and serves as a base area; an N-type heavily doped area is arranged on a surface of the P well, and serves as the emission area; and a P-type heavily doped area is arranged on the surface of the P well, is arranged on both sides of the N-type heavily doped area, and is electrically connected to the P well to serve as a base area lead-out end. The application can overcome the defect that the low Early voltage of the existing vertical parasitic NPN triode is caused by the low net doping concentration of the base area, and meanwhile, the adverse effects caused by directly increasing the P well concentration of the base area on other devices of a process platform can be avoided.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and in particular to a vertical parasitic NPN transistor device and its manufacturing method. Background Technology

[0002] Transistors, as fundamental semiconductor devices, have wide applications in circuits. They are mainly divided into two categories: NPN and PNP. NPN transistors are often used as switches, and their amplification or conduction state can be controlled by current signals. Current amplification factor (beta), collector-emitter breakdown voltage (BVCEO), and Erlich voltage (VA) are important electrical parameters of NPN transistors, which directly affect the device's operating performance.

[0003] Vertical parasitic NPN transistors are common parasitic devices in semiconductor circuits. Their traditional structure features an N-type deep well collector, a P-well base, and a heavily doped N-type emitter. The N-type deep well in the collector is led out from the two side N-wells and the heavily doped N-type region, while the P-well in the base is led out from the surface heavily doped P-type region. In practical applications, the low net doping concentration in the base region of this traditional vertical parasitic NPN transistor results in a low Earliest voltage (VA), limiting its application in high-precision circuits.

[0004] Increasing the overall doping concentration of the P-well in the base region directly can improve the Erlie voltage, but it will have an adverse effect on other devices on the same semiconductor process platform, destroy the original electrical performance of other devices on the platform, and cannot balance the performance improvement of the vertical parasitic NPN transistor with the compatibility of other devices on the platform. Summary of the Invention

[0005] The summary of this invention introduces a series of simplified concepts, all of which are simplifications of existing technologies in the field, and will be further explained in detail in the detailed description section. This summary is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0006] The technical problem to be solved by the present invention is to provide a vertical parasitic NPN transistor device and its manufacturing method that can overcome the defect of low Erling voltage caused by low net doping concentration in the base region of existing vertical parasitic NPN transistors, while avoiding the adverse effects on other devices in the process platform caused by directly increasing the P-well concentration in the base region, thereby achieving an effective improvement in the Erling voltage of the vertical parasitic NPN transistor without affecting the normal performance of other devices in the platform.

[0007] To solve the above-mentioned technical problems, the present invention provides a vertical parasitic NPN transistor device, comprising: a P-type substrate 101, an N-type deep well 102, a shallow trench isolation 103, an N-well 104, a P-well 105, an N-type heavily doped region 106, and a P-type heavily doped region 107. The N-type deep well 102 is disposed on the P-type substrate 101. The N-type deep well 102 is formed in a segmented structure on both sides of the P-type substrate 101 at the corresponding position of the emitter region. The two ends of the segmented N-type deep well 102 are connected to each other, and the N-type deep well 102 serves as a collector region. Shallow trench isolation 103 is provided on N-well 104 and P-well 105; N-well 104 is located in N-type deep well 102; P-well 105 is located inside the segmented N-type deep wells 102 on both sides, between N-wells 104, and P-well 105 serves as the base region. An N-type heavily doped region 106 is disposed on the surface of the P-well 105, and the N-type heavily doped region 106 serves as the emitter region. The P-type heavily doped region 107 is located on the surface of the P-well 105, on both sides of the N-type heavily doped region 106, and electrically connected to the P-well 105 as the base region lead-out terminal.

[0008] Preferably, the vertical parasitic NPN transistor device is further improved in that the N-type deep well 102 is formed by high-energy N-type impurity ion implantation, and after being processed by a thermal propulsion process, the two ends of the segmented N-type deep well 102 are connected to each other, and the doping concentration of the N-type deep well 102 at the corresponding position of the emitter region is reduced.

[0009] Preferably, the vertical parasitic NPN transistor device is further improved in that the N-well 104 is symmetrically disposed on both sides of the N-type deep well 102, and the P-type heavily doped region 107 is symmetrically disposed on both sides of the N-type heavily doped region 106.

[0010] This invention provides a method for manufacturing a vertical parasitic NPN transistor device, which is used to manufacture the vertical parasitic NPN transistor device described in any one of the above-mentioned methods, and includes the following steps: 1. High-energy N-type impurities are selectively implanted into a P-type substrate 101 to form segmented N-type deep wells 102 at the emitter region. The segmented N-type deep wells 102 are subjected to a thermal propulsion process to connect the two ends of the segmented N-type deep wells 102 to each other and reduce the doping concentration of the N-type deep wells 102 at the emitter region. 2. Using active region photolithography, etching and filling processes, a shallow trench isolation region 103 is formed on a P-type substrate 101; 3. Photolithography opens the well implantation region, and N-type impurity ions are implanted between the N-type deep well 102 and the shallow trench isolation 103 to form N-well 104. P-type impurity ions are implanted inside the two N-type deep wells 102 to form P-well 105. 4. Source and drain ion implantation is performed to form an N-type heavily doped region 106 and a P-type heavily doped region 107 on the surface of the P-well 105, thus completing the fabrication of the vertical parasitic NPN transistor.

[0011] Preferably, in the further improved method for manufacturing the vertical parasitic NPN transistor device, in step 1, the processing temperature of the thermal propulsion process is 800℃-1200℃, and the processing time is 1h-3h.

[0012] Preferably, in the further improved method for manufacturing the vertical parasitic NPN transistor device, in step 1), the N-type impurity is phosphorus or arsenic; Preferably, in the further improved method for manufacturing the vertical parasitic NPN transistor device, in step 3), the P-type impurity is boron.

[0013] Preferably, in the further improved method for manufacturing the vertical parasitic NPN transistor device, in step 4), the N-type heavily doped region 106 is located at the emitter region position on the surface of the P-well 105, and the P-type heavily doped region 107 is located at the base region lead-out position on the surface of the P-well 105.

[0014] Based on the above technical solution, the working principle of the present invention is as follows; This invention segments the N-type deep well in the collector region of a vertical parasitic NPN transistor into segments at the emitter region. After a thermal propulsion process, the two ends of the segments are connected to form a complete collector region. Due to the segmented implantation process, the doping concentration of the N-type deep well at the emitter region is significantly reduced. The N-type deep well in the collector region and the P-well in the base region have a complementary doping concentration relationship. The reduction in the N-type deep well concentration at the emitter region passively increases the net doping concentration (effective base concentration) in the base region, thereby improving the device's Erley voltage. At the same time, this invention does not directly change the overall doping concentration of the P-well and will not affect the performance of other devices within the process platform.

[0015] Based on the above technical solution and working principle, the present invention can achieve at least the following technical effects compared with the prior art: 1. In the existing technology, the N-type deep well in the collector region is not segmented. The N-type deep well concentration at the emitter region remains at the original level, and the net doping concentration in the base region cannot be increased. Therefore, the Erlie voltage is always low and cannot be increased to this extent.

[0016] This invention can effectively improve the Erling voltage of a vertical parasitic NPN transistor. Simulation results show that the Erling voltage VA of the device can be increased from 5.6V to 8.6V, an increase of 3V.

[0017] 2. In the existing technology, if the net doping concentration of the base region is to be increased, it can only be done by directly increasing the overall doping concentration of the P-well. This method will change the electrical parameters of other devices in the platform that depend on the doping concentration of the P-well, destroy their original performance, and cannot take into account both the improvement of transistor performance and platform compatibility.

[0018] This invention improves the Oerlikon voltage without adversely affecting other devices on the same process platform, thus ensuring the compatibility of the process platform.

[0019] 3. Existing technologies lack relevant structural improvement ideas and have not optimized the injection process for N-type deep wells. If other methods are used to increase the Oerlikon voltage, additional process steps or equipment are often required, which increases production difficulty and cost.

[0020] The improvement in device structure in this invention is only for the layout of the N-type deep well in the collector region. The process steps are only adjusted based on the original method of injecting into the N-type deep well. No new complex process equipment is required, and it is easy to achieve mass production in existing semiconductor manufacturing processes.

[0021] 4. If the base concentration is adjusted by other means in the existing technology, it is easy to cause large fluctuations in the current amplification factor, making it difficult to maintain the original core performance of the device while increasing the Erlier voltage.

[0022] The current amplification factor (beta) of the device of the present invention only decreases slightly. While increasing the Erli voltage, the original amplification performance of the device is basically maintained, and the normal switching and amplification functions of the device are not affected. Attached Figure Description

[0023] The accompanying drawings are intended to illustrate the general characteristics of the methods, structures, and / or materials used in specific exemplary embodiments of the invention, supplementing the description in the specification. However, the drawings are schematic diagrams not drawn to scale and may not accurately reflect the precise structural or performance characteristics of any of the given embodiments. The drawings should not be construed as limiting or restricting the range of numerical values ​​or properties covered by exemplary embodiments of the invention. The invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0024] Figure 1 This is a schematic cross-sectional view of the vertical parasitic NPN transistor device of the present invention.

[0025] Figure 2 This is a schematic diagram of the intermediate structure of the vertical parasitic NPN transistor device manufacturing method of the present invention. Figure 1 .

[0026] Figure 3 This is a schematic diagram of the intermediate structure of the vertical parasitic NPN transistor device manufacturing method of the present invention. Figure 2 .

[0027] Figure 4 This is a schematic diagram of the intermediate structure of the vertical parasitic NPN transistor device manufacturing method of the present invention. Figure 3 .

[0028] Explanation of reference numerals in the attached figures: 101—P-type substrate; 102-N type deep trap; 103—Shallow trench isolation; 104-N well; 105—P-trap; 106—N-type heavily doped region; 107—P-type heavily doped region. Detailed Implementation

[0029] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can fully understand other advantages and technical effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through different specific embodiments, and various details in this specification can also be applied based on different viewpoints, with various modifications or changes made without departing from the overall design concept of the invention. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. The following exemplary embodiments of the present invention can be implemented in many different forms and should not be construed as being limited to the specific embodiments set forth herein. It should be understood that these embodiments are provided to make the disclosure of the present invention thorough and complete, and to fully convey the technical solutions of these exemplary embodiments to those skilled in the art. It should be understood that when an element is referred to as "connected" or "combined" to another element, the element can be directly connected or combined to the other element, or there may be intermediate elements. The difference is that when an element is referred to as "directly connected" or "directly combined" to another element, there are no intermediate elements. Throughout the drawings, the same reference numerals always denote the same elements.

[0030] First embodiment; refer to Figure 1 As shown, the present invention provides a vertical parasitic NPN transistor device, comprising: a P-type substrate 101, an N-type deep well 102, a shallow trench isolation 103, an N-well 104, a P-well 105, an N-type heavily doped region 106, and a P-type heavily doped region 107. The N-type deep well 102 is disposed on the P-type substrate 101. The N-type deep well 102 is formed in a segmented structure on both sides of the P-type substrate 101 at the corresponding position of the emitter region. The two ends of the segmented N-type deep well 102 are connected to each other, and the N-type deep well 102 serves as a collector region. Shallow trench isolation 103 is provided on N-well 104 and P-well 105. N-well 104 is located in N-type deep well 102; P-well 105 is located inside the segmented N-type deep wells 102 on both sides, between N-wells 104, and P-well 105 serves as the base region. An N-type heavily doped region 106 is disposed on the surface of the P-well 105, and the N-type heavily doped region 106 serves as the emitter region. The P-type heavily doped region 107 is located on the surface of the P-well 105, on both sides of the N-type heavily doped region 106, and electrically connected to the P-well 105 as the base region lead-out terminal.

[0031] Preferably, in the first embodiment, the N-type deep trap 102 is formed by high-energy N-type impurity ion implantation, and the two ends of the thermally propelled segmented N-type deep trap 102 are connected to each other.

[0032] Preferably, in the first embodiment, the N-well 104 is symmetrically disposed on both sides of the N-type deep well 102, and the P-type heavily doped region 107 is symmetrically disposed on both sides of the N-type heavily doped region 106.

[0033] Second embodiment; This invention provides a method for manufacturing a vertical parasitic NPN transistor device, which is used to manufacture the vertical parasitic NPN transistor device described in the first embodiment, and includes the following steps: 1) High-energy N-type impurities are selectively implanted into the P-type substrate 101 to form segmented N-type deep wells 102 at the emitter region. The segmented N-type deep wells 102 are then subjected to a thermal propulsion process to connect the two ends of each segment, and to reduce the doping concentration of the N-type deep wells 102 at the emitter region. Figure 2 As shown; 2) Using active region photolithography, etching, and filling processes, a shallow trench isolation region 103 is formed on the P-type substrate 101, as referenced. Figure 3 As shown; 3) Photolithography opens the well implantation region. N-type impurity ions are implanted between the N-type deep well 102 and the shallow trench isolation 103 to form an N-well 104. P-type impurity ions are implanted inside the two N-type deep wells 102 to form a P-well 105. (Refer to...) Figure 4 As shown; 4) Perform source / drain ion implantation to form an N-type heavily doped region 106 and a P-type heavily doped region 107 on the surface of the P-well 105. The N-type heavily doped region 106 is located at the emitter region position on the surface of the P-well 105, and the P-type heavily doped region 107 is located at the base region lead-out position on the surface of the P-well 105, thus completing the fabrication of the vertical parasitic NPN transistor and forming... Figure 1 The device structure is shown.

[0034] Preferably, in the second embodiment, the processing temperature of the thermal propulsion process is 800℃-1200℃, and the processing time is 1h-3h.

[0035] The N-type impurity is phosphorus or arsenic, and the P-type impurity is boron.

[0036] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will also be understood that, unless explicitly defined herein, terms such as those defined in a general dictionary shall be interpreted as having the meaning consistent with their meaning in the relevant field context, and not as having an idealized or overly formal meaning.

[0037] The present invention has been described in detail above through specific embodiments and examples, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A vertical parasitic NPN transistor device, characterized in that, include: P-type substrate (101), N-type deep well (102), shallow trench isolation (103), N-well (104), P-well (105), N-type heavily doped region (106) and P-type heavily doped region (107); An N-type deep well (102) is disposed on a P-type substrate (101). The N-type deep well (102) is formed in a segmented structure on both sides of the P-type substrate (101) at the corresponding position of the emission region. The two ends of the segmented N-type deep well (102) are connected to each other, and the N-type deep well (102) serves as a collector region. Shallow trench isolation (103) is provided on N-well (104) and P-well (105); The N-well (104) is located in the N-type deep well (102); The P-well (105) is located inside the two segmented N-type deep wells (102) and between the N-wells (104). The P-well (105) serves as the base region. An N-type heavily doped region (106) is disposed on the surface of the P-well (105), and the N-type heavily doped region (106) serves as the emitter region; The P-type heavily doped region (107) is located on the surface of the P-well (105), on both sides of the N-type heavily doped region (106), and electrically connected to the P-well (105) as the base region lead-out terminal.

2. The vertical parasitic NPN transistor device according to claim 1, characterized in that: The N-type deep trap (102) is formed by high-energy N-type impurity ion implantation and the two ends of the N-type deep trap (102) are connected to each other through thermal propulsion segmentation.

3. The vertical parasitic NPN transistor device according to claim 1, characterized in that: The N-well (104) is symmetrically arranged on both sides of the N-type deep well (102), and the P-type heavily doped region (107) is symmetrically arranged on both sides of the N-type heavily doped region (106).

4. A method for manufacturing a vertical parasitic NPN transistor device, used to manufacture the vertical parasitic NPN transistor device according to any one of claims 1-3, characterized in that, Includes the following steps: 1) Selectively implant high-energy N-type impurities into a P-type substrate (101) to form segmented N-type deep wells (102) at the emitter region. Perform a thermal propulsion process on the segmented N-type deep wells (102) to connect the two ends of the segmented N-type deep wells (102) to each other, and reduce the doping concentration of the N-type deep wells (102) at the emitter region. 2) Using active region photolithography, etching and filling processes, a shallow trench isolation region (103) is formed on a P-type substrate (101). 3) Photolithography opens the well implantation region, and N-type impurity ions are implanted between the N-type deep well (102) and the shallow trench isolation (103) to form an N-well (104). P-type impurity ions are implanted inside the two N-type deep wells (102) to form a P-well (105). 4) Perform source and drain ion implantation to form an N-type heavily doped region (106) and a P-type heavily doped region (107) on the surface of the P-well (105) to complete the fabrication of the vertical parasitic NPN transistor.

5. The method for manufacturing a vertical parasitic NPN transistor device according to claim 4, characterized in that, In step 1), the processing temperature of the thermal propulsion process is 800℃-1200℃, and the processing time is 1h-3h.

6. The method for manufacturing a vertical parasitic NPN transistor device according to claim 4, characterized in that, In step 1), the N-type impurity is phosphorus or arsenic.

7. The method for manufacturing a vertical parasitic NPN transistor device according to claim 4, characterized in that, In step 3), the P-type impurity is boron.

8. The method for manufacturing a vertical parasitic NPN transistor device according to claim 4, characterized in that, In step 4), the N-type heavily doped region (106) is located at the emitter region position on the surface of the P-well (105), and the P-type heavily doped region (107) is located at the base region lead-out position on the surface of the P-well (105).

Images