Method for manufacturing deep via and method for manufacturing backside illuminated image sensor

Abstract

The present application relates to the technical field of semiconductor, in particular to a deep via hole preparation method and a preparation method of back-illuminated image sensor, comprising the following steps: providing a semiconductor stack structure, the semiconductor stack structure comprising a composite layer and a termination layer, a local stop layer being formed on the composite layer and being close to the termination layer; etching the composite layer to the termination layer and stopping at the local stop layer; removing the local stop layer, etching the composite layer to the termination layer and stopping at the termination layer to form the deep via hole. According to the design position of the deep via hole and the vertical depth of the first etching, the local stop layer is preset in the corresponding area of the composite layer, so that the damage of the lower structure caused by over-etching in the traditional process can be avoided.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for fabricating deep through-holes and a method for fabricating back-illuminated image sensors. Background Technology

[0002] In semiconductor manufacturing, deep via (VV) technology is a key technology for constructing three-dimensional interconnect structures, and its morphological accuracy directly affects device performance and reliability. In a typical VV process, a first and second etching process can be used to fabricate deep vias (high aspect ratio vias), overcoming the limitations of single-process methods in terms of penetration, uniformity, and damage control. During VV fabrication, the first etching penetrates the upper composite layer, and the second etching removes the lower composite layer and terminates at the stop layer.

[0003] The specific composition of the composite layer and the terminating layer depends on the application scenario and function. Depending on the requirements of different application scenarios or embodiments, the composite layer may be a single-layer structure or a multi-layer structure with multiple layers stacked together. The terminating layer may be, for example, a metal layer, a substrate layer, or a dielectric layer.

[0004] For example, a typical deep via application involves fabricating channel holes in 3D NAND memory devices. In this application, the channel hole needs to penetrate alternating stacked polysilicon and dielectric layers (composite layers), ultimately terminating at the bottom monocrystalline silicon substrate (termination layer). During fabrication, a first etching process is performed using a fluorine-containing gas to etch the composite layers, forming the initial structure of the deep via. A second etching process is then performed to ensure that the vertical via completely penetrates to the silicon substrate, removing any remaining dielectric layers.

[0005] For example, a typical deep via application involves fabricating pad openings on back-illuminated (BSI) image sensor devices. In this application, the pad opening needs to penetrate stacked composite layers (such as a composite dielectric layer, a silicon substrate layer, and an interlayer dielectric layer), ultimately terminating at the first metal layer (termination layer) in the interlayer dielectric (ILD) layer. During fabrication, a first etching process is performed to etch the composite dielectric layer and the silicon substrate layer, followed by a second etching process to continue etching the silicon substrate layer and the ILD layer, terminating at the first metal layer.

[0006] However, the aforementioned deep via fabrication process suffers from a large initial etching depth and lacks an effective first etch stop layer. In actual fabrication, even minor process fluctuations, such as uneven gas distribution or delayed endpoint detection, can lead to over-etching. Excessive etching gas may penetrate the metal layer, causing metal corrosion, forming a conductive oxide layer or voids, ultimately resulting in a surge in contact resistance and a decrease in device yield. In CMOS image sensors, defects in the deep via process (such as metal corrosion or residues) directly increase inter-pixel crosstalk or dark current, reducing signal-to-noise ratio (SNR) and color fidelity. Summary of the Invention

[0007] To address the shortcomings of the prior art, the technical problem to be solved by the present invention is to provide a method for fabricating deep vias and a method for fabricating back-illuminated image sensors that can avoid over-etching problems and improve the overall performance and yield of devices.

[0008] To solve the above-mentioned technical problems, the present invention provides a method for preparing deep through holes, comprising the following steps: A semiconductor stack structure is provided, the semiconductor stack structure including a composite layer and a termination layer, wherein a local stop layer is formed on the composite layer and the local stop layer is close to the termination layer; The composite layer is etched towards the termination layer and stops at a local stop layer; Remove the local stop layer, etch the composite layer towards the termination layer and stop at the termination layer to form the deep via.

[0009] Furthermore, the cross-sectional dimensions of the local stop layer are adapted to the cross-sectional dimensions of the deep through-hole; and / or The local stop layer is configured as a local carbon layer.

[0010] Furthermore, the composite layer includes a first structural layer and a second structural layer formed on a first surface of the first structural layer near the termination layer; the local stop layer is formed on the side of the first structural layer near the second structural layer; The step of providing a semiconductor stacked structure includes the following sub-steps: A first structural layer is provided, and a first trench is formed on a first surface of the first structural layer; The local stop layer is filled into the first trench; The second structural layer is formed on the first surface of the first structural layer.

[0011] Furthermore, a first hard mask layer is conformally distributed on the surface of the first trench.

[0012] Furthermore, the step of etching the composite layer towards the termination layer and stopping at the local stop layer includes: performing a first etching process to etch the first structural layer towards the termination layer and stopping at the local stop layer. The step of etching the composite layer towards the termination layer and stopping at the termination layer to form the deep via includes: performing a second etching process to etch the second structural layer towards the termination layer and stopping at the termination layer to form the deep via.

[0013] Furthermore, the deep via is configured as a pad opening; the first structural layer includes a substrate layer, the second structural layer is configured as an ILD layer, and the termination layer is configured as a metal layer disposed on the ILD layer; a plurality of isolation trenches are formed on the first surface of the substrate layer near the metal layer, wherein an isolation trench corresponding to the pad opening forms the first trench; The step of filling the local stop layer within the first trench includes the following sub-steps: A stop material layer is formed on the first surface of the substrate and within the isolation trench, and a second trench is formed on the surface of the stop material layer within the first trench. A second hard mask layer is filled into the second trench; Using the second hard mask layer as a mask, excess stop material layers on the substrate surface and in the isolation trench are removed, leaving the stop material layer below the second hard mask layer to form the local stop layer; a filling space is formed between the local stop layer and the first trench, and the filling space is used to fill the isolation medium; After the step of filling the local stop layer in the first trench, the following step is further included: An isolation medium is filled into the isolation trench to form a trench isolation structure.

[0014] Furthermore, the cross-sectional dimension of the first trench is larger than the cross-sectional dimension of the other isolation trenches; In the step of forming a stop material layer on the first surface of the substrate layer and in the isolation trench, and forming a second trench on the surface of the stop material layer in the first trench, the second trench is naturally formed during the formation of the stop material layer based on the larger cross-sectional size of the first trench.

[0015] Furthermore, the first structural layer further includes a composite dielectric layer formed on the second surface of the substrate layer facing away from the metal layer; the step of performing the first etching process, etching the first structural layer towards the stop layer and stopping at the local stop layer, specifically includes: The first etching process is performed, sequentially etching the composite dielectric layer and the substrate layer towards the metal layer and stopping at the local stop layer.

[0016] Furthermore, the composite dielectric layer includes a first dielectric layer, a second dielectric layer, and a high-k dielectric layer sandwiched therebetween.

[0017] To solve the above-mentioned technical problems, another technical solution adopted by the present invention is: to provide a method for fabricating a back-illuminated image sensor, including the above-mentioned deep through-hole fabrication method.

[0018] In summary, the deep hole fabrication method and image sensor fabrication method of the present invention have the following unexpected technical effects: (i) During the fabrication of the stacked structure, a local stop layer is pre-placed in the corresponding region of the composite layer according to the design location of the deep via and the vertical depth of the first etching. During the first etching, the local stop layer has a high selectivity for etching compared with the surrounding dielectric layer, ensuring that the etching automatically terminates when it reaches the stop layer; the local stop layer can also avoid damage to the lower metal layer or substrate caused by over-etching in traditional processes, thus significantly improving the stability of the device's electrical performance.

[0019] (ii) The local stop layer adopts an embedded design, which is formed locally in the corresponding area of ​​the stacked structure rather than fully matching the stacked structure (the planar geometry of the local stop layer is adapted to the cross-sectional size of the first channel). Compared with the global etching stop layer (the planar geometry matches the planar size of the stacked structure), it has the following advantages: the local stop layer only exists in the key etching area and is removed during the etching process, avoiding wafer warping caused by the internal stress of the material in the global hard mask.

[0020] (III) Using a local carbon layer as a local stop layer, the local carbon layer exhibits an extremely low reaction rate with plasmas containing F (such as CF4, C4F8) or Cl (such as Cl2, BCl3), effectively suppressing over-etching. The surface of the local carbon layer can react with Cl / F-based plasma to form a carbide passivation layer (such as CCl4, CF4), which can further absorb plasma energy, thereby further preventing over-etching. The local carbon layer can be completely removed by Blanket Asher ETCH (global ashing etching). The ashing process is a purely chemical reaction without high-energy ion bombardment, thus causing minimal physical damage to the already formed shallow trench isolation and ILD layer.

[0021] (iv) Based on the substrate structure of a back-illuminated image sensor, a low-cost embedding of a local stop layer is achieved by differentiating the geometry of the first trench and the remaining isolation trenches. Specifically, the cross-sectional dimension of the first trench is larger than that of the remaining isolation trenches. During the deposition of the stop material layer, the difference in spatial capacity forms a natural filling boundary. When the remaining isolation trenches are completely filled, the interior of the first trench retains an unfilled area due to its larger space. This area directly forms a second trench for protecting the local stop layer, thus eliminating the need for a separate photolithography step to prepare the second trench. This reduces photolithography and etching processes, lowering manufacturing costs.

[0022] (v) Using a pad nitride layer and a second hard mask layer distributed on the first surface of the substrate as etching stop layers, the substrate is globally processed using the Blanket Asher ETCH process. Selective removal of the carbon material layer is achieved by controlling plasma-related parameters. This allows the carbon material layer in the area covered by the second hard mask layer to be retained to form a local stop layer, while the carbon material layer in the unprotected area is completely removed. After etching, a filling space naturally forms between the local stop layer and the sidewalls of the isolation trench. This space is designed primarily for filling the isolation medium in subsequent processes to achieve electrical isolation of the device structure. This process eliminates the need for additional photolithography technology, simplifying the process flow and reducing manufacturing costs. Attached Figure Description

[0023] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings: Figure 1 This is a process flow diagram of an embodiment of the deep through-hole preparation method of the present invention.

[0024] Figure 2 This is a schematic cross-sectional view of a semiconductor stacked structure in one embodiment of the deep through-hole fabrication method of the present invention.

[0025] Figure 3 This is a schematic cross-sectional view of the first trench fabrication stage in one embodiment of the deep through-hole fabrication method of the present invention.

[0026] Figure 4 This is a schematic cross-sectional view of the local stop layer fabrication stage in one embodiment of the deep through-hole fabrication method of the present invention.

[0027] Figure 5 This is a schematic cross-sectional view of the second structural layer fabrication stage in one embodiment of the deep through-hole fabrication method of the present invention.

[0028] Figure 6 This is a schematic cross-sectional view of the first channel fabrication stage in an embodiment of the deep through-hole preparation method of the present invention.

[0029] Figure 7 This is a schematic cross-sectional view of the second channel fabrication stage in one embodiment of the deep through-hole preparation method of the present invention.

[0030] Figure 8 This is a schematic cross-sectional view of an embodiment of the back-illuminated image sensor of the present invention.

[0031] Figure 9 This is a process flow diagram of an embodiment of the fabrication method of the back-illuminated image sensor of the present invention.

[0032] Figure 10 This is a schematic cross-sectional view of the substrate, pad oxide layer and pad nitride layer fabrication stages in one embodiment of the fabrication method of the back-illuminated image sensor of the present invention.

[0033] Figure 11 This is a schematic cross-sectional view of the patterned photoresist layer fabrication stage in one embodiment of the back-illuminated image sensor fabrication method of the present invention.

[0034] Figure 12 This is a schematic cross-sectional view of the isolation trench fabrication stage in one embodiment of the back-illuminated image sensor fabrication method of the present invention.

[0035] Figure 13 This is a schematic cross-sectional view of the first hard mask layer fabrication stage in one embodiment of the back-illuminated image sensor fabrication method of the present invention.

[0036] Figure 14 This is a schematic cross-sectional view of the stopping material layer fabrication stage in one embodiment of the back-illuminated image sensor fabrication method of the present invention.

[0037] Figure 15 This is a schematic cross-sectional view of the fabrication stage of the second hard mask material layer in one embodiment of the fabrication method of the back-illuminated image sensor of the present invention.

[0038] Figure 16 This is a schematic cross-sectional view of the second hard mask layer fabrication stage in one embodiment of the back-illuminated image sensor fabrication method of the present invention.

[0039] Figure 17 This is a schematic cross-sectional view of the local stop layer fabrication stage in one embodiment of the back-illuminated image sensor fabrication method of the present invention.

[0040] Figure 18 This is a schematic cross-sectional view of the isolation medium filling stage in one embodiment of the fabrication method of the back-illuminated image sensor of the present invention.

[0041] Figure 19 This is a schematic cross-sectional view of the pad nitride layer removal stage in one embodiment of the fabrication method of the back-illuminated image sensor of the present invention.

[0042] Figure 20 This is a schematic cross-sectional view of the thinning stage of the isolation medium in one embodiment of the fabrication method of the back-illuminated image sensor of the present invention.

[0043] Figure 21 This is a schematic cross-sectional view of the metal interconnect structure fabrication stage in one embodiment of the back-illuminated image sensor fabrication method of the present invention. The figure simply illustrates the structure of the ILD and the first metal layer.

[0044] Figure 22 This is a schematic cross-sectional view of the composite dielectric layer fabrication stage in one embodiment of the back-illuminated image sensor fabrication method of the present invention.

[0045] Figure 23 This is a schematic cross-sectional view of the first channel fabrication stage in one embodiment of the back-illuminated image sensor fabrication method of the present invention.

[0046] Figure 24 This is a schematic cross-sectional view of the local stop layer removal stage in one embodiment of the fabrication method of the back-illuminated image sensor of the present invention.

[0047] Figure 25 This is a schematic cross-sectional view of the second channel fabrication stage in one embodiment of the back-illuminated image sensor fabrication method of the present invention.

[0048] The diagrams in the instruction manual are labeled as follows: Semiconductor stacked structure 100; first side 100a; second side 100b; composite layer 110; first structural layer 111; first trench 111a; second structural layer 112; termination layer 120; local stop layer 130; first channel 141; second channel 142; Back-illuminated image sensor 200; first side 200a; second side 200b; sensor element 201; photosensitive area 201a; transfer gate 202; reset gate 203; source / drain region 204; color filter layer 205; microlens layer 206; substrate 210; pad oxide layer 211; pad nitride layer 212; patterned photoresist layer 213; window 213a; trench isolation structure 220; isolation trench 221; first hard mask layer 222; local stop layer 2 23; Stop material layer 223a; Second trench 223b; Second hard mask layer 224; Second hard mask material layer 224a; Fill space 225; Metal interconnect structure 230; ILD layer 231; Contact 232; Metal layer 233; First metal layer 233a; Composite dielectric layer 240; First dielectric layer 241; High-k dielectric layer 242; Second dielectric layer 243; Pad opening 250; First via 251; Sidewall protection layer 251a; Second via 252. Detailed Implementation

[0049] The following disclosure provides various embodiments or examples for implementing different features of the invention. Specific examples of components and arrangements will be described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, or embodiments where other components may be formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. Such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations.

[0050] Furthermore, spatial relation terms such as "below," "under," "below," "above," and "above" may be used herein to readily describe the relationship between one element or component and another element (or component) or component (or component) as shown in the figure. In addition to the orientations shown in the figure, spatial relation terms will encompass various different orientations of the device in use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations) and will be interpreted accordingly through the spatial relation descriptors used herein.

[0051] Although the numerical ranges and parameter settings presented in this invention are approximations, the numerical settings in specific instances are reported as precisely as possible. Any numerical value, however, inherently contains certain inevitable errors arising from the standard deviation found in the respective test measurements. Similarly, as used herein, the term "about" generally refers to within 10%, 5%, 1%, or 0.5% of a given value or range. Alternatively, the term "about" means within an acceptable average standard error that can be conceived by one of ordinary skill in the art. Except in instances of operation / work, or unless expressly stated otherwise, all numerical ranges, totals, values, and percentages, such as those for material quantities, durations, temperatures, operating conditions, amounts, and other similarities disclosed herein, should be understood to be modified by the term "about" in all cases. Therefore, unless otherwise stated, the numerical parameter settings set forth in this invention and the appended claims are approximations that can be changed upon request. At a minimum, each numerical parameter should be interpreted based on the number of significant figures reported and the application of ordinary rounding techniques. A range herein may be expressed as from one endpoint to another or between two endpoints. All scopes disclosed herein include endpoints unless otherwise stated.

[0052] Furthermore, the technical parts described in this invention and the appended claims are primarily the improved technical parts of this invention, and do not limit the object protected by this invention to only having these technical parts. Other known essential components (structures and / or methods) and / or non-essential components of the object protected, besides the technical parts described in this invention and the appended claims, are not included in this invention and the appended claims because they do not fall within the scope of improvements of this invention; however, this does not mean that the object protected by this invention does not possess these known components.

[0053] Please see Figure 1 , Figure 1 A process flow diagram of an embodiment of the deep through-hole fabrication method of the present invention is shown. In the illustrated embodiment, the deep through-hole fabrication method includes the following steps: S110, Provides a semiconductor stacked structure 100.

[0054] Please see Figure 2 The semiconductor stacked structure 100 includes a composite layer 110 and a termination layer 120. A local stop layer 130 is formed on the composite layer 110 and is close to the termination layer 120.

[0055] In this document, the stacking direction of the semiconductor stacked structure 100 is defined as the vertical direction (also known as the up-down direction), the side containing the termination layer 120 is defined as the first side 100a, and the side containing the composite layer 110 is defined as the second side 100b. Based on this, the surface orientation of each component of the semiconductor stacked structure 100 is defined as follows: the surface facing the first side 100a is defined as the first surface, and the surface facing the second side 100b is defined as the second surface. For example, the surface of the composite layer 110 facing or close to the termination layer 120 is defined as the first surface, and the surface of the composite layer 110 away from the termination layer 120 is defined as the second surface.

[0056] The specific composition of the semiconductor stacked structure 100 depends on the application scenario and functional requirements. The composite layer 110 may be a single-layer structure or a multilayer structure with multiple layers stacked together. The termination layer 120 may be, for example, a metal layer, a substrate layer, or a dielectric layer.

[0057] For example, one application scenario for deep vias includes fabricating vias in a 3D NAND memory device. In this application scenario, the via needs to penetrate alternating stacked polysilicon and dielectric layers, ultimately terminating at the bottom monocrystalline silicon substrate. Therefore, in this application scenario, composite layer 110 includes the polysilicon layer and dielectric layer, and termination layer 120 is configured as a monocrystalline silicon substrate layer. Termination layer 120 is defined as an etch stop layer for the deep via, that is, the etching process stops at termination layer 120, exposing termination layer 120 through the deep via. Another example is a deep via application scenario including fabricating pad openings in a back-illuminated image sensor device. In this application scenario, the pad opening needs to penetrate stacked composite dielectric layer, silicon substrate layer, and interlayer dielectric layer (ILD layer), ultimately terminating at the first metal layer. Therefore, in this application scenario, composite layer 110 includes the composite dielectric layer, silicon substrate layer, and ILD layer, and termination layer 120 is configured as the first metal layer.

[0058] Based on the orientation defined above, the local stop layer 130 is formed on the first side of the composite layer 110. The planar geometry of the local stop layer 130 (the surface perpendicular to the stacking direction) is adapted to the cross-sectional dimensions of the via to be formed, rather than matching the overall planar dimensions of the composite layer 110. This design ensures that the stop layer only functions as an etch stop at the corresponding location of the via, while avoiding process impact on other areas of the semiconductor stack structure 100.

[0059] The local stop layer 130 is embedded on the first side 100a of the composite layer 110, specifically at the position on the composite layer corresponding to the deep through-hole to be formed. The composite layer 110 can be two or more structural layers. Depending on different requirements, the local stop layer 130 can be embedded between two adjacent structural layers. For example, when the composite layer 110 is composed of a first structural layer 111 and a second structural layer 112 formed by its first surface, the local stop layer 130 can be embedded on the first side 100a of the first structural layer 111 (the side closer to the second structural layer 112 and the metal layer).

[0060] For example, the local stop layer 130 can be formed on the first side 100a of the composite layer 110 by the following process: S111, A first structural layer 111 is provided, and a first trench 111a is formed on the first surface of the first structural layer 111.

[0061] Please see Figure 3The material of the first structural layer 111 can be configured according to different application scenarios. For example, in this embodiment, the first structural layer 111 can be a substrate layer (hereinafter referred to as the substrate). The substrate can be an undoped silicon substrate or a silicon substrate doped with a p-type dopant such as boron, and thus used as a p-type substrate. Alternatively, the substrate may comprise another suitable semiconductor material. For example, the substrate may be a silicon substrate doped with an n-type dopant such as phosphorus or arsenic, and thus used as an n-type substrate. Moreover, the substrate may include other elemental semiconductors such as germanium and diamond. The substrate may optionally include compound semiconductors and / or alloy semiconductors.

[0062] In this step, substrate material is quantitatively removed from the first surface of the substrate using any known etching process such as dry etching and / or wet etching to obtain a first trench 111a with the opening facing the first side 100a.

[0063] To avoid damaging the underlying structure during the removal of the local stop layer 130, and to control the etching depth of the local stop layer 130, a first hard mask layer can be conformally distributed on the surface of the first trench 111a after its formation. This first hard mask layer can be made of a material system with a different chemical composition and physical properties than the local stop layer 130. This differentiated material selection avoids interference between materials and ensures a clear interface between the local stop layer 130 and the first hard mask layer. For example, when the local stop layer 130 is made of carbon (i.e., when the local stop layer 130 is a local carbon layer), the first hard mask layer can be a silicon nitride layer.

[0064] S112. The local stop layer 130 is filled into the first trench 111a.

[0065] Please see Figure 4 The local stop layer 130 can be a hard mask layer made of materials such as silicon nitride or carbon. The local stop layer 130 can be partially (not fully) or fully filled in the first trench 111a. The planar geometry of the local stop layer 130 is adapted to the cross-sectional dimensions of the deep through hole to be formed. The local stop layer 130 can be formed in the first trench 111a using any known suitable process.

[0066] S113. The second structural layer 112 is formed on the first surface of the first structural layer 111.

[0067] Please see Figure 5 The second structural layer 112 may be an ILD layer located between the first metal layer and the silicon substrate. The ILD layer may be formed on the first side 100a of the silicon substrate using chemical vapor deposition (CVD) or other suitable processes. The second structural layer 112 may also be configured as other material layers according to different needs, and the present invention does not impose specific limitations.

[0068] S120, Etch composite layer 110 toward termination layer 120 and stop at local stop layer 130.

[0069] During the etching process, the local stop layer 130 achieves depth control by automatically terminating the etching process, while protecting the underlying structure from damage. Finally, a first channel 141 is formed in the composite layer 110, extending from the second surface to the local stop layer 130, providing a foundation for subsequent deep hole processing.

[0070] Please see Figure 6 Taking the composite layer 110 consisting of the first structural layer 111 and the second structural layer 112 as an example, in this step, the first etching process is performed. The etching medium, selectivity, etching time and other parameters suitable for the first structural layer 111 are selected. The first structural layer 111 is etched from the second surface of the first structural layer 111 to the first surface and stops at the local stop layer 130, thereby forming the first channel 141.

[0071] When the first structural layer 111 and the second structural layer 112 are a silicon substrate and an ILD layer, respectively, the local stop layer 130 can be a local carbon layer. Compared to a silicon nitride stop layer, carbon-based materials have significantly different chemical bond energy distributions and crystal structure characteristics compared to silicon substrates. This characteristic allows the etching reaction to produce an exponentially decaying chemical reaction rate at the carbon / silicon interface, thereby achieving atomic-level precision control of etching termination while avoiding damage to the microstructure of adjacent material layers.

[0072] S130, remove the local stop layer 130, etch the composite layer 110 towards the termination layer 120 and stop at the termination layer 120 to form the deep via.

[0073] When removing the local stop layer 130, known etching processes or other suitable processes can be used. For example, when the local stop layer 130 is a local carbon layer, it can be removed non-destructively using the oxygen Blanket Asher ETCH process. This process utilizes oxygen plasma to chemically react with carbon to generate CO / CO2 gas, thereby completing the removal of the local stop layer 130.

[0074] Please see Figure 7After the local stop layer 130 is completely removed, a second etching process is performed on the composite layer 110 (second structural layer 112). The second etching process optimizes the parameters of the material properties of the second structural layer 112, including but not limited to: the ratio of fluorine-based to chlorine-based etching gases, control of the sidewall passivation layer deposition rate, and real-time endpoint detection. The etching direction advances along the axis of the deep via towards the termination layer 120, and the etching terminates when it reaches the interface of the termination layer 120, ultimately forming a second channel 142 that is coaxially connected to the first channel 141. Together, they constitute a deep via structure with vertical sidewalls.

[0075] Based on this embodiment, the deep hole preparation method of the present invention has the following unexpected technical effects: (i) During the fabrication of the stacked structure, a local stop layer is pre-placed in the corresponding region of the composite layer according to the design location of the deep via and the vertical depth of the first etching. During the first etching, the local stop layer has a high selectivity for etching compared with the surrounding dielectric layer, ensuring that the etching automatically terminates when it reaches the stop layer; the local stop layer can also avoid damage to the lower metal layer or substrate caused by over-etching in traditional processes, thus significantly improving the stability of the device's electrical performance.

[0076] (ii) The local stop layer adopts an embedded design, which is formed locally in the corresponding area of ​​the stacked structure rather than fully matching the stacked structure (the planar geometry of the local stop layer is adapted to the cross-sectional size of the first channel). Compared with the global etching stop layer (the planar geometry matches the planar size of the stacked structure), it has the following advantages: the local stop layer only exists in the key etching area and is removed during the etching process, avoiding wafer warping caused by the internal stress of the material in the global hard mask.

[0077] The following section uses the fabrication method of a back-illuminated image sensor 200 as an example to detail the fabrication method of pad openings 250 (deep vias) in a semiconductor stacked structure. This method focuses on the fabrication of pad openings 250 (see...). Figure 25 The process implementation of the device and its related structures is described, while the fabrication steps of other devices are omitted or refer to the prior art.

[0078] Please see Figure 8 The back-illuminated image sensor 200 includes a substrate 210. The substrate 210 has a first surface (front side) facing a first side 200a and a second surface (back side) facing an opposite second side 200b.

[0079] Substrate 210 is a silicon-containing semiconductor substrate. Optionally or additionally, substrate 210 includes another elemental semiconductor, such as germanium and / or diamond; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. According to one or more embodiments, substrate 210 is a semiconductor on insulator (SOI). Substrate 210 includes a doped epitaxial layer, a gradient semiconductor layer, and / or a semiconductor layer located on top of another different type of semiconductor layer, such as a silicon-germanium-on-silicon layer. In the illustrated embodiments, substrate 210 is a p-type doped substrate 210. The p-type dopant of the doped substrate includes boron, gallium, indium, other suitable p-type dopant, or combinations thereof. In one or more embodiments, substrate 210 is an n-type doped substrate 210, and the n-type dopant of the doped substrate includes phosphorus, arsenic, other suitable n-type dopant, or combinations thereof. According to one or more embodiments, regardless of the doping type of the substrate 210, the substrate 210 includes various p-type doped regions and / or n-type doped regions. In one or more embodiments, doping can be performed using processes such as ion implantation or diffusion at various steps and techniques.

[0080] The substrate 210 includes a trench isolation structure 220 to separate (or isolate) various regions or devices formed on or within the substrate 210. For example, the trench isolation structure 220 separates sensor element 201 from adjacent sensor elements 201. The trench isolation structure 220 may be a shallow trench isolation structure (STI).

[0081] As described above, the back-illuminated image sensor 200 includes a sensor element 201 (or sensor pixel) formed on a substrate 210. The sensor element 201 detects the intensity or brightness of radiation directed toward the back of the substrate 210, such as incident radiation. The incident radiation is visible light, and the radiation is infrared (IR), ultraviolet (UV), X-rays, microwaves, other suitable types of radiation, or combinations thereof. The sensor element 201 is configured to correspond to a specific wavelength, such as red, green, or blue light, for detecting the intensity or brightness of that specific wavelength. The sensor element 201 includes a photodetector, such as a photodiode, which includes a photosensitive region 201a (or photosensing region). The photosensitive region 201a is in the substrate 210, specifically a doped region formed within the substrate 210 with n-type and / or p-type dopants.

[0082] The sensor element 201 also includes various transistors, such as a transfer transistor associated with a transfer gate, a reset transistor associated with a reset gate, a source follower transistor, a select transistor, other suitable transistors, or combinations thereof. The photosensitive region 201a and the various transistors (collectively referred to as pixel circuitry) allow the sensor element 201 to detect the intensity of a specific light wavelength. Additional circuitry, inputs, and / or outputs may be provided to the sensor element 201 to provide an operating environment for the sensor element 201 and / or support communication with the sensor element 201.

[0083] The substrate 210 is provided with various transistor gates for the pixel circuit, such as a transfer gate 202 and a reset gate 203, which are formed by suitable processes, including deposition, photolithography patterning, and etching. The transfer gate 202 is situated between the source / drain region 204 and the photosensitive region 201a of the substrate 210, thereby defining a channel between the source / drain region 204 and the photosensitive region 201a. The reset gate 203 is situated between the source / drain regions 204 of the substrate 210, thereby defining a channel between the two source / drain regions 204. In the illustrated embodiment, the source / drain region 204 is an N+ source / drain diffusion region. The source / drain region 204 may be referred to as a floating diffusion region. The transfer gate 202 and the reset gate 203 comprise gate stacks having a gate dielectric layer and a gate electrode. The gate dielectric layer comprises a dielectric material, such as silicon oxide, a high-k dielectric material, other dielectric materials, or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, hafnium dioxide-alumina (HfO2-Al2O3) alloys, other high-k dielectric materials, or combinations thereof. The gate electrode comprises polycrystalline silicon and / or metals, including Al, Cu, Ti, Ta, W, Mo, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, other conductive materials, or combinations thereof. The transfer gate 202 and the reset gate 203 include spacer structures disposed on the sidewalls of the gate stack. The spacer structures include a gate offset spacer and / or a gate sidewall spacer 205 (shown together as an element) and a sidewall spacer 205. The gate offset spacer is the layer closest to the gate, followed by the gate sidewall spacer 205. The spacer structure can be different oxides. The sidewall spacer 205 can be silicon nitride, silicon oxynitride, other suitable materials, or combinations thereof, located in a multilayer structure.

[0084] The back-illuminated image sensor 200 also includes a metal interconnect structure 230 disposed on a first surface of a substrate 210. The metal interconnect structure 230 is connected to various elements of the back-illuminated image sensor 200, such as sensor element 201, such that the elements of the back-illuminated image sensor 200 can be operated to respond correctly to illumination light (imaging radiation). The metal interconnect structure 230 includes an ILD layer 231 and various conductive components disposed on the ILD layer 231, which may be vertical interconnects, such as contacts 232 and / or vias; and / or horizontal interconnects, such as lines (metal layer 233). The various conductive components comprise conductive materials such as metals. In specific examples, metals may be used, including aluminum, aluminum / silicon / copper alloys, titanium, titanium nitride, tungsten, polycrystalline silicon, metal silicides, or combinations thereof, and the various conductive components may be referred to as aluminum interconnects. Aluminum interconnects may be formed by processes including physical vapor deposition (PVD), chemical vapor deposition (CVD), or combinations thereof. Other manufacturing techniques used to form the various conductive components may include photolithography and etching to pattern the conductive material to form vertical and horizontal interconnects. Other manufacturing processes may also be implemented to form the metal interconnect structure 230, such as thermal annealing to form metal silicides. The metal silicides used in the metal interconnect structure 230 may include nickel silicide, cobalt silicide, tungsten silicide, tantalum silicide, titanium silicide, platinum silicide, erbium silicide, palladium silicide, or combinations thereof. Optionally, the various conductive components may include copper, copper alloys, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, polycrystalline silicon, metal silicides, or combinations thereof. Copper interconnects may be formed by processes including PVD, CVD, or combinations thereof. The metal interconnect structure 230 is not limited by the number, material, size, and / or dimensions of the described conductive components, and thus, depending on the design requirements of the back-illuminated image sensor 200, the metal interconnect structure 230 may include any number, material, size, and / or dimensions of conductive components.

[0085] The back-illuminated image sensor 200 further includes a composite dielectric layer 240 disposed on the second surface of the substrate 210. The composite dielectric layer 240 may include a first dielectric layer 241, a second dielectric layer 243, and a high-k dielectric layer 242 sandwiched therebetween. The first dielectric layer 241 and the second dielectric layer 243 may be made of silicon oxide, silicon nitride, or silicon oxynitride. The high-k dielectric layer 242 may be made of aluminum oxide, magnesium oxide, calcium oxide, hafnium oxide, zirconium oxide, yttrium oxide, tantalum oxide, strontium oxide, titanium oxide, lanthanum oxide, barium oxide, or other metal oxides that can form high-k films using existing semiconductor deposition techniques. High-k metal oxides may be deposited using chemical vapor deposition (CVD) or physical vapor deposition (PVD) techniques. The CVD process may be plasma-enhanced chemical vapor deposition (PECVD), including ICPECVD, low-pressure chemical vapor deposition (LPCVD), or atomic layer deposition (ALD) with / without plasma. These processes can be tailored to favor negative charge accumulation by altering process parameters (including various flow rate and power parameters), and these processes can include post-film deposition processing steps to increase negative charge. The resulting high-k metal oxide films can have an oxygen-rich composition with negatively charged interstitial oxygen atoms and / or dangling / broken metal oxide bonds, both of which can generate accumulated negative charge.

[0086] The back-illuminated image sensor 200 further includes a color filter layer 205 and a microlens layer 206 disposed on a second side 200b of the substrate 210 (the side facing away from the metal interconnect structure 230). The color filter layer 205 includes a plurality of color filters configured such that incident radiation is directed onto and through it. The color filters comprise dye-based (or pigment-based) polymers or resins for filtering incident radiation of specific wavelength bands, corresponding to a color spectrum (e.g., red, green, blue). A microlens layer 206 with a plurality of microlenses is formed above the color filter layer 205. The microlenses direct and concentrate incident radiation toward specific radiation concentration areas in the image sensor, such as photosensitive areas. The microlenses can be placed in different configurations and have different shapes depending on the refractive index of the material used for the microlenses and their distance from the image sensor surface.

[0087] The back-illuminated image sensor 200 can employ any known back-illuminated image sensor structure and may include various devices of any back-illuminated image sensor known in the art. The improvement of this embodiment lies in the fabrication of pad openings 250 during the fabrication of the back-illuminated image sensor 200. Since the pad openings 250 penetrate the first surface of the substrate 210 from the second surface through a corresponding trench isolation structure 220, and further extend into the ILD layer 231 up to the first metal layer 233a, the entire fabrication process is independent of the manufacturing processes of other devices in the image sensor. Therefore, in the following process description, only the relevant fabrication methods for this part will be described in detail. For the fabrication processes of other devices in the image sensor, please refer to the prior art; they will not be elaborated upon further here.

[0088] Please see Figure 9 The preparation method includes the following steps: S210, providing a substrate 210.

[0089] Please see Figure 10 The substrate 210 is a part of the first structural layer 111 of the composite layer 110 in the stacked structure described in the above embodiments. The substrate 210 can be any material suitable for forming a semiconductor device. In this embodiment, the substrate 210 is configured as a silicon substrate.

[0090] S220, a pad oxide layer 211 and a pad nitride layer 212 are sequentially formed on the first surface of the substrate 210.

[0091] The pad oxide layer 211 serves as a buffer layer to improve the stress between the substrate 210 and the pad nitride layer 212. The pad oxide layer 211 can be configured as a dense silicon oxide material, which can be formed on the first surface of the substrate 210 by known methods such as dry oxidation, wet oxidation or in-situ steam generation (ISSG).

[0092] A pad nitride layer 212 is formed on the first surface of the pad oxide layer 211. The pad nitride layer 212 can be configured as a silicon nitride material. The pad oxide layer 211 can be formed on the first surface of the pad oxide layer 211 by known processes such as low-pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition.

[0093] S230, Prepare isolation trench 221.

[0094] Please see Figure 11 A patterned photoresist layer 213 is formed on the first surface of the pad nitride layer 212. The patterned photoresist layer 213 has a window 213a corresponding to the trench isolation structure 220, which defines the position of the trench isolation structure 220 on the substrate 210.

[0095] Please see Figure 12 Using the patterned photoresist layer 213 as a mask, the pad nitride layer 212, pad oxide layer 211, and substrate 210 located below the patterned photoresist layer 213 are quantitatively removed using any known etching process, such as dry etching and / or wet etching, to obtain an isolation trench 221. The remaining patterned photoresist layer 213 is removed after etching. As shown in the figure, among the several isolation trenches 221, the cross-sectional dimension of the isolation trench 221 corresponding to the pad opening 250 is larger than the cross-sectional dimensions of the other isolation trenches 221. This isolation trench 221 corresponding to the pad opening 250 is the first trench 111a in the above embodiment, and therefore will be described below as the first trench 111a.

[0096] Please see Figure 13 A first hard mask layer 222 is conformally distributed on the surface of the isolation trench 221. The first hard mask layer 222 may be a silicon nitride material layer or a titanium nitride material layer, and may be formed on the bottom and side surfaces of the isolation trench 221 by chemical vapor deposition such as low-pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition.

[0097] S240, Prepare a local stop layer 223.

[0098] Please see Figure 14 to Figure 17 For example, this step includes the following sub-steps: S241. A stop material layer 223a is formed on the first surface of the substrate 210 and in the isolation trench 221, and a second trench 223b is formed on the surface of the stop material layer 223a in the first trench 111a.

[0099] The stop material layer 223a can be formed on the isolation trench 221 and the first side 100a (above the first surface) of the substrate 210 (above the first surface) using chemical vapor deposition, atomic layer deposition, or other suitable processes. According to the silicon substrate 210 provided in this embodiment, the stop material layer 223a is configured as a carbon material layer. The carbon material layer has a significantly different chemical bond energy distribution and crystal structure characteristics from the silicon substrate. This characteristic allows the etching reaction to produce an exponentially decaying chemical reaction rate at the carbon / silicon interface, thereby achieving atomically precise etching termination control while avoiding damage to the microstructure of adjacent material layers. Those skilled in the art should understand that the stop material layer 223a should not be limited to a carbon material layer. When the substrate 210 is of other materials, the stop material layer 223a can be other corresponding materials with different chemical bond energy distributions and crystal structure characteristics from the substrate 210.

[0100] When the cross-sectional dimension of the first trench 111a is larger than that of the other isolation trenches 221, during the deposition of the stop material layer 223a, due to the difference in space capacity, when the other isolation trenches 221 are completely filled, an unfilled area will naturally remain inside the first trench 111a, thereby forming the second trench 223b. In another embodiment, if the size of the first trench 111a matches that of the other isolation trenches 221, the second trench 223b needs to be oriented and etched into the stop material layer 223a within the first trench 111a using photolithography and etching processes.

[0101] S242, Fill the second hard mask layer 224 into the second trench 223b.

[0102] The second hard mask layer 224 employs a material system with a different chemical composition and physical properties than the stop material layer 223a. When the stop material layer 223a is made of carbon, the second hard mask layer 224 can be made of silicon oxide or other suitable materials. The second hard mask layer 224 is preferably made of the same material as the isolation medium, allowing the isolation medium to be deposited directly without removing the second hard mask layer 224. A second hard mask material layer 224a can be formed above the stop material layer 223a using chemical vapor deposition, atomic layer deposition, or other suitable processes. Using the stop material layer 223a as a stop layer, the second hard mask material layer 224a is thinned using a thinning process such as chemical mechanical polishing (CMP) to obtain the second hard mask layer 224 that fills the second trench 223b and is flush with the stop material layer 223a.

[0103] S243. Using the second hard mask layer 224 as a mask, remove excess stop material layer 223a from the surface of substrate 210 and within isolation trench 221, retaining the stop material layer 223a located below the second hard mask layer 224, to form the local stop layer 223. A filling space 225 is formed between the local stop layer 223 and the isolation trench 221, and the filling space 225 is used to fill the isolation medium.

[0104] In this step, the substrate 210 is globally processed using the Blanket Asher ETCH process, with the pad nitride layer 212 and the second hard mask layer 224 on the first surface of the substrate 210 as etching stop layers. By controlling plasma-related parameters, selective removal of the carbon material layer is achieved. The carbon material layer in the area covered by the second hard mask layer 224 is retained to form a local stop layer 223, while the carbon material layer in the unprotected area is completely removed. After etching, a filling space 225 is naturally formed between the local stop layer 223 and the sidewall of the isolation trench 221. This space is designed primarily for filling the isolation medium (such as SiO2 or low-k materials) in subsequent processes to achieve electrical isolation of the device structure. This process eliminates the need for an additional photolithography step, simplifying the process flow and reducing costs.

[0105] When the material of the second hard mask layer 224 is different from that of the isolation medium, after the formation of the local stop layer 223, the second hard mask layer 224 needs to be removed by dry, wet or other suitable removal processes to facilitate the deposition of the isolation medium.

[0106] S250. Fill the isolation trench 221 with an isolation medium to form a trench isolation structure 220.

[0107] Please see Figure 18 In this step, an insulating medium is deposited in the trench using methods such as high-density plasma chemical vapor deposition (HDP-CVD) or high aspect ratio chemical vapor deposition (HARP-CVD). The insulating medium is, for example, an insulating material such as silicon oxide.

[0108] Please see Figure 19 The pad nitride layer 212 on the substrate 210 is removed. In this embodiment, any known process, such as a wet process, can be used to remove the pad nitride layer 212.

[0109] Please see Figure 20 A thinning process is performed on the top of the isolation medium to thin it. This thinning process can employ mechanical polishing techniques, such as chemical mechanical polishing. During mechanical polishing, a sufficient amount of isolation medium can be removed to match the height of the first surface of the isolation medium with the height of the first surface of the substrate 210, resulting in a trench isolation structure 220. The trench isolation structure 220 is used to isolate different semiconductor devices and reduce mutual interference between them.

[0110] S260, a metal interconnect structure 230 is formed on the first surface of the substrate 210.

[0111] Please see Figure 21The metal interconnect structure 230 may include multiple patterned ILD layers 231 and conductive layers that provide interconnections (e.g., wiring) between different doped components, circuits, and inputs / outputs of the image sensor. The metal interconnect structure 230 includes ILD layers 231 and multiple metal layers 233, wherein the first metal layer 233a near the substrate 210 serves as the termination layer 120 in the above embodiment, and the ILD layers 231 located between the first metal layer 233a and the substrate 210 serve as the second structural layer 112 of the composite layer 110 in the above embodiment. The first metal layer 233a, ILD layers 231, substrate 210, and composite dielectric layer 240 constitute the semiconductor stacked structure 100 described in the above embodiment.

[0112] The multilayer metal layer 233 may include contacts 232, vias, and metal wires. The multilayer metal layer 233 may include conductive materials such as aluminum, aluminum / silicon / copper alloys, copper, titanium, titanium nitride, tungsten, polycrystalline silicon, metal silicides, or combinations thereof.

[0113] S270, a composite dielectric layer 240 is formed on the second surface of the substrate 210.

[0114] Please see Figure 22 The composite dielectric layer 240, as another part of the first structural layer 111 in the above embodiments, forms the first structural layer 111 together with the substrate 210. The composite dielectric layer 240 includes a first dielectric layer 241, a high-k dielectric layer 242, and a second dielectric layer 243 sequentially formed on the second surface of the substrate 210. The first dielectric layer 241 and the second dielectric layer 243 may be made of silicon oxide, silicon nitride, or silicon oxynitride. The high-k dielectric layer 242 may be made of aluminum oxide, magnesium oxide, calcium oxide, hafnium oxide, zirconium oxide, yttrium oxide, tantalum oxide, strontium oxide, titanium oxide, lanthanum oxide, barium oxide, or other metal oxides that can form high-k films using existing semiconductor deposition techniques. High-k metal oxides can be deposited using chemical vapor deposition (CVD) or physical vapor deposition (PVD) techniques. The CVD process may include plasma-enhanced chemical vapor deposition (ICPECVD), low-pressure chemical vapor deposition (LPCVD), or atomic layer deposition with / without plasma.

[0115] In an exemplary embodiment, silicon dioxide with a thickness of about 20 Å is first deposited on the second surface of the substrate 210 as a first dielectric layer 241. Then, aluminum oxide with a thickness of about 70 Å and tantalum oxide with a thickness of about 520 Å are sequentially deposited on the first dielectric layer 241 as a high-k dielectric stack. Finally, silicon dioxide with a thickness of about 2000 Å is deposited on the high-k dielectric layer 242 as a second dielectric layer 243.

[0116] In another exemplary embodiment, a silicon dioxide layer with a thickness of about 20 Å is first deposited on the second surface of the substrate 210 as a first dielectric layer 241, then a hafnium oxide layer with a thickness of about 70 Å is sequentially deposited on the first dielectric layer 241 as a high-k dielectric layer 242, and finally a silicon dioxide layer with a thickness of about 2000 Å is deposited on the high-k dielectric layer 242 as a second dielectric layer 243.

[0117] S280, Prepare pad openings 250.

[0118] Please see Figure 23 to Figure 25 For example, the forming process of the pad opening 250 of the back-illuminated image sensor 200 includes the following sub-steps: S281. Perform the first etching process, sequentially etching the composite dielectric layer 240 and the substrate 210 in the direction of the metal layer 233 and stopping at the local stop layer 223.

[0119] In the area of ​​the pad opening 250 of the image sensor, the composite dielectric layer 240 (second dielectric layer 243, high-k dielectric layer 242, and first dielectric layer 241) and part of the substrate 210 are sequentially etched towards the metal layer 233 until the local stop layer 223 is exposed. During the etching process, the etching gas composition, selectivity, and time parameters need to be dynamically adjusted according to the characteristics of each material layer (such as dielectric constant, hardness, etc.) (this is a conventional process, and the specific parameters are not limited). When the local carbon layer at the bottom of the first trench 111a is exposed, it serves as an etching termination marker, precisely controlling the first etching depth to form the first channel 251 with vertical sidewalls.

[0120] S282, Remove the local stop layer 223.

[0121] After the first etching process, the Blanket Asher ETCH process is used to selectively remove the exposed local carbon layer at the bottom of the first via 251. The Asher process, which involves introducing oxygen, ensures that only the carbon layer is removed without damaging the underlying substrate 210 or the sidewall dielectric layer. After the local carbon layer is removed, a clean dielectric layer surface is formed at the bottom of the first via 251, providing a flat substrate for subsequent processes. After the local carbon layer is removed, a sidewall protective layer 251a can be conformally distributed on the side and bottom surfaces of the first via 251. The sidewall protective layer 251a can be formed by CVD or other suitable processes, and can be made of materials such as SiO2, SiCN, or SiCO.

[0122] S283. Perform the second etching process, etching the ILD layer 231 towards the direction of the metal layer 233 and stopping at the first metal layer 233a.

[0123] After the local carbon layer is completely removed, the ILD layer 231 is etched vertically along the first channel 251 as a reference until the first metal layer 233a is exposed. During the etching process, the process parameters need to be adjusted according to the material characteristics of the ILD layer 231 (e.g., using a fluorine-containing gas C4F8 / Ar mixed gas to optimize the selectivity), and the etching depth is monitored in real time through an endpoint detection system (e.g., optical emission spectroscopy, OES). When the surface of the first metal layer 233a is exposed, the etching is stopped immediately, forming a second channel 252 that penetrates the ILD layer 231 and has vertical sidewalls. This ensures precise alignment with the first metal layer 233a. The cross-sectional size of the second channel 252 can be smaller than that of the first channel 251, and the second channel 252 is coaxially connected to the first channel 251. Together, they form a pad opening 250 (deep through-hole) structure with vertical sidewalls.

[0124] Based on this embodiment, the deep via (pad opening 250) fabrication method and image sensor fabrication method of the present invention have the following unexpected technical effects: (i) During the fabrication of the stacked structure, a local stop layer is pre-placed in the corresponding region of the composite layer according to the design location of the deep via and the vertical depth of the first etching. During the first etching, the local stop layer has a high selectivity for etching compared with the surrounding dielectric layer, ensuring that the etching automatically terminates when it reaches the stop layer; the local stop layer can also avoid damage to the lower metal layer or substrate caused by over-etching in traditional processes, thus significantly improving the stability of the device's electrical performance.

[0125] (ii) The local stop layer adopts an embedded design, which is formed locally in the corresponding area of ​​the stacked structure rather than fully matching the stacked structure (the planar geometry of the local stop layer is adapted to the cross-sectional size of the first channel). Compared with the global etching stop layer (the planar geometry matches the planar size of the stacked structure), it has the following advantages: the local stop layer only exists in the key etching area and is removed during the etching process, avoiding wafer warping caused by the internal stress of the material in the global hard mask.

[0126] (III) A local carbon layer is used as a local stop layer. The local carbon layer has an extremely low reaction rate with plasmas containing F (such as CF4, C4F8) or Cl (such as Cl2, BCl3), which can effectively suppress over-etching. The surface of the local carbon layer can react with Cl / F-based plasma to form a carbide passivation layer (such as CCl4, CF4). This layer can further absorb plasma energy, thereby further avoiding the problem of over-etching. The local carbon layer can be completely removed by the Blanket Asher ETCH process. The ashing process is a purely chemical reaction without high-energy ion bombardment, so the physical damage to the already formed shallow trench isolation and ILD layer is minimal.

[0127] (iv) Based on the substrate structure of a back-illuminated image sensor, a low-cost embedding of a local stop layer is achieved by differentiating the geometry of the first trench and the remaining isolation trenches. Specifically, the cross-sectional dimension of the first trench is larger than that of the remaining isolation trenches. During the deposition of the stop material layer, the difference in spatial capacity forms a natural filling boundary. When the remaining isolation trenches are completely filled, the interior of the first trench retains an unfilled area due to its larger space. This area directly forms a second trench for protecting the local stop layer, thus eliminating the need for a separate photolithography step to prepare the second trench. This reduces photolithography and etching processes, lowering manufacturing costs.

[0128] (v) Using a pad nitride layer and a second hard mask layer distributed on the first surface of the substrate as etching stop layers, the substrate is globally processed using the Blanket Asher ETCH process. Selective removal of the carbon material layer is achieved by controlling plasma-related parameters. This allows the carbon material layer in the area covered by the second hard mask layer to be retained to form a local stop layer, while the carbon material layer in the unprotected area is completely removed. After etching, a filling space naturally forms between the local stop layer and the sidewalls of the isolation trench. This space is designed primarily for filling the isolation medium in subsequent processes to achieve electrical isolation of the device structure. This process eliminates the need for additional photolithography technology, simplifying the process flow and reducing manufacturing costs.

[0129] In summary, the deep via fabrication method and the back-illuminated image sensor fabrication method of the present invention can improve device performance, reduce dark current, reduce manufacturing costs, have strong process compatibility, and can be extended to other multilayer stacked structure devices.

[0130] The above embodiments merely illustrate preferred implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention should be determined by the appended claims.

Claims

1. A method for preparing deep through holes, characterized in that, Includes the following steps: A semiconductor stack structure is provided, the semiconductor stack structure including a composite layer and a termination layer, the composite layer including a first structural layer and a second structural layer formed on a first surface of the first structural layer near the termination layer; the first structural layer includes a substrate layer, the second structural layer is configured as an ILD layer, and the termination layer is disposed on the ILD layer; a plurality of trench isolation structures are formed on the substrate layer, and a local stop layer is embedded in the trench isolation structure corresponding to the location of the deep via. The substrate layer is etched towards the termination layer and stops at a local stop layer; Remove the local stop layer, etch the ILD layer towards the termination layer and stop at the termination layer to form the deep via.

2. The method for preparing deep through holes as described in claim 1, characterized in that, The cross-sectional dimensions of the local stop layer are adapted to the cross-sectional dimensions of the deep through hole; and / or The local stop layer is configured as a local carbon layer.

3. The method for preparing deep through holes as described in claim 1, characterized in that: The deep via is configured as a pad opening; the termination layer is configured as a metal layer.

4. The method for preparing deep through holes as described in claim 1, characterized in that, The embedding step of the local stop layer includes: A plurality of isolation trenches are formed on the substrate layer, and the isolation trench corresponding to the location of the deep via is designated as the first trench; A stop material layer is formed on the first surface of the substrate and within the isolation trench, and a second trench is formed on the surface of the stop material layer within the first trench. A second hard mask layer is filled into the second trench; Using the second hard mask layer as a mask, excess stop material layers on the substrate surface and in the isolation trench are removed, leaving the stop material layer below the second hard mask layer to form the local stop layer; a filling space is formed between the local stop layer and the first trench, and the filling space is used to fill the isolation medium; An isolation medium is filled into the isolation trench to form a trench isolation structure.

5. The method for preparing deep through holes as described in claim 4, characterized in that: The second hard mask layer is made of the same material as the isolation medium.

6. The method for preparing a deep through-hole as described in claim 4, characterized in that: A first hard mask layer is conformally distributed on the surface of the first trench.

7. The method for preparing deep through holes as described in claim 4, characterized in that, The cross-sectional dimension of the first trench is larger than the cross-sectional dimension of the other isolation trenches; In the step of forming a stop material layer on the first surface of the substrate layer and in the isolation trench, and forming a second trench on the surface of the stop material layer in the first trench, the second trench is naturally formed during the formation of the stop material layer based on the larger cross-sectional size of the first trench.

8. The method for preparing deep through holes as described in claim 4, characterized in that, The first structural layer further includes a composite dielectric layer formed on the second surface of the substrate layer facing away from the termination layer; the step of etching the substrate layer towards the termination layer and stopping at the local stop layer specifically includes: The first etching process is performed, sequentially etching the composite dielectric layer and the substrate layer towards the termination layer and stopping at the local stop layer.

9. The method for preparing a deep through hole as described in claim 8, characterized in that, The composite dielectric layer includes a first dielectric layer, a second dielectric layer, and a high-k dielectric layer sandwiched therebetween.

10. A method for fabricating a back-illuminated image sensor, characterized in that, This includes the method for preparing deep through holes as described in any one of claims 1 to 9.

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