Electronic device and method of manufacturing the same

Abstract

The present disclosure relates to electronic devices and methods of manufacturing the same. A method for manufacturing an electronic device includes forming a material layer suitable for forming an etched layer over a first substrate, forming a hard mask layer over a second substrate, bonding the first substrate and the second substrate to each other with the material layer and the hard mask layer facing each other, removing the second substrate from an upper portion of the hard mask layer, and forming a pattern of the etched layer by performing an etching process with the hard mask layer serving as an etching stopper.

Description

Cross-references to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2024-0171631, filed on November 27, 2024, which is incorporated herein by reference in its entirety. Technical Field

[0002] The embodiments of this disclosure generally relate to semiconductor technology, and more specifically, to memory circuits or devices and their application in electronic devices. Background Technology

[0003] In recent years, the demand for miniaturization, low power consumption, high performance, and versatility in electronic devices has required semiconductor devices capable of storing data in various electronic devices (such as computers, portable communication devices, etc.), and researchers and industry are working to develop such semiconductor devices. These semiconductor devices include those capable of storing data by utilizing the characteristic of switching between different resistance states according to applied voltage or current, such as resistive random access memory (RRAM), phase-change random access memory (PRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), and electric fuses. Summary of the Invention

[0004] The embodiments of this disclosure aim to address the problem of deterioration in the operational characteristics of electronic devices including magnetic tunnel junction (MTJ) structures or selection elements that may occur when performing high-temperature processes after depositing MTJs or selection elements in the process of manufacturing electronic devices including magnetic tunnel junction (MTJ) structures or selection elements by forming a hard mask layer via a high-temperature process, and to ensure process margin.

[0005] According to one embodiment of the present disclosure, an electronic device includes: an etched layer disposed on a substrate and having a vertical profile; a hard mask pattern disposed on the etched layer; and a bonding layer disposed between the etched layer and the hard mask pattern and including a dielectric material, wherein the hard mask pattern includes a material having etch selectivity relative to the etched layer.

[0006] According to another embodiment of the present disclosure, a method for manufacturing an electronic device includes: forming a material layer suitable for forming an etched layer on a first substrate; forming a hard mask layer on a second substrate; bonding the first substrate and the second substrate to each other such that the material layer and the hard mask layer are opposite to each other; removing the second substrate from the top of the hard mask layer; and forming an etched layer pattern by performing an etching process using the hard mask layer as an etch barrier.

[0007] According to another embodiment of the present disclosure, a method for manufacturing an electronic device includes: forming a material layer suitable for forming a selection element on a third substrate; forming a hard mask layer on a fourth substrate; bonding the third substrate and the fourth substrate to each other such that the material layer and the hard mask layer are opposite to each other; removing the fourth substrate from the top of the hard mask layer; and forming a selection element pattern with a vertical profile by performing an etching process using the hard mask layer as an etch barrier.

[0008] These and other features and advantages of the embodiments disclosed herein will become apparent to those skilled in the art from the following detailed description taken in conjunction with the accompanying drawings. Attached Figure Description

[0009] Figure 1A and Figure 1B This is a cross-sectional view showing an electronic device according to an embodiment of the present disclosure.

[0010] Figures 2A to 2E This is a cross-sectional view illustrating an electronic device and a method of manufacturing the same according to another embodiment of the present disclosure.

[0011] Figures 3A to 3E This is a cross-sectional view showing an electronic device and a method of manufacturing the same according to yet another embodiment of the present disclosure. Detailed Implementation

[0012] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0013] Various embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. However, embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make the present disclosure thorough and complete, and to fully convey the scope of the disclosure to those skilled in the art. Throughout this disclosure, the same reference numerals refer to the same parts in the various drawings and embodiments of the present disclosure.

[0014] The accompanying drawings are not necessarily drawn to scale, and in some cases, the scale may be exaggerated to clearly show the features of the embodiments. When referring to the first layer "on" the second layer or "on" the substrate, it means not only that the first layer is formed directly on the second layer or the substrate, but also that there is a third layer between the first layer and the second layer or the substrate.

[0015] Figure 1A and Figure 1B This is a cross-sectional view showing an electronic device having etched layers (such as a variable resistance layer and a selection element unit SU) according to an embodiment of the present disclosure.

[0016] Reference Figure 1AAfter forming a first interlayer dielectric layer 110 on the substrate 100, a lower contact plug 120 may be formed to extend through the first interlayer dielectric layer 110 to be operatively coupled to a portion of the substrate 100. The lower contact plug 120 may contact the substrate 100. A plurality of lower contact plugs 120 may be formed to be spaced apart from each other.

[0017] Subsequently, a selection element unit SU can be formed on the contact plug 120. The selection element unit SU may include a lower electrode layer 140, a selection element layer 150, and an intermediate electrode layer 160. The lower electrode layer 140 may contact the top surface of the lower contact plug 120. The selection element layer 150 and the intermediate electrode layer 160 may be sequentially disposed on the lower electrode layer 140. Subsequently, a variable resistance element 130 can be formed on the selection element unit SU. The variable resistance element 130 may include a lower layer 131, a free layer 132, a tunnel barrier layer 133, a fixed layer 134, a magnetic compensation layer 135, and a cover layer 136 stacked on the first interlayer dielectric layer 110 and the lower contact plug 120. The selection element unit SU and the variable resistance element 130 may have a vertical profile.

[0018] When layers such as the free layer 132, tunnel barrier layer 133, and fixed layer 134 are precisely patterned and maintain a vertical profile, the performance of the MTJ structure included in the variable resistor element 130 can be optimized. However, to maintain the characteristics of the MTJ structure, only cryogenic processes of about 300°C or lower can be performed, which limits the formation of high-quality ion beam etched (IBE) hard masks HM. This makes it difficult to form MTJ structures with vertical profiles and limits the fabrication of high-density MRAM. According to one embodiment of this disclosure, a method for forming a high-quality hard mask is provided, which is required for IBE etching processes using wafer bonding techniques at high temperatures exceeding about 300°C. Furthermore, by ensuring that the select element cells SU have a vertical profile, space efficiency can be maximized, thereby enabling high-density integrated circuits. In addition, since the select element cells SU are formed with clear and uniform boundaries, leakage current can be minimized. Furthermore, by achieving precise alignment between layers in a multilayer structure, the performance and reliability of the device can be improved. In this way, a method is provided such as Figure 1A The electronic device shown has a selection element unit SU and a memory unit MU with vertical profiles.

[0019] The selection element unit SU may include a lower electrode layer 140, a selection element layer 150, and an intermediate electrode layer 160. The memory unit MU may include an intermediate electrode layer 160, a variable resistor element 130, and an upper electrode layer 170. Therefore, the intermediate electrode layer 160 can be shared by the selection element unit SU and the memory unit MU.

[0020] The lower electrode layer 140 and the upper electrode layer 170 can be respectively disposed at both ends of the memory cell, i.e., the bottom and top of the memory cell MC, and can serve to transmit the voltage or current required for the operation of the memory cell MC. The intermediate electrode layer 160 can serve to electrically connect the select element layer 150 and the variable resistor element 130 to each other and physically separate them. The lower electrode layer 140, the intermediate electrode layer 160, or the upper electrode layer 170 can be formed of various conductive materials, including, for example, metals (such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), tantalum (Ta), titanium (Ti), etc.), metal nitrides (such as titanium nitride (TiN), tantalum nitride (TaN), etc.) and combinations thereof. In addition, the lower electrode layer 140, the intermediate electrode layer 160, or the upper electrode layer 170 may include carbon electrodes.

[0021] According to the substrate bonding and separation processes described below, a bonding layer 180 and a hard mask pattern 190 can be formed on the upper electrode layer 170.

[0022] The selector layer 150 serves to prevent current leakage that may occur between memory cells MC sharing a first or second conductor and to control access to the variable resistor element 130. To this end, the selector layer 150 may have threshold switching characteristics: that is, when the voltage levels supplied to the upper and lower ends of the selector layer 150 are below a predetermined threshold voltage level, current is blocked or current flow is impeded; conversely, at voltage levels equal to or higher than the threshold voltage level, current flows rapidly. The selector layer 150 can be turned on at or above the threshold voltage level and turned off below the threshold voltage level. For example, the selector layer 150 may comprise a dielectric material implanted with dopant.

[0023] A magnetic tunnel junction (MTJ) structure may include a free layer 132 with a variable magnetization direction, a tunnel barrier layer 133 that allows electrons to tunnel according to an applied voltage or current, and a fixed layer 134 with a fixed magnetization direction. The lower layer 131 may be disposed beneath the MTJ structure and helps to efficiently inject spin into the free layer 132, which can improve the switching characteristics of the MTJ structure. The lower layer 131 can help improve the magnetization stability of the free layer 132 and can improve the overall reliability of the structure by enhancing the mechanical and electrical connection between the free layer 132 and the tunnel barrier layer 133. A magnetic compensation layer 135 can counteract or reduce the effects of stray magnetic fields formed by the fixed layer 134. The magnetic compensation layer 135 can enhance the magnetization of the fixed layer 134 to help prevent the magnetization direction of the fixed layer 134 from changing due to external magnetic fields or temperature variations, and can enhance the magnetic anisotropy of the fixed layer 134 so that the fixed layer 134 can maintain a more stable magnetization state. The capping layer 136 serves to protect the layers disposed beneath and below it during the patterning process used to form the variable resistance element 130, and also connects the variable resistance element 130 to the constituent elements above it. For this purpose, the capping layer 136 can be formed of a low-resistance material, such as a metal. The capping layer 136 protects the MTJ structure from external environmental influences to prevent oxidation, thereby maintaining the lifespan and performance of the MTJ structure.

[0024] Reference Figure 1B Based on Figure 1A After the spacer 200 is formed by the process, a second interlayer dielectric layer 210 can be formed on the spacer 200. The spacer 200 can be formed by the following steps: depositing the dielectric layer onto the spacer using a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process. Figure 1A In the process results, an anisotropic etching process is then performed to... Figure 1A The structure has a uniform dielectric layer on its side and top surfaces.

[0025] Subsequently, the upper contact plug 220 can be formed by selectively etching the second interlayer dielectric layer 210, the spacer 200, the hard mask pattern 190, and the bonding layer 180 to form a hole exposing the upper surface of the upper electrode layer 170, and then filling the hole with a conductive material. The spacer 200 may be a thin and narrow dielectric layer formed on the side of the variable resistor element to protect the surface and side of the variable resistor element and prevent damage or contamination during subsequent processes.

[0026] Figures 2A to 2E This is a cross-sectional view illustrating an electronic device and a method of manufacturing the same according to embodiments of the present disclosure.

[0027] First, the manufacturing method will be described.

[0028] Reference Figure 2A A first substrate 200 is provided. The first substrate 200 may include desired predetermined structures, such as, for example, one or more switching elements (not shown). For example, the switching element may be operatively coupled to a variable resistor element described below to control whether current or voltage is supplied to the variable resistor element, and the switching element may include, for example, a transistor, a diode, etc. One end of the switching element may be electrically connected to a lower contact plug 220 described below, and the other end may be electrically connected to an interconnect (e.g., a source line, not shown). The first substrate 200 may be a semiconductor substrate formed of bulk silicon, bulk silicon germanium, or a semiconductor substrate in which a silicon or silicon germanium epitaxial layer is formed on the bulk silicon or bulk silicon germanium. Furthermore, the first substrate 200 may include a semiconductor structure selected from the group consisting of silicon-on-sapphire (SOS), silicon-on-insulator (SOI), thin-film transistors (TFTs), doped and undoped semiconductors, and silicon epitaxial layers supported by a substrate semiconductor.

[0029] Although not shown, the first substrate 200 may include a substrate obtained after predetermined processes, such as forming a well, an isolation layer, a gate, a source / drain, multiple contacts, interconnects, etc. In addition to including driving elements (i.e., peripheral circuit units), the first substrate 200 may also include interconnects.

[0030] Subsequently, a first interlayer dielectric layer 210 is formed on the first substrate 200. Then, a lower contact plug 220 is formed through the first interlayer dielectric layer 210 to electrically connect to a portion of the first substrate 200 (e.g., one end of a switching element). The first interlayer dielectric layer 210 may include various dielectric materials, such as silicon oxide, silicon nitride, or combinations thereof. The lower contact plug 220 may be formed by the following steps: first, selectively etching the first interlayer dielectric layer 210 to form contact holes exposing a portion of the first substrate 200; then, depositing a conductive material of sufficient thickness to fill the contact holes; and performing a planarization process (e.g., chemical mechanical polishing (CMP)) until the upper surface of the first interlayer dielectric layer 210 is exposed. The lower contact plug 220 may include conductive materials with excellent filling properties and high conductivity, such as tungsten (W), tantalum (Ta), or titanium nitride (TiN). Figure 2A As shown, multiple lower contact plugs 220 can be formed simultaneously.

[0031] Subsequently, material layers for forming variable resistance elements, such as lower layer 231, free layer 232, tunnel barrier layer 233, fixed layer 234, magnetic compensation layer 235 and cover layer 236, can be formed on the first interlayer dielectric layer 210 and lower contact plug 220.

[0032] The free layer 232 can store different data by having a variable magnetization direction. The free layer 232 can also be referred to as a storage layer. The fixed layer 234 can be a layer that contrasts with the magnetization direction of the free layer 232 by having a fixed magnetization direction. The fixed layer 234 can also be referred to as a reference layer. The free layer 232 and the fixed layer 234 can have a single-layer structure or a multi-layer structure comprising ferromagnetic materials. For example, the free layer 232 and the fixed layer 234 may comprise alloys primarily comprising Fe, Ni, or Co, such as Fe-Pt alloys, Fe-Pd alloys, Co-Pd alloys, Co-Pt alloys, Fe-Ni-Pt alloys, Co-Fe-Pt alloys, Co-Ni-Pt alloys, Fe-Pd alloys, Co-Pd alloys, Co-Pt alloys, Fe-Ni-Pt alloys, Co-Fe-Pt alloys, Co-Ni-Pt alloys, Co-Fe-B alloys, etc., or the free layer 232 and the fixed layer 234 may comprise a stacked structure such as Co / Pt or Co / Pd. The magnetization directions of the free layer 232 and the fixed layer 234 may be perpendicular to or substantially perpendicular to the layer surfaces. The magnetization direction of the free layer 232 may vary between a top-down direction and a bottom-up direction, while the magnetization direction of the fixed layer 234 may be fixed in a top-down direction or a bottom-up direction. This change in the magnetization direction of the free layer 232 may occur due to spin-transfer torque. The relative positions of the free layer 232 and the fixed layer 234 can vary with the tunnel barrier layer 233 between them. For example, with Figure 2A Unlike other embodiments (not shown), in other embodiments, the fixed layer 234 may be disposed below the tunnel barrier layer 233, while the free layer 232 may be disposed above the tunnel barrier layer 233.

[0033] During a write operation that changes the resistance state of a variable resistive element, the tunnel barrier layer 233 allows electrons to tunnel between the free layer 232 and the stationary layer 234, thereby altering the magnetization direction of the free layer 232. The tunnel barrier layer 233 may include dielectric oxides such as MgO (magnesium oxide), CaO (calcium oxide), SrO (strontium oxide), TiO (titanium oxide), VO (vanadium oxide), NbO (niobium oxide), etc.

[0034] The free layer 232, the tunnel barrier layer 233, and the fixed layer 234 can form an MTJ structure.

[0035] In addition to the MTJ structure, the variable resistor element 230 may also include layers with various uses for improving the characteristics or process of the MTJ structure. For example, such as Figure 2AThe illustrated embodiment may further include a lower layer 231, a magnetic compensation layer 235, and a cover layer 236. However, according to other embodiments of this disclosure, at least one of the lower layer 231 and the magnetic compensation layer 235 may be omitted, or may be further included. Figure 2A Additional layers not shown.

[0036] The lower layer 231 may include any constituent element of a variable resistive element below the MTJ structure, which can improve various characteristics required for the MTJ structure. The lower layer 231 may have a single-layer or multi-layer structure. For example, the lower layer 231 may serve to improve the vertical magnetic anisotropy of the MTJ structure. The lower layer 231 may facilitate the efficient injection of spin into the free layer 232, thereby improving the switching characteristics of the MTJ structure and contributing to increased magnetization stability of the free layer 232. The lower layer 231 may be distinguished from the lower contact plug 220 used for electrically connecting the variable resistive element and the lower constituent elements located below the variable resistive element to each other. According to the embodiments shown in this disclosure, the lower layer 231 may be disposed above the first interlayer dielectric layer 210; however, if desired, in a variation of this embodiment, part or all of the lower layer 231 may be disposed above the lower contact plug 220 and embedded together with the lower contact plug 220 in the first interlayer dielectric layer 210.

[0037] The magnetic compensation layer 235 can counteract or weaken the influence of the stray magnetic field formed by the fixed layer 234. In this case, the influence of the stray magnetic field of the fixed layer 234 on the free layer 232 can be weakened, thereby weakening the deflection magnetic field in the free layer 232. The magnetic compensation layer 235 can have a magnetization direction antiparallel to the magnetization direction of the fixed layer 234. For example, when the fixed layer 234 has a top-down magnetization direction, the magnetic compensation layer 235 can have a bottom-up magnetization direction. Conversely, when the fixed layer 234 has a bottom-up magnetization direction, the magnetic compensation layer 235 can have a top-down magnetization direction. The magnetic compensation layer 235 can enhance the magnetization of the fixed layer 234 to help prevent the magnetization direction of the fixed layer 234 from changing due to external magnetic field or temperature variations, and can enhance the magnetic anisotropy of the fixed layer 234 so that the fixed layer 234 can maintain a more stable magnetization state. The magnetic compensation layer 235 can have a single-layer structure or a multi-layer structure including ferromagnetic materials.

[0038] According to the embodiments shown in this disclosure, the magnetic compensation layer 235 may exist on the fixed layer 234, but the position of the magnetic compensation layer 235 can be modified in various ways. For example, the magnetic compensation layer 235 may be disposed below the MTJ structure. Furthermore, for example, the magnetic compensation layer 235 may be patterned separately from the MTJ structure and disposed above, below, or beside the MTJ structure.

[0039] The capping layer 236 can be used to couple the variable resistive element to the constituent elements above the variable resistive element, and to protect the layer disposed beneath the capping layer 236 during the patterning of the variable resistive element. For this purpose, the capping layer 236 can include a metal as a low-resistivity material. The capping layer 236 can protect the MTJ structure from external environmental influences to prevent oxidation, thereby maintaining the lifetime and performance of the MTJ structure. For example, the capping layer 236 can include a noble metal, such as ruthenium (Ru), having a small number of pinholes in the layer and high resistance to wet and / or dry etching.

[0040] Subsequently, a bonding layer 237 can be formed on the uppermost layer of the first substrate 200 (i.e., on the capping layer 236). The bonding layer 237 can be provided for bonding the first substrate 200 and the second substrate 300, and can include a structure in which heterogeneous layers are stacked. The bonding layer 237 can include, for example, a stacked structure of nitride and oxide layers. The nitride layer can include, for example, a silicon nitride layer, and the oxide layer can include, for example, a silicon oxide layer. The bonding layer 237 can include silicon oxide, a polymer, a metal, or a glass frit. In a particular embodiment, silicon oxide formed by a thermal oxidation process or a chemical deposition process can be used as the bonding layer, and in this case, two substrates in which oxide layers are formed can be brought into contact, and then heat-treated at a high temperature to form chemical bonds. Furthermore, polymeric materials such as, for example, benzocyclobutene (BCB) or epoxy-negative photoresist such as SU-8 can be used as the bonding layer, and polymer bonding can achieve bonding at low temperatures and provide flexible mechanical properties. Furthermore, metal bonding layers such as Au-Au or Cu-Cu bonds can be used, and these metal layers can provide conductivity and can be used for interlayer connections in three-dimensional (3D) integrated circuits. Additionally, bonding layers can be formed using glass frits that exhibit glass-like properties at low temperatures.

[0041] However, according to another embodiment of this disclosure, the bonding layer 237 can be omitted. When the bonding layer 237 is absent, the surfaces of the two substrates can be chemically treated to allow the two substrates to be directly bonded. For example, the two substrates can be bonded using a hydrophobic bonding method, wherein the substrate surfaces are bonded by hydrogen bonds.

[0042] Reference Figure 2B A hard mask layer 340 for patterning the variable resistance element 230 can be formed on the second substrate 300. For example, the hard mask layer 340 may have an island shape to pattern the variable resistance element 230 into a columnar shape. The second substrate 300 may be a substrate obtained after a predetermined process. For example, the second substrate 300 may include a silicon substrate.

[0043] The hard mask layer 340 may include one or more materials selected from the group consisting of polysilicon, metal, silicon-germanium, and carbon. Preferably, the hard mask layer 340 may include at least one material selected from the group consisting of polysilicon and carbon. The hard mask layer 340 may include a material with etching selectivity relative to the etched layers (such as the variable resistor layer and the selection element unit SU). Since the hard mask layer 340 is formed on a second substrate 300 rather than on a first substrate 200 on which the variable resistor element 230 is formed, a highly selective hard mask layer 340 can be formed in an ion beam etching (IBE) process or a reactive ion etching (RIE) process with a high temperature exceeding about 300°C. In the processes described below, when the variable resistor element 230 including the MTJ structure is etched by an IBE or RIE process, the high selectivity of the hard mask layer 340 enables the formation of a variable resistor element 230 with a vertical profile.

[0044] To facilitate separation of the second substrate 300 in subsequent processes, a separation layer 301 can be formed at a predetermined depth within a desired depth of the second substrate 300. The separation layer 301 can be formed by performing a hydrogen ion implantation process at the predetermined depth of the second substrate 300. Materials such as silicon oxide (SiO2) or silicon nitride (Si3N4) can be used as the separation layer 301, and it can be selectively removed by a chemical etching process, allowing the bonded substrates to be separated, leaving only the remaining layer. Polymer materials such as polyimide or SU-8 can be used as the separation layer 301, and they can be easily separated at low temperatures. Alternatively, a low-adhesion tape that can be detached at high temperatures can be used as the separation layer 301, and the adhesive layer can weaken and separate when the bonded substrates are heated at high temperatures. Furthermore, the two substrates can be mechanically separated by inserting a layer with weak mechanical bonding between them without separately providing the separation layer 301, and by applying external force.

[0045] Reference Figure 2CThe first substrate 200 and the second substrate 300 can be bonded to each other using a bonding layer 237 of the first substrate 200 and a hard mask layer 340 of the second substrate 300. The bonding of the first substrate 200 and the second substrate 300 can occur via oxide-to-oxide bonding or van der Waals force bonding. Furthermore, the first substrate 200 and the second substrate 300 can be bonded by the electro-attraction between the two substrates caused by charges retained on the surfaces or by charges generated through plasma treatment. Additionally, bonding can be performed by hydrogen bonds formed on the silicon oxide surfaces of the two substrates, which provide a stronger bond than van der Waals forces. Chemical reactions occurring during the bonding process can also enhance the bonding between the two substrates. For example, in metallic bonding, strong metallic bonds can be formed as metal ions diffuse and chemical reactions occur between metal atoms. The bonding of these two substrates can be performed by high-temperature bonding processes or ultrasonic bonding processes. This can be primarily used for bonding silicon substrates or metal-to-metal bonding by placing the two substrates facing each other and applying high temperatures and pressures to them. Ultrasonic bonding can be a method of bonding two substrates using ultrasonic energy. During ultrasonic bonding, ultrasonic vibrations in the range of approximately 20 kHz to 60 kHz are typically applied between two substrates. This vibration can induce small frictions on the surface of the substrates to form bonds.

[0046] Reference Figure 2D A separation process can be performed on the bonded second substrate 300. This separation process can be performed by grinding, polishing, or etching the upper surface of the second substrate 300. Furthermore, when a separation layer 301 is formed in the second substrate 300 via hydrogen ion implantation, grinding, polishing, or etching processes can be performed until the separation layer is exposed. When the separation layer 301 is applied, anisotropic or isotropic etching processes can be performed after the separation layer 301 is exposed to planarize the remaining second substrate 300.

[0047] The hard mask layer 340 can be exposed on the top layer of the structure obtained after the bonding process of the substrate and the separation process of the second substrate 300 are completed.

[0048] Reference Figure 2EThe variable resistor element 230 can be formed with a vertical profile having a stacked pattern of the lower layer pattern 231A, free layer pattern 232A, tunnel barrier layer pattern 233A, fixed layer pattern 234A, magnetic compensation layer pattern 235A, and capping layer pattern 236A, by etching the capping layer 236A, magnetic compensation layer pattern 232A, tunnel barrier layer pattern 233A, fixed layer pattern 234A, magnetic compensation layer pattern 235A, and capping layer pattern 236A, using the hard mask layer 340 as an etching barrier. Although not shown, a portion of the bonding layer pattern 237A and a portion of the hard mask pattern 340A may remain on the variable resistor element 230. This is likely because the etching load can vary depending on the position of the variable resistor element 230.

[0049] According to existing technology, when a hard mask layer 340 is formed on a variable resistor element 230 on a substrate and the variable resistor element 230 is patterned by an IBE or RIE process, the process may have to be performed at a low temperature of about 300°C or lower to maintain the characteristics of the variable resistor element 230. Therefore, it is difficult to form a hard mask layer with high IBE or RIE selectivity. However, since the variable resistor element 230 and the hard mask layer 340 are formed in a first substrate 200 and a second substrate 300 respectively, and the bonding and separation processes of the first substrate 200 and the second substrate 300 are performed, a hard mask layer 340 with high IBE or RIE selectivity can be formed by a high-temperature process exceeding about 300°C. In the process of manufacturing electronic devices including MTJ structures, by forming the hard mask layer via a high-temperature process exceeding about 300°C, the problem of deterioration in operating characteristics that may occur when performing high-temperature processes after MTJ deposition can be solved, while ensuring process margin.

[0050] The above process can be used to manufacture such as Figure 2E The electronic device shown.

[0051] Return to reference Figure 2E An electronic device according to an embodiment of the present disclosure may include: a lower contact plug 220 disposed on and coupled to a portion of a first substrate 200; a variable resistor element 230 disposed on and coupled to the lower contact plug 220; a remaining bonding layer pattern 237A (not shown); a hard mask pattern 340A (not shown); and a first interlayer dielectric layer 210 surrounding the lower contact plug 220.

[0052] In this electronic device, the variable resistor element 230 can store data by switching between different resistance states based on the voltage or current applied to the upper and lower ends of the variable resistor element 230 via the lower contact plug 220 and the upper contact plug (not shown). For example, data can be stored by changing the magnetization direction of the free layer pattern 232A according to the voltage or current applied to the variable resistor element 230. When the magnetization directions of the free layer pattern 232A and the fixed layer pattern 234A are parallel to each other, the variable resistor element 230 can be in a low resistance state and can store, for example, data "1". Conversely, when the magnetization directions of the free layer pattern 232A and the fixed layer pattern 234A are antiparallel to each other, the variable resistor element 230 can be in a high resistance state and can store, for example, data "0".

[0053] Based on the aforementioned electronic devices and their manufacturing methods, when a variable resistance element and a hard mask layer are formed on a substrate, a variable resistance element with an excellent vertical profile can be achieved, which is difficult to obtain using existing methods. In particular, the hard mask formed through a high-temperature process can provide high selectivity in IBE or RIE processes, enabling the fabrication of high-density magnetic random access memory (MRAM) devices and maintaining the characteristics of the MTJ structure even after patterning processes. This can significantly improve the performance of MRAM devices and the reliability of the manufacturing process.

[0054] The embodiments described above in this disclosure illustrate patterning of a variable resistor element 230 using a bonding and separation process of two substrates. This process can be used for all patterning processes employing IBE (Integrated Beta Embedding) technology, and can be particularly used when patterning selected elements. The following refers to... Figures 3A to 3D The method will be described in detail. The description will focus on the differences from the embodiments described above in this disclosure.

[0055] Reference Figure 3A A first interlayer dielectric layer 410 and a lower contact plug 420 may be formed on the third substrate 400, the lower contact plug 420 passing through the first interlayer dielectric layer 410 to be operatively coupled to a portion of the third substrate 400.

[0056] Subsequently, a lower electrode layer 430 and a select element layer 440 can be formed on the third substrate 400. The lower electrode layer 430 can be formed by depositing a conductive material. The select element layer 440 can be formed by depositing a dielectric material layer on the lower electrode layer 430 and then implanting a dopant into the dielectric material layer. The dopant implantation can be performed, for example, by ion implantation, and can be performed toward the dielectric material layer in a direction perpendicular to or substantially perpendicular to the surface of the third substrate 400. An intermediate electrode layer 450 can be formed on the select element layer 440. The intermediate electrode layer 450 can be formed by depositing a conductive material.

[0057] Reference Figure 3B A hard mask layer 540 can be formed on the fourth substrate 500. This hard mask layer 540 is used to pattern selection element units SU, including the selection element layer 440. To facilitate separation of the fourth substrate 500 in subsequent processes, a separation layer 501 can be formed inside the fourth substrate 500 at a predetermined depth. As described above, a layer with weak mechanical bonds can be inserted between the two substrates without separately providing the separation layer 501, so that the two substrates can be mechanically separated from each other by applying external force.

[0058] Reference Figure 3C The third substrate 400 and the fourth substrate 500 can be bonded together by using the bonding layer 437 of the third substrate 400 and the hard mask layer 540 of the fourth substrate 500.

[0059] Reference Figure 3D Following the bonding process, the separation process of the fourth substrate 500 is completed. The separation process can be performed by grinding, polishing, or etching the upper surface of the fourth substrate 500. Furthermore, when a separation layer 501 is formed in the fourth substrate 500 via hydrogen ion implantation, grinding, polishing, or etching processes can be performed until the separation layer is exposed. When the separation layer 501 is applied, anisotropic or isotropic etching processes can be performed after the separation layer 501 is exposed to planarize the remaining fourth substrate 500.

[0060] The hard mask layer 540 can be exposed in the top layer of the structure obtained after the bonding process of the substrate and the separation process of the fourth substrate 500 are completed.

[0061] Reference Figure 3E By using a hard mask layer 540 as an etching barrier and etching the lower electrode layer 430, the select element layer 440, and the upper electrode layer 450, a structure including a select element with a vertical profile, a remaining bonding layer pattern 437A, and a hard mask pattern 540A can be formed, in which the lower electrode layer pattern 430A, the select element layer pattern 440A, and the upper electrode layer pattern 450A are stacked.

[0062] The above process can be used to manufacture such as Figure 3E The electronic device shown above, and its manufacturing method thereof, enables the realization of selectable elements with excellent vertical profiles, which is difficult to achieve when the selectable elements and hard mask layers are formed on a single substrate. This allows for the realization of high-density integrated circuits by maximizing space efficiency. Furthermore, the selectable elements can be formed with clear and uniform boundaries, minimizing leakage current. Moreover, the method of the present invention allows for precise alignment between layers in a multilayer structure, thereby improving the performance and reliability of various components and the entire device.

[0063] According to embodiments of the present disclosure, a semiconductor device and its manufacturing method can solve the problem of deterioration of operating characteristics that may occur when performing a high-temperature process after MTJ deposition by forming a hard mask layer in another substrate via a high-temperature process, and ensure process margin.

[0064] While embodiments of the present disclosure have been described with reference to specific examples, those skilled in the art will recognize that various changes and modifications can be made without departing from the spirit and scope of the present disclosure as defined by the following claims. Furthermore, embodiments can be combined to form additional embodiments.

Claims

1. An electronic device, comprising: The etched layer is disposed on the substrate; Hard mask pattern, which is formed on the etched layer; as well as A bonding layer pattern is disposed between the etched layer and the hard mask pattern. The bonding layer pattern includes a dielectric material, and The hard mask pattern includes a material that has etching selectivity relative to the etched layer.

2. The electronic device according to claim 1, wherein, The material of the hard mask pattern includes at least one selected from the group consisting of polysilicon, metal, silicon germanium, and carbon.

3. The electronic device according to claim 1, wherein, The material of the hard mask pattern includes at least one selected from the group consisting of polysilicon and carbon.

4. The electronic device according to claim 1, wherein, The etched layer includes: An MTJ structure includes: a free layer having a variable magnetization direction; a fixed layer having a fixed magnetization direction; and a tunnel barrier layer between the free layer and the fixed layer, wherein the MTJ is a magnetic tunnel junction; and A cover layer is disposed on the MTJ structure and includes metal.

5. The electronic device according to claim 4, wherein, The etched layer also includes: A magnetic compensation layer is disposed between the MTJ structure and the cover layer, and counteracts or weakens the influence of stray magnetic fields formed by the fixed layer.

6. The electronic device according to claim 1, further comprising: A dielectric layer suitable for protecting the surface of the etched layer.

7. The electronic device according to claim 1, wherein, The bonding layer pattern includes silicon oxide, polymer, metal, or glass frit.

8. The electronic device according to claim 1, further comprising: Select the element layer, which controls access to the etched layer and has a vertical profile.

9. The electronic device according to claim 1, wherein, The etched layer is a variable resistance layer.

10. A method for manufacturing an electronic device, the method comprising: A material layer suitable for forming the etched layer is formed on the first substrate; A hard mask layer is formed on the second substrate; The first substrate and the second substrate are bonded together with the material layer and the hard mask layer facing each other; Remove the second substrate from the top of the hard mask layer; as well as The etched layer pattern is formed by performing an etching process using the hard mask layer as an etch barrier.

11. The method according to claim 10, wherein, Forming a material layer suitable for forming the etched layer on the first substrate includes: A magnetic tunnel junction (MTJ) structure is formed, comprising: a free layer having a variable magnetization direction; a fixed layer having a fixed magnetization direction; and a tunnel barrier layer situated between the free layer and the fixed layer, wherein the MTJ is a magnetic tunnel junction; and A metal-based overlay is formed on top of the MTJ structure.

12. The method according to claim 10, wherein, The hard mask layer includes a material that has etching selectivity relative to the etched layer pattern.

13. The method according to claim 12, wherein, The hard mask layer includes at least one selected from the group consisting of polysilicon, metal, silicon-germanium, and carbon.

14. The method according to claim 12, wherein, The hard mask layer includes at least one selected from the group consisting of polysilicon and carbon.

15. The method according to claim 10, wherein, The etching process includes ion beam etching (IBE) or reactive ion etching (RIE).

16. The method of claim 10, wherein, Bonding the first substrate and the second substrate includes a high-temperature bonding process or an ultrasonic bonding process.

17. The method of claim 10, further comprising: After the etching process used to form the etched layer pattern, a dielectric layer suitable for protecting the surface of the etched layer is formed.

18. The method according to claim 17, wherein, The dielectric layer is formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD) processes.

19. The method according to claim 10, wherein, The etched layer is a variable resistance layer.

20. A method for manufacturing an electronic device, the method comprising: A material layer suitable for forming a selection element is formed on a third substrate; A hard mask layer is formed on the fourth substrate; The third substrate and the fourth substrate are bonded to each other with the material layer and the hard mask layer facing each other; Remove the fourth substrate from the top of the hard mask layer; as well as A pattern of selectable elements with a vertical profile is formed by performing an etching process using the hard mask layer as an etch barrier.

21. The method according to claim 20, wherein, The etching process includes ion beam etching (IBE) or reactive ion etching (RIE).

22. The method according to claim 20, wherein, Bonding the third substrate and the fourth substrate includes a high-temperature bonding process or an ultrasonic bonding process.

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