Chip package pin

Abstract

The application discloses a chip packaging pin, which comprises a pin body, the pin body comprising a base material, a solder pad arranged on the base material, and an electroplated coating arranged on the surface of the solder pad; the pin body has two opposite end faces, and the two end faces are both provided with a first step structure; and the contact surface between the solder pad and the electroplated coating is provided with a second step structure. The chip packaging pin has the advantages that the first step structure is arranged on the two end faces of the pin body, the second step structure is arranged on the contact surface between the solder pad and the electroplated coating, the two step structures work in cooperation, the mechanical strength of the pin against deformation and peeling is improved while the integrity of high-speed signals is greatly improved, the contradiction between the extreme electrical performance and the physical reliability, which is difficult to be considered in the prior art, is preferentially solved, and the strict transmission requirement of super-high-speed signals such as PCIe Gen7 is met.

Description

Technical Field

[0001] This invention relates to the field of chip packaging technology, and more particularly to a chip packaging pin. Background Technology

[0002] With the rapid development of integrated circuits and information communication technologies, the data processing and communication capabilities of chips are constantly improving, which in turn places extremely high demands on chip packaging technology. Currently, high-speed serial computer expansion bus standards (such as the PCIe standard) are accelerating their evolution towards higher frequency bands.

[0003] Taking PCIe Gen7 as an example, its signal transmission rate reaches 128 GT / s or even higher. In such extreme high-frequency and high-speed application scenarios, chip package pins are no longer just simple physical connection media; their electrical performance directly determines the signal integrity (SI) of the entire package link and even the entire chip system. However, existing traditional chip package pin designs typically use regular cylindrical or pure rectangular structures. This traditional design exposes the following significant defects when dealing with the ultra-high-speed signals at PCIe Gen7 levels: Firstly, in terms of electrical performance, due to the edge effect and skin effect present in ultra-high frequency signal transmission, traditional rectangular or flat, straight pin structures result in extremely uneven current distribution within the pins. This current accumulation and uneven distribution generate large parasitic inductance and capacitance, which can easily cause signal attenuation, signal reflection, and crosstalk between adjacent pins, leading to extremely poor impedance matching in the transmission link and making it impossible to guarantee lossless transmission of high-speed signals.

[0004] Secondly, in terms of mechanical reliability, traditional flat-structured package pins lack adequate mechanical strength due to the lack of reasonable stress buffering and dispersion mechanisms. Under long-term operation of the equipment, accompanied by thermal stress cycles (thermal expansion and contraction) or in external mechanical vibration environments, stress concentration is prone to occur at the pin interface (especially between the pad and the coating, and at the pin connection points), which in turn leads to frequent pin deformation, coating peeling, or complete breakage, seriously affecting the long-term service life of the chip product.

[0005] To alleviate these problems, existing conventional solutions mostly involve external measures, such as adding an extra shielding layer around the package structure or shortening the physical length of the pins within the limits of layout allowance. However, adding a shielding layer significantly changes the package size and increases manufacturing costs; simply shortening the pin length greatly encroaches on wiring space and reduces the flexibility of package design. Traditional methods are all stopgap measures and cannot simultaneously achieve excellent electrical performance (low parasitic parameters, high parasitic matching) and robust mechanical reliability in the pin structure itself.

[0006] Therefore, there is an urgent need in this field for a novel chip packaging pin structure. Summary of the Invention

[0007] The purpose of this invention is to provide a chip package pin that can balance signal transmission quality and physical and mechanical strength.

[0008] To achieve the above objectives, the present invention provides a chip package pin, which includes a pin body, the pin body including a substrate, a pad disposed on the substrate, and an electroplated coating disposed on the surface of the pad; The pin body has two opposing end faces, each of which is provided with a first stepped structure; the contact surface between the pad and the electroplated coating has a second stepped structure.

[0009] Preferably, the first stepped structure and / or the second stepped structure includes at least two steps.

[0010] Preferably, the pin body has at least two chamfered, arc-shaped corners.

[0011] Preferably, the substrate is a modified polyimide substrate.

[0012] Preferably, the dielectric constant of the substrate is less than or equal to 3.2.

[0013] Preferably, the pad is a copper pad.

[0014] Preferably, the electroplated coating is a nano-silver layer.

[0015] Preferably, the thickness of the electroplated coating is 0.5 μm to 1 μm.

[0016] Compared to existing technologies, the chip package pins provided by the above technical solution, through the setting of a first-step structure on both ends of the pin body, avoid concentrated current distribution and effectively reduce the parasitic inductance of the pins, thereby improving impedance matching for high-speed signal transmission and reducing signal reflection and crosstalk. Simultaneously, the setting of a second-step structure on the contact surface between the pad and the electroplated coating not only optimizes the high-frequency current conduction path in the thickness direction but also significantly increases the three-dimensional bonding area between the interfaces and effectively disperses thermal and mechanical stress. Furthermore, the synergistic effect of these two step designs significantly improves high-speed signal integrity while enhancing the pin's resistance to deformation and peeling, thus prioritizing the resolution of the contradiction between extreme electrical performance and physical reliability that existing technologies struggle to balance, meeting the stringent transmission requirements of ultra-high-speed signals such as PCIe Gen7. Attached Figure Description

[0017] Figure 1 This is a planar structural diagram of the chip package pins in an embodiment of the present invention.

[0018] Figure 2 This is a cross-sectional view of the chip package pins along the thickness direction in an embodiment of the present invention. Detailed Implementation

[0019] To illustrate the technical content, structural features, objectives, and effects of the present invention in detail, the following description is provided in conjunction with the embodiments and accompanying drawings.

[0020] This embodiment discloses a chip package pin that combines optimized high-frequency electrical performance with high mechanical strength.

[0021] like Figure 1 and Figure 2 The chip package includes a pin body 100. The pin body 100 is not made of a single material, but is a multi-layer heterogeneous composite structure, specifically including: a substrate 10, pads 11 disposed on the substrate 10, and an electroplated coating 12 disposed on the surface of the pads 11. Typically, the substrate 10 serves as an insulating and structural support layer, the pads 11 serve as a first conductive medium layer, and the electroplated coating 12 serves as a surface contact and anti-oxidation layer.

[0022] To address the issue of excessively large parasitic parameters in traditional rectangular pins under extremely high frequency signals, this embodiment makes two improvements to the pin's external structure: Firstly, in the spatial end-face direction, the pin body 100 has two opposing end faces, and a first stepped structure 13 is provided on both end faces. Due to the presence of the first stepped structure 13, the pin body 100 forms a stepped change in cross-sectional area or width in its horizontal extension direction.

[0023] Secondly, in the thickness direction (i.e., the stacking direction of each film layer), the contact surface between the pad 11 and the electroplated coating 12 has a second stepped structure 14. That is, the surface of the pad 11 is not flat, but has a stepped unevenness, so that the electroplated coating 12 covering it will have a stepped interface.

[0024] During ultra-high frequency signal transmission such as PCIe Gen7, the skin effect of high-frequency current is severe, and the current easily concentrates at the edge of the pin, causing a sharp increase in the local magnetic field strength and generating a large parasitic inductance. This embodiment introduces a first stepped structure 13 in the end face direction of the pin body 100, breaking the traditional uniform straight edge current path and changing the concentrated distribution characteristics of the current, so that it is dispersed and conducted inside the pin body 100, effectively reducing the parasitic inductance caused by uneven current distribution.

[0025] Meanwhile, the second-step structure 14 further increases the three-dimensional interlocking area between the pad 11 and the electroplated coating 12 in the thickness direction. This staggered contact surface not only provides a more stable electrical conduction impedance (which is beneficial for high-speed signal impedance matching), but also significantly improves the bonding force between the coating and the pad 11 interface in terms of mechanical principle. It can effectively disperse the interface shear stress caused by thermal expansion and contraction and external vibration, thereby effectively preventing the peeling and deformation of the internal film layer of the pin body 100.

[0026] The aforementioned bidirectional stepped structure, from the perspective of physical structure, takes into account both the requirements of high-frequency signal integrity and pin vibration resistance.

[0027] It should also be noted that the high-speed signal transmission environment (such as PCIe Gen7, with a transmission rate of 128 GT / s and above) used in this embodiment is only an application scenario listed to demonstrate the beneficial effects of the technical solution of this application, and does not constitute a limitation on the specific usage environment of the chip package pins of this invention.

[0028] Optionally, the first step structure 13 and / or the second step structure 14 include at least two steps. For example, in a specific example, three steps are provided at the contact surface between the pad 11 and the electroplated coating 12, so that the thickness profile from the substrate 10 to the outer surface of the coating presents a "V"-shaped step transition from low to high and then from high to low.

[0029] On the other hand, the pin body 100 has at least two chamfered, arc-shaped corners 15.

[0030] Sharp right angles or single right-angle steps are prone to causing severe charge accumulation (i.e., tip discharge effect) electromagnetically, leading to increased parasitic capacitance. Multi-stage steps (at least two stages) make the transition smoother; and the rounded chamfer at corner 15 further eliminates sharp edges on the pin's physical profile. This not only further suppresses charge accumulation at extremely high frequencies and smooths signal transmission, but also completely eliminates points of mechanical stress concentration, further preventing breakage of the pin body 100 under long-term vibration. Simulation experiments show that the multi-stage step combined with the rounded chamfer design reduces the parasitic inductance of the pin body 100 by 20%-30%.

[0031] On the other hand, the following selection is made for the composite material of the pin body 100: (1) The substrate 10 is made of modified polyimide. In some embodiments, in order to strictly control signal transmission loss, the dielectric constant of the modified polyimide substrate 10 is configured to be less than or equal to 3.2 (the dielectric constant of conventional Fr4 substrate 10 is generally greater than 4.0).

[0032] (2) The pads 11 provided on the substrate 10 are copper pads 11 (Cu pads 11), serving as the main metal conductors in the interconnect design.

[0033] (3) The electroplated coating 12 on the surface of the copper pad 11 is a nano-silver layer, used to replace the traditional gold (Au) surface treatment layer. Optionally, the thickness of the electroplated coating 12 (nano-silver layer) is controlled in the range of 0.5 μm to 1 μm. For example, 0.8 μm can be selected.

[0034] In ultra-high frequency transmission, dielectric polarization loss is a significant factor leading to parasitic capacitance and signal attenuation. If the dielectric constant of the substrate 10 is too high, it will result in excessively high inter-pin coupling capacitance, exacerbating signal crosstalk. This embodiment employs a modified polyimide with a low dielectric constant (≤3.2) combined with a highly conductive nano-silver layer, effectively reducing the polarization effect within the insulating medium from a materials science perspective, thereby reducing dielectric loss.

[0035] Furthermore, the silver nanolayer with a thickness controlled between 0.5 μm and 1 μm ensures sufficient coverage of the copper pad 11 with the second-step structure 14, improving overall conductivity and preventing oxidation; it also avoids the cost surge caused by excessive coating thickness or the self-brittleness caused by excessive hardness. Based on the above-mentioned joint optimization of low-dielectric materials and silver nanolayer conductive layers, the capacitance of the chip package pins can be reduced by 15%-25%.

[0036] In summary, this invention discloses a chip packaging pin, comprising: a modified polyimide substrate 10 with a dielectric constant of 3.0, copper pads 11, and a 0.6 μm thick nano-silver layer (electroplated coating 12). Its molding process can be summarized as follows: On both ends of the modified polyimide substrate 10, a first stepped structure 13 with two-stage descending steps is processed by laser cutting or etching; at the same time, the cutting edges are treated with arc chamfering. Copper is deposited on the surface of the substrate 10 and patterned to form a copper pad 11 with a high and low undulating morphology, so that a second stepped structure 14 with two steps is formed on the surface of the copper pad 11. A nano-silver layer is deposited on the stepped surface of the copper pad 11 by electroplating. The nano-silver layer covers the surface of the copper pad 11 in a conformal manner, and finally forms a complete pin body 100.

[0037] The package pins can effectively maintain impedance matching under high-speed signal impact of 128 GT / s, avoid signal reflection, and maintain the long-term stability of the connection structure under complex vibration and thermal stress conditions.

[0038] The above-disclosed embodiments are merely preferred embodiments of the present invention and should not be construed as limiting the scope of the present invention. Therefore, any equivalent variations made in accordance with the claims of the present invention are still within the scope of the present invention.

Claims

1. A chip package pin, characterized in that, It includes a pin body, the pin body comprising a substrate, a pad disposed on the substrate, and an electroplated coating disposed on the surface of the pad; The pin body has two opposing end faces, each of which is provided with a first stepped structure; the contact surface between the pad and the electroplated coating has a second stepped structure.

2. The chip package pins according to claim 1, characterized in that, The first stepped structure and / or the second stepped structure include at least two steps.

3. The chip package pins according to claim 1, characterized in that, The pin body has at least two chamfered, arc-shaped corners.

4. The chip package pins according to claim 1, characterized in that, The substrate is a modified polyimide substrate.

5. The chip package pins according to claim 4, characterized in that, The dielectric constant of the substrate is less than or equal to 3.

2.

6. The chip package pins according to claim 1, characterized in that, The solder pad is a copper pad.

7. The chip package pins according to claim 1, characterized in that, The electroplated coating is a nano-silver layer.

8. The chip package pins according to claim 7, characterized in that, The thickness of the electroplated coating is 0.5 μm to 1 μm.

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