A topography-aware OPC method, apparatus, device and storage medium
By identifying sensitive graphics in shape-aware OPC and using smaller DML partitions for TOPC processing, the circuit performance bottleneck in the traditional OPC process is solved, achieving efficient circuit performance improvement within a short design cycle.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HUAXINCHENG (HANGZHOU) TECH CO LTD
- Filing Date
- 2026-05-06
- Publication Date
- 2026-06-02
AI Technical Summary
In the existing technology, the traditional shape-aware OPC process, in pursuit of minimizing geometric errors, results in unsatisfactory circuit performance and prolongs the mask design cycle, making it difficult to achieve both high computational efficiency and high circuit performance within a short design cycle.
By acquiring design intent data, sensitive graphics are identified and TOPC processing is performed on them using DML partitions of different sizes. The DML partition size of sensitive graphics is smaller than that of non-sensitive graphics, optimizing the allocation of computing resources to graphics that have the greatest impact on circuit performance, thereby improving critical path timing and clock stability.
Without significantly increasing the mask design cycle and computation time, it improved circuit performance, optimized chip performance, and saved computing resources and mask manufacturing budget.
Smart Images
Figure CN122131540A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit manufacturing, and in particular to a shape-sensing OPC method, apparatus, device, and storage medium. Background Technology
[0002] At advanced process nodes, manufacturing process variations have an increasingly significant impact on circuit performance. To minimize these variations, existing technologies often employ Topology-Aware Process Control (TOPC) for correction, which plays a crucial role in improving lithography fidelity and chip yield. However, traditional OPC / TOPC processes primarily aim to minimize the geometric errors of all patterns (such as edge placement errors). A one-sided focus on reducing geometric errors may lead to a final correction result that contradicts the circuit design's performance objectives, resulting in unsatisfactory circuit performance.
[0003] In other words, the traditional shape-aware OPC process uses a single geometry-driven correction strategy for all patterns in the chip layout, resulting in a bottleneck in circuit performance. To further improve circuit performance in the current technology, the only option is to extend the computation time of shape-aware OPC, which greatly extends the mask design cycle and slows down production efficiency.
[0004] Therefore, how to improve circuit performance while ensuring a shorter mask design cycle and higher topography-sensing OPC efficiency is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention
[0005] The purpose of this invention is to provide a shape-aware OPC method, apparatus, device, and storage medium to solve the problem that short design cycle, high computational efficiency, and high circuit performance cannot be achieved simultaneously in the prior art.
[0006] To solve the above-mentioned technical problems, the present invention provides a shape-aware OPC method, comprising:
[0007] Obtain design intent data and layout to be processed;
[0008] Based on the design intent data, the sensitive graphics in the layout to be processed are determined;
[0009] TOPC processing is performed on the sensitive and non-sensitive graphics using DML partitions of different sizes to obtain TOPC mask correction data; the DML partition size of the sensitive graphics is smaller than the DML partition size of the non-sensitive graphics.
[0010] Optionally, in the aforementioned shape-aware OPC method, the sensitive pattern is at least one of a time-sensitive pattern, a current density-sensitive pattern, and a voltage drop-sensitive pattern.
[0011] Optionally, in the shape-aware OPC method, the convergence criterion for edge placement error of the sensitive graphic is more stringent than that for the edge placement error of the non-sensitive graphic.
[0012] Optionally, in the aforementioned shape-aware OPC method, after acquiring the design intent data and the layout to be processed, the method further includes:
[0013] Based on the design intent data, matching device pattern pairs are determined in the layout to be processed; each matching device pattern pair includes multiple matching device patterns.
[0014] All matching device graphics in a single matching device graphic pair are assigned the same DML configuration.
[0015] Optionally, in the aforementioned shape-aware OPC method, after acquiring the design intent data and the layout to be processed, the method further includes:
[0016] Based on the design intent data, a rough graphic in the layout to be processed is determined;
[0017] Accordingly, TOPC processing is performed on the sensitive and non-sensitive graphics using DML partitions of different sizes to obtain TOPC mask correction data, including:
[0018] The rough graphics are subjected to planar OPC processing, and the non-rough graphics are subjected to TOPC processing; wherein, the size of the DML partition used in the TOPC processing of the sensitive graphics is smaller than the size of the DML partition used in the TOPC processing of the non-sensitive graphics, thus obtaining TOPC mask correction data.
[0019] Optionally, in the aforementioned shape-aware OPC method, the roughness pattern is at least one of a ground line pattern and a filled metal pattern.
[0020] A shape-sensing OPC device, comprising:
[0021] The acquisition module is used to acquire design intent data and layouts to be processed;
[0022] The graphic determination module is used to determine the sensitive graphics in the layout to be processed based on the design intent data;
[0023] The TOPC processing module is used to perform TOPC processing on the sensitive and non-sensitive graphics using DML partitions of different sizes to obtain TOPC mask correction data; the DML partition size of the sensitive graphics is smaller than the DML partition size of the non-sensitive graphics.
[0024] Optionally, in the aforementioned shape-sensing OPC device, the acquisition module further includes:
[0025] A matching graphic unit is used to determine matching device graphic pairs in the layout to be processed based on the design intent data; the matching device graphic pair includes multiple matching device graphics.
[0026] A matching synchronization unit is used to assign the same DML configuration to all matching device patterns in a single matching device pattern pair.
[0027] A shape-sensing OPC device, comprising:
[0028] Memory, used to store computer programs;
[0029] A processor, configured to implement the steps of any of the above-described shape-aware OPC methods when executing the computer program.
[0030] A computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of any of the above-described shape-aware OPC methods.
[0031] The shape-aware OPC method provided by this invention acquires design intent data and a layout to be processed; determines sensitive graphics in the layout to be processed based on the design intent data; performs TOPC processing on the sensitive graphics and non-sensitive graphics using DML partitions of different sizes to obtain TOPC mask correction data; the DML partition size of the sensitive graphics is smaller than the DML partition size of the non-sensitive graphics.
[0032] This invention takes into account the critical differences in the impact of different patterns on circuit performance (such as timing, functionality, and yield). It allocates smaller DML partitions to sensitive patterns that affect circuit performance, utilizing more OPC computation time to cover a wider process window. This allows optimized computing power and mask budget to be precisely invested in the sensitive patterns that have the greatest impact on performance, achieving optimal critical path timing and clock stability, directly increasing the upper limit of chip performance. This avoids the significant consumption of limited computing resources and mask manufacturing budget on non-sensitive patterns with minimal performance impact. Without significantly increasing the mask design cycle or slowing down the efficiency of shape-aware OPC, it improves circuit performance indicators. This invention also provides a shape-aware OPC device, apparatus, and storage medium with the above-mentioned beneficial effects. Attached Figure Description
[0033] To more clearly illustrate the technical solutions of the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0034] Figure 1 A flowchart illustrating a specific implementation of the shape-sensing OPC method provided by the present invention;
[0035] Figure 2 This is a schematic diagram of a specific embodiment of the shape-sensing OPC device provided by the present invention.
[0036] Figure label:
[0037] 100 - Acquisition module; 200 - Graphics determination module; 300 - TOPC processing module. Detailed Implementation
[0038] To enable those skilled in the art to better understand the present invention, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0039] The core of this invention is to provide a shape-aware OPC method, the flowchart of one specific implementation of which is shown below. Figure 1 As shown, this is referred to as Specific Implementation Method One, which includes:
[0040] S101: Obtain design intent data and layout to be processed.
[0041] The design intent data includes graphic information of key components of the circuit corresponding to the layout to be processed on the layout to be processed. Of course, the key components can be determined by preset rules or manually by staff. This invention does not limit this.
[0042] S102: Based on the design intent data, determine the sensitive graphics in the layout to be processed.
[0043] In this step, the sensitive graphics in the plot to be processed are marked. The sensitive graphics are those that require special attention to the imaging effect.
[0044] S103: Perform TOPC processing on the sensitive and non-sensitive graphics using DML partitions of different sizes to obtain TOPC mask correction data; the DML partition size of the sensitive graphics is smaller than the DML partition size of the non-sensitive graphics.
[0045] In this step, a smaller DML (mask data layer) partition is used to perform TOPC (topography-aware optical proximity correction) correction on the sensitive pattern. The smaller DML partition can bring more refined correction, specifically a larger k value (Rayleigh constant), a wider process window, and other beneficial effects. Of course, the simulation time consumed by the sensitive pattern will also be slightly extended.
[0046] In one specific implementation, the sensitive pattern is at least one of a timing-sensitive pattern, a current density-sensitive pattern, and a voltage drop-sensitive pattern. The timing-sensitive pattern corresponds to timing-critical path interconnects, clock lines, etc., in the circuit; the current density-sensitive pattern corresponds to devices with high current density in the circuit; and the voltage drop-sensitive pattern corresponds to sensitive devices in the circuit that are prone to generating large voltage drops.
[0047] This specific embodiment provides sensitive patterns corresponding to three key circuit components. Setting the patterns corresponding to these three components as sensitive patterns can greatly improve the electrical performance of the circuit after TOPC. Of course, it is not limited to the above three sensitive patterns, and can be extended to signal integrity (such as crosstalk noise), power integrity (such as IR-Drop), or specific functional hotspots. This invention does not impose any limitations on these aspects.
[0048] Furthermore, the convergence criterion for the edge placement error of the sensitive graphic is more stringent than that for the edge placement error of the non-sensitive graphic. In this specific embodiment, compared with other non-sensitive graphics, the convergence criterion for the edge placement error of the sensitive graphic is set more strictly. By increasing the amount of computation, the setting accuracy of the sensitive graphic is improved, thereby ensuring the performance of the devices in the circuit.
[0049] As a preferred embodiment, after acquiring the design intent data and the layout to be processed, the method further includes:
[0050] A1: Based on the design intent data, determine the matching device pattern pairs in the layout to be processed; the matching device pattern pairs include multiple matching device patterns.
[0051] The matching device pattern pair is the pattern corresponding to the matching device in the layout of the analog / RF circuit.
[0052] A2: Assign the same DML configuration to all matching device graphics in a single matching device graphic pair.
[0053] It is readily apparent that steps A1 and A2 in this specific embodiment do not have a fixed sequential relationship with steps S102 and S103 mentioned earlier, and can be adjusted according to actual needs. In this preferred embodiment, the same DML configuration is forcibly assigned to matched devices or interconnects to ensure that they are corrected under a completely consistent process variation model, thereby maintaining a high degree of characteristic consistency in back-end manufacturing and significantly improving the accuracy, gain, and offset voltage of matched devices in analog circuits.
[0054] In addition, after obtaining the design intent data and the layout to be processed, the following steps are also included:
[0055] B1: Based on the design intent data, determine the rough graphics in the layout to be processed.
[0056] The coarse pattern can be considered the opposite of the sensitive pattern, and is the pattern in the layout corresponding to a device that has no impact on circuit performance or has a very small impact that can be ignored in actual use.
[0057] Specifically, the coarse pattern is at least one of a ground plane pattern and a fill metal pattern. The shape comparison between the ground plane pattern and the fill metal pattern and the layout does not need to be too strict, and they have little impact on circuit performance; therefore, they can be directly classified as coarse patterns, thereby reducing the computational load required for TOPC.
[0058] Accordingly, TOPC processing is performed on the sensitive and non-sensitive graphics using DML partitions of different sizes to obtain TOPC mask correction data, including:
[0059] B2: Perform planar OPC processing on the rough graphics and TOPC processing on the non-rough graphics; wherein, the size of the DML partition used in the TOPC processing of the sensitive graphics is smaller than the size of the DML partition used in the TOPC processing of the non-sensitive graphics, to obtain TOPC mask correction data.
[0060] In this specific embodiment, a new category of rough graphics is added. For rough graphics corresponding to devices whose performance is not significantly affected, this embodiment bypasses TOPC and instead uses planar OPC for simulation, greatly saving system resources. That is, this embodiment adopts a significantly simplified correction strategy for performance-insensitive areas (i.e., the rough graphics), which can greatly reduce OPC runtime and compress mask data volume, effectively reducing development and manufacturing costs.
[0061] Of course, in addition to the sensitive graphics and the coarse graphics, there may be many unclassified graphics in the layout to be processed. These graphics can be processed using standard, chip-wide DML partitioning and TOPC correction processes, or non-sensitive graphics and non-coarse graphics can be processed in batches. Then, the correction level information corresponding to each batch processing graphic is determined according to the design intent data. Finally, the preset correction strategy corresponding to the correction level information is called according to the correction level information to drive the TOPC engine to perform differentiated simulation processing.
[0062] Furthermore, the correction level is determined by continuously optimizing the intensity coefficient, thereby achieving smoother and more refined resource allocation.
[0063] Furthermore, differentiated simulation processing can be achieved by modifying the OPC rule file, that is, predefining different DML configurations and correction parameters for graphics with different attributes (such as layers and graphic labels) in the layout, without changing the architecture of the core OPC engine.
[0064] As another preferred embodiment, the present invention can modify the objective function of OPC optimization from the traditional "minimize total edge placement error" to an indicator directly linked to circuit performance, such as "minimize the variance of timing relaxation" or "minimize the total running time while meeting the preset timing target", thereby shifting the optimization objective of OPC from geometric precision (EPE) to circuit performance indicators (such as timing relaxation), and achieving the optimization of circuit performance.
[0065] The shape-aware OPC method provided by this invention acquires design intent data and a layout to be processed; based on the design intent data, it identifies sensitive patterns in the layout to be processed; and it performs TOPC processing on the sensitive and non-sensitive patterns using DML partitions of different sizes to obtain TOPC mask correction data; the DML partition size of the sensitive pattern is smaller than that of the non-sensitive pattern. This invention considers the critical differences in the impact of different patterns on circuit performance (such as timing, functionality, and yield), assigning smaller DML partitions to sensitive patterns that affect circuit performance. It utilizes more OPC computation time to cover a wider process window, precisely allocating optimized computing power and mask budget to the sensitive patterns that have the greatest impact on performance. This optimizes critical path timing, clock stability, etc., directly improving the upper limit of chip performance. It avoids the large-scale consumption of limited computing resources and mask manufacturing budget on non-sensitive patterns with minimal impact on performance, improving circuit performance indicators without significantly increasing the mask design cycle or slowing down the efficiency of shape-aware OPC.
[0066] The following describes the shape-sensing OPC device provided in the embodiments of the present invention. The shape-sensing OPC device described below and the shape-sensing OPC method described above can be referred to in correspondence.
[0067] Figure 2 The structural block diagram of the shape-sensing OPC device provided in this embodiment of the invention is referred to as Specific Embodiment Two, and is described below. Figure 2 Shape-sensing OPC devices may include:
[0068] Module 100 is used to acquire design intent data and layout to be processed.
[0069] The graphic determination module 200 is used to determine the sensitive graphics in the layout to be processed based on the design intent data;
[0070] TOPC processing module 300 is used to perform TOPC processing on the sensitive and non-sensitive graphics using DML partitions of different sizes to obtain TOPC mask correction data; the DML partition size of the sensitive graphics is smaller than the DML partition size of the non-sensitive graphics.
[0071] In one specific implementation, the acquisition module 100 further includes:
[0072] A matching graphic unit is used to determine matching device graphic pairs in the layout to be processed based on the design intent data; the matching device graphic pair includes multiple matching device graphics.
[0073] A matching synchronization unit is used to assign the same DML configuration to all matching device patterns in a single matching device pattern pair.
[0074] In one specific implementation, the acquisition module 100 further includes:
[0075] A rough determination unit is used to determine a rough graphic in the layout to be processed based on the design intent data;
[0076] Accordingly, the TOPC processing module 300 includes:
[0077] The roughening unit is used to perform planar OPC processing on the roughened graphics and TOPC processing on the non-roughened graphics; wherein, the size of the DML partition used in the TOPC processing of the sensitive graphics is smaller than the size of the DML partition used in the TOPC processing of the non-sensitive graphics, so as to obtain TOPC mask correction data.
[0078] The shape-aware OPC method provided by this invention includes: an acquisition module 100 for acquiring design intent data and a layout to be processed; a graphic determination module 200 for determining sensitive graphics in the layout to be processed based on the design intent data; and a TOPC processing module 300 for performing TOPC processing on the sensitive graphics and non-sensitive graphics using DML partitions of different sizes to obtain TOPC mask correction data; wherein the DML partition size of the sensitive graphics is smaller than the DML partition size of the non-sensitive graphics. This invention takes into account the critical differences in the impact of different patterns on circuit performance (such as timing, functionality, and yield). It allocates smaller DML partitions to sensitive patterns that affect circuit performance, utilizes more OPC computation time to cover a wider process window, and precisely invests optimized computing power and mask budget into the sensitive patterns that have the greatest impact on performance. This optimizes critical path timing, clock stability, etc., and directly improves the upper limit of chip performance. It avoids the waste of limited computing resources and mask manufacturing budget on non-sensitive patterns that have little impact on performance. Without significantly increasing the mask design cycle or slowing down the efficiency of topography-aware OPC, it improves circuit performance indicators.
[0079] The shape-aware OPC device in this embodiment is used to implement the aforementioned shape-aware OPC method. Therefore, the specific implementation of the shape-aware OPC device can be found in the embodiment section of the shape-aware OPC method above. For example, the acquisition module 100, the image determination module 200, and the TOPC processing module 300 are used to implement steps S101, S102, and S103 in the above-mentioned shape-aware OPC method, respectively. Therefore, the specific implementation can be referred to the description of the corresponding embodiments, which will not be repeated here.
[0080] The present invention also provides a shape-sensing OPC device, comprising:
[0081] Memory, used to store computer programs;
[0082] A processor is configured to implement the steps of any of the above-described shape-aware OPC methods when executing the computer program. The shape-aware OPC method provided by this invention involves: acquiring design intent data and a layout to be processed; determining sensitive graphics in the layout to be processed based on the design intent data; performing TOPC processing on the sensitive and non-sensitive graphics using DML partitions of different sizes to obtain TOPC mask correction data; wherein the DML partition size of the sensitive graphics is smaller than the DML partition size of the non-sensitive graphics. This invention takes into account the critical differences in the impact of different patterns on circuit performance (such as timing, functionality, and yield). It allocates smaller DML partitions to sensitive patterns that affect circuit performance, utilizes more OPC computation time to cover a wider process window, and precisely invests optimized computing power and mask budget into the sensitive patterns that have the greatest impact on performance. This optimizes critical path timing, clock stability, etc., and directly improves the upper limit of chip performance. It avoids the waste of limited computing resources and mask manufacturing budget on non-sensitive patterns that have little impact on performance. Without significantly increasing the mask design cycle or slowing down the efficiency of topography-aware OPC, it improves circuit performance indicators.
[0083] This invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of any of the above-described shape-aware OPC methods. The shape-aware OPC method provided by this invention involves: acquiring design intent data and a layout to be processed; determining sensitive graphics in the layout to be processed based on the design intent data; performing TOPC processing on the sensitive and non-sensitive graphics using DML partitions of different sizes to obtain TOPC mask correction data; wherein the DML partition size of the sensitive graphics is smaller than the DML partition size of the non-sensitive graphics. This invention takes into account the critical differences in the impact of different patterns on circuit performance (such as timing, functionality, and yield). It allocates smaller DML partitions to sensitive patterns that affect circuit performance, utilizes more OPC computation time to cover a wider process window, and precisely invests optimized computing power and mask budget into the sensitive patterns that have the greatest impact on performance. This optimizes critical path timing, clock stability, etc., and directly improves the upper limit of chip performance. It avoids the waste of limited computing resources and mask manufacturing budget on non-sensitive patterns that have little impact on performance. Without significantly increasing the mask design cycle or slowing down the efficiency of topography-aware OPC, it improves circuit performance indicators.
[0084] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.
[0085] It should be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0086] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.
[0087] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.
[0088] The above provides a detailed description of the shape-sensing OPC method, apparatus, device, and storage medium provided by this invention. Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of this invention. It should be noted that those skilled in the art can make various improvements and modifications to this invention without departing from its principles, and these improvements and modifications also fall within the protection scope of this invention.
Claims
1. A shape-aware OPC method, characterized in that, include: Obtain design intent data and layout to be processed; Based on the design intent data, the sensitive graphics in the layout to be processed are determined; TOPC processing is performed on the sensitive and non-sensitive graphics using DML partitions of different sizes to obtain TOPC mask correction data; The DML partition size of the sensitive graphic is smaller than the DML partition size of the non-sensitive graphic.
2. The shape-perceived OPC method as described in claim 1, characterized in that, The sensitive pattern is at least one of the following: a time-sensitive pattern, a current density-sensitive pattern, and a voltage drop-sensitive pattern.
3. The shape-sensing OPC method as described in claim 1, characterized in that, The convergence criterion for edge placement error of sensitive graphics is more stringent than that for edge placement error of non-sensitive graphics.
4. The shape-perceived OPC method as described in claim 1, characterized in that, After obtaining the design intent data and the layout to be processed, the process also includes: Based on the design intent data, matching device pattern pairs are determined in the layout to be processed; each matching device pattern pair includes multiple matching device patterns. All matching device graphics in a single matching device graphic pair are assigned the same DML configuration.
5. The shape-sensing OPC method as described in claim 1, characterized in that, After obtaining the design intent data and the layout to be processed, the process also includes: Based on the design intent data, a rough graphic in the layout to be processed is determined; Accordingly, TOPC processing is performed on the sensitive and non-sensitive graphics using DML partitions of different sizes to obtain TOPC mask correction data, including: The rough graphics are subjected to planar OPC processing, and the non-rough graphics are subjected to TOPC processing; wherein, the size of the DML partition used in the TOPC processing of the sensitive graphics is smaller than the size of the DML partition used in the TOPC processing of the non-sensitive graphics, thus obtaining TOPC mask correction data.
6. The shape-aware OPC method as described in claim 5, characterized in that, The rough pattern is at least one of a ground line pattern and a filled metal pattern.
7. A shape-sensing OPC device, characterized in that, include: The acquisition module is used to acquire design intent data and layouts to be processed; The graphic determination module is used to determine the sensitive graphics in the layout to be processed based on the design intent data; The TOPC processing module is used to perform TOPC processing on the sensitive and non-sensitive graphics using DML partitions of different sizes to obtain TOPC mask correction data. The DML partition size of the sensitive graphic is smaller than the DML partition size of the non-sensitive graphic.
8. The shape-sensing OPC device as described in claim 7, characterized in that, The acquisition module further includes: A matching graphic unit is used to determine matching device graphic pairs in the layout to be processed based on the design intent data; the matching device graphic pair includes multiple matching device graphics. A matching synchronization unit is used to assign the same DML configuration to all matching device patterns in a single matching device pattern pair.
9. A shape-sensing OPC device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the shape-aware OPC method as described in any one of claims 1 to 6 when executing the computer program.
10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the shape-aware OPC method as described in any one of claims 1 to 6.