Semiconductor structure and method of manufacturing the same, storage system

Abstract

The disclosure provides a semiconductor structure and a preparation method thereof and a storage system, and relates to the technical field of semiconductor chips, and aims to solve the problem of difficulty in improving the facing area between two capacitor electrodes in a capacitor structure. The semiconductor structure comprises a semiconductor layer and a first capacitor structure. The first capacitor structure comprises a first electrode structure, a first dielectric layer and a second electrode structure. The first electrode structure penetrates the semiconductor layer along a first direction; the first direction is parallel to the thickness direction of the semiconductor layer; the second electrode structure penetrates the semiconductor layer along the first direction and is located between the semiconductor layer and the first electrode structure; the second electrode structure is arranged around the first electrode structure; and the first dielectric layer is located between the first electrode structure and the second electrode structure. Through the above arrangement, the facing area between the first electrode structure and the second electrode structure can be improved by only improving the thickness of the second electrode structure in the first direction, and the capacitance value of the first capacitor structure can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor structure, its fabrication method, and a storage system. Background Technology

[0002] With the continuous evolution of Dynamic Random Access Memory (DRAM), the storage density of planar DRAM has gradually approached the limits of process technology. Summary of the Invention

[0003] Embodiments of this disclosure provide a semiconductor structure, a method for fabricating the same, and a memory system.

[0004] The embodiments of this disclosure adopt the following technical solutions:

[0005] On one hand, a semiconductor structure is provided. The semiconductor structure includes a semiconductor layer and a first capacitor structure. The first capacitor structure includes a first electrode structure, a second electrode structure, and a first dielectric layer. The first electrode structure penetrates the semiconductor layer along a first direction; the first direction is parallel to the thickness direction of the semiconductor layer; the second electrode structure penetrates the semiconductor layer along the first direction and is located between the semiconductor layer and the first electrode structure, the second electrode structure being disposed around the first electrode structure; the first dielectric layer is located between the first electrode structure and the second electrode structure.

[0006] In some embodiments, the first electrode structure has a reference surface parallel to the semiconductor layer, the shape of the reference surface includes a circle, and the diameter of the reference surface is L. The second electrode structure has a dimension D in the first direction, and D and L satisfy the following formula: D > (2 / 3)L.

[0007] In some embodiments, the second electrode structure does not overlap with the first electrode structure in the first direction.

[0008] In some embodiments, the semiconductor structure includes a plurality of semiconductor layers stacked along the first direction; the first capacitor structure includes a plurality of second electrode structures stacked along the first direction, one second electrode structure being connected to one of the semiconductor layers; the first electrode structure penetrates the plurality of second electrode structures along the first direction; the first dielectric layer penetrates the plurality of second electrode structures along the first direction, and the first dielectric layer is disposed around the first electrode structure.

[0009] In some embodiments, the semiconductor layer includes a first sub-layer and a second sub-layer arranged along a second direction; at least one first capacitor structure penetrates the first sub-layer, and at least one first capacitor structure penetrates the second sub-layer; the semiconductor structure further includes a second capacitor structure located between the first sub-layer and the second sub-layer; the second direction intersects the first direction; the second capacitor structure includes a third electrode structure, a fourth electrode structure, and a second dielectric layer. The third electrode structure penetrates the semiconductor layer along the first direction; the fourth electrode structure penetrates the semiconductor layer along the first direction, and the fourth electrode structure includes a first sub-electrode and a second sub-electrode spaced apart along the second direction, the first sub-electrode located between the first sub-layer and the third electrode structure, and the second sub-electrode located between the second sub-layer and the third electrode structure; the second dielectric layer penetrates the semiconductor layer along the first direction and is located between the third electrode structure and the fourth electrode structure.

[0010] In some embodiments, the semiconductor structure includes a plurality of semiconductor layers stacked along the first direction; the second capacitor structure includes a plurality of fourth electrode structures stacked along the first direction, one of the fourth electrode structures being connected to one of the semiconductor layers; the third electrode structure penetrates the plurality of fourth electrode structures along the first direction; the second dielectric layer penetrates the plurality of fourth electrode structures along the first direction, and the second dielectric layer is disposed around the third electrode structure.

[0011] In some embodiments, the semiconductor structure includes an isolation structure that extends through the semiconductor layer along the first direction and is located between the first sublayer and the second sublayer.

[0012] In some embodiments, the isolation structure includes an isolation pillar and a second dielectric layer; the isolation pillar includes a first sub-pillar, a second sub-pillar, and a third sub-pillar arranged sequentially along a third direction; the third direction intersects the plane containing the first direction and the second direction.

[0013] In some embodiments, the semiconductor structure further includes a gate layer stacked with the semiconductor layer, the gate layer including a first gate layer and a second gate layer, the first gate layer being located on one side of the semiconductor layer along the first direction, and the second gate layer being located on the other side of the semiconductor layer along the first direction; on the plane where the gate layer is located, the second sub-pillar is spaced apart from the first sub-pillar and the third sub-pillar respectively, and the gate layer is disposed around the second sub-pillar.

[0014] In some embodiments, on the plane where the gate layer is located, the area of ​​the second sub-pillar is smaller than the area of ​​the first sub-pillar, and the area of ​​the second sub-pillar is smaller than the area of ​​the third sub-pillar.

[0015] In some embodiments, on the plane where the semiconductor layer is located, the second sub-pillar is connected between the first sub-pillar and the third sub-pillar.

[0016] In some embodiments, the edge of the isolation post includes at least one arcuate edge in the plane containing the second direction and the third direction.

[0017] In some embodiments, the semiconductor structure further includes a plurality of bit lines, the plurality of bit lines being spaced apart along the second direction, the bit lines penetrating the semiconductor layer along the first direction, and the bit lines being connected to the semiconductor layer; the isolation structure is also located between two adjacent bit lines.

[0018] In some embodiments, the semiconductor layer further includes a third sublayer and a fourth sublayer arranged along the second direction, the third sublayer and the first sublayer being arranged along the third direction and connected to the same bit line, the fourth sublayer and the second sublayer being arranged along the third direction and connected to the same bit line; at least one first capacitor structure penetrates the third sublayer along the first direction, and at least one first capacitor structure penetrates the fourth sublayer along the first direction.

[0019] In some embodiments, the semiconductor structure further includes a third capacitor structure located between the third sub-layer and the fourth sub-layer; the third capacitor structure includes a fifth electrode structure, a sixth electrode structure, and a third dielectric layer. The fifth electrode structure penetrates the semiconductor layer along the first direction; the sixth electrode structure penetrates the semiconductor layer along the first direction, and the sixth electrode structure includes the third sub-electrode and the fourth sub-electrode spaced apart along the second direction, the third sub-electrode being located between the third sub-layer and the fifth electrode structure, and the fourth sub-electrode being located between the fourth sub-layer and the fifth electrode structure; the third dielectric layer penetrates the semiconductor layer along the first direction and is located between the fifth electrode structure and the sixth electrode structure.

[0020] In some embodiments, the semiconductor structure further includes a plurality of dielectric layers and a plurality of semiconductor layers, wherein the plurality of dielectric layers and the plurality of semiconductor layers are alternately stacked along the first direction; a portion of the first electrode structure is located between two adjacent dielectric layers along the first direction.

[0021] In some embodiments, the first electrode structure includes: a first conductive portion and a second conductive portion, the first conductive portion penetrating the semiconductor layer along the first direction, the second conductive portion being disposed around the first conductive portion, and the second conductive portion being in contact with the first dielectric layer.

[0022] In some embodiments, the first conductive portion and the second electrode structure do not overlap in the first direction.

[0023] On the other hand, some embodiments of this disclosure also provide a method for fabricating a semiconductor structure, including: forming a semiconductor layer; forming a first capacitor structure, the first capacitor structure including: a first electrode structure, a second electrode structure, and a first dielectric layer, the first electrode structure penetrating the semiconductor layer along a first direction; the second electrode structure penetrating the semiconductor layer along the first direction and located between the semiconductor layer and the first electrode structure, the second electrode structure being disposed around the first electrode structure; the first dielectric layer being located between the first electrode structure and the second electrode structure; the first direction being parallel to the thickness direction of the semiconductor layer.

[0024] In some embodiments, forming a semiconductor layer includes: forming a stacked structure, the stacked structure including the semiconductor layer and the sacrificial layer alternately stacked along a first direction; after forming the semiconductor layer, the method further includes: forming an isolation pillar, the isolation pillar penetrating the stacked structure along the first direction, the semiconductor layer in the same layer including a first sub-layer and a second sub-layer arranged along a second direction, the isolation pillar being located between the first sub-layer and the second sub-layer, the second direction being parallel to the semiconductor layer; forming a gate layer, the gate layer being stacked with the semiconductor layer, the gate layer including a first gate layer and a second gate layer, the first gate layer being located on one side of the semiconductor layer along the first direction, and the second gate layer being located on the other side of the semiconductor layer along the first direction; forming a bit line, the bit line penetrating the stacked structure along the first direction, and the bit line being connected to the semiconductor layer.

[0025] In some embodiments, forming an isolation pillar includes: forming a first structural aperture that penetrates the stacked structure along a first direction; removing the sacrificial layer through the first structural aperture; forming a dielectric layer including a first dielectric layer, a second dielectric layer, and a third dielectric layer, wherein the first dielectric layer surrounds the semiconductor layer, the second dielectric layer surrounds the first dielectric layer, and the third dielectric layer surrounds the second dielectric layer; removing a portion of the dielectric layer covering the aperture wall of the first structural aperture to expose the semiconductor layer; removing a portion of the semiconductor layer; and filling the first structural aperture with an insulating material to form a portion of the isolation pillar.

[0026] In some embodiments, forming the gate layer includes: forming a second structural aperture that penetrates the stacked structure along the first direction; removing a portion of the dielectric layer covering the sidewall of the second structural aperture; removing a portion of the second dielectric layer through the second structural aperture to form a first filling space; filling the first filling space with a first conductive material to form the gate layer; and filling the second structural aperture with an insulating material to form a portion of the isolation pillar.

[0027] In some embodiments, after filling the first filling space with a first conductive material and before filling the second structural hole with an insulating material, the method further includes: removing a portion of the semiconductor layer through the second structural hole.

[0028] In some embodiments, forming a bit line includes: forming a third structural hole that penetrates the stacked structure along a first direction; removing a portion of the dielectric layer covering the sidewall of the third structural hole; filling the third structural hole with a second conductive material to form the bit line; and filling the third structural hole with a third conductive material to form a contact, the contact being stacked with the bit line along the first direction.

[0029] In some embodiments, after forming the contact and before forming the capacitor structure, the method further includes: forming a fourth dielectric layer, the fourth dielectric layer being stacked with the stack structure along the first direction, and the fourth dielectric layer being located on the side of the contact away from the bit line.

[0030] In some embodiments, forming the first capacitor structure includes: forming a fourth structural via and a fifth structural via, the fourth structural via and the fifth structural via being arranged along a second direction, the fourth structural via penetrating the stacked structure along the first direction, the fifth structural via penetrating the stacked structure and a portion of the isolation pillars along the first direction, the second direction intersecting the first direction; removing a portion of the semiconductor layer and a portion of the first dielectric layer through the fourth structural via and the fifth structural via to form a second filling space and a third filling space; forming a second electrode structure and a fourth electrode structure in the second filling space and the third filling space, respectively, the fourth electrode structure including a first sub-electrode and a second sub-electrode spaced apart along the second direction; and forming a second electrode structure and a fourth electrode structure through the fourth structural via. The first dielectric layer and the fifth structural hole respectively form the first dielectric layer and the second dielectric layer. The first dielectric layer penetrates the plurality of semiconductor layers and the second electrode structure along the first direction. The second dielectric layer penetrates the plurality of semiconductor layers and the fourth electrode structure along the first direction. The first electrode structure and the third electrode structure are formed through the fourth structural hole and the fifth structural hole respectively. The first electrode structure is located on the side of the first dielectric layer away from the stacked structure. The third electrode structure is located on the side of the second dielectric layer away from the stacked structure. The first electrode structure, the second electrode structure and the first dielectric layer together constitute the first capacitor structure. The third electrode structure, the fourth electrode structure and the second dielectric layer together constitute the second capacitor structure.

[0031] In another aspect, a storage system is also provided, comprising: a semiconductor structure as described above and a controller, the controller being coupled to the semiconductor structure to control the semiconductor structure to store data. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0033] Figure 1 A block diagram of an electronic device according to some embodiments;

[0034] Figure 2 A block diagram of a memory according to some embodiments;

[0035] Figure 3This is a schematic diagram of a semiconductor structure according to some embodiments;

[0036] Figure 4 This is a circuit diagram of a semiconductor structure according to some embodiments;

[0037] Figure 5 This is a schematic diagram of another semiconductor structure according to some embodiments;

[0038] Figure 6 This is a schematic diagram of a first capacitor structure according to some embodiments;

[0039] Figure 7 This is a schematic diagram of the structure of a second electrode plate according to some embodiments;

[0040] Figure 8 This is a schematic diagram of another semiconductor structure according to some embodiments;

[0041] Figure 9 This is a schematic diagram of the structure of a semiconductor structure in the plane containing the semiconductor layer according to some embodiments;

[0042] Figure 10 This is a schematic diagram of a second capacitor structure according to some embodiments;

[0043] Figure 11 This is a schematic diagram of another semiconductor structure according to some embodiments;

[0044] Figure 12 This is a schematic diagram of another semiconductor structure according to some embodiments;

[0045] Figure 13 This is a schematic diagram of another semiconductor structure according to some embodiments;

[0046] Figure 14 This is a schematic diagram of the structure of another semiconductor structure according to some embodiments in the plane where the semiconductor layer is located;

[0047] Figure 15 This is a schematic diagram of another semiconductor structure according to some embodiments;

[0048] Figure 16 This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments;

[0049] Figure 17 This is a schematic diagram of the structure after the stacked structure is formed according to some embodiments;

[0050] Figure 18This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments;

[0051] Figures 19 to 70 This is a schematic diagram of the fabrication process of a semiconductor structure according to some embodiments.

[0052] Reference numerals: T, transistor; C, capacitor; 9132, first electrode plate; 9133, second electrode plate; 9134, dielectric layer; 1000, semiconductor structure; X, first direction; Y, second direction; Z, third direction; 100, semiconductor layer; 110, first sublayer; 120, second sublayer; 130, third sublayer; 140, fourth sublayer; 200, first capacitor structure; 210, first electrode structure; 2101, reference plane; 211, first conductive part; 212, second conductive part. Electrical components; 220, second electrode structure; 230, first dielectric layer; 300, second capacitor structure; 400, gate layer; 410, first gate layer; 420, second gate layer; 500, dielectric layer; 510, first dielectric layer; 520, second dielectric layer; 530, third dielectric layer; 540, fourth dielectric layer; 600, second capacitor structure; 610, third electrode structure; 620, fourth electrode structure; 621, first sub-electrode; 622, second sub-electrode; 630, second dielectric layer 700, Isolation structure; 710, Isolation pillar; 711, First sub-pillar; 712, Second sub-pillar; 713, Third sub-pillar; 714, Fourth sub-pillar; 715, Fifth sub-pillar; 800, Third capacitor structure; 810, Fifth electrode structure; 820, Sixth electrode structure; 821, Third sub-electrode; 822, Fourth sub-electrode; 830, Third dielectric layer; 150, Stacked structure; 151, Sacrificial layer; 101, First structural via; 102, Second structural via; 103, Third structural via; 104. Fourth structural hole; 105. Fifth structural hole; 152. Isolation layer; 153. Isolation material layer; 154. Electrode layer; 1011. First sacrificial pillar; 1021. Second sacrificial pillar; 1031. Third sacrificial pillar; 1041. Fourth sacrificial pillar; 1051. Fifth sacrificial pillar; 160. Contact point; 171. First filling space; 172. Second filling space; 173. Third filling space; 181. First conductive material; 182. Second conductive material; 183. Third conductive material. Detailed Implementation

[0053] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0054] In the description of this disclosure, it should be understood that the terms “center,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0055] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0056] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0057] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0058] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0059] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0060] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0061] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0062] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0063] In this disclosure, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something with intermediate features or layers in between, and “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers in between (i.e., directly on something).

[0064] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0065] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0066] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0067] Figure 1 This is a block diagram of an electronic device according to some embodiments. Some embodiments of this disclosure provide an electronic device 9000. The electronic device 9000 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device (e.g., smartwatch, smart bracelet, smart glasses, etc.), smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein.

[0068] like Figure 1 As shown, the electronic device 9000 may include a storage system 910 and a motherboard 920. The storage system 910 can be integrated into various types of storage devices, such as memory cards. These memory cards include any of the following: PC cards (PCMCIA, Personal Computer Memory Card International Association), compact flash (CF) cards, smart media (SM) cards, memory sticks, multimedia cards (MMC), secure digital memory cards (SD cards), and universal flash storage (UFS). In other words, the storage system 910 can be applied to and packaged into different types of electronic products.

[0069] The motherboard 920 may include a processor of the electronic device 9000, such as a central processing unit (CPU) or a system-on-chip (SoC), such as an application processor (AP). The motherboard 920 may be configured to send data to or receive data from memory.

[0070] In some embodiments, the storage system 910 may have one or more memories 911 and a controller 912. For example, the controller 912 may be configured to operate in a low duty cycle environment, such as with an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones. Alternatively, in other examples, the controller 912 is configured to operate in a high duty cycle environment with an SSD or eMMC, which is used as data storage in mobile devices such as smartphones, tablets, and laptops, as well as in enterprise storage arrays. Or, in some examples, the controller 912 is coupled to the memory 911 and the motherboard 920 and is configured to control data in the memory 911 while also being able to communicate with external devices (e.g., a host computer).

[0071] The number of memories 911 in the storage system 910 can be one or more. Figure 1The diagram illustrates three memories 911 as an example. The controller 912 manages the data stored in each memory 911 and communicates with the motherboard 920. The controller 912 can be configured to control the operation of each memory 911, such as read, write, and refresh operations. The controller 912 can also be configured to manage various functions related to the data stored or to be stored in each memory 911, including but not limited to refresh and timing control, command / request translation, buffering and scheduling, and power management. In some embodiments, the controller 912 is also configured to determine the maximum memory capacity usable by the computer system, the number of memory banks, memory type and speed, memory particle data depth and data width, and other important parameters. The controller 912 can also perform any other suitable functions. The controller 912 can communicate with external devices (e.g., the motherboard 920) according to a specific communication protocol. For example, the controller 912 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.

[0072] Figure 2 This is a block diagram of a memory according to some embodiments. This disclosure provides a memory 911 according to some embodiments. For example... Figure 2 As shown, memory 911 includes a memory cell array 913 and peripheral circuitry 914 for controlling the memory cell array 913. Peripheral circuitry 914 (also referred to as control and sensing circuitry) may include any suitable digital, analog, and / or mixed-signal circuitry for facilitating the operation of memory cell array 913. For example, peripheral circuitry 914 may include one or more of the following: page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), input / output (I / O) circuitry, charge pumps, voltage sources or generators, current or voltage references, any portion of the aforementioned functional circuitry (e.g., sub-circuits), or any active or passive component of the circuitry (e.g., transistors, diodes, resistors, or capacitors).

[0073] For example, the peripheral circuit 914 can use complementary metal-oxide-semiconductor (CMOS) technology, which can be implemented using logic processes (e.g., technology nodes such as 90nm, 65nm, 60nm, 45nm, 32nm, 28nm, 22nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.).

[0074] The memory cell array 913 and the peripheral circuitry 914 can be arranged side-by-side in the same plane, for example, on the same wafer; that is, the memory cell array 913 and the peripheral circuitry 914 can be located in the same semiconductor structure. The memory cell array 913 and the peripheral circuitry 914 can also be stacked on the same wafer, for example, the memory cell array 913 and the peripheral circuitry 914 can be formed sequentially on one wafer, with the peripheral circuitry 914 located on the side of the memory cell array 913 away from the wafer. Alternatively, the memory cell array 913 and the peripheral circuitry 914 can be formed on different wafers and bonded together face-to-face. Figure 2 As shown, when the memory cell array 913 and the peripheral circuitry 914 are formed on different wafers and bonded together face-to-face, the memory 911 may include a first semiconductor structure 901 and a second semiconductor structure 902, as well as a bonding interface 903 between the first semiconductor structure 901 and the second semiconductor structure 902. The first semiconductor structure 901 may include the memory cell array 913, and the second semiconductor structure 902 may include the peripheral circuitry 914.

[0075] The memory cell array 913 may be an array of memory cells that use vertical transistors as switching and selection devices. In some embodiments, the memory cell array 913 may be a dynamic random access memory (DRAM) cell array. For ease of description, a DRAM cell array may be used to describe an example of the memory cell array 913 in this disclosure. However, it should be understood that the memory cell array 913 is not limited to a DRAM cell array, and may include any other suitable type of memory cell array 913 that can use vertical transistors as switching and selection devices, such as a PCM cell array, a static random-access memory (SRAM) cell array, a FRAM cell array, a resistive memory cell array, a magnetic memory cell array, a spin-transfer torque (STT) memory cell array, etc.

[0076] When the memory cell array 913 is a DRAM cell array, the memory cells therein are DRAM cells. A DRAM cell includes a capacitor and one or more transistors. The capacitor stores data as positive or negative charge, and the one or more transistors (also called transfer transistors) control (e.g., switching and selecting) access to the DRAM cell. In some embodiments, each DRAM cell is a transistor and a capacitor (1T1C) cell. According to some embodiments, the DRAM cell can be refreshed by peripheral circuitry 914 to retain data.

[0077] As DRAM technology continues to evolve, the storage density of DRAM cells on a plane has gradually approached the limits of process technology. To further improve the storage density of DRAM cells, this disclosure provides some embodiments of a memory with 3D stacked DRAM cells. (Reference) Figure 2 , Figure 3 and Figure 4 The memory cell array 913 in the memory 911 provided in this embodiment includes a plurality of memory cells 9131 (e.g., DRAM cells) arranged in a second direction Y and a third direction Z, and the plurality of memory cells 9131 can also be stacked along the first direction X.

[0078] In this embodiment, the second direction Y and the third direction Z intersect, and the first direction X intersects the plane containing the second direction Y and the third direction Z. For ease of understanding, this embodiment uses the example of the second direction Y and the third direction Z being perpendicular to each other, and the first direction X being perpendicular to the plane containing the second direction Y and the third direction Z, to explain the semiconductor structure.

[0079] refer to Figure 3 , Figure 4 and Figure 5 A memory cell 9131 includes a transistor T and a capacitor C. The transistor T may be formed of a semiconductor layer and a gate layer adjacent to the semiconductor layer. A gate dielectric layer is also disposed between the semiconductor layer and the corresponding gate layer.

[0080] The semiconductor layer may include semiconductor materials. Examples of semiconductor materials include monocrystalline silicon, polycrystalline silicon, monocrystalline germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials.

[0081] The semiconductor layer may have a source and a drain, and the materials of the source and drain may include semiconductor materials doped with P-type or N-type dopants. P-type dopants include boron or gallium. N-type dopants include phosphorus or arsenic.

[0082] The drain of transistor T is connected to bit line BL, which can be parallel to the first direction X. The source of transistor T is connected to one plate of capacitor C, and the other plate of capacitor C can be connected to a reference voltage, which can be ground or another voltage. The capacitor C can represent logical 1 and 0 by the amount of charge stored within it, or the high or low voltage difference across capacitor C. The gate of transistor T is connected to word line WL, which can be parallel to the second direction Y. With the above configuration, memory 911 can control transistor T to be turned on or off by applying a voltage to word line WL. When transistor T is on, bit line BL performs a read or write operation on capacitor C.

[0083] This disclosure provides a semiconductor structure in some embodiments. This semiconductor structure can be part of the memory 911 in some of the above embodiments; for example, the semiconductor structure can be a first semiconductor structure 901. Alternatively, if the semiconductor structure is used as memory 911, it may further include peripheral circuitry 914, which is not a limitation of this disclosure.

[0084] In some embodiments, please refer to Figure 5 The semiconductor structure 1000 may include a semiconductor layer 100 and a first capacitor structure 200. The first capacitor structure 200 includes a first electrode structure 210, a second electrode structure 220, and a first dielectric layer 230. The first electrode structure 210 penetrates the semiconductor layer 100 along a first direction X. The first direction X is parallel to the thickness direction of the semiconductor layer 100. The second electrode structure 220 penetrates the semiconductor layer 100 along the first direction X, and is located between the semiconductor layer 100 and the first electrode structure 210, with the second electrode structure 220 arranged around the first electrode structure 210. The first dielectric layer 230 is located between the first electrode structure 210 and the second electrode structure 220.

[0085] refer to Figure 6 On a plane intersecting the first direction X, for example on the YZ plane, the second electrode structure 220 is disposed around the first electrode structure 210. The first dielectric layer 230 is located between the first electrode structure 210 and the second electrode structure 220, and the first dielectric layer 230 is also disposed around the first electrode structure 210. The second electrode structure 220 is also disposed around the first dielectric layer 230 located between the first electrode structure 210 and the second electrode structure 220.

[0086] For example, the first electrode structure 210 can be an electrode post, and the second electrode structure 220 can be a ring structure arranged around the first electrode structure.

[0087] For example, the material of the first electrode structure 210 can be a single-layer structure formed by one of the following materials: W, Al, Cu, Ag, Au, Co, Pt, Ni, Ti, Ta, TiN, TaN, TaC, TaSiN, NiSi, CoSi, TiAl, and WSi, or a stacked structure formed by two or more of the above materials. In this embodiment, the constituent material of the first electrode structure 210 may include titanium nitride. Titanium nitride material has a high melting point, high hardness, high-temperature chemical stability, and excellent electrical conductivity. Using titanium nitride material to prepare the first electrode structure 210 is beneficial to improving the conductivity of the first electrode structure 210 and also beneficial to improving the stability of the first capacitor structure 200.

[0088] For example, the material of the first dielectric layer 230 may include a high-k (k greater than 2.8) dielectric material to increase the capacitance value per unit area of ​​the capacitor. In a specific embodiment, the first dielectric layer 230 may be a single-layer structure formed by one of the following materials: HfO2, TiO2, HfZrO, HfSiNO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, or BaSrTiO, or a stacked structure formed by two or more of the above materials.

[0089] For example, the material of the second electrode structure 220 can be a single-layer structure formed by one of the following materials: W, Al, Cu, Ag, Au, Co, Pt, Ni, Ti, Ta, TiN, TaN, TaC, TaSiN, NiSi, CoSi, TiAl, and WSi, or a stacked structure formed by two or more of the above materials.

[0090] In this embodiment, we continue to refer to Figure 4 , Figure 5 and Figure 6 The second electrode structure 220 can be connected to the source electrode of the semiconductor layer 100. A second electrode structure 220, along with the first dielectric layer 230 and the first electrode structure 210 surrounding it, can together form a capacitor C (see reference). Figure 4 The semiconductor layer 100 and the adjacent gate layer 400 can together form a transistor T, and 1T1C can form a memory cell.

[0091] Factors affecting the capacitance of the first capacitor structure 200 include: the area between the first electrode structure 210 and the second electrode structure 220, the dielectric constant of the first dielectric layer 230, and the distance between the first electrode structure 210 and the second electrode structure 220. When other factors affecting the capacitance of the first capacitor structure 200 remain constant, the larger the area between the first electrode structure 210 and the second electrode structure 220, the larger the capacitance of the first capacitor structure 200.

[0092] Continue to refer to Figure 5 and Figure 6 In this embodiment, the second electrode structure 220 is arranged around the first electrode structure 210, and the peripheral surface of the first electrode structure 210 is opposite to the inner surface of the second electrode structure 220. By simply increasing the dimensions (thickness) of the first electrode structure 210 and the second electrode structure 220 in the first direction X, the facing area between the first electrode structure 210 and the second electrode structure 220 can be increased, thereby increasing the capacitance value of the first capacitor structure 200. This arrangement simplifies the process of increasing the facing area between the first electrode structure 210 and the second electrode structure 220, improves the problem of difficulty in increasing the capacitance value of capacitors in some embodiments, and further increases the capacitance value of the first capacitor structure 200, thereby increasing the storage capacity of the semiconductor structure 1000.

[0093] Furthermore, the above configuration does not increase the dimensions of the semiconductor structure 1000 in the second direction Y and the third direction Z. This is beneficial to increasing the facing area between the first electrode plate and the second electrode plate while keeping the dimensions of the semiconductor structure 1000 in the second direction Y and the third direction Z unchanged, thereby increasing the capacitance value of the semiconductor structure 1000 and improving the storage density of the semiconductor structure 1000.

[0094] Furthermore, the semiconductor structure 1000 provided in this embodiment only requires increasing the dimensions of the first electrode structure 210 and the second electrode structure 220 in the first direction X during the fabrication process, without adding any new process steps, making the process relatively simple. Moreover, the second electrode structure 220 only surrounds the periphery of the first electrode structure 210, resulting in a simple structure and fabrication method, which helps to reduce the process cost and difficulty of fabricating the semiconductor structure 1000.

[0095] In some embodiments, reference Figure 5 and Figure 6 The first electrode structure 210 has a reference surface 2101, which is parallel to the semiconductor layer 100. For example, a cross-section of the first electrode structure 210 parallel to the second direction Y and the third direction Z can be used as the reference surface 2101. The shape of the reference surface 2101 can include regular shapes such as rectangles, circles, and ellipses, or other irregular shapes.

[0096] When the reference surface 2101 is circular, the first electrode structure 210 can be a cylindrical structure, and the first electrode structure 210 extends along the first direction X.

[0097] In this embodiment, taking the first electrode structure 210 as a cylindrical structure as an example, the first electrode structure 210 has a reference surface 2101, which is circular in shape. The area between the first electrode structure 210 and the second electrode structure 220 in this embodiment is calculated as the product of the perimeter of the reference surface 2101 and the dimension of the second electrode structure 220 in the first direction X. Let the diameter of the reference surface 2101 be L, and the dimension of the second electrode structure 220 in the first direction X be D. Then, the area between the first electrode structure 210 and the second electrode structure 220 in this embodiment is: πL × D.

[0098] Here, the dimension of the second electrode structure 220 in the first direction X can be understood as the thickness of the second electrode structure 220 in the first direction X.

[0099] refer to Figure 4 and Figure 7 In some embodiments, capacitor C includes a first electrode plate, a second electrode plate, and a dielectric layer. The second electrode plate is parallel to the second direction Y and the third direction Z, and a portion of the first electrode plate covers two surfaces of the second electrode plate disposed along the first direction X. A portion of the first electrode plate and the second electrode plate are disposed directly opposite each other in the first direction X. Therefore, the area of ​​the directly opposite first electrode plate and the second electrode plate in this embodiment is calculated as twice the area of ​​the surface of the second electrode plate in the first direction X. When the second electrode plate 9133 in this embodiment has the same dimensions as the first electrode structure 210 in this embodiment in the second direction Y and the third direction Z, the area of ​​the directly opposite first electrode plate in this embodiment is 2 × L. 2 .

[0100] In this embodiment, reference Figure 6 The diameter of the reference surface 2101 is L, and the dimension of the second electrode structure 220 in the first direction X is D. D and L satisfy the following equation: D > (2 / 3)L. With the above settings, (πL × D) > 2 × L 2 That is, the area of ​​the first electrode structure 210 and the second electrode structure 220 facing each other is greater than the area of ​​the first electrode plate and the second electrode plate facing each other. When the second electrode plate and the first electrode structure 210 have the same dimensions in the second direction Y and the third direction Z, the above arrangement can increase the area of ​​the first electrode structure 210 and the second electrode structure 220 facing each other, which is beneficial to increasing the capacitance value of the first capacitor structure 200, and thus increasing the storage capacity of the semiconductor structure 1000.

[0101] In some embodiments, such as Figure 5 As shown, the second electrode structure 220 and the first electrode structure 210 do not overlap in the first direction X.

[0102] The second electrode structure 220 and the first electrode structure 210 do not overlap in the first direction X. This can be understood as the orthographic projection of the second electrode structure 220 in the first direction X having no overlapping part with the orthographic projection of the first electrode structure 210 in the first direction X.

[0103] The second electrode structure 220 surrounds only the periphery of the first electrode structure 210, and the first electrode structure 210 surrounded by the second electrode structure 220 together with all the second electrode structures 220 constitute the first capacitor structure 200. All the second electrode structures 220 can store charge, which is beneficial for making full use of the second electrode structures 220.

[0104] In addition, with the above configuration, the second electrode structure 220 only surrounds the periphery of the first electrode structure 210, which is simple in structure and easy to prepare. This helps to reduce the process cost of preparing the first capacitor structure 200 and also helps to reduce the difficulty of increasing the capacitance value of the first capacitor structure 200.

[0105] In some embodiments, such as Figure 8 As shown, the semiconductor structure 1000 includes a plurality of dielectric layers and a plurality of semiconductor layers 100, which are alternately stacked along a first direction X. For example, dielectric layers and semiconductor layers 100 are alternately stacked along the first direction X to form a plurality of dielectric layers and a plurality of semiconductor layers 100 spaced apart from each other.

[0106] In this embodiment, the first electrode structure 210 can extend along the first direction X and penetrate multiple dielectric layers and multiple semiconductor layers 100. A portion of the first electrode structure 210 can also be located between two adjacent dielectric layers along the first direction X to ensure that there are no gaps between the first electrode structure 210 and the first dielectric layer, thereby improving the structural stability of the first capacitor structure 200 and optimizing its storage performance.

[0107] In some embodiments, such as Figure 8As shown, the semiconductor structure 1000 includes a plurality of semiconductor layers 100 stacked along a first direction X. The first capacitor structure 200 includes a plurality of second electrode structures 220 stacked along the first direction X, with each second electrode structure 220 connected to a semiconductor layer 100. Exemplarily, a second electrode structure 220 and a semiconductor layer 100 may be located on the same layer. Exemplarily, a dielectric layer 500 may be disposed between two adjacent semiconductor layers 100 along the first direction X, and the dielectric layer 500 may also be located between two adjacent second capacitor structures 600 along the first direction X.

[0108] In this embodiment, we continue to refer to Figure 8 The first electrode structure 210 penetrates through multiple second electrode structures 220 and multiple semiconductor layers 100 along a first direction X. The first dielectric layer 230 penetrates through the multiple second electrode structures 220 and multiple semiconductor layers 100 along the first direction X, and the first dielectric layer 230 is disposed around the first electrode structure 210. Thus, the first dielectric layer 230 can be located between the first electrode structure 210 and the second electrode structures 220, and the first dielectric layer 230 can also be located between the first electrode structure 210 and the dielectric layer.

[0109] With the above configuration, the multiple second electrode structures 220 stacked along the first direction X are configured one-to-one with the multiple semiconductor layers 100. The multiple second electrode structures 220 stacked along the first direction X can share the same first electrode structure 210. The first electrode structure 210 extends along the first direction X, which facilitates the connection of the first electrode structure 210 to a reference voltage. The reference voltage can be ground voltage or other voltages.

[0110] In addition, in this embodiment, the first electrode structure 210 penetrates multiple second electrode structures 220 and multiple semiconductor layers 100 along the first direction X. Therefore, it is only necessary to increase the size of the second electrode structure 220 in the first direction X to increase the facing area of ​​the first electrode structure 210 and the second electrode structure 220, thereby increasing the capacitance value of the first capacitor structure 200. This helps to improve the problem of the difficulty in increasing the capacitance value of the semiconductor structure 1000. The process is simple and helps to reduce the difficulty of increasing the capacitance value.

[0111] In some embodiments, such as Figure 9 As shown, the semiconductor layer 100 includes a first sublayer 110 and a second sublayer 120 arranged along the second direction Y.

[0112] The semiconductor structure 1000 may include a plurality of first capacitor structures 200, at least one first capacitor structure 200 penetrating the first sublayer 110, and at least one first capacitor structure 200 penetrating the second sublayer 120.

[0113] For example, one first capacitor structure 200 penetrates the first sublayer 110, and another first capacitor structure 200 penetrates the second sublayer 120; or, multiple first capacitor structures 200 penetrate the first sublayer 110, and multiple first capacitor structures 200 penetrate the second sublayer 120. The multiple first capacitor structures 200 penetrating the first sublayer 110 can be arranged in multiple rows and columns along the second direction Y and the third direction Z. Similarly, the multiple first capacitor structures 200 penetrating the second sublayer 120 can be arranged in multiple rows and columns along the second direction Y and the third direction Z. By providing multiple first capacitor structures, it is beneficial to increase the capacitance value of the semiconductor structure 1000.

[0114] In this embodiment, as Figure 9 and Figure 10 As shown, the semiconductor structure 1000 also includes a second capacitor structure 600, which is located between the first sublayer 110 and the second sublayer 120.

[0115] The second capacitor structure 600 includes a third electrode structure 610, a fourth electrode structure 620, and a second dielectric layer 630. The third electrode structure 610 penetrates the semiconductor layer 100 along a first direction X. The fourth electrode structure 620 penetrates the semiconductor layer 100 along the first direction X and includes a first sub-electrode 621 and a second sub-electrode 622 spaced apart along a second direction Y. The first sub-electrode 621 is located between the first sub-layer 110 and the third electrode structure 610, and the second sub-electrode 622 is located between the second sub-layer 120 and the third electrode structure 610. The second dielectric layer 630 penetrates the semiconductor layer 100 along the first direction X. The second dielectric layer 630 is located between the third electrode structure 610 and the fourth electrode structure 620, that is, the second dielectric layer 630 is located between the first sub-electrode 621 and the third electrode structure 610, and the second dielectric layer 630 is also located between the second sub-electrode 622 and the third electrode structure 610. For example, the second dielectric layer 630 may be disposed around the third electrode structure 610.

[0116] For example, the constituent materials of the third electrode structure 610 and the fourth electrode structure 620 may both include electrode materials, such as W, Al, Cu, Ag, Au, Co, Pt, Ni, Ti, Ta, TiN, TaN, TaC, TaSiN, NiSi, CoSi, TiAl, WSi, etc.

[0117] For example, the material of the second dielectric layer 630 may include a high-k (k greater than 2.8) dielectric material to increase the capacitance value per unit area of ​​the capacitor. In some embodiments, the material of the second dielectric layer 630 may be the same as the material of the first dielectric layer 230. In some embodiments, the first dielectric layer 230 and the second dielectric layer 630 may be an integral structure.

[0118] The first sub-electrode 621, the third electrode structure 610, and the second dielectric layer 630 located between the first sub-electrode 621 and the third electrode structure 610 constitute a portion of the second capacitor structure 600, wherein the first sub-electrode 621 is connected to the first sub-layer 110.

[0119] The second sub-electrode 622, the third electrode structure 610, and the second dielectric layer 630 located between the second sub-electrode 622 and the third electrode structure 610 constitute a portion of the second capacitor structure 600, wherein the second sub-electrode 622 is connected to the second sub-layer 120.

[0120] Therefore, through the above arrangement, a portion of the second capacitor structure 600 is connected to the first sublayer 110, and a portion of the second capacitor structure 600 is connected to the second sublayer 120. Compared to storing charge only through the first capacitor structure 200, the semiconductor structure 1000 in this embodiment can store charge in both the first capacitor structure 200 and the second capacitor structure 600, which is beneficial to improving the storage capacity of the semiconductor structure 1000, and thus improving the storage density of the semiconductor structure 1000.

[0121] In some embodiments, reference Figure 8 , Figure 9 , Figure 10 and Figure 11 The semiconductor structure 1000 includes a plurality of semiconductor layers 100 stacked along a first direction X.

[0122] The second capacitor structure 600 includes a plurality of fourth electrode structures 620 stacked along a first direction X, each fourth electrode structure 620 being connected to a semiconductor layer 100. A third electrode structure 610 extends through the plurality of fourth electrode structures 620 along the first direction X. A second dielectric layer 630 extends through the plurality of fourth electrode structures 620 along the first direction X, and is disposed around the third electrode structure 610.

[0123] In this embodiment, the plurality of semiconductor layers 100 stacked along the first direction X may include a plurality of first sub-layers 110 stacked along the first direction X and a plurality of second sub-layers 120 stacked along the first direction X. The plurality of first sub-layers 110 and the plurality of second sub-layers 120 are arranged in a one-to-one correspondence. For example, one first sub-layer 110 and one second sub-layer 120 are arranged along the second direction Y.

[0124] The plurality of fourth electrode structures 620 stacked along the first direction X may include a plurality of first sub-electrodes 621 stacked along the first direction X and a plurality of second sub-electrodes 622 stacked along the first direction X. The plurality of first sub-electrodes 621 and the plurality of second sub-electrodes 622 are arranged in a one-to-one correspondence. For example, a first sub-electrode 621 and a second sub-electrode 622 are spaced apart along the second direction Y.

[0125] A plurality of first sub-electrodes 621 stacked along the first direction X are connected one-to-one with a plurality of first sub-layers 110 stacked along the first direction X. Each first sub-electrode 621 is connected to one first sub-layer 110. A plurality of second sub-electrodes 622 stacked along the first direction X are connected one-to-one with a plurality of second sub-layers 120 stacked along the first direction X. Each second sub-electrode 622 is connected to one second sub-layer 120.

[0126] With the above configuration, multiple memory cells stacked along the first direction X can be formed to increase the memory capacity of the semiconductor structure 1000.

[0127] In some embodiments, such as Figure 9 As shown, the semiconductor layer 100 in the same layer may include multiple sublayers arranged along the second direction Y. For example, the semiconductor layer 100 in the same layer may include a first sublayer 110, a second sublayer 120, ..., an Nth sublayer, etc., semiconductor sublayers arranged along the second direction Y. This disclosure does not limit the number of semiconductor sublayers included in the semiconductor layer 100 in the same layer.

[0128] In some embodiments, such as Figure 9 As shown, the semiconductor structure 1000 includes an isolation structure 700 that extends through the semiconductor layer 100 along a first direction X, and is also located between adjacent semiconductor sublayers along a second direction Y. The isolation structure 700 is used to isolate adjacent semiconductor sublayers along the second direction Y.

[0129] Taking a semiconductor layer 100 comprising a first sub-layer 110 and a second sub-layer 120 arranged along the second direction Y as an example, an isolation structure 700 is located between the first sub-layer 110 and the second sub-layer 120. The isolation structure 700 is used to isolate the first sub-layer 110 and the second sub-layer 120 arranged along the second direction Y. Here, it can also be understood that the isolation structure 700 divides the semiconductor layer 100 into the first sub-layer 110 and the second sub-layer 120.

[0130] In this embodiment, the first sub-layer 110 and the second sub-layer 120 can be disposed on the same layer. Disposal on the same layer means that multiple patterns are on the same pattern layer. A pattern layer refers to a film layer formed through a single patterning process. A patterning process refers to a process capable of forming at least one pattern with a certain shape. For example, a thin film is formed on a substrate using any of various film deposition processes such as deposition, coating, or sputtering, and then the thin film is patterned to form a film layer containing at least one pattern, which is called a pattern layer. The patterning steps include: coating photoresist, exposure, development, etching, and photoresist stripping. In this embodiment, the positional relationship of multiple patterns belonging to the same pattern layer is referred to as disposal on the same layer.

[0131] In this embodiment, multiple semiconductor sublayers can be arranged along the second direction Y to form multiple transistor structures. Through this arrangement, the semiconductor structure 1000 forms multiple memory cells in the second direction Y, which helps to increase the storage capacity of the semiconductor structure 1000. Furthermore, the isolation structure 700 helps to isolate the first sublayer 110 and the second sublayer 120, allowing each memory cell to perform read and write operations independently, thereby improving the storage stability of the semiconductor structure 1000.

[0132] In other embodiments, such as Figure 9 and Figure 11 As shown, the isolation structure 700 may include an isolation pillar 710 and a second dielectric layer 630. The isolation pillar 710 may include a first sub-pillar 711, a second sub-pillar 712, and a third sub-pillar 713 arranged sequentially along a third direction Z. Exemplarily, the first sub-pillar 711 may penetrate a portion of the second capacitor structure 600 along a first direction X, thereby allowing the first sub-pillar 711 to contact the second dielectric layer 630. The second dielectric layer 630, the first sub-pillar 711, the second sub-pillar 712, and the third sub-pillar 713 together serve to isolate the first sub-layer 110 and the second sub-layer 120.

[0133] The material of the insulating post 710 may include an insulating material. The insulating material may include one or a combination of silicon oxide, silicon nitride, silicon oxynitride, and high dielectric constant insulating materials, or other suitable insulating materials.

[0134] It should be noted that the first sub-pillar 711, the second sub-pillar 712, and the third sub-pillar 713 can all be regular or irregular columnar structures. In some embodiments, the maximum dimension of the first sub-pillar 711 in the third direction Z can be greater than the maximum dimension of the first sub-pillar 711 in the second direction Y, the maximum dimension of the second sub-pillar 712 in the third direction Z can be greater than the maximum dimension of the second sub-pillar 712 in the second direction Y, and the maximum dimension of the third sub-pillar 713 in the third direction Z can be greater than the maximum dimension of the third sub-pillar 713 in the second direction Y. For example, on the YZ plane, the edge of the isolation column 710 can include at least one arc-shaped edge. For example, the first sub-pillar 711, the second sub-pillar 712, and the third sub-pillar 713 can all include arc-shaped edges. With the above configuration, the isolation column 710 as a whole can extend along the third direction Z to isolate the first sub-layer 110 and the second sub-layer 120 arranged along the second direction Y.

[0135] Furthermore, the maximum width of the second sub-pillar 712 in the second direction Y is less than the maximum width of the first sub-pillar 711 in the second direction Y, and the maximum width of the second sub-pillar 712 in the second direction Y is less than the maximum width of the third sub-pillar 713 in the second direction Y, so that the semiconductor layer 100 obtains a larger area.

[0136] In this embodiment, the second dielectric layer 630 and the isolation pillar 710 in the capacitor structure are used to jointly isolate the first sublayer 110 and the second sublayer 120, preventing the first sublayer 110 from connecting with the second sublayer 120. This allows multiple memory cells to operate independently, which is beneficial for improving the storage stability of the semiconductor structure 1000. Furthermore, the above arrangement makes full use of the existing second dielectric layer 630 in the second capacitor structure 600, incorporating the second dielectric layer 630 as part of the isolation structure 700. This helps save materials required for fabricating the isolation structure 700 and reduces the fabrication cost of the semiconductor structure 1000.

[0137] Furthermore, while isolating the first sublayer 110 and the second sublayer 120, the isolation structure 700 also isolates the first capacitor structure 200 connected to the first sublayer 110 and the first capacitor structure 200 connected to the second sublayer 120. Simultaneously, the isolation structure 700 also divides the second capacitor structure 600 into two parts: one part is connected to the first sublayer 110, and the other part is connected to the second sublayer 120.

[0138] With the above setup, a second capacitor structure 600 is formed at the location where the isolation structure 700 was originally required, which helps to increase the storage capacity of the semiconductor structure 1000 and thus increase the storage density of the semiconductor structure 1000.

[0139] In some embodiments, such as Figure 11 and Figure 12 As shown, the semiconductor structure 1000 also includes a gate layer 400 stacked with the semiconductor layer 100. The gate layer 400 may include a first gate layer 410 and a second gate layer 420. The first gate layer 410 is located on one side of the semiconductor layer 100 along the first direction X, and the second gate layer 420 is located on the other side of the semiconductor layer 100 along the first direction X.

[0140] The constituent materials of the gate layer 400 may include conductive materials, including but not limited to one or more combinations of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, and silicides, or other suitable conductive materials. In some examples, the gate layer 400 includes a metal layer, such as a tungsten layer. In some examples, the gate layer 400 includes a doped polysilicon layer. Polysilicon can be doped to a desired doping concentration using suitable dopant to become a conductive material that can be used as the material for the gate layer 400.

[0141] On the plane containing the gate layer 400 (either the first gate layer 410 or the second gate layer 420), the second sub-pillar 712 is spaced apart from the first sub-pillar 711 and the third sub-pillar 713, respectively, and the gate layer 400 is disposed around the second sub-pillar 712. For example, the gate layer 400 may be disposed around the second sub-pillar 712, in which case the gate layer 400 may be located between the first sub-pillar 711 and the second sub-pillar 712, or between the second sub-pillar 712 and the third sub-pillar 713.

[0142] It should be noted here that the plane containing the gate layer 400 can be understood as a cross-section of the semiconductor structure 1000 along the extension direction of the gate layer 400 (the second direction Y and the third direction Z); or, it can be understood as a cross-section of the semiconductor structure 1000 parallel to the second direction Y and the third direction Z, and the cross-section exposes the gate layer 400.

[0143] In addition, the second sub-pillar 712 is spaced apart from the first sub-pillar 711 and the third sub-pillar 713 respectively, and the gate layer 400 is arranged around the second sub-pillar 712, all of which are positional relationships on the same plane where the gate layer 400 is located.

[0144] With the above configuration, the isolation pillar 710 does not restrict the first gate layer 410 from extending along the second direction Y. The first gate layer 410 can extend along the second direction Y to form a word line WL (see reference). Figure 3 and Figure 4 Similarly, the second gate layer 420 can also extend along the second direction Y. The transistor T can be composed of a semiconductor layer 100 and a gate layer 400 adjacent to the semiconductor layer 100. The semiconductor structure 1000 can apply a voltage to the semiconductor layer 100 through the gate layer 400, thereby controlling the transistor T to be turned on or off.

[0145] It should be noted that in this embodiment, when the semiconductor layer 100 of the same layer has multiple semiconductor sub-layers arranged along the second direction Y, the gate layer 400 can extend along the second direction Y, and then one gate layer 400 can apply a voltage to the semiconductor sub-layers located in the same row along the second direction Y.

[0146] In some embodiments, the gate layer 400 may only include the first gate layer 410, without the second gate layer 420, in which case the gate layer 400 and its adjacent semiconductor layer 100 can form a single-gate transistor. In this embodiment, the gate layer 400 includes both the first gate layer 410 and the second gate layer 420, thus forming a dual-gate transistor. Compared to a single-gate transistor, when the voltage of the first gate layer 410 is reduced, the voltage of the second gate layer 420 can be transferred to the semiconductor layer 100 through the common-gate effect, thereby reducing the impact of stress effects and improving the transistor's operational reliability and stability. Furthermore, due to the presence of the second gate layer 420, when the electrical signal changes, the dual-gate transistor can respond and change its conduction state more quickly, improving the transistor's switching speed. Additionally, the second gate layer 420 can also be used to adjust the voltage of the first gate layer 410, expanding the operating voltage range of the dual-gate transistor and thus adapting to more application scenarios.

[0147] In some embodiments, such as Figure 12 As shown, the shapes of the first sub-pillar 711, the second sub-pillar 712, and the third sub-pillar 713 on the same cross-section (YZ plane) can be different. For example, on the plane where the gate layer 400 is located, the area of ​​the second sub-pillar 712 can be smaller than the area of ​​the first sub-pillar 711, and the area of ​​the second sub-pillar 712 can also be smaller than the area of ​​the third sub-pillar 713. The areas of the first sub-pillar 711 and the third sub-pillar 713 can be the same or different.

[0148] With the above configuration, on the plane where the gate layer 400 is located, among the first sub-pillar 711, the second sub-pillar 712, and the third sub-pillar 713, the area of ​​the second sub-pillar 712 is the smallest, so that the gate layer 400 can pass through the gap between the first sub-pillar 711 and the second sub-pillar 712, and also through the gap between the second sub-pillar 712 and the third sub-pillar 713. This facilitates the extension of the gate layer 400 along the second direction Y, so that the semiconductor structure 1000 can apply voltage to the multiple semiconductor sub-layers arranged along the second direction Y through the gate layer 400.

[0149] In some embodiments, reference Figure 9 On the plane where the semiconductor layer 100 is located, the second sub-pillar 712 is connected between the first sub-pillar 711 and the third sub-pillar 713. That is, on the plane where the semiconductor layer 100 is located, the second sub-pillar 712 is in contact with the first sub-pillar 711, and the second sub-pillar 712 is in contact with the third sub-pillar 713.

[0150] With the above configuration, the dielectric layer, the first sub-pillar 711, the second sub-pillar 712, and the third sub-pillar 713 can jointly isolate the first sub-layer 110 and the second sub-layer 120 arranged along the second direction Y, so that the semiconductor structure 1000 can selectively control the first sub-layer 110 and the second sub-layer 120, avoid mutual interference between the first sub-layer 110 and the second sub-layer 120, and improve the working stability of the semiconductor structure 1000.

[0151] In some embodiments, such as Figure 12 and Figure 13 As shown, the semiconductor structure 1000 also includes multiple bit lines BL, which penetrate the semiconductor layer 100 along a first direction X and are connected to the semiconductor layer 100. For example, the bit line BL can be connected to the drain of the semiconductor layer 100. The multiple bit lines BL can be arranged along a second direction Y. When the semiconductor layer 100 in the same layer includes multiple semiconductor sublayers, the multiple bit lines BL can be connected one-to-one with the multiple semiconductor sublayers; for example, one bit line BL connects to one semiconductor sublayer. The third sub-pillar 713 in the isolation pillar 710 is also located between two adjacent bit lines BL along the second direction Y. Figure 9 As shown, on the plane where semiconductor layer 100 is located, the third sub-pillar 713 can contact both bit lines BL adjacent to each other along the second direction Y. Figure 12 As shown, on the plane where the gate layer 400 is located, the third sub-pillar 713 can be spaced apart from the two adjacent bit lines BL.

[0152] With the above configuration, when the transistor is turned on, the bit line BL can perform read or write operations on the first capacitor structure 200 and the second capacitor structure 600. Furthermore, the third sub-pillar 713 can isolate two adjacent bit lines BL along the second direction Y, preventing mutual interference between them and improving the operational stability of the semiconductor structure 1000.

[0153] In some embodiments, such as Figure 14 As shown, the semiconductor layer 100 further includes a third sub-layer 130 and a fourth sub-layer 140 arranged along the second direction Y, wherein the third sub-layer 130 and the first sub-layer 110 are arranged along the third direction Z and are connected to the same bit line BL, and the fourth sub-layer 140 and the second sub-layer 120 are arranged along the third direction Z and are connected to the same bit line BL.

[0154] The semiconductor structure 1000 includes a plurality of first capacitor structures 200. At least one first capacitor structure 200 penetrates a third sublayer 130 along a first direction X, and at least one first capacitor structure 200 penetrates a fourth sublayer 140 along the first direction X.

[0155] For example, the first sub-layer 110 and the third sub-layer 130 can be arranged in a centrally symmetrical configuration with the bit line BL as the symmetry point. Here, "central symmetry" means that the multiple semiconductor layers 100 can include absolute central symmetry and approximate central symmetry. Approximate central symmetry can be understood as the overall structure of the first sub-layer 110 and the third sub-layer 130 exhibiting a symmetrical trend, and local variations may exist in the first sub-layer 110 or the second sub-layer 120.

[0156] Similarly, the second sublayer 120 and the fourth sublayer 140 can be arranged in a centrally symmetrical manner with the bit line BL as the point of symmetry. The multiple first capacitor structures 200 can also be arranged in a centrally symmetrical manner with the bit line BL as the point of symmetry, which will not be elaborated further in this disclosure.

[0157] With the above configuration, the storage cells can be arranged along the second direction Y and the third direction Z, and stacked along the first direction X, which is beneficial to forming a semiconductor structure 1000 of 3D stacked storage cells and to improving the storage capacity of the semiconductor structure 1000.

[0158] In this embodiment, a bit line BL can be connected to the first sub-layer 110 and the third sub-layer 130. Thus, a bit line BL can transmit electrical signals to two columns of memory cells, which helps reduce the number of bit lines BL, increases the storage density of the semiconductor structure 1000, and reduces the fabrication cost of the semiconductor structure 1000.

[0159] In some embodiments, such as Figure 14 As shown, the semiconductor structure 1000 also includes a third capacitor structure 800, which is located between the third sublayer 130 and the fourth sublayer 140. The third capacitor structure 800 and the second capacitor structure 600 can be centrally symmetrically arranged with the bit line BL as the point of symmetry.

[0160] In this embodiment, as shown in Figure 15, the third capacitor structure 800 includes a fifth electrode structure 810, a sixth electrode structure 820, and a third dielectric layer 830. The fifth electrode structure 810 penetrates the semiconductor layer 100 along a first direction X. The sixth electrode structure 820 penetrates the semiconductor layer 100 along the first direction X, and includes a third sub-electrode 821 and a fourth sub-electrode 822 spaced apart along a second direction Y. The third sub-electrode 821 is located between the third sub-layer 130 and the fifth electrode structure 810, and is connected to the third sub-layer 130. The fourth sub-electrode 822 is located between the fourth sub-layer 140 and the fifth electrode structure 810, and is connected to the fourth sub-layer 140.

[0161] The third dielectric layer 830 extends through the semiconductor layer 100 along the first direction X and is located between the fifth electrode structure 810 and the sixth electrode structure 820. Exemplarily, the third dielectric layer 830 may be disposed around the fifth electrode structure 810.

[0162] In this embodiment, the isolation structure 700 may further include a third dielectric layer 830. The third dielectric layer 830 and the isolation pillar 710 together isolate the third sub-layer 130 and the fourth sub-layer 140. The isolation pillar 710 may include a fourth sub-pillar 714 and a fifth sub-pillar 715. The fourth sub-pillar 714 may be located between the third sub-pillar 713 and the fifth sub-pillar 715, and the third dielectric layer 830 may penetrate the fifth sub-pillar 715 along the first direction X. With this configuration, the third sub-pillar 713, the fourth sub-pillar 714, the fifth sub-pillar 715, and the third dielectric layer 830 can jointly isolate the third sub-layer 130 and the fourth sub-layer 140.

[0163] For example, the isolation column 710 can be a centrally symmetric structure or an approximately centrally symmetric structure.

[0164] With the above configuration, the storage cells can be arranged along the second direction Y and the third direction Z, and stacked along the first direction X, which is beneficial to forming a semiconductor structure 1000 of 3D stacked storage cells and to improving the storage capacity of the semiconductor structure 1000.

[0165] Furthermore, the isolation structure 700 can also extend along the third direction Z, which is beneficial for isolating adjacent memory cells along the second direction Y.

[0166] In some embodiments, reference Figure 8 and Figure 15 The first electrode structure 210 includes a first conductive portion 211 and a second conductive portion 212. The first conductive portion 211 penetrates the semiconductor layer 100 along a first direction X. The second conductive portion 212 also penetrates the semiconductor layer 100 along the first direction X, and the second conductive portion 212 is disposed around the first conductive portion 211. The second conductive portion 212 is in contact with the first dielectric layer 230.

[0167] In this embodiment, both the first conductive part 211 and the second conductive part 212 can be made of conductive materials. Conductive materials include, but are not limited to, one or more combinations of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, and silicides, or other suitable conductive materials.

[0168] The materials used to make the first conductive part 211 and the second conductive part 212 can be the same or different.

[0169] When the first conductive part 211 and the second conductive part 212 are made of the same material, the first electrode structure 210 can be a complete columnar structure, and the first conductive part 211 and the second conductive part 212 can be integrally formed, so there is no distinction between the first conductive part 211 and the second conductive part 212.

[0170] When the first conductive part 211 and the second conductive part 212 are made of different materials, for example, the first conductive part 211 may be made of tungsten and the second conductive part 212 may be made of titanium nitride.

[0171] With the above configuration, the constituent materials of the first conductive part 211 and the second conductive part 212 can be selected according to different needs. Since the second conductive part 212 is in contact with the first dielectric layer 230, the second conductive part 212 can be made of titanium nitride to reduce contact resistance. The first conductive part 211 can be made of a material with good conductivity, such as tungsten, to facilitate the connection of the first conductive part 211 to a reference voltage.

[0172] In some embodiments, such as Figure 8 and Figure 15 As shown, the first conductive part 211 and the second electrode structure 220 do not overlap in the first direction X.

[0173] With the above configuration, since the first conductive part 211 and the second electrode structure 220 do not overlap in the first direction X, it is convenient to extend the second electrode structure 220 along the first direction X to increase the capacitance value of the first capacitor structure 200, thereby increasing the storage capacity of the semiconductor structure 1000.

[0174] This disclosure also provides a method for fabricating a semiconductor structure 1000 in some embodiments, which is described below in conjunction with... Figures 16 to 61 The method for preparing the semiconductor structure 1000 in some of the above embodiments will be explained.

[0175] like Figure 16 As shown, the method for fabricating the semiconductor structure 1000 includes: S1 to S2.

[0176] S1, Forming a semiconductor layer.

[0177] like Figure 17As shown, in this step, a thin film deposition process can be used to form a semiconductor layer 100 and a sacrificial layer 151 alternately stacked along the first direction X to form a stacked structure 150. The thin film deposition process includes any one of Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), and Atomic Layer Deposition (ALD).

[0178] For example, the semiconductor layer 100 can be formed using a semiconductor material. Semiconductor materials include, for example, monocrystalline silicon, polycrystalline silicon, monocrystalline germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials.

[0179] In this step, a portion of the semiconductor layer 100 may be doped to form the source and drain. The materials for the source and drain may include semiconductor materials doped with P-type or N-type dopants. P-type dopants include boron or gallium. N-type dopants include phosphorus or arsenic.

[0180] For example, germanium-silicon can be used to form the sacrificial layer 151, or other materials with different etching rates than the semiconductor layer 100 can be used to selectively remove the sacrificial layer 151 in subsequent steps. The thickness of the sacrificial layer 151 in the first direction X can be greater than the thickness of the semiconductor layer 100 in the first direction X.

[0181] like Figure 18 As shown, after forming the semiconductor layer 100 and before forming the capacitor structure, the process further includes steps S11 to S13.

[0182] S11. An isolation pillar is formed, which penetrates the stacked structure along a first direction. The semiconductor layer in the same layer includes a first sub-layer and a second sub-layer arranged along a second direction. The isolation pillar is located between the first sub-layer and the second sub-layer, and the second direction is parallel to the semiconductor layer.

[0183] In this step, such as Figure 17 and Figure 19As shown, the first structural hole 101, the second structural hole 102, the third structural hole 103, the fourth structural hole 104, and the fifth structural hole 105 can be formed in the same process step. The first structural hole 101, the second structural hole 102, the third structural hole 103, the fourth structural hole 104, and the fifth structural hole 105 all penetrate the stacked structure 150 along a first direction X. The first structural hole 101, the second structural hole 102, the third structural hole 103, the fourth structural hole 104, and the fifth structural hole 105 can be formed by any suitable manufacturing process. For example, a patterned photoresist layer can be formed over the stacked structure 150. Here, the patterned photoresist layer can be formed, for example, sequentially using a coating process, an exposure process, and a development process. The patterned photoresist layer can expose the portions of the stacked structure 150 used to form the first structural hole 101, the second structural hole 102, the third structural hole 103, the fourth structural hole 104, and the fifth structural hole 105. An appropriate etching process can be performed to remove portions of the stacked structure 150 used to form the first structural hole 101, the second structural hole 102, the third structural hole 103, the fourth structural hole 104, and the fifth structural hole 105. For example, the etching process may include a dry etching process.

[0184] In this step, by forming the first structural hole 101, the second structural hole 102, the third structural hole 103, the fourth structural hole 104 and the fifth structural hole 105 in the same process step, the drilling process step is combined, which helps to reduce the number of process steps and reduce the cost of preparing the semiconductor structure 1000.

[0185] refer to Figure 19 , Figure 20 and Figure 21 After forming the first structural hole 101, the second structural hole 102, the third structural hole 103, the fourth structural hole 104, and the fifth structural hole 105, an isolation layer 152 can be formed within the first structural hole 101, the second structural hole 102, the third structural hole 103, the fourth structural hole 104, and the fifth structural hole 105 using an ALD deposition process. The isolation layer 152 covers the sidewalls of the first structural hole 101, the second structural hole 102, the third structural hole 103, the fourth structural hole 104, and the fifth structural hole 105.

[0186] For example, the material of the isolation layer 152 may be silicon oxide.

[0187] After forming an isolation layer 152 in the first structural hole 101, the second structural hole 102, the third structural hole 103, the fourth structural hole 104, and the fifth structural hole 105, a sacrificial material, such as carbon, can be deposited in the first structural hole 101, the second structural hole 102, the third structural hole 103, the fourth structural hole 104, and the fifth structural hole 105 by employing one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD, thereby forming a first sacrificial pillar 1011, a second sacrificial pillar 1021, a third sacrificial pillar 1031, a fourth sacrificial pillar 1041, and a fifth sacrificial pillar 1051, respectively, in the first structural hole 101, the second structural hole 102, the third structural hole 103, the fourth structural hole 104, and the fifth structural hole 105.

[0188] refer to Figure 21 and Figure 22 After forming the first sacrificial pillar 1011, the second sacrificial pillar 1021, the third sacrificial pillar 1031, the fourth sacrificial pillar 1041, and the fifth sacrificial pillar 1051, isolation material can be deposited on the stacked structure 150 to form an isolation material layer 153. In the first direction X, the isolation material layer 153 can cover the first sacrificial pillar 1011, the second sacrificial pillar 1021, the third sacrificial pillar 1031, the fourth sacrificial pillar 1041, and the fifth sacrificial pillar 1051. This configuration facilitates the selective removal of sacrificial pillars in subsequent steps, such as selectively removing the first sacrificial pillar 1011. Furthermore, in subsequent etching steps, the isolation material layer 153 can protect the structural morphology of sacrificial pillars that do not need to be removed from being damaged. For example, the composition of the isolation material layer 153 can be silicon oxide. When the composition of the isolation material layer 153 is the same as that of the isolation layer 152, the two can be connected together, and the boundary is difficult to distinguish, forming a near-integral structure.

[0189] refer to Figure 21 , Figure 22 , Figure 23 and Figure 24After forming an isolation material layer 153 on the stacked structure 150, the isolation material layer 153 covering the first sacrificial pillar 1011 can be removed by a dry etching process after forming a patterned photoresist layer on the stacked structure 150, thereby exposing the first sacrificial pillar 1011. The first sacrificial pillar 1011 and the isolation layer 152 located within the first structural aperture 101 can be removed to open the first structural aperture 101. Exemplarily, when the material of the first sacrificial pillar 1011 includes carbon, the process of removing all the first sacrificial pillars 1011 within the first structural aperture 101 can include ashing. Exemplarily, a dry etching process can also be used to remove the first sacrificial pillar 1011. In some other examples, other processes that can remove sacrificial materials, such as wet etching, can also be used to remove the first sacrificial pillar 1011, which are not specifically limited in this disclosure. In this step, a wet etching process can be used to remove the isolation layer 152 located within the first structural aperture 101.

[0190] refer to Figure 24 and Figure 25 After opening the first structural hole 101, for example, a wet etching process can be used to inject etching solution into the first structural hole 101 to remove the sacrificial layer 151.

[0191] refer to Figure 25 , Figure 26 , Figure 27 , Figure 28 and Figure 29 After removing the sacrificial layer 151, a first dielectric layer 510, a second dielectric layer 520, and a third dielectric layer 530 can be sequentially formed at the location of the original sacrificial layer 151 using one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD, to form a dielectric layer 500. The first dielectric layer 510, the second dielectric layer 520, and the third dielectric layer 530 can be arranged sequentially in a direction away from the semiconductor layer 100. Specifically, the first dielectric layer 510 is disposed around the semiconductor layer 100, the second dielectric layer 520 is disposed around the first dielectric layer 510, and the third dielectric layer 530 is disposed around the second dielectric layer 520.

[0192] For example, the materials of the first dielectric layer 510, the second dielectric layer 520, and the third dielectric layer 530 may all include insulating materials. The insulating material may include one or more of silicon oxide, silicon nitride, silicon oxynitride, and high dielectric constant insulating materials, or may be other suitable insulating materials.

[0193] It should be noted that in some subsequent steps, a portion of the second dielectric layer 520 needs to be replaced with the gate layer 400. Therefore, the material of the second dielectric layer 520 needs to be different from the material of the first dielectric layer 510, and also different from the material of the third dielectric layer 530. Thus, in some subsequent steps, a portion of the second dielectric layer 520 can be selectively removed. For example, the material of the first dielectric layer 510 may include silicon oxide, the material of the second dielectric layer 520 may include silicon nitride, and the material of the third dielectric layer 530 may include silicon oxide.

[0194] refer to Figure 29 , Figure 30 , Figure 31 and Figure 32 After the dielectric layer 500 is formed, a wet etching process can be used to remove a portion of the dielectric layer 500 covering the hole wall of the first structural hole 101, for example, by sequentially removing the third dielectric layer 530, the second dielectric layer 520 and the first dielectric layer 510, thereby exposing the semiconductor layer 100 in the first structural hole 101.

[0195] It should be noted that the reference Figure 32 , Figure 33 and Figure 34 In the above steps, if the material of the third dielectric layer 530 is the same as that of the first dielectric layer 510, then when a portion of the first dielectric layer 510 is removed using a wet etching process, a portion of the third dielectric layer 530 will also be removed. Therefore, on the YZ plane, a portion of the second dielectric layer 520 will protrude from the first dielectric layer 510 and the third dielectric layer 530. To improve the morphological regularity of the semiconductor structure 1000, refer to... Figure 28 , Figure 29 and Figure 30 After removing a portion of the first dielectric layer 510 and before removing a portion of the semiconductor layer 100 through the first structural hole 101, the second dielectric layer 520 protruding from the first dielectric layer 510 and the third dielectric layer 530 can be removed through the first structural hole 101 to maintain the regularity of the semiconductor structure 1000 morphology. By removing the portion of the second dielectric layer 520 protruding from the first dielectric layer 510 and the third dielectric layer 530 through the above steps, it is beneficial to maintain the sidewalls of the first structural hole 101 to be approximately flush, prevent uneven sidewalls, and improve the situation where material in recessed areas is difficult to remove.

[0196] refer to Figure 35Through the first structural hole 101, a portion of the semiconductor layer 100 can be removed using a wet etching process. By removing a portion of the semiconductor layer 100, the same semiconductor layer 100 is divided into multiple semiconductor sub-layers. For example, a portion of the semiconductor layer 100 is removed to expose a portion of the isolation layer 152 located within the second structural hole 102 and the isolation layer 152 located within the third structural hole 103. Through the above steps, the semiconductor layer 100 can be divided into multiple spaced semiconductor sub-layers, such as a first sub-layer 110 and a second sub-layer 120 arranged along the second direction Y. The first structural hole 101, the second structural hole 102, and the third structural hole 103 are located between the first sub-layer 110 and the second sub-layer 120.

[0197] refer to Figure 35 and Figure 36 After removing part of the semiconductor layer 100, an insulating material can be filled into the first structural hole 101 using one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD, to form a partial isolation pillar 710.

[0198] The insulating material may include one or a combination of silicon oxide, silicon nitride, silicon oxynitride, and high dielectric constant insulating materials, or other suitable insulating materials.

[0199] S12. Form a gate layer. The gate layer is stacked with the semiconductor layer. The gate layer includes a first gate layer and a second gate layer. The first gate layer is located on one side of the semiconductor layer along the first direction, and the second gate layer is located on the other side of the semiconductor layer along the first direction.

[0200] like Figure 37 , Figure 38 and Figure 39 As shown, in this step, the second structural hole 102 can be opened by removing the isolation material layer 153 covering the second sacrificial pillar 1021 along the first direction X, the second sacrificial pillar 1021, and the isolation layer 152 located in the second structural hole 102.

[0201] For example, when the material of the second sacrificial pillar 1021 includes carbon, the process of removing all the second sacrificial pillars 1021 located within the second structural hole 102 may include ashing. After removing the second sacrificial pillars 1021, a wet etching process may be used to remove the isolation layer 152 located within the second structural hole 102.

[0202] refer to Figure 39 , Figure 40 and Figure 41 After opening the second structural hole 102, remove part of the dielectric layer 500 covering the sidewall of the second structural hole 102 to expose the second dielectric layer 520.

[0203] refer to Figure 41 and Figure 42 A portion of the second dielectric layer 520 is removed through the second structural hole 102 to form the first filling space 171. For example, a wet etching process can be used to remove the second dielectric layer 520. In this step, since the material of the second dielectric layer 520 is different from that of the first dielectric layer 510 and the third dielectric layer 530, the etching amount of the first dielectric layer 510 and the third dielectric layer 530 is small or negligible when the second dielectric layer 520 is processed by wet etching, which is beneficial to protecting the structural morphology of the first dielectric layer 510 and the third dielectric layer 530 from being damaged.

[0204] Furthermore, in this step, there can be multiple second structural holes 102. After the etching solution is introduced into some of the second structural holes 102, the etching solution removes the second dielectric layer 520, enabling the multiple second structural holes 102 to communicate with each other. Therefore, the etching solution can quickly flow out from other second structural holes 102, which helps reduce the amount of material or other impurities (such as substances obtained from the reaction between the etching solution and the second dielectric layer 520) remaining in the first filling space 171. Through the above process steps, the integrity of the gate layer 400 morphology is improved, thereby optimizing the electrical performance of the gate layer 400.

[0205] refer to Figure 42 , Figure 43 and Figure 44 After forming the first filling space 171, a first conductive material 181 can be filled into the first filling space 171 using one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD, to form a gate layer 400. The gate layer 400 located on one side of the semiconductor layer 100 along the first direction X is the first gate layer 410, and the gate layer 400 located on the other side of the semiconductor layer 100 along the first direction X is the second gate layer 420. A first dielectric layer located between the semiconductor layer 100 and the first gate layer 410 constitutes a gate dielectric layer, and a first dielectric layer located between the semiconductor layer 100 and the second gate layer 420 also constitutes a gate dielectric layer.

[0206] For example, the first conductive material 181 includes, but is not limited to, one or more combinations of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, silicide, or other suitable conductive materials.

[0207] During the step of filling the first filling space 171 with the first conductive material 181, the second structural hole 102 is also filled with the first conductive material 181. In order to isolate the multiple gate layers 400 stacked along the first direction X from each other, after filling with the first conductive material 181, an etching process can be used to remove the first conductive material 181 located in the second structural hole 102 until the dielectric layer 500 is exposed.

[0208] refer to Figure 43 , Figure 44 , Figure 45 and Figure 46 After removing the first conductive material 181 located in the second structural hole 102 to expose the dielectric layer 500, an insulating material can be filled in the second structural hole 102 using one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD, to form a partial isolation pillar 710.

[0209] In some embodiments, such as Figure 44 and Figure 45 As shown, when a portion of the dielectric layer 500 covering the sidewall of the second structural hole 102 is removed by wet etching through the second structural hole 102, since the etching solution cannot be precisely controlled to stop etching, a portion of the semiconductor layer 100 will be exposed in the second structural hole 102 after this step.

[0210] After the first conductive material 181 is filled into the first filling space 171, in order to isolate the multiple gate layers 400 stacked along the first direction X from each other, a portion of the gate layers 400 is removed through the second structural hole 102 using a wet etching process until the dielectric layer 500 is exposed. A portion of the semiconductor layer 100 is also exposed within the second structural hole 102. Consequently, the semiconductor layer 100 protrudes from the gate layer 400, which affects the control performance of the gate layer 400 over the semiconductor layer 100.

[0211] Based on this, in some embodiments, such as Figure 44 and Figure 45 As shown, after the first conductive material 181 is filled in the first filling space 171 and before the insulating material is filled in the second structural hole, a portion of the semiconductor layer 100 can be removed by a wet etching process through the second structural hole so that the edge of the semiconductor layer 100 is approximately aligned with the edge of the gate layer 400, which is beneficial to optimizing the control performance of the gate layer 400 on the semiconductor layer 100.

[0212] S13. A bit line is formed, which penetrates the stacked structure along a first direction and is connected to the semiconductor layer.

[0213] like Figure 47 , Figure 48 and Figure 49As shown, in this step, the third structural hole 103 can be opened by removing the isolation material layer 153 covering the third sacrificial pillar 1031 in the first direction X, the third sacrificial pillar 1031, and the isolation layer 152 located in the third structural hole 103.

[0214] refer to Figure 49 and Figure 50 The dielectric layer 500 covering the sidewall of the third structural hole 103 can be removed by wet etching through the third structural hole 103 to expose the semiconductor layer 100.

[0215] refer to Figure 49 , Figure 50 , Figure 51 and Figure 52 After the semiconductor layer 100 is exposed in the third structural hole 103, a second conductive material 182 can be filled in the third structural hole 103 by one or more thin film deposition processes including but not limited to PVD, CVD, and ALD to form a bit line BL, which can then be connected to the semiconductor layer 100.

[0216] For example, the second conductive material 182 includes, but is not limited to, one or more combinations of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, and silicides, or may be other suitable conductive materials. The second conductive material 182 may be the same as or different from the first conductive material 181 used in forming the gate layer 400. For example, the material of the gate layer 400 may include tungsten, and the material of the bit line BL may include polysilicon.

[0217] refer to Figure 50 , Figure 51 , Figure 52 , Figure 53 and Figure 54 After forming the bit line BL, a portion of the bit line BL can be etched back, and a third conductive material 183 can be filled into the third structural hole 103 using one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD, to form a contact 160. The contact 160 and the bit line BL are stacked along the first direction X. (Reference) Figure 49 and Figure 50 In this step, when the third conductive material 183 is filled into the third structural hole 103, a portion of the third conductive material 183 will be located outside the third structural hole 103. Therefore, after filling the third conductive material 183 into the third structural hole 103, the surface of the third conductive material 183 can be planarized by chemical mechanical polishing (CMP), for example, making the upper surface of the contact 160 flush with the upper surface of the stacked structure 150.

[0218] The third conductive material 183 includes, but is not limited to, one or more combinations of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, and silicides, or may be other suitable conductive materials.

[0219] The volume of bit line BL is larger than that of contact 160. Therefore, the amount of material required to fabricate bit line BL is greater than that required to fabricate contact 160. Thus, in this embodiment, the material of contact 160 can be different from the material of bit line BL to save on the fabrication cost of semiconductor structure 1000.

[0220] refer to Figure 54 and Figure 55 After the contact 160 is formed, a fourth dielectric layer 944 can be formed on the stacked structure 150 using one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD. The fourth dielectric layer 944 is stacked with the stacked structure 150 along the first direction X, and the fourth dielectric layer 944 is located on the side of the contact 160 away from the bit line BL. The material of the fourth dielectric layer 944 may include an insulating material.

[0221] For example, the insulating material may include one or a combination of silicon oxide, silicon nitride, silicon oxynitride, and high dielectric constant insulating materials, or other suitable insulating materials.

[0222] S2. A first capacitor structure is formed, comprising: a first electrode structure, a second electrode structure, and a first dielectric layer. The first electrode structure penetrates the semiconductor layer along a first direction. The second electrode structure penetrates the semiconductor layer along the first direction and is located between the semiconductor layer and the first electrode structure. The second electrode structure is arranged around the first electrode structure. The first dielectric layer is located between the first electrode structure and the second electrode structure. The first direction is parallel to the thickness direction of the semiconductor layer.

[0223] like Figure 56 , Figure 57 and Figure 58 As shown, in this step, the fourth structural hole 104 can be opened by removing the isolation material layer 153 covering the fourth sacrificial post 1041, the fourth sacrificial post 1041, and the isolation layer 152 located in the fourth structural hole 104 in the first direction X. Similarly, the fifth structural hole 105 can be opened by removing the isolation material layer 153 covering the fifth sacrificial post 1051, the fifth sacrificial post 1051, and the isolation layer 152 located in the fifth structural hole 105.

[0224] The fourth structural hole 104 and the fifth structural hole 105 are arranged along the second direction Y. The fourth structural hole penetrates the stacked structure 150 along the first direction X, and the fifth structural hole penetrates the stacked structure 150 and part of the isolation pillar 710 along the first direction X.

[0225] For example, in the same step, a dry etching process can be used to remove the isolation material layer 153 covering the fourth sacrificial pillar 1041 and the isolation material layer 153 covering the fifth sacrificial pillar 1051 in the first direction X.

[0226] For example, when the materials of the fourth sacrificial pillar 1041 and the fifth sacrificial pillar 1051 both include carbon, the process of removing all the fourth sacrificial pillars 1041 located in the fourth structural hole 104 and all the fifth sacrificial pillars 1051 located in the fifth structural hole 105 may include ashing. After removing the fourth sacrificial pillars 1041 and the fifth sacrificial pillars 1051, the isolation layer 152 located in the fourth structural hole 104 and the fifth structural hole 105 may be removed by a wet etching process.

[0227] In some embodiments, reference Figure 58 , Figure 59 and Figure 60 The isolation layer 152 and the third dielectric layer 530 can be made of the same material. For example, both the isolation layer 152 and the third dielectric layer 530 may be made of silicon oxide. Therefore, in the step of removing the isolation layer 152 located in the fourth structural hole 104 and the fifth structural hole 105 using a wet etching process, the third dielectric layer 530 exposed in the fourth structural hole 104 and the fifth structural hole 105 can also be removed, thereby exposing the semiconductor layer 100 in the fourth structural hole 104 and the fifth structural hole 105.

[0228] refer to Figure 60 , Figure 61 and Figure 62 After removing the isolation layer 152 located in the fourth structural hole 104 and the fifth structural hole 105, a wet etching process can be used to remove part of the semiconductor layer 100 and part of the first dielectric layer 510 through the fourth structural hole 104 and the fifth structural hole 105, so that the semiconductor layer 100 and the first dielectric layer 510 are recessed into the second dielectric layer 520 and the third dielectric layer 530 to form the second filling space 172 and the third filling space 173.

[0229] refer to Figure 62 , Figure 63 and Figure 64 After forming the second filling space 172 and the third filling space 173, the first dielectric layer 510 located in the second filling space 172 and the third filling space 173 can be removed by a wet etching process. Then, a portion of the semiconductor layer 100 can be doped through the fourth structural via 104 and the fifth structural via 105, for example, by using a P-type dopant to dope a portion of the semiconductor layer 100, thereby forming a source electrode that connects to the first capacitor structure 200 and the second capacitor structure 600 formed in subsequent steps. The P-type dopant includes boron or gallium.

[0230] refer to Figure 64 , Figure 65 , Figure 66 , Figure 67 and Figure 68 After doping a portion of the semiconductor layer 100, a second electrode structure 220 and a fourth electrode structure 620 can be formed in the second filling space 172 and the third filling space 173, respectively, using one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD.

[0231] In this step, refer to Figure 65 and Figure 66 Electrode layers 154 can be formed in both the second filling space 172 and the third filling space 173 using one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD. The electrode layers 154 fill the second filling space 172 and the third filling space 173, and also cover the sidewalls of the fourth structural hole 104 and the fifth structural hole 105.

[0232] For example, the material of the electrode layer 154 may include one or more of the following materials: W, Al, Cu, Ag, Au, Co, Pt, Ni, Ti, Ta, TiN, TaN, TaC, TaSiN, NiSi, CoSi, TiAl, and WSi.

[0233] refer to Figure 62 , Figure 63 , Figure 64 , Figure 65 , Figure 66 , Figure 67 and Figure 68 After electrode layers 154 are formed in both the second filling space 172 and the third filling space 173, a portion of the electrode layers 154 can be removed using a wet etching process through the fourth structural hole 104 and the fifth structural hole 105. For example, the electrode layer 154 covering the sidewall of the fourth structural hole 104 can be removed, leaving the electrode layer 152 in the second filling space. The electrode layer 154 remaining in the second filling space 172 can be recessed within the second dielectric layer 520 to form a plurality of second electrode structures 220 stacked along the first direction X in the second filling space 172. For example, the electrode layer 154 covering the sidewall of the fifth structural hole 105 can be removed, leaving the electrode layer 154 in the third filling space 173. The electrode layer 154 remaining in the third filling space 173 can be recessed within the second dielectric layer 520 to form a fourth electrode structure 620.

[0234] In the above steps, at least the electrode layers 154 located at both ends of the fifth structural hole 105 along the third direction Z are removed so that the electrode layers 154 located in the same YZ plane are broken, thereby forming first sub-electrodes 621 and second sub-electrodes 622 spaced apart along the second direction Y, so that a plurality of first sub-electrodes 621 and a plurality of second sub-electrodes 622 stacked along the first direction X are formed in the third filling space 173.

[0235] refer to Figure 68 , Figure 69 and Figure 70 After forming the second electrode structure 220 and the fourth electrode structure 620, one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD, can be used to form the first dielectric layer 230 and the second dielectric layer 630 through the fourth structural hole and the fifth structural hole, respectively.

[0236] A first dielectric layer 230 covers the wall of the fourth structural hole and penetrates the plurality of semiconductor layers 100 and the second electrode structure 220 along the first direction X. A second dielectric layer 630 covers the wall of the fifth structural hole and penetrates the plurality of semiconductor layers 100 and the fourth electrode structure 620 along the first direction X.

[0237] For example, the materials of the first dielectric layer 230 and the second dielectric layer 630 may include high-k (k greater than 2.8) dielectric materials to increase the capacitance value per unit area of ​​the capacitor. In specific embodiments, the first dielectric layer 230 and the second dielectric layer 630 may include one or more materials selected from HfO2, TiO2, HfZrO, HfSiNO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, or BaSrTiO.

[0238] In this step, the first dielectric layer 230 does not completely fill the fourth structural via 104, and the second dielectric layer 630 does not completely fill the fifth structural via 105. Furthermore, the second dielectric layer 630 can contact the isolation pillar 710. The second dielectric layer 630 and the isolation pillar 710 together constitute the isolation structure 700. The isolation structure 700 is located between the first sublayer 110 and the second sublayer 120 arranged along the second direction Y.

[0239] After forming the first dielectric layer 230 and the second dielectric layer 630, one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD, can be used to deposit electrode materials in the fourth structural hole 104 and the fifth structural hole 105 to form the first electrode structure 210 and the third electrode structure 610, respectively. The first electrode structure 210 is located on the side of the first dielectric layer 230 facing away from the stacked structure 150, and the first dielectric layer 230 is disposed around the first electrode structure 210. The first electrode structure 210, the second electrode structure 220, and the first dielectric layer 230 together constitute the first capacitor structure 200. The third electrode structure 610 is located on the side of the second dielectric layer 630 facing away from the stacked structure 150, and the second dielectric layer 630 is disposed around the third electrode structure 610. The third electrode structure 610, the fourth electrode structure 620, and the second dielectric layer 630 together constitute the second capacitor structure 600.

[0240] For example, in this step, the first electrode structure 210 can be formed through two deposition processes. For instance, a second conductive portion 212 can be formed on the surface of the first dielectric layer 230 facing away from the stacked structure 150 using an ALD process, and then a first conductive portion 211 is formed on the side of the second conductive portion 212 facing away from the first dielectric layer 230 using a thin film deposition process. Both the first conductive portion 211 and the second conductive portion 212 penetrate the stacked structure 150 along a first direction X, and the second conductive portion 212 is disposed around the first conductive portion 211. The first conductive portion 211 and the second conductive portion 212 can together constitute the first electrode structure 210. The constituent materials of the first conductive portion 211 and the second conductive portion 212 can be different; for example, the constituent material of the first conductive portion 211 is tungsten, and the constituent material of the second conductive portion 212 is titanium nitride.

[0241] The first capacitor structure 200 formed through the above steps includes a second electrode structure 220 arranged around the first electrode structure 210. The peripheral surface of the first electrode structure 210 and the inner surface of the second electrode structure 220 are directly opposite each other. By simply increasing the thickness of the second electrode structure 220 in the first direction X, the facing area between the first electrode structure 210 and the second electrode structure 220 can be increased, thereby increasing the capacitance value of the first capacitor structure 200. This arrangement simplifies the process of increasing the facing area between the first electrode structure 210 and the second electrode structure 220, further improving the capacitance value of the first capacitor structure 200 and thus increasing the storage capacity of the semiconductor structure 1000.

[0242] Furthermore, the above configuration does not increase the dimensions of the semiconductor structure 1000 in the second direction Y and the third direction Z. This is beneficial to increase the facing area between the first electrode plate and the second electrode plate and improve the capacitance value of the semiconductor structure 1000 without increasing the dimensions of the semiconductor structure 1000 in the second direction Y and the third direction Z.

[0243] In addition, to increase the dimensions of the first electrode structure 210 and the second electrode structure 220 in the first direction X, it is only necessary to increase the thickness of the semiconductor layer 100 when forming the stacked structure 150, or to increase the thickness of the first dielectric layer in the first direction X. This will increase the dimensions of the first electrode structure 210 and the second electrode structure 220 in the first direction X without adding any new process steps. The process is relatively simple and helps to reduce the difficulty of fabricating the semiconductor structure 1000.

[0244] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: Semiconductor layer and first capacitor structure; The first capacitor structure includes: A first electrode structure extends through the semiconductor layer along a first direction; the first direction is parallel to the thickness direction of the semiconductor layer. The second electrode structure penetrates the semiconductor layer along the first direction and is located between the semiconductor layer and the first electrode structure. The second electrode structure is arranged around the first electrode structure. The first dielectric layer is located between the first electrode structure and the second electrode structure.

2. The semiconductor structure according to claim 1, characterized in that, The first electrode structure has a reference surface parallel to the semiconductor layer. The reference surface has a circular shape and a diameter of L. The second electrode structure has a dimension of D in the first direction. D and L satisfy the following formula: D > (2 / 3)L.

3. The semiconductor structure according to claim 1, characterized in that, The second electrode structure does not overlap with the first electrode structure in the first direction.

4. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure includes a plurality of semiconductor layers stacked along the first direction; The first capacitor structure includes a plurality of second electrode structures stacked along the first direction, and one second electrode structure is connected to one of the semiconductor layers; The first electrode structure penetrates through a plurality of second electrode structures along the first direction; the first dielectric layer penetrates through a plurality of second electrode structures along the first direction, and the first dielectric layer is disposed around the first electrode structure.

5. The semiconductor structure according to claim 1, characterized in that, The semiconductor layer includes a first sub-layer and a second sub-layer arranged along a second direction; at least one first capacitor structure penetrates the first sub-layer, and at least one first capacitor structure penetrates the second sub-layer. The semiconductor structure further includes a second capacitor structure, which is located between the first sub-layer and the second sub-layer. The second direction intersects with the first direction; The second capacitor structure includes: A third electrode structure extends through the semiconductor layer along the first direction; A fourth electrode structure extends through the semiconductor layer along the first direction. The fourth electrode structure includes a first sub-electrode and a second sub-electrode spaced apart along the second direction. The first sub-electrode is located between the first sub-layer and the third electrode structure, and the second sub-electrode is located between the second sub-layer and the third electrode structure. The second dielectric layer extends through the semiconductor layer along the first direction and is located between the third electrode structure and the fourth electrode structure.

6. The semiconductor structure according to claim 5, characterized in that, The semiconductor structure includes a plurality of semiconductor layers stacked along the first direction; The second capacitor structure includes a plurality of fourth electrode structures stacked along the first direction, and one of the fourth electrode structures is connected to one of the semiconductor layers; The third electrode structure penetrates through multiple fourth electrode structures along the first direction; the second dielectric layer penetrates through multiple fourth electrode structures along the first direction, and the second dielectric layer is arranged around the third electrode structure.

7. The semiconductor structure according to claim 5, characterized in that, The semiconductor structure includes an isolation structure that extends through the semiconductor layer along the first direction and is located between the first sub-layer and the second sub-layer.

8. The semiconductor structure according to claim 7, characterized in that, The isolation structure includes an isolation pillar and a second dielectric layer; The isolation column includes a first sub-column, a second sub-column, and a third sub-column arranged sequentially along a third direction; the third direction intersects the plane containing the first direction and the second direction.

9. The semiconductor structure according to claim 8, characterized in that, The semiconductor structure further includes a gate layer stacked with the semiconductor layer. The gate layer includes a first gate layer and a second gate layer. The first gate layer is located on one side of the semiconductor layer along the first direction, and the second gate layer is located on the other side of the semiconductor layer along the first direction. On the plane where the gate layer is located, the second sub-pillar is disposed at intervals from the first sub-pillar and the third sub-pillar, and the gate layer is disposed around the second sub-pillar.

10. The semiconductor structure according to claim 9, characterized in that, On the plane where the gate layer is located, the area of ​​the second sub-pillar is smaller than the area of ​​the first sub-pillar, and the area of ​​the second sub-pillar is smaller than the area of ​​the third sub-pillar.

11. The semiconductor structure according to claim 8, characterized in that, On the plane where the semiconductor layer is located, the second sub-pillar is connected between the first sub-pillar and the third sub-pillar.

12. The semiconductor structure according to any one of claims 8-11, characterized in that, In the plane containing the second direction and the third direction, the edge of the isolation post includes at least one arc-shaped edge.

13. The semiconductor structure according to claim 7, characterized in that, The semiconductor structure further includes a plurality of bit lines, which are spaced apart along the second direction. The bit lines penetrate the semiconductor layer along the first direction and are connected to the semiconductor layer. The isolation structure is also located between two adjacent bit lines.

14. The semiconductor structure according to claim 13, characterized in that, The semiconductor layer further includes a third sub-layer and a fourth sub-layer arranged along the second direction. The third sub-layer and the first sub-layer are arranged along the third direction and are connected to the same bit line. The fourth sub-layer and the second sub-layer are arranged along the third direction and are connected to the same bit line. At least one of the first capacitor structures penetrates the third sublayer along the first direction, and at least one of the first capacitor structures penetrates the fourth sublayer along the first direction.

15. The semiconductor structure according to claim 14, characterized in that, The semiconductor structure further includes a third capacitor structure, which is located between the third sub-layer and the fourth sub-layer. The third capacitor structure includes: The fifth electrode structure penetrates the semiconductor layer along the first direction; A sixth electrode structure extends through the semiconductor layer along the first direction. The sixth electrode structure includes a third sub-electrode and a fourth sub-electrode spaced apart along the second direction. The third sub-electrode is located between the third sub-layer and the fifth electrode structure, and the fourth sub-electrode is located between the fourth sub-electrode and the fifth electrode structure. A third dielectric layer extends through the semiconductor layer along the first direction and is located between the fifth electrode structure and the sixth electrode structure.

16. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes a plurality of dielectric layers and a plurality of semiconductor layers, wherein the plurality of dielectric layers and the plurality of semiconductor layers are alternately stacked along the first direction; Part of the first electrode structure is located between two adjacent dielectric layers along the first direction.

17. The semiconductor structure according to claim 1, characterized in that, The first electrode structure includes: a first conductive portion and a second conductive portion, the first conductive portion penetrating the semiconductor layer along the first direction, the second conductive portion being disposed around the first conductive portion, and the second conductive portion being in contact with the first dielectric layer.

18. The semiconductor structure according to claim 17, characterized in that, The first conductive portion and the second electrode structure do not overlap in the first direction.

19. A method for fabricating a semiconductor structure, characterized in that, include: Forming a semiconductor layer; A first capacitor structure is formed, the first capacitor structure comprising: a first electrode structure, a second electrode structure and a first dielectric layer, wherein the first electrode structure penetrates the semiconductor layer along a first direction; The second electrode structure penetrates the semiconductor layer along the first direction and is located between the semiconductor layer and the first electrode structure. The second electrode structure is arranged around the first electrode structure. The first dielectric layer is located between the first electrode structure and the second electrode structure. The first direction is parallel to the thickness direction of the semiconductor layer.

20. The method for preparing a semiconductor structure according to claim 19, characterized in that, The formation of the semiconductor layer includes: A stacked structure is formed, the stacked structure comprising the semiconductor layer and the sacrificial layer alternately stacked along a first direction; After forming the semiconductor layer, the method further includes: An isolation pillar is formed, which penetrates the stacked structure along the first direction. The semiconductor layer in the same layer includes a first sub-layer and a second sub-layer arranged along a second direction. The isolation pillar is located between the first sub-layer and the second sub-layer, and the second direction is parallel to the semiconductor layer. A gate layer is formed, which is stacked with the semiconductor layer. The gate layer includes a first gate layer and a second gate layer. The first gate layer is located on one side of the semiconductor layer along the first direction, and the second gate layer is located on the other side of the semiconductor layer along the first direction. A bit line is formed, which penetrates the stacked structure along the first direction and is connected to the semiconductor layer.

21. The method for preparing a semiconductor structure according to claim 20, characterized in that, The formation of the isolation column includes: A first structural hole is formed, and the first structural hole penetrates the stacked structure along the first direction; The sacrificial layer is removed through the first structural hole; A dielectric layer is formed, the dielectric layer including a first dielectric layer, a second dielectric layer and a third dielectric layer, wherein the first dielectric layer is disposed around the semiconductor layer, the second dielectric layer is disposed around the first dielectric layer, and the third dielectric layer is disposed around the second dielectric layer; Remove a portion of the dielectric layer covering the hole wall of the first structural hole to expose the semiconductor layer; Remove part of the semiconductor layer; Insulating material is filled into the first structural hole to form a portion of the isolation pillar.

22. The method for preparing a semiconductor structure according to claim 21, characterized in that, The formation of the gate layer includes: A second structural hole is formed, which penetrates the stacked structure along the first direction; Remove a portion of the dielectric layer covering the sidewall of the second structural hole; A portion of the second dielectric layer is removed through the second structural pore to form a first filling space; The first conductive material is filled into the first filling space to form the gate layer; Insulating material is filled into the second structural hole to form a portion of the isolation pillar.

23. The method for preparing a semiconductor structure according to claim 22, characterized in that, After filling the first filling space with the first conductive material and before filling the second structural hole with the insulating material, the method further includes: Part of the semiconductor layer is removed through the second structural hole.

24. The method for preparing a semiconductor structure according to claim 21, characterized in that, The formation of bit lines includes: A third structural hole is formed, which penetrates the stacked structure along the first direction; Remove a portion of the dielectric layer covering the sidewall of the third structural hole; The third structural hole is filled with a second conductive material to form the bit line; A third conductive material is filled into the third structural hole to form a contact, and the contact and the bit line are stacked together along the first direction.

25. The method for preparing a semiconductor structure according to claim 24, characterized in that, After forming the contact and before forming the capacitor structure, the method further includes: A fourth dielectric layer is formed, which is stacked with the stacked structure along the first direction, and the fourth dielectric layer is located on the side of the contact away from the bit line.

26. The method for preparing a semiconductor structure according to any one of claims 21-25, characterized in that, The formation of the first capacitor structure includes: A fourth structural hole and a fifth structural hole are formed, the fourth structural hole and the fifth structural hole are arranged along a second direction, the fourth structural hole penetrates the stacked structure along the first direction, and the fifth structural hole penetrates the stacked structure and part of the isolation column along the first direction, the second direction intersects the first direction; Part of the semiconductor layer and part of the first dielectric layer are removed through the fourth and fifth structural holes to form a second filling space and a third filling space; The second electrode structure and the fourth electrode structure are formed in the second filling space and the third filling space, respectively. The fourth electrode structure includes a first sub-electrode and a second sub-electrode that are spaced apart along the second direction. The first dielectric layer and the second dielectric layer are formed through the fourth structural hole and the fifth structural hole, respectively. The first dielectric layer penetrates the plurality of semiconductor layers and the second electrode structure along the first direction, and the second dielectric layer penetrates the plurality of semiconductor layers and the fourth electrode structure along the first direction. The first electrode structure and the third electrode structure are formed through the fourth structural hole and the fifth structural hole, respectively. The first electrode structure is located on the side of the first dielectric layer away from the stacked structure, and the third electrode structure is located on the side of the second dielectric layer away from the stacked structure. The first electrode structure, the second electrode structure and the first dielectric layer together constitute the first capacitor structure, and the third electrode structure, the fourth electrode structure and the second dielectric layer together constitute the second capacitor structure.

27. A storage system, characterized in that, include: The semiconductor structure according to any one of claims 1-18; A controller coupled to the semiconductor structure to control the semiconductor structure to store data.

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