A chip design verification system and method, electronic equipment and storage medium
By using a dynamic scheduler and bypass channel mechanism, combined with coverage and performance data monitoring, the problem of low chip verification efficiency was solved, enabling rapid verification and coverage convergence, thus improving verification efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- JINAN MAIWEI INTELLIGENT TECHNOLOGY CO LTD
- Filing Date
- 2026-01-30
- Publication Date
- 2026-06-05
AI Technical Summary
Existing chip verification methods are inefficient, especially in large-scale SoCs, high-speed interfaces, and multi-channel modules. Traditional serial execution modes and coverage collection methods rely on manual intervention, resulting in long verification cycles and low efficiency.
A dynamic scheduler is used to generate a linked list of excitation descriptors. Based on the pass-through attributes, a bypass channel or traditional path is selected to bypass the complex calculation process of the reference model. Combined with coverage and performance data monitoring, test priority and traffic balancing are dynamically adjusted to reduce manual intervention.
It improved the efficiency of chip verification, shortened the verification cycle, reduced manual intervention, and achieved rapid convergence of coverage and balanced traffic.
Smart Images
Figure CN122154623A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit design technology, and in particular to a chip design verification system, method, electronic device and storage medium. Background Technology
[0002] As chip size and complexity continue to increase, verification has become a core element in ensuring product quality and functional reliability. At the same time, verification has also become a key bottleneck restricting chip development efficiency.
[0003] In related technologies, verification is typically based on a Universal Verification Methodology (UVM). After the stimulus is generated, it is sequentially passed to the design under test (DUT) and a reference model along a fixed path. Finally, the reference model calculates the result, which is then compared with the output of the DUT in the scoring module. The entire process is executed serially, which reduces the verification efficiency of the DUT. Summary of the Invention
[0004] This application provides a chip design verification system, method, electronic device, and storage medium to at least address the problem of reduced verification efficiency of devices under test in related technologies.
[0005] This application provides a chip design verification system, including: a dynamic scheduler, a reference model, a module under test (DUT) and an output comparator, wherein the DUT includes the design under test, and a bypass channel is provided between the dynamic scheduler and the output comparator;
[0006] The dynamic scheduler generates a linked list of stimulus descriptors based on the target test scenario. If the linked list of stimulus descriptors contains pass-through attributes, it transmits the linked list of stimulus descriptors to the module under test and transmits it to the output comparator through a bypass channel. If the linked list of stimulus descriptors does not contain pass-through attributes, it transmits the linked list of stimulus descriptors to the reference model and the module under test. The reference model is used to determine the target execution result based on the stimulus descriptor linked list and transmit the target execution result to the output comparator; The module under test is used to determine the execution result to be verified based on the stimulus descriptor linked list, and transmit the execution result to be verified to the output comparator; The output comparator is used to determine the verification result of the design under test in the target test scenario based on the stimulus descriptor list and the execution result to be verified, or based on the target execution result and the execution result to be verified.
[0007] This application also provides a chip design verification method, including: Generate an incentive descriptor linked list based on the target test scenario; If the stimulus descriptor list contains pass-through attributes, the stimulus descriptor list is transmitted to the module under test and transmitted to the output comparator through a bypass channel. If the incentive descriptor list does not contain pass-through attributes, the incentive descriptor list is transmitted to the reference model and the module under test to obtain the target execution result determined by the reference model based on the incentive descriptor list and the execution result to be verified determined by the module under test based on the incentive descriptor list. Based on the output comparator, the verification result of the design under test in the target test scenario is determined according to the stimulus descriptor linked list and the execution result to be verified, or the verification result of the design under test in the target test scenario is determined according to the target execution result and the execution result to be verified. The module under test includes the design under test.
[0008] This application also provides a chip design verification apparatus, including: The generation module is used to generate a linked list of stimulus descriptors based on the target test scenario; The first transmission module is used to transmit the stimulus descriptor linked list to the module under test when the stimulus descriptor linked list contains a pass-through attribute, and to transmit the stimulus descriptor linked list to the output comparator through a bypass channel. The second transmission module is used to transmit the stimulus descriptor linked list to the reference model and the module under test when the stimulus descriptor linked list does not contain a pass-through attribute, so as to obtain the target execution result determined by the reference model based on the stimulus descriptor linked list and the execution result to be verified determined by the module under test based on the stimulus descriptor linked list. The verification module is used to determine the verification result of the design under test in the target test scenario based on the output comparator, the stimulus descriptor linked list and the execution result to be verified, or based on the target execution result and the execution result to be verified. The module under test includes the design under test.
[0009] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of any of the above-described chip design verification methods.
[0010] This application also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the above-described chip design verification methods.
[0011] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described chip design verification methods.
[0012] This application provides a mechanism for differentiated path selection. By changing the data flow direction of the verification platform, the incentive descriptor list generated by the dynamic scheduler based on the target test scenario can directly reflect whether it contains pass-through attributes. If pass-through attributes exist, the descriptor list is directly transmitted to the output comparator via a bypass channel, bypassing the complex calculation process of the reference model. If no pass-through attributes exist, the traditional path is followed and the reference model is used for processing. When the incentive descriptor list contains pass-through attributes, the comparison between the incentive descriptor list and the execution result to be verified can be performed in advance without waiting for the reference model to complete the calculation, thus improving the verification efficiency of the design under test. Attached Figure Description
[0013] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0014] Figure 1 This is a schematic diagram of the interaction flow of the chip design verification system provided in the embodiments of this application; Figure 2 This is a schematic diagram of the connection structure of the bypass channel provided in an embodiment of this application; Figure 3 This is a schematic diagram of the structure of the dynamic scheduler provided in the embodiments of this application; Figure 4 This is a schematic diagram of the output comparator provided in an embodiment of this application; Figure 5 This is a schematic diagram of the chip design verification system provided in an embodiment of this application; Figure 6 A schematic flowchart illustrating the chip design verification method provided in this application embodiment; Figure 7 This is a schematic diagram of the structure of the chip design verification device provided in the embodiments of this application; Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation
[0015] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.
[0016] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.
[0017] As chip complexity increases exponentially, verification has become a key bottleneck restricting chip development efficiency. Current mainstream UVM verification methodologies face several challenges: First, the verification cycle accounts for 60%-70% of the entire chip development process. The traditional serial execution mode severely restricts verification efficiency. Since the stimulus runs through the entire UVM component, its arrival at the scoreboard for comparison with real data occurs relatively late, leading to slow defect detection. Second, coverage convergence for modules or higher-level systems relies on large-scale regression testing. Traditional coverage collection methods require manual analysis of the database files generated after each round of regression testing to determine the coverage of uncovered functions or code, thereby further determining the test cases to run in the next round of regression testing, ultimately achieving coverage convergence. This process requires significant manual intervention, is time-consuming and labor-intensive, especially for multi-channel modules, where these drawbacks are particularly pronounced. Finally, chip performance testing is a crucial step in ensuring that chip design, manufacturing, and application meet expected goals, directly impacting product reliability, market success rate, and user experience. To ensure optimal performance of the current design, front-end verification requires testers to manually adjust the input stimuli based on test results, such as bandwidth adjustments and parameter settings. These challenges are particularly prominent in the verification of large-scale SoCs, high-speed interfaces, and multi-channel IPs.
[0018] Currently, traditional UVM reference model architectures employ a strictly linear execution flow. Sequences send stimuli to both the reference model and the driver simultaneously via a TLM port, and the reference model's computation results are compared with the DUT output on a scoreboard. This architecture has inherent flaws: reference model computation and DUT simulation in a single-threaded environment are essentially time-slice-based pseudo-parallelism, and complex calculations can directly block simulation progress; coverage optimization relies on manual intervention, resulting in low efficiency. Some technical case studies propose reference model algorithm optimization schemes to improve speed by modifying computational logic. Real-world testing shows some performance improvement, but it fails to resolve the architecture-level serial bottleneck. This technology still maintains the inherent "trigger-computation-comparison" pattern, and reference model computation latency remains a major bottleneck on the critical path.
[0019] To address the aforementioned technical problems, this application provides a chip design verification system, method, electronic device, and storage medium. Since the stimulus descriptor linked list generated by the dynamic scheduler based on the target test scenario can directly indicate whether it contains a pass-through attribute, if the pass-through attribute exists, the descriptor linked list is directly transmitted to the output comparator through a bypass channel, bypassing the complex calculation process of the reference model; if it does not exist, the traditional path is followed and processed by the reference model. This application provides a differentiated path selection mechanism, changing the data flow direction of the verification platform. When the stimulus descriptor linked list contains a pass-through attribute, the comparison between the stimulus descriptor linked list and the execution result to be verified can be performed in advance without waiting for the reference model to calculate, improving the verification efficiency of the design under test.
[0020] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0021] This application provides a chip design verification system for verifying the design of a chip to confirm whether its functions and performance meet development expectations.
[0022] like Figure 1 The diagram shown is an interactive flow diagram of the chip design verification system provided in this application embodiment. The system includes: a dynamic scheduler, a reference model, a module under test, and an output comparator. The module under test includes the design under test, and a bypass channel is provided between the dynamic scheduler and the output comparator.
[0023] The dynamic scheduler generates a linked list of stimulus descriptors based on the target test scenario. If the linked list contains pass-through attributes, it transmits the linked list to the module under test (DUT) and then to the output comparator via a bypass channel. If the linked list does not contain pass-through attributes, it transmits the linked list to both the reference model and the DUT. The reference model determines the target execution result based on the linked list and transmits it to the output comparator. The DUT determines the execution result to be verified based on the linked list and transmits it to the output comparator. The output comparator determines the verification result of the design under test in the target test scenario based on the linked list and the execution result to be verified, or it determines the verification result of the design under test in the target test scenario based on the target execution result and the execution result to be verified.
[0024] The design under test can be a PCIe switch chip, an AI chip, or a network processor, etc.
[0025] It's important to note that the target test scenario is a sequence of stimuli designed to verify the specific functionality of the chip under test, such as functional tests, performance tests, and anomaly tests. The dynamic scheduler abstracts this sequence of stimuli into a linked list of stimuli descriptors. This linked list of stimuli descriptors is a parameterized data structure that essentially encapsulates key attributes of the target test scenario, such as the data source (data source component), target address (target component), and transmission attributes, into a sequence of descriptors. Transparent attributes include attribute fields in the stimuli descriptors that can be directly transmitted and compared, such as routing IDs, address mapping information, or error injection flags. The expected results corresponding to these attributes can be directly compared without complex calculations, enabling early detection of defects such as address out-of-bounds errors.
[0026] Specifically, such as Figure 2 The diagram shows the connection structure of the bypass channel provided in this application embodiment. The bypass channel, also known as the Bypass channel, traditionally delivers the expected result of stimulus execution via the TLM interface through the stimulus generator (deployed in the dynamic scheduler) and reference model to the scoring board (output comparator). This method requires the stimulus to undergo complex calculations in the reference model before being transmitted to the scoring board via the TLM interface. The scoring board then compares the obtained DUT output (execution result to be verified) with the reference model result (target execution result). This makes the entire comparison process time-consuming; that is, under complex calculations, the reference model output may lag behind the DUT. Therefore, this application proposes to directly deliver the transparent stimulus to the scoring board, i.e., establishing a bypass channel between the stimulus generator and the scoring board, so that the stimulus arrives at the scoring board earlier than in the traditional method, enabling early detection of defects such as route ID and address out-of-bounds errors. A non-blocking TLM port is used, allowing the output comparator to capture the stimulus descriptor list transmitted via the Bypass channel. The bypass channel includes in_port and out_port. in_port is responsible for receiving the descriptor list output from the dynamic scheduler, and out_port is responsible for outputting the stimulus descriptor list to the output comparator. During the process, the bypass channel will make relevant records on the descriptor list, such as the descriptor list reception time.
[0027] Based on the above embodiments, such as Figure 3 This is a schematic diagram of the structure of a dynamic scheduler provided in an embodiment of this application. As one possible implementation, in one embodiment, the dynamic scheduler includes: The coverage data monitoring module is used to acquire the stimulus coverage data of the design under test. The performance data monitoring module is used to acquire performance data of each data channel in the design under test; The dynamic scheduling decision module is used to determine the target test scenario based on the stimulus coverage data of the design under test and / or the performance data of each data channel; The stimulus generator is used to generate a linked list of stimulus descriptors based on the target test scenario.
[0028] It should be noted that, to ensure the completeness of the test scenarios for chip design, coverage results are needed to evaluate the completeness of the verification work. Accelerating coverage convergence is undoubtedly one method to improve verification efficiency. This application proposes using real-time coverage data (stimulus coverage data) to ensure the priority execution of uncovered test scenarios. The coverage data monitoring module periodically checks the coverage data based on the defined `coverage_descriptor` class and the set `time_interval`. Furthermore, coverage group information can be pre-defined, meaning each coverage group corresponds to at least one chip function. This module initializes based on this information (such as assigning a coverage group number), and finally obtains three sets of coverage information according to the set time interval (`time_interval`): code coverage, functional coverage, and assertion coverage. The coverage group information includes not only the coverage group number (coverage group ID) but also coverage metric thresholds, real-time coverage metrics, and adjustment granularity. The coverage data descriptor contains code coverage, functional coverage, and assertion coverage, while the priority scheduling descriptor contains the coverage group ID, coverage metric threshold, real-time coverage metrics, and adjustment granularity.
[0029] It should be further noted that, to ensure optimal chip performance, it is typically necessary to guarantee that the chip's data channels meet the principle of traffic balancing. This application's embodiment designs a performance data monitoring module to prepare for traffic adjustment. Each data channel of the chip is modeled using a defined `performance_descriptor` class, and each data channel is numbered using `chnl_id`. Based on the `time_interval` in this class, performance data such as throughput, latency, cache capacity, and occupancy rate of each data channel are monitored periodically to obtain the performance data of each data channel in the design under test.
[0030] Specifically, the dynamic scheduler adjusts the execution priority of descriptors based on real-time coverage data (functional coverage, code coverage, and assertion coverage), automatically focusing on uncovered scenarios and avoiding invalid tests and repetitive testing of covered areas. It can also adjust the bandwidth allocation of each stimulus generator based on performance data. This improves verification efficiency and reduces manual intervention, making it suitable for scenarios such as complex state machine verification. This solution is particularly suitable for verifying chip designs with multiple channels (or multiple instantiations of submodules with the same function at a higher level).
[0031] Specifically, in one embodiment, the dynamic scheduling decision module can determine the incentive coverage of each function to be verified based on the incentive coverage data of the design under test; determine the verification priority of each function to be verified based on the incentive coverage of each function to be verified, so as to determine the target function to be verified with the highest verification priority; obtain the contribution of each test case to the target function to be verified; and take the test case with the highest contribution as the target test case, so that the incentive coverage of the target function to be verified grows according to a preset granularity.
[0032] The target test scenario includes the target test cases.
[0033] It should be noted that the function to be verified refers to the specific functional unit or logic module in the chip design (design under test) that needs to be verified, such as the single-channel transmission function in a multi-channel DMA controller, the protocol processing state machine, etc.; the verification priority is the test execution order weight assigned to each function to be verified based on coverage data, with functions with low coverage receiving higher priority; contribution refers to the effectiveness evaluation result of a specific test case in improving the coverage of the target function, reflecting the ability of the test case to trigger the relevant logic of the target function; the preset granularity is the step control parameter for coverage growth, such as the percentage of coverage expected to be improved in each scheduling (e.g., 1% or 5%).
[0034] Specifically, when considering an entire design under test as a unit, the execution priority of the coverage group can be dynamically adjusted based on the set covgrp_cov_thres and the set cov_ajust_granularity, i.e., adjusting is_high_priority. First, the returned monitoring data is sorted in descending order, then the descriptor list with the highest priority is obtained, and finally the descriptor list is executed in sequence until the coverage threshold is reached.
[0035] Specifically, by determining target test cases based on incentive coverage data, it ensures that each test cycle targets the functional areas that most need coverage, avoiding waste of test resources. The entire decision-making process requires no manual intervention, accelerating coverage convergence and further improving verification efficiency.
[0036] Specifically, in one embodiment, the dynamic scheduling decision module further includes: a coverage prediction unit, used to establish a prediction model based on historical coverage data, and to determine the coverage prediction result based on the coverage change data of the design under test; a predictive scheduling strategy generator, used to dynamically adjust the test priority allocation according to the coverage prediction result, and adjust the verification priority of each function to be verified in advance; wherein, the prediction model uses a time series analysis algorithm to predict the convergence trend of each coverage group.
[0037] Specifically, in one embodiment, the dynamic scheduling decision module can determine the incentive coverage of each data channel based on the incentive coverage data of the design under test; and determine the incentive priority of each data channel based on the incentive coverage of each data channel, so as to determine the target data channel with the highest incentive priority, so as to achieve a balance between the incentive coverage of the target data channel and the incentive coverage of other data channels.
[0038] The target test scenario includes the target data channel.
[0039] It's important to note that a data channel refers to an independent data transmission path or processing unit in a chip design. In multi-channel designs, among data channels where coverage needs to be considered, each data channel has the same logical function but operates independently, such as the data channel of CPU1 and the data channel of CPU2. Both are used to implement CPU functions, but they are two independent hardware components. The stimulus coverage here refers to the coverage of a specific data channel, reflecting the degree to which the relevant functional points and code logic of that channel are triggered by test stimuli. Stimulus priority is the test resource weight allocated based on the differences in coverage among channels, with channels having lower coverage receiving higher priority. Coverage balancing refers to the process of dynamically scheduling to make the coverage levels of each data channel more consistent, avoiding situations where some channels are over-tested while others are under-covered.
[0040] Specifically, if we take a single channel as a unit, and obtain the coverage result of each channel based on the real-time returned monitoring data, if the coverage group of some channels has reached the set threshold, then by adjusting the execution priority of the coverage group, the existing test stimuli can be executed first on the channels with lower coverage, thereby achieving a target-oriented rapid balance of coverage and shortening the convergence time.
[0041] Specifically, by continuously monitoring the coverage of each channel, test resources are dynamically directed to the most needed channels, achieving AI-based allocation of test attention, avoiding repetitive testing of already covered areas, and further improving verification efficiency.
[0042] Specifically, in one embodiment, the dynamic scheduling decision module can determine the input bandwidth weight of each data channel based on the performance data of each data channel in the design under test; wherein, the performance data includes at least latency and cache utilization, the input bandwidth weight is negatively correlated with latency, and the input bandwidth weight is negatively correlated with cache utilization; and the target data channel traffic balancing strategy of the design under test is determined based on the input bandwidth weight of each data channel.
[0043] The target test scenario includes a target data channel traffic balancing strategy. The input bandwidth weight is a bandwidth adjustment coefficient assigned to each data channel, reflecting the proportion of incentive input that channel should receive under its current performance state. This weight value can be dynamically calculated using an algorithm to optimize resource allocation.
[0044] Specifically, the input bandwidth of each channel can be adjusted based on the performance metrics returned by the performance data monitoring module. For example, based on metrics such as latency and buffer utilization of each channel, weights are assigned to each metric according to the verification personnel's requirements. Finally, a weighted comprehensive evaluation algorithm is used to obtain the new weight of the input bandwidth for each channel, thus determining the input bandwidth weight. Then, based on the determined traffic balancing strategy, the input bandwidth is readjusted, thus determining the current bandwidth, thereby achieving traffic balancing across channels. Table 1 below shows the performance data analysis for data channel 0 and data channel 1: Table 1 Performance Data Analysis of Data Channel 0 and Data Channel 1
[0045] Specifically, each test scenario contains a specific set of stimuli used to trigger specific behaviors of the DUT. The test scenario determines which stimuli need to be applied, as well as the order and conditions of these stimuli. For each test scenario, verifiers can typically extract key information to constrain the stimulus behavior and evaluate whether the DUT's functionality and performance meet expectations. Simultaneously, to quickly converge coverage, it is desirable to obtain coverage-related feedback during chip simulation to dynamically adjust test scenario execution. Therefore, embodiments of this application propose two main categories of descriptors: test scenario descriptors and coverage monitoring descriptors. The coverage monitoring category includes the aforementioned coverage data descriptor and wired scheduling descriptor.
[0046] The test scenario categories include functional test descriptors, performance test descriptors, and exception or interrupt descriptors. Functional test descriptors define key information such as packet ID, burst size, burst length, and target transmission address. They offer a choice of dedicated protocol descriptors, such as PCIe, AXI, and NVMe. For user-defined protocols, descriptor extensions based on the user protocol are supported. Performance test descriptors define key performance metrics such as throughput, latency, cache capacity, and cache utilization based on architecture requirements. They also support extensions to dedicated or user-defined protocol descriptors based on user needs. Exception or interrupt descriptors define exception or interrupt insertion enable descriptors and exception or interrupt type descriptors based on the evaluation of existing exception or interrupt scenarios in the chip.
[0047] Based on the above embodiments, such as Figure 4The diagram shown is a structural schematic of an output comparator provided in an embodiment of this application. As one possible implementation, in one embodiment, the output comparator includes: The expected result matcher is used to obtain the target execution result of the reference model and the incentive descriptor chain transmitted through the bypass channel; if the incentive descriptor chain contains pass-through attributes, the robustness check result of the reference model is determined based on the incentive descriptor chain and the target execution result. The scoreboard is used to obtain the execution results to be verified. Based on the incentive descriptor linked list and the execution results to be verified, it determines the verification results of the design under test in the target test scenario, or based on the target execution results and the execution results to be verified, it determines the verification results of the design under test in the target test scenario.
[0048] It should be noted that, when robustness checks of the reference model are required, an excitation descriptor list containing transparent attributes can also be sent to the reference model.
[0049] Specifically, the expected result matcher first obtains the stimulus descriptor list (including transparent attributes) through the bypass channel and compares it with the target execution result output by the reference model to achieve a robustness check on the reference model itself (verify its computational consistency); at the same time, the scoring board receives the actual output result of the design under test and directly compares the descriptor list with the result under test to achieve rapid defect detection.
[0050] Specifically, the expected result matcher obtains the linked list of excitation descriptors transmitted by the previous bypass channel and stores it in the relevant queue desc_q. When the linked list of descriptors (desc_item) output by the reference model is obtained, it automatically searches for the relevant linked list of descriptors corresponding to desc_item in desc_q through pkt_id in the descriptor, performs descriptor concatenation, and determines the robustness check result of the reference model, thus realizing the robustness check of the reference model.
[0051] Specifically, in one embodiment, such as Figure 5 The diagram shown is a schematic of the chip design verification system provided in this application embodiment. The module under test also includes a monitor, which is used to collect the verification execution results of the design under test and send the verification execution results to the scoring board.
[0052] The driver is used to drive the reference model and the design under test to start the simulation based on the stimulus descriptor linked list.
[0053] The chip design verification system provided in this application allows the dynamic scheduler to directly indicate whether the stimulus descriptor list generated based on the target test scenario contains transparent attributes. If transparent attributes exist, the descriptor list is directly transmitted to the output comparator via a bypass channel, bypassing the complex calculation process of the reference model. If not, the traditional path is followed and processed by the reference model. This application provides a differentiated path selection mechanism, changing the data flow direction of the verification platform. When the stimulus descriptor list contains transparent attributes, the comparison between the stimulus descriptor list and the execution result to be verified can be performed in advance without waiting for the reference model to calculate, thus improving the verification efficiency of the design under test.
[0054] Furthermore, a dynamic scheduler is designed. Based on real-time monitoring and feedback of coverage data, it parses and adjusts dynamic descriptors to enable the stimulus generator to adjust the execution order of test scenario stimuli. This achieves automatic centralized verification of uncovered scenarios and low-coverage channels, while avoiding duplicate verification of covered scenarios. Simultaneously, based on performance data monitoring, it ensures that all channels of the chip achieve traffic balance. This adaptive stimulus reordering mechanism greatly frees up verification personnel's time, reduces manual intervention, accelerates coverage convergence, and further improves verification efficiency.
[0055] This application provides a chip design verification method, applied to the system provided in the above embodiments. The execution subject of this application embodiment is an electronic device, such as a server, desktop computer, laptop computer, tablet computer, and other electronic devices that can be used for chip design verification.
[0056] like Figure 6 The diagram shown is a flowchart illustrating a chip design verification method provided in an embodiment of this application. The method includes: Step 601: Generate an incentive descriptor linked list based on the target test scenario; Step 602: If the stimulus descriptor list contains pass-through attributes, transmit the stimulus descriptor list to the module under test and transmit the stimulus descriptor list to the output comparator through the bypass channel. Step 603: If the incentive descriptor list does not contain pass-through attributes, the incentive descriptor list is transmitted to the reference model and the module under test to obtain the target execution result determined by the reference model based on the incentive descriptor list and the execution result to be verified determined by the module under test based on the incentive descriptor list. Step 604: Based on the output comparator, determine the verification result of the design under test in the target test scenario according to the stimulus descriptor linked list and the execution result to be verified, or determine the verification result of the design under test in the target test scenario according to the target execution result and the execution result to be verified.
[0057] The module under test includes the design under test.
[0058] For a description of the features in the embodiments corresponding to the chip design verification method, please refer to the relevant descriptions in the embodiments corresponding to the chip design verification system, which will not be repeated here.
[0059] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.
[0060] Embodiments of this application also provide a chip design verification apparatus for performing the chip design verification method provided in the above embodiments.
[0061] like Figure 7 The diagram shown is a schematic representation of the chip design verification apparatus provided in an embodiment of this application. The chip design verification apparatus 70 includes: a generation module 701, a first transmission module 702, a second transmission module 703, and a verification module 704.
[0062] The system comprises the following modules: a generation module for generating a linked list of stimulus descriptors based on the target test scenario; a first transmission module for transmitting the linked list of stimulus descriptors to the module under test (DUT) if the linked list contains a pass-through attribute, and transmitting the linked list of stimulus descriptors to the output comparator via a bypass channel; a second transmission module for transmitting the linked list of stimulus descriptors to both the reference model and the DUT if the linked list does not contain a pass-through attribute, to obtain the target execution result determined by the reference model based on the linked list of stimulus descriptors and the execution result to be verified determined by the DUT based on the linked list of stimulus descriptors; and a verification module for determining the verification result of the design under test in the target test scenario based on the output comparator, the linked list of stimulus descriptors, and the execution result to be verified, or the verification result of the design under test in the target test scenario based on the target execution result and the execution result to be verified.
[0063] The module under test includes the design under test.
[0064] For a description of the features in the embodiment corresponding to the chip design verification device, please refer to the relevant description of the embodiment corresponding to the chip design verification method, which will not be repeated here.
[0065] Embodiments of this application also provide an electronic device, such as... Figure 8 The diagram shown is a schematic diagram of the structure of an electronic device provided in an embodiment of this application, including a processor 10 and a memory 20. The memory 20 stores a computer program, and the processor 10 is configured to run the computer program to execute the steps in any of the chip design verification method embodiments described above.
[0066] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described chip design verification method embodiments when run.
[0067] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.
[0068] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the chip design verification method embodiments described above.
[0069] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the chip design verification method embodiments described above.
[0070] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0071] The foregoing has provided a detailed description of a chip design verification system, method, electronic device, and storage medium provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only intended to aid in understanding the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.
Claims
1. A chip design verification system, characterized in that, It includes: a dynamic scheduler, a reference model, a module under test (DUT) and an output comparator, wherein the DUT includes the design under test, and a bypass channel is provided between the dynamic scheduler and the output comparator; The dynamic scheduler is used to generate a linked list of incentive descriptors based on the target test scenario; If the stimulus descriptor list contains a pass-through attribute, the stimulus descriptor list is transmitted to the module under test and transmitted to the output comparator through the bypass channel; if the stimulus descriptor list does not contain a pass-through attribute, the stimulus descriptor list is transmitted to the reference model and the module under test. The reference model is used to determine the target execution result based on the stimulus descriptor linked list, and to transmit the target execution result to the output comparator; The module under test is used to determine the execution result to be verified based on the stimulus descriptor linked list, and transmit the execution result to be verified to the output comparator; The output comparator is used to determine the verification result of the design under test in the target test scenario based on the stimulus descriptor linked list and the execution result to be verified, or to determine the verification result of the design under test in the target test scenario based on the target execution result and the execution result to be verified.
2. The chip design verification system according to claim 1, characterized in that, The dynamic scheduler includes: The coverage data monitoring module is used to acquire the stimulus coverage data of the design under test; The performance data monitoring module is used to acquire the performance data of each data channel in the design under test; The dynamic scheduling decision module is used to determine the target test scenario based on the stimulus coverage data of the design under test and / or the performance data of each data channel; An excitation generator is used to generate a linked list of excitation descriptors based on the target test scenario.
3. The chip design verification system according to claim 2, characterized in that, The dynamic scheduling decision module is specifically used for: Based on the stimulus coverage data of the design under test, determine the stimulus coverage for each function to be verified; Based on the incentive coverage of each of the functions to be verified, the verification priority of each of the functions to be verified is determined, so as to identify the target function to be verified with the highest verification priority. Obtain the contribution of each test case to the target function to be verified; The test case with the highest contribution is used as the target test case, so that the incentive coverage of the target function to be verified increases according to a preset granularity. The target test scenario includes the target test cases.
4. The chip design verification system according to claim 2, characterized in that, The dynamic scheduling decision module is specifically used for: Based on the excitation coverage data of the design under test, determine the excitation coverage for each of the data channels; Based on the incentive coverage of each data channel, the incentive priority of each data channel is determined, so as to identify the target data channel with the highest incentive priority, so as to achieve a balance between the incentive coverage of the target data channel and the incentive coverage of other data channels. The target test scenario includes the target data channel.
5. The chip design verification system according to claim 2, characterized in that, The dynamic scheduling decision module is specifically used for: Based on the performance data of each data channel in the design under test, the input bandwidth weight of each data channel is determined; wherein, the performance data includes at least latency and cache utilization, the input bandwidth weight is negatively correlated with the latency, and the input bandwidth weight is negatively correlated with the cache utilization. Based on the input bandwidth weights of each data channel, the target data channel traffic balancing strategy of the design under test is determined. The target test scenario includes a target data channel traffic balancing strategy.
6. The chip design verification system according to claim 1, characterized in that, The output comparator includes: An expected result matcher is used to obtain the incentive descriptor chain and the target execution result of the reference model transmitted through the bypass channel; if the incentive descriptor chain contains pass-through attributes, the robustness check result of the reference model is determined based on the incentive descriptor chain and the target execution result. The scoring board is used to obtain the execution result to be verified, and to determine the verification result of the design under test in the target test scenario based on the incentive descriptor linked list and the execution result to be verified, or to determine the verification result of the design under test in the target test scenario based on the target execution result and the execution result to be verified.
7. The chip design verification system according to claim 6, characterized in that... The module under test also includes: The monitor is used to collect the execution results of the design under test and send the execution results to the scoring board.
8. A chip design verification method, characterized in that, include: Generate an incentive descriptor linked list based on the target test scenario; If the stimulus descriptor list contains a pass-through attribute, the stimulus descriptor list is transmitted to the module under test and transmitted to the output comparator through a bypass channel. If the incentive descriptor list does not contain pass-through attributes, the incentive descriptor list is transmitted to the reference model and the module under test to obtain the target execution result determined by the reference model based on the incentive descriptor list and the execution result to be verified determined by the module under test based on the incentive descriptor list. Based on the output comparator, the verification result of the design under test in the target test scenario is determined according to the stimulus descriptor linked list and the execution result to be verified, or the verification result of the design under test in the target test scenario is determined according to the target execution result and the execution result to be verified. The module under test includes the design under test.
9. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the chip design verification method as described in claim 8.
10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the chip design verification method as described in claim 8.