A low temperature drift calibratable RC relaxation oscillator circuit

Abstract

The application discloses a low-temperature-drift calibratable RC relaxation oscillator circuit, which comprises an oscillator core module, a voltage reference module, a voltage-to-current conversion module and a current DAC module, wherein the voltage reference module generates a reference voltage VREF; the voltage-to-current conversion module converts the obtained reference voltage into a reference current IREF; the current DAC module provides the adjusted currents I1, I2 and I3 to the oscillator core module, and the non-linear influence of process corners on the output frequency of the RC oscillator is reduced by adjusting the currents; the oscillator core module finally generates a clock signal CLK, and the problems that the comparator delay and the comparator offset are greatly changed with temperature are reduced by using the current self-compensation technology and the chopping technology, and thus the performance of the oscillator output frequency is improved. Compared with the traditional RC relaxation oscillator, the application reduces the temperature drift of the output frequency and improves the accuracy of the frequency by structural optimization and technical innovation.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design, and specifically relates to a low-temperature drift calibrable RC relaxation oscillator circuit. Background Technology

[0002] With the rapid development of applications such as the Internet of Things, portable electronic devices, wearable devices, and biomedical electronics, the requirements for miniaturization, low power consumption, and high integration of integrated circuits are constantly increasing. Therefore, while crystal oscillators have traditionally been widely used due to their high precision and excellent frequency stability, their large size and high cost make them difficult to integrate into chips, contradicting the current demand for highly integrated chips. RC oscillators, with their small size, short start-up time, wide output frequency range, and high stability, have become an effective alternative.

[0003] However, the output frequency of an RC oscillator is significantly affected by variations in the PVT (Programmable Voltage Transmission), with temperature changes being the most prominent factor. This is because the comparator has delay and offset voltage, both of which are greatly affected by temperature changes, directly worsening the temperature characteristics of the RC oscillator's output frequency. Furthermore, in actual production, variations in process angles can cause significant changes in the RC oscillator's output frequency. When frequency deviations accumulate and generate large timing errors, serious problems such as signal transmission / reception mismatch and data packet loss can occur. Traditional comparator-type RC oscillators consist of a reference current, a charging / discharging capacitor, and a comparator. Their working principle involves periodically charging and discharging the capacitor with a constant current, then comparing this charge with a reference voltage at the inverting input of the comparator. When the voltage is lower or higher than the reference voltage, the output state changes, ultimately obtaining a clock signal of a specific frequency. These non-ideal characteristics are the core factors limiting the performance of traditional RC oscillators. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention proposes a low-temperature drift calibrable RC relaxation oscillator circuit. This oscillator reduces the output frequency drift caused by comparator delay by increasing the charging current during the comparator delay time, and simultaneously uses chopping technology to reduce the output frequency drift caused by comparator offset voltage. In addition, this invention utilizes a current DAC to calibrate the charging and discharging current of the RC oscillator, reducing the nonlinear changes of the oscillator caused by process angle variations. These improvements enhance the temperature drift of the oscillator's output frequency.

[0005] To achieve the above objectives, the technical solution of the present invention is as follows:

[0006] A low-temperature drift calibrable RC relaxation oscillator circuit includes: an oscillator core module, a voltage reference module, a voltage-to-current conversion module, and a current DAC module; wherein,

[0007] The voltage reference module and the voltage-to-current conversion module are used to provide a first reference voltage to the voltage-to-current conversion module;

[0008] The voltage-to-current conversion module is connected to the current DAC module and is used to provide a first reference current to the current DAC module;

[0009] The current DAC module is connected to the oscillator core module and is used to provide the oscillator core module with a first charging current, a second charging current, and a first discharging current.

[0010] The oscillator core module is used to generate square wave signals.

[0011] Furthermore, the core module of the oscillator includes two identical integrator modules, a chopper comparator module, and logic circuitry; wherein,

[0012] The two identical integration modules are respectively connected to the input terminal of the chopper comparator module to generate the charging and discharging integrated voltage signal of the timing capacitor.

[0013] The chopper comparator module is connected to the input terminal of the logic circuit and is used to chop and compare the integrated voltage signal, and output a comparison signal.

[0014] The output terminal of the logic circuit is connected to the controlled terminal of the two identical integration modules, and is used to generate a switch control signal based on the comparison signal.

[0015] Furthermore, the integration module has a built-in switching component, which closes at a certain level and turns off at another level during each cycle of the square wave signal output by the oscillator, depending on the switching control signal.

[0016] Furthermore, one of the integration modules includes a first current source, a second current source, a third current source, a first integrating switch, a second integrating switch, a third integrating switch, a fourth integrating switch, and a first timing capacitor; wherein,

[0017] The output terminal of the first current source is connected to the first terminal of the first integrating switch, and the second terminal of the first integrating switch is connected to the first terminal of the third integrating switch; the second terminal of the third integrating switch is grounded.

[0018] The output terminal of the second current source is connected to the first terminal of the second integral switch, and the second terminal of the second integral switch is connected to the first terminal of the fourth integral switch.

[0019] The second terminal of the fourth integral switch is connected to the output terminal of the third current source, and the other terminal of the third current source is grounded.

[0020] The controlled terminals of the first to fourth integral switches are all connected to the output terminals of the logic circuit to receive switch control signals; one end of the first timing capacitor is connected to the common connection node of the first to fourth integral switches, and the other end is grounded, which is used to charge and discharge based on the current of the current source to output the first integral voltage signal.

[0021] The other integration module has the same structure as the first integration module and shares the same current source, outputting a second integration voltage signal.

[0022] Furthermore, the voltage reference module includes: a PTAT circuit, a CTAT circuit, a ninth reference transistor, a tenth reference crystal, a first reference resistor, and a first capacitor; wherein,

[0023] The PTAT circuit is used to generate a current that is positively correlated with absolute temperature;

[0024] The CTAT circuit is used to generate a current that is negatively correlated with absolute temperature.

[0025] The gate of the ninth reference transistor is connected to the PTAT circuit, and the gate of the tenth reference transistor is connected to the CTAT circuit. The drains of the ninth and tenth reference transistors are connected to the first reference resistor and the first capacitor, respectively. The first reference resistor and the first capacitor are connected in parallel to ground.

[0026] Further, the PTAT circuit includes: a first current mirror clamping circuit, a first transistor, a second transistor, and a second reference resistor. The first current mirror clamping circuit includes a first reference transistor to a fourth reference transistor. The source of the first reference transistor and the source of the second reference transistor are respectively connected to the collector of the first transistor and the first end of the second reference resistor. The emitter of the first transistor is connected to ground, and the base of the first transistor is connected to the collector of the first transistor. The second end of the second reference resistor is connected to the collector of the second transistor. The emitter of the second transistor is connected to ground, and the base of the second transistor is connected to the collector of the second transistor.

[0027] Furthermore, the CTAT circuit includes a second current mirror clamping circuit, a third transistor, and a third reference resistor. The second current mirror clamping circuit includes a fifth to an eighth reference transistor. The source of the fifth and sixth reference transistors of the second current mirror clamping circuit are respectively connected to the collector of the third transistor and the first end of the third reference resistor. The emitter of the third transistor is connected to ground, and the base of the third transistor is connected to the collector of the third transistor. The second end of the third reference resistor is connected to ground.

[0028] Furthermore, the sources of the third, fourth, seventh, eighth, ninth, and tenth reference transistors are connected to the power supply. The drain of the third reference transistor is connected to the drain and gate of the first reference transistor and the gate of the second reference transistor. The gate of the third reference transistor is connected to the gate and drain of the fourth reference transistor and the drain of the second reference transistor. The drain of the seventh reference transistor is connected to the drain and gate of the fifth reference transistor and the gate of the sixth reference transistor. The gate of the seventh reference transistor is connected to the gate and drain of the eighth reference transistor and the drain of the sixth reference transistor. The gate of the ninth reference transistor is connected to the gates of the third and fourth reference transistors. The gate of the tenth reference transistor is connected to the gates of the seventh and eighth reference transistors.

[0029] Furthermore, the voltage-to-current conversion module includes an operational amplifier, a first conversion resistor, a first conversion transistor, a second conversion transistor, and a third conversion transistor. The positive input terminal of the operational amplifier is connected to the output terminal of the voltage reference, the negative input terminal is connected to the source of the first conversion transistor and the first end of the first conversion resistor, and the output terminal is connected to the gate of the first conversion transistor. The drain of the first conversion transistor is connected to the drain of the second conversion transistor. The second end of the first conversion resistor is connected to ground. The source of the second conversion transistor is connected to the power supply, and the gate of the second conversion transistor is connected to the current DAC module.

[0030] Furthermore, the current DAC module includes: nine transistors and eight switches, wherein the sources of all nine transistors are connected to the power supply, the gates of all nine transistors are connected to the output terminal of the voltage-to-current conversion module, the drain of the first transistor is connected to the oscillator core module, the drains of the second to ninth transistors are connected to the first terminals of the first to eighth switches respectively, and the second terminals of the first to eighth switches are connected to the oscillator core module.

[0031] Compared with the prior art, the beneficial effects of the present invention are as follows: The present invention uses current self-compensation technology combined with chopping technology to reduce the impact of comparator delay and offset on the output frequency; it uses a current DAC circuit to perform single-point calibration of the charging and discharging current through digital adjustment; the oscillator of the present invention reduces the output frequency offset caused by comparator delay by increasing the charging current during the comparator delay time, and at the same time uses chopping technology to reduce the output frequency offset caused by comparator offset voltage; in addition, the present invention uses a current DAC to calibrate the charging and discharging current of the RC oscillator, reducing the nonlinear changes of the oscillator caused by process angle changes; these improvements improve the temperature drift of the oscillator's output frequency. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a block diagram of a low-temperature drift RC oscillator structure based on current self-compensation technology provided in an embodiment of the present invention.

[0034] Figure 2 This is a schematic diagram of the core circuit of the oscillator provided in an embodiment of the present invention.

[0035] Figure 3 This is a schematic diagram of a voltage reference module provided in an embodiment of the present invention.

[0036] Figure 4 This is a schematic diagram of the voltage-to-current converter module provided in an embodiment of the present invention.

[0037] Figure 5 This is a schematic diagram of a current DAC module provided in an embodiment of the present invention. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to its embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not limit the scope of protection of the invention.

[0039] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings:

[0040] like Figure 1 As shown, this invention proposes a low-temperature drift RC oscillator based on current self-compensation technology, comprising a voltage reference module, a voltage-to-current conversion module, a current DAC module, and an oscillator core module connected in sequence.

[0041] The oscillator core module is connected to the current DAC module and is used to generate a square wave signal;

[0042] The voltage reference module and the voltage-to-current conversion module are used to provide a first reference voltage to the voltage-to-current conversion module;

[0043] The voltage-to-current conversion module is connected to the current DAC module and is used to provide a first reference current to the current DAC module;

[0044] The current DAC module is connected to the oscillator core module and is used to provide the oscillator core module with a first charging current, a second charging current, and a first discharging current.

[0045] This invention proposes a low-temperature drift RC oscillator based on current self-compensation technology. By increasing the charging current during the comparator delay time, the output frequency shift caused by comparator delay is reduced. Simultaneously, chopping technology completely reduces the output frequency shift caused by comparator offset voltage. Furthermore, this invention utilizes a current DAC to calibrate the charging and discharging current of the RC oscillator, reducing the impact of nonlinear factors caused by manufacturing processes during mass production.

[0046] like Figure 2 As shown, in one embodiment of the present invention, the oscillator core module circuit includes two integration modules, a chopper comparator module, and logic circuitry. Wherein,

[0047] The two identical integration modules are respectively connected to the input terminal of the chopper comparator module, and are used to generate integrated voltage signals VC1 and VC2 by charging and discharging the timing capacitor;

[0048] The chopper comparator module is connected to the input terminal of the logic circuit and is used to chop and compare the integrated voltage signals VC1 and VC2, and output a comparison signal.

[0049] The output terminal of the logic circuit is connected to the controlled terminal of the two identical integration modules, and is used to generate a switch control signal based on the comparison signal;

[0050] The integration module has a built-in switching component. During each cycle of the square wave signal output by the oscillator, the switching component closes at a certain level stage and turns off at another level stage of the square wave, depending on the switching control signal.

[0051] In one embodiment of the present invention, two integration modules share a first current source I1, a second current source I2, and a third current source I3. The first integration module further includes a first integration switch S2-1 to a fourth integration switch S2-4 and a first timing capacitor CAP1. The second integration module further includes a fifth integration switch S2-5 to an eighth integration switch S2-8 and a second timing capacitor CAP2. For the first integration module, one end of the first current source I1 and the second current source I2 are connected to the power supply, and the other end is connected to the first integration switch S2-1 and the second integration switch S2-2, respectively. The other end of the first integration switch S2-1 is connected to one end of the third integration switch S2-3 and the other end is connected to pin C2 of the logic circuit. The other end of the second integration switch S2-2 is connected to the fourth integration switch S2-4 and CAP1, and the other end is connected to pin D2 of the logic circuit. The other end of the third integration switch S2-3 is connected to ground and one end is connected to pin E1 of the logic circuit. The other end of the fourth integrating switch S2-4 is connected to the third current source I3, and one end is connected to the logic circuit pin D1. The other end of the third current source I3 is connected to ground. Similarly, for the second integrating module, one end of the first current source I1 and the second current source I2 are connected to the power supply, and the other end is connected to the fifth integrating switch S2-5 and the sixth integrating switch S2-6 respectively. The other end of the fifth integrating switch S2-5 is connected to one end of the seventh integrating switch S2-7. The other end of the seventh integrating switch S2-7 is connected to the logic circuit pin C1. The other end of the sixth integrating switch S2-6 is connected to the eighth integrating switch S2-8 and the second timing capacitor CAP2. One end is connected to the logic circuit pin D1. The other end of the seventh integrating switch S2-7 is connected to ground, and one end is connected to the logic circuit pin E2. The other end of the eighth integrating switch S2-8 is connected to the third current source I3, and one end is connected to the logic circuit pin D2. The other end of the third current source I3 is connected to ground.

[0052] In one embodiment of the present invention, the chopper comparator module includes a switch selection module, a first comparator CMP1, and a second comparator CMP2. One end of the switch selection module is connected to the voltage reference voltage VREF, one end is connected to pin C1 of the logic circuit, and one end is connected to pin C2 of the logic circuit. The positive and negative input terminals of the first comparator CMP1 and the second comparator CMP2 are both connected to the switch selection module. The chopper comparator module and the logic circuit are conventional and well-known circuits in the art, and will not be described in detail here.

[0053] The specific working process of the oscillator core circuit is as follows:

[0054] First, the first integrator module is activated. VC1 is shorted to A1 inside the switching module. During the time interval t0-t2, the voltage at VC1 rises linearly, and the slope of the charging waveform is ΔV / Δt = 2IREF / CAP1. During charging, at t=t1, the voltage at VC1 equals the reference voltage VREF. However, due to the influence of the main comparator, namely the offset voltage VOFF1 and the delay td1, the output B1 of the main comparator does not flip, and the current source continues to charge the capacitor. The output of the main comparator only flips at t=t2.

[0055] The change in signal B1 causes signals C1, C2, D1, and E2 to also flip. C1 changes from low to high, and C2 changes from high to low. The state of the chopper comparator is determined by these two signals, therefore the chopper comparator switches to the φ2 state. During this time period, the second integration module is not activated.

[0056] The time interval t1-t2 can be expressed as:

[0057]

[0058] The second integration module is also activated at time t2 (ignoring the delay of the logic circuit). At this time, VC2 is shorted to A2 inside the switching module, while VC1 is shorted to A4.

[0059] During the time interval t2-t4, the voltage at point VC2 begins to rise, while the voltage at point VC1 begins to fall with a slope of ΔV / Δt = -2IREF / CAP1. At t=t3, the voltage at VC1 again equals the reference voltage VREF. However, the secondary comparator also suffers from the same problem as the primary comparator: affected by the offset voltage VOFF2 and td2, the output of the secondary comparator does not flip in time. It is not until t=t4 that the output B2 of the secondary comparator changes from low to high.

[0060] The time interval t2-t4 can be expressed as:

[0061]

[0062] Based on the state changes of the outputs B1 and B2 of the two comparators, the logic module generates a pulse signal, named D1, during the time period t2-t4. This signal enables the current source I2, causing CAP2 to charge faster. Therefore, the voltage rise slope at point VC2 during the time period t2-t4 becomes ΔV / Δt = 3IREF / CAP2. This behavior is to actively compensate for the effect of the main comparator delay.

[0063] At t=t4, D1 changes from high level to low level, the second current source I2 is turned off, the voltage rise slope at point VC2 becomes 2IREF / CAP2, and the signal E1 changes from low level to high level. Therefore, capacitor CAP1 is shorted to low, and the voltage at VC1 becomes low level.

[0064] At t=t5, the voltage at point VC2 is equal to the reference voltage VREF.

[0065] At t=t6, the output B1 of the main comparator transitions from high level to low level.

[0066] The change in signal B1 causes a jump in the states of signals C1, C2, D2, and E1, thus the chopper comparator switches to state φ1.

[0067] Assuming there is a positive input offset voltage VOFF at the negative input terminals of both the main comparator and the sub-comparator, the chopper comparator module switches the input voltage of the comparator throughout the process, making the polarity of the positive and negative terminals opposite to that of the previous half-cycle. Therefore, the offset voltage has the opposite effect on this process, thus significantly reducing the impact of the comparator offset voltage on the output frequency from the design perspective.

[0068] The times t4-t5 and t5-t6 can be expressed as follows:

[0069]

[0070]

[0071] Where VC2(t4) can be expressed as:

[0072]

[0073] Since the chopper comparator has switched to the φ1 state, VC1 is shorted to A1 again inside the switching module. The current source I1 in the first integrator module is enabled, and the voltage at VC1 begins to rise again. Similarly, at this moment, the logic module generates a positive pulse D2, which enables the current source I2 of the first integrator module. Therefore, the voltage at VC1 begins to rise with a slope of ΔV / Δt = 3IREF / CAP1. This behavior again actively compensates for the delay of the main comparator, reducing the impact of the main comparator delay on the final output frequency during this period. Simultaneously, the voltage at VC2 begins to decrease with a slope of ΔV / Δt = -2IREF / CAP2.

[0074] At t=t7, the voltage at VC2 equals the reference voltage VREF. Similarly, due to the offset voltage and delay of the secondary comparator, its output B2 only transitions from high to low at t=t8. At this moment, signal D2 changes from high to low, the current source I2 of the first integrator module turns off, the charging slope of the voltage at VC1 becomes 2IREF / CAP1, and signal E2 transitions from low to high, causing capacitor CAP2 to be shorted to ground, and the voltage at VC2 becomes low. Similar to how the offset voltage is offset by switching the polarity of the primary comparator, the secondary comparator also switches its polarity during this process, significantly reducing the impact of the offset voltage on the final frequency output.

[0075] The time interval t6-t8 can be expressed as:

[0076]

[0077] Similarly, at t=t9, the voltage at VC1 is equal to the reference voltage VREF. Due to the offset voltage of the main comparator and the propagation delay, signal B1 only flips at t=t10.

[0078] The times t8-t9 and t9-t10 can be expressed as follows:

[0079]

[0080]

[0081] Where VC1(t8) can be represented as:

[0082]

[0083] Simplifying the formulas for all the above time periods yields:

[0084]

[0085] like Figure 3 As shown, in one embodiment of the present invention, the voltage reference module itself is a bandgap reference source. The voltage reference module includes: PTAT circuit, CTAT circuit, ninth reference transistor M3-9 to tenth reference crystal M3-10, first reference resistor R3-3, and first capacitor C3-1.

[0086] The PTAT circuit is used to generate a current that is positively correlated with absolute temperature, and includes: a first current mirror clamping circuit, a first transistor Q3-1, a second transistor Q3-2, and a second reference resistor R3-1; the first current mirror clamping circuit includes a first reference transistor M3-1 to a fourth reference transistor M3-4.

[0087] The CTAT circuit is used to generate a current that is negatively correlated with absolute temperature, and includes: a second current mirror clamping circuit, a third transistor Q3-3, and a third reference resistor R3-2; the second current mirror clamping circuit includes a fifth reference transistor M3-5 to an eighth reference transistor M3-8;

[0088] The sources of the third reference transistor M3-3, the fourth reference transistor M3-4, the seventh reference transistor M3-7, the eighth reference transistor M3-8, the ninth reference transistor M3-9, and the tenth reference transistor M3-10 are connected to the power supply. The drain of the third reference transistor M3-3 is connected to the drain and gate of the first reference transistor M3-1 and the gate of the second reference transistor M3-2. The gate of the third reference transistor M3-3 is connected to the gate and drain of the fourth reference transistor M3-4 and the drain of the second reference transistor M3-2. The source of reference transistor M3-1 is connected to the collector and base of the first transistor Q3-1. The source of the second reference transistor M3-2 is connected to the second reference resistor R3-1. The emitters of the first transistor Q3-1 and the second transistor Q3-2 are connected to ground. The base of the second transistor Q3-2 is connected to the other end of the second reference resistor R3-1. The drain of the seventh reference transistor M3-7 is connected to the drain and gate of the fifth reference transistor M3-5 and the gate of the sixth reference transistor M3-6. The gate of M3-7 is connected to the gate and drain of the eighth reference transistor M3-8 and the drain of the sixth reference transistor M3-6. The source of the fifth reference transistor M3-5 is connected to the collector and base of the third transistor Q3-3. The source of the sixth reference transistor M3-6 is connected to the third reference resistor R3-2. The emitter of the third transistor Q3-3 is connected to ground. The other end of the third reference resistor R3-2 is connected to ground. The gate of the ninth reference transistor M3-9 is connected to the gate of the third reference transistor M3-3 and the fourth reference transistor M3-6. The gate of transistor 4 is connected to the gate of the tenth reference transistor M3-10, which is connected to the gates of the seventh reference transistor M3-7 and the eighth reference transistor M3-8. The drain of the ninth reference transistor M3-9 and the drain of the tenth reference transistor M3-10 are connected to the first reference resistor R3-3 and the first capacitor C3-1. The other end of the first reference resistor R3-3 and the first capacitor C3-1 is connected to ground. This module generates PTAT and CTAT currents through current mirror clamping, and after a certain ratio combination, they flow through the resistor to generate a low-temperature drift voltage reference.

[0089] The specific working principle of the voltage reference in this invention is as follows:

[0090] M3-1 to M3-4 are used to generate positive temperature coefficient current, M3-5 to M3-8 are used to generate negative temperature coefficient current, PMOS transistor M3-9 is used to copy positive temperature coefficient current, and M3-10 is used to copy negative temperature coefficient current. The voltage at the output of the circuit is composed of the output current formed by the combination of positive temperature coefficient current and negative temperature coefficient current in a certain ratio (current mirror copy ratio) and resistor R3-3.

[0091] like Figure 4 As shown, in one embodiment of the present invention, the voltage-to-current conversion module and the current DAC module include an operational amplifier, a first conversion resistor R4-1, a first conversion transistor M4-0, a second conversion transistor M4-1, and a third conversion transistor M4-2. The positive input terminal of the operational amplifier is connected to the reference voltage VREF0, and the negative input terminal is connected to the source of the first conversion transistor M4-0 and one end of the first conversion resistor R4-1. The output of the operational amplifier is connected to the gate of the first conversion transistor M4-0, and the other end of the second conversion transistor R4-1 is connected to ground. The drain of the first conversion transistor M4-0 is connected to the second conversion resistor R4-2. The drain and gate of transistor M4-1 are connected to the gate of the third conversion transistor M4-2. The source of the second conversion transistor M4-1 is connected to the power supply. The gates of the second conversion transistor M4-1 and the third conversion transistor M4-2 are interconnected. The drain of the third conversion transistor M4-2 is directly output. The drain of the third conversion transistor M4-2 is connected to the corresponding switches before outputting. The voltage-to-current conversion module converts the voltage signal into a current signal to charge the timing capacitor through an operational amplifier. The current DAC module is used to adjust the modulation code according to the actual frequency to reduce the impact of nonlinear factors caused by the manufacturing process in mass production.

[0092] In this invention, the voltage-to-current conversion module is a gain-multiplying current source circuit, which can increase the output impedance of the current source. When the output impedance is sufficiently large, it can ensure the stability of the current and reduce the deviation of the output current. The output impedance is:

[0093]

[0094] like Figure 5 As shown, in one embodiment of the present invention, the current DAC module includes: a first DAC transistor M5-1 to a ninth DAC transistor M5-10, and a first DAC switch S5-1 to an eighth DAC switch S5-8.

[0095] Among them, the first terminals of the first to ninth transistors are all connected to the power supply, the second terminals of the first transistors are all connected to the output terminal of the voltage-current conversion module, the third terminal of the first DAC transistor M5-1 is connected to the oscillator core module, and the third terminals of the second to ninth transistors are all connected to the first terminals of the corresponding first to eighth switches.

[0096] The second terminals of the first to eighth switches are connected to the oscillator core module. In this invention, the current DAC module selects different trimming codes at different process corners, allowing different numbers of current mirrors to be connected to the circuit, thereby pulling the frequencies generated at different process corners back to the target value.

[0097] This invention's voltage reference module generates a reference voltage VREF; a voltage-to-current conversion module converts the obtained reference voltage into a reference current IREF; a current DAC module provides adjusted currents I1, I2, and I3 to the oscillator core module, reducing the nonlinear impact of process angles on the RC oscillator output frequency through current self-compensation and chopping techniques; the oscillator core module ultimately generates a clock signal CLK, which, through current self-compensation and chopping techniques, reduces comparator delay and comparator offset issues caused by significant temperature variations, thereby improving the oscillator output frequency performance. Through structural optimization and technological innovation, this invention significantly reduces output frequency temperature drift and improves frequency accuracy compared to traditional RC relaxation oscillators.

[0098] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features of the invention herein.

Claims

1. A low-temperature drift calibrable RC relaxation oscillator circuit, characterized in that, include: The module consists of an oscillator core module, a voltage reference module, a voltage-to-current conversion module, and a current DAC module; among which, The voltage reference module and the voltage-to-current conversion module are used to provide a first reference voltage to the voltage-to-current conversion module; The voltage-to-current conversion module is connected to the current DAC module and is used to provide a first reference current to the current DAC module; The current DAC module is connected to the oscillator core module and is used to provide the oscillator core module with a first charging current, a second charging current, and a first discharging current. The oscillator core module is used to generate square wave signals.

2. The low-temperature drift calibrable RC relaxation oscillator circuit according to claim 1, characterized in that, The core module of the oscillator includes two identical integrator modules, a chopper comparator module, and logic circuitry; wherein... The two identical integration modules are respectively connected to the input terminal of the chopper comparator module to generate the charging and discharging integrated voltage signal of the timing capacitor. The chopper comparator module is connected to the input terminal of the logic circuit and is used to chop and compare the integrated voltage signal, and output a comparison signal. The output terminal of the logic circuit is connected to the controlled terminal of the two identical integration modules, and is used to generate a switch control signal based on the comparison signal.

3. The low-temperature drift calibrable RC relaxation oscillator circuit according to claim 2, characterized in that, The integration module has a built-in switching component. During each cycle of the square wave signal output by the oscillator, the switching component closes at a certain level stage and turns off at another level stage of the square wave, depending on the switching control signal.

4. The low-temperature drift calibrable RC relaxation oscillator circuit according to claim 3, characterized in that, One of the integration modules includes a first current source (I1), a second current source (I2), a third current source (I3), a first integrating switch (S2-1), a second integrating switch (S2-2), a third integrating switch (S2-3), a fourth integrating switch (S2-4), and a first timing capacitor (CAP1); wherein, The output terminal of the first current source (I1) is connected to the first terminal of the first integrating switch (S2-1), and the second terminal of the first integrating switch (S2-1) is connected to the first terminal of the third integrating switch (S2-3); the second terminal of the third integrating switch (S2-3) is grounded. The output terminal of the second current source (I2) is connected to the first terminal of the second integral switch (S2-2), and the second terminal of the second integral switch (S2-2) is connected to the first terminal of the fourth integral switch (S2-4). The second terminal of the fourth integral switch (S2-4) is connected to the output terminal of the third current source (I3), and the other terminal of the third current source (I3) is grounded; The controlled terminals of the first integral switch (S2-1) to the fourth integral switch (S2-4) are all connected to the output terminal of the logic circuit to receive switch control signals; one end of the first timing capacitor (CAP1) is connected to the common connection node of the first integral switch (S2-1) to the fourth integral switch (S2-4), and the other end is grounded, which is used to realize charging and discharging based on the current of the current source to output the first integral voltage signal (VC1). The other integration module has the same structure as the first integration module and shares the same current source, outputting a second integration voltage signal (VC2).

5. The low-temperature drift calibrable RC relaxation oscillator circuit according to claim 1, characterized in that, The voltage reference module includes: a PTAT circuit, a CTAT circuit, a ninth reference transistor (M3-9), a tenth reference crystal (M3-10), a first reference resistor (R3-3), and a first capacitor (C3-1); wherein... The PTAT circuit is used to generate a current that is positively correlated with absolute temperature; The CTAT circuit is used to generate a current that is negatively correlated with absolute temperature. The gate of the ninth reference transistor (M3-9) is connected to the PTAT circuit, and the gate of the tenth reference transistor (M3-10) is connected to the CTAT circuit. The drains of the ninth reference transistor (M3-9) and the tenth reference transistor (M3-10) are connected to the first reference resistor (R3-3) and the first capacitor (C3-1). The first reference resistor (R3-3) and the first capacitor are connected in parallel to ground.

6. The low-temperature drift calibrable RC relaxation oscillator circuit according to claim 5, characterized in that, The PTAT circuit includes: a first current mirror clamping circuit, a first transistor (Q3-1), a second transistor (Q3-2), and a second reference resistor (R3-1). The first current mirror clamping circuit includes a first reference transistor (M3-1) to a fourth reference transistor (M3-4). The source of the first reference transistor (M3-1) and the source of the second reference transistor (M3-2) in the first current mirror clamping circuit are respectively connected to the collector of the first transistor (Q3-1) and the second reference transistor. The first end of resistor (R3-1) is connected to the ground, the emitter of the first transistor (Q3-1) is connected to the ground, and the base of the first transistor (Q3-1) is connected to the collector of the first transistor (Q3-1). The second end of the second reference resistor (R3-1) is connected to the collector of the second transistor (Q3-2). The emitter of the second transistor (Q3-2) is connected to the ground, and the base of the second transistor (Q3-2) is connected to the collector of the second transistor (Q3-2).

7. A low-temperature drift calibrable RC relaxation oscillator circuit according to claim 6, characterized in that, The CTAT circuit includes a second current mirror clamping circuit, a third transistor (Q3-3), and a third reference resistor (R3-2). The second current mirror clamping circuit includes a fifth reference transistor (M3-5) to an eighth reference transistor (M3-8). The source of the fifth reference transistor (M3-5) and the source of the sixth reference transistor (M3-6) in the second current mirror clamping circuit are respectively connected to the collector of the third transistor (Q3-3) and the first terminal of the third reference resistor (R3-2). The emitter of the third transistor (Q3-3) is connected to ground, and the base of the third transistor (Q3-3) is connected to the collector of the third transistor (Q3-3). The second terminal of the third reference resistor (R3-2) is connected to ground.

8. A low-temperature drift calibrable RC relaxation oscillator circuit according to claim 7, characterized in that, The sources of the third reference transistor (M3-3), fourth reference transistor (M3-4), seventh reference transistor (M3-7), eighth reference transistor (M3-8), ninth reference transistor (M3-9), and tenth reference transistor (M3-10) are connected to the power supply. The drain of the third reference transistor (M3-3) is connected to the drain and gate of the first reference transistor (M3-1) and the gate of the second reference transistor (M3-2). The gate of the third reference transistor (M3-3) is connected to the gate and drain of the fourth reference transistor (M3-4) and the drain of the second reference transistor (M3-2). The seventh reference transistor... The drain of transistor (M3-7) is connected to the drain and gate of the fifth reference transistor (M3-5) and the gate of the sixth reference transistor (M3-6). The gate of the seventh reference transistor (M3-7) is connected to the gate and drain of the eighth reference transistor (M3-8) and the drain of the sixth reference transistor (M3-6). The gate of the ninth reference transistor (M3-9) is connected to the gates of the third reference transistor (M3-3) and the fourth reference transistor (M3-4). The gate of the tenth reference transistor (M3-10) is connected to the gates of the seventh reference transistor (M3-7) and the eighth reference transistor (M3-8).

9. A low-temperature drift calibrable RC relaxation oscillator circuit according to claim 1, characterized in that, The voltage-to-current conversion module includes an operational amplifier, a first conversion resistor (R4-1), a first conversion transistor (M4-0), a second conversion transistor (M4-1), and a third conversion transistor (M4-2). The positive input terminal of the operational amplifier is connected to the output terminal of the voltage reference, the negative input terminal is connected to the source of the first conversion transistor (M4-0) and the first terminal of the first conversion resistor (R4-1), and the output terminal is connected to the gate of the first conversion transistor (M4-0). The drain of the first conversion transistor (M4-0) and the drain of the second conversion transistor (M4-1) are connected. The second terminal of the first conversion resistor (R4-1) is connected to ground. The source of the second conversion transistor (M4-1) is connected to the power supply, and the gate of the second conversion transistor (M4-1) is connected to the current DAC module.

10. A low-temperature drift calibrable RC relaxation oscillator circuit according to claim 1, characterized in that, The current DAC module includes nine transistors and eight switches. The sources of all nine transistors are connected to the power supply, and the gates of all nine transistors are connected to the output terminal of the voltage-to-current conversion module. The drain of the first transistor is connected to the oscillator core module. The drains of the second to ninth transistors are connected to the first terminals of the first to eighth switches respectively. The second terminals of the first to eighth switches are connected to the oscillator core module.

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