Level shifting circuit

Abstract

The application discloses a level conversion circuit, comprising: a pull-up module, a first pull-down module, a second pull-down module and a protection module; when a first mode signal is received, in response to a first input signal received by a first input node, the pull-up module pulls up the voltage of a pull-up output node to a first voltage, the first voltage being greater than the maximum withstand voltage of a transistor, and the protection module is used for limiting the voltage difference between the ports of the transistor in the pull-up module, so that the voltage difference between the ports of the same transistor is less than or equal to the maximum withstand voltage of the transistor; by limiting the voltage difference between the ports of the transistor by the protection module in the high-voltage domain, the safe working of the transistor is ensured, the voltage conversion of the super-transistor withstand voltage value is realized, and the working voltage range of the level conversion circuit is widened.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and more specifically, to a level conversion circuit. Background Technology

[0002] With the increasing demand for portable devices such as mobile phones and laptops, low power consumption is one of the core concerns in circuit design, and multi-power supply voltage domain technology is an effective way to reduce power consumption.

[0003] In systems employing multi-power supply voltage domain technology, the system is divided into multiple independent voltage domains, each operating at a different voltage level. Level conversion circuits convert signals from one voltage level to another, providing a pathway for interaction between modules operating in different voltage domains and ensuring correct signal transmission between them.

[0004] However, when the voltage in the high voltage domain exceeds the maximum withstand voltage of the transistor in the level shifting circuit, the transistor will be damaged due to excessive source-drain voltage or gate-source voltage, affecting the reliability of the circuit and resulting in a limited actual operating voltage range for the level shifting circuit. Summary of the Invention

[0005] In view of the above problems, the present invention proposes a level conversion circuit to improve the above technical problems.

[0006] In a first aspect, embodiments of this application provide a level conversion circuit, which includes: a pull-up module, a first pull-down module, a second pull-down module, and a protection module; wherein, the first pull-down module is connected to a first input node, a second input node, a first output node, a mode control node, a second output node, the pull-up module, the second pull-down module, and the protection module; the second pull-down module is connected to the pull-up module, the first pull-down module, the protection module, the first output node, and the second output node; the pull-up module is connected to the protection module and the second output node, and the pull-up module is also used to receive power supply voltage; When the mode control node receives the first mode signal, in response to the first input signal received by the first input node, the pull-up module is used to pull up the voltage of the pull-up output node to the power supply voltage, and the second pull-down module is used to pull down the voltage of the pull-down output node to the third voltage; the protection module is used to limit the voltage difference between the ports of the transistors in the pull-up module so that the voltage difference between the ports of the same transistor is less than or equal to the maximum withstand voltage of the transistor. When the mode control node receives the second mode signal, in response to the first input signal received by the first input node, the pull-up module is used to pull up the voltage of the pull-up output node to the power supply voltage, and when the pull-down output node is the first output node, the first pull-down module is used to pull down the voltage of the pull-down output node to the reference ground voltage; when the pull-down output node is the second output node, the second pull-down module is used to pull down the voltage of the pull-down output node to the reference ground voltage; the protection module is used to limit the pull-up current of the pull-up module during the level conversion process of the first input signal, so as to speed up the conversion speed of the level conversion process; Specifically, when the first input signal is the fourth voltage, the pull-up output node is the first output node, and the pull-down output node is the second output node; when the first input signal is the reference ground voltage, the pull-up output node is the second output node, and the pull-down output node is the first output node. When the mode control node receives the first mode signal, the power supply voltage is the first voltage; when the mode control node receives the second mode signal, the power supply voltage is the second voltage; the first voltage is greater than the maximum withstand voltage value, the first voltage is greater than the second voltage, the second voltage is greater than the third voltage; the third voltage is greater than the fourth voltage; the logic state of the second input signal input by the second input node is opposite to that of the first input signal.

[0007] The technical solution provided by this invention includes a level conversion circuit comprising: a pull-up module, a first pull-down module, a second pull-down module, and a protection module; wherein, the first pull-down module is connected to a first input node, a second input node, a first output node, a mode control node, a second output node, the pull-up module, the second pull-down module, and the protection module; the second pull-down module is connected to the pull-up module, the first pull-down module, the protection module, the first output node, and the second output node; the pull-up module is connected to the protection module and the second output node, and the pull-up module is also used to receive power supply voltage; when the mode control node receives a first mode signal... In response to the first input signal received by the first input node, the pull-up module is used to pull up the voltage of the pull-up output node to the power supply voltage, and the second pull-down module is used to pull down the voltage of the pull-down output node to the third voltage; the protection module is used to limit the voltage difference between the ports of the transistors in the pull-up module, so that the voltage difference between the ports of the same transistor is less than or equal to the maximum withstand voltage of the transistor; when the mode control node receives the second mode signal, in response to the first input signal received by the first input node, the pull-up module is used to pull up the voltage of the pull-up output node to the power supply voltage, and when the pull-down output node is the first output node... The first pull-down module is used to pull down the voltage of the pull-down output node to the reference ground voltage; when the pull-down output node is the second output node, the second pull-down module is used to pull down the voltage of the pull-down output node to the reference ground voltage; the protection module is used to limit the pull-up current of the pull-up module during the level conversion process of the first input signal, so as to speed up the level conversion process; wherein, when the first input signal is the fourth voltage, the pull-up output node is the first output node and the pull-down output node is the second output node; when the first input signal is the reference ground voltage, the pull-up output node is the second output node and the pull-down output node is the first output node. Point; when the mode control node receives the first mode signal, the power supply voltage is the first voltage; when the mode control node receives the second mode signal, the power supply voltage is the second voltage; the first voltage is greater than the maximum withstand voltage value, the first voltage is greater than the second voltage, the second voltage is greater than the third voltage; the third voltage is greater than the fourth voltage; the second input signal input by the second input node has the opposite logic state to the first input signal. The protection module limits the voltage difference between the transistor ports in the high voltage domain to ensure the safe operation of the transistor while realizing voltage conversion beyond the withstand voltage value of the transistor and widening the operating voltage range of the level conversion circuit. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments and drawings obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0009] Figure 1 A schematic diagram of a high-speed I / O circuit provided in an embodiment of this application is shown.

[0010] Figure 2 A schematic diagram of a level conversion circuit structure provided in the embodiments of this application is shown.

[0011] Figure 3 This illustration shows another level conversion circuit structure in the related technology provided in the embodiments of this application.

[0012] Figure 4 A schematic diagram of a level conversion circuit provided in an embodiment of this application is shown.

[0013] Figure 5 A schematic diagram of the structure of a pull-up module provided in an embodiment of this application is shown.

[0014] Figure 6 A schematic diagram of another pull-up module provided in an embodiment of this application is shown.

[0015] Figure 7 This illustration shows a structural schematic diagram of another pull-up module provided in an embodiment of this application.

[0016] Figure 8 A schematic diagram of the structure of a first drop-down module provided in an embodiment of this application is shown.

[0017] Figure 9 A schematic diagram of another first drop-down module provided in an embodiment of this application is shown.

[0018] Figure 10 A schematic diagram of the structure of a second drop-down module provided in an embodiment of this application is shown.

[0019] Figure 11 A schematic diagram of the structure of a high-voltage pull-up auxiliary unit provided in an embodiment of this application is shown.

[0020] Figure 12 A schematic diagram of the structure of a first high-voltage pull-down unit provided in an embodiment of this application is shown.

[0021] Figure 13A schematic diagram of a low-voltage pull-down unit provided in an embodiment of this application is shown.

[0022] Figure 14 A schematic diagram of the structure of a second high-voltage pull-down unit provided in an embodiment of this application is shown.

[0023] Figure 15 A schematic diagram of the structure of a dynamic adjustment subunit provided in an embodiment of this application is shown.

[0024] Figure 16 A schematic diagram of the structure of a protection module provided in an embodiment of this application is shown.

[0025] Figure 17 A schematic diagram of another protection module provided in an embodiment of this application is shown.

[0026] Figure 18 A schematic diagram of the structure of another protection module provided in an embodiment of this application is shown.

[0027] Figure 19 A schematic diagram of another level conversion circuit structure provided in an embodiment of this application is shown.

[0028] Figure 20 The diagram shows the signal waveforms of the second input node and the second output node in a high-voltage domain mode according to an embodiment of this application.

[0029] Figure 21 The diagram shows the signal waveforms of the second input node and the second output node in a low-voltage domain mode according to an embodiment of this application. Detailed Implementation

[0030] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

[0031] In the embodiments of this application, the Levelshifter is a level conversion circuit that converts low voltage to high voltage or high voltage to low voltage.

[0032] In the embodiments of this application, the I / O (Input / Output) circuit is a circuit used to handle data transmission between the inside and outside of the chip.

[0033] With the increasing demand for portable devices such as mobile phones and laptops, low power consumption is one of the core concerns in circuit design, and multi-power supply voltage domain technology is an effective way to reduce power consumption.

[0034] In this technology, the module is divided into multiple independent voltage domains, each operating at a different voltage level. The level shifting circuit (also known as a voltage level shifter) is a circuit that can convert a signal from one voltage level to another.

[0035] In multi-supply voltage domain design, level shifting circuits can be used to connect different voltage domains, for example, such as... Figure 1 As shown, in a high-speed I / O circuit, the input signal is provided by the storage module, and the level conversion circuit performs level conversion on the input signal to obtain the output signal. The output signal is connected to the enable port of the operational amplifier to control the operational amplifier to enable or enter the tuning mode.

[0036] In related technologies, such as Figure 2 As shown, the level conversion circuit 100 includes an input inverter 110, a level conversion module 120, and a drive circuit 130.

[0037] The input inverter 110 operates at a low voltage source V1, the level conversion module 120 operates at a high voltage source V2, the level conversion module 120 uses a cross-coupled PMOS half-latch, the drive circuit 130 operates at a high voltage source V2, and the drive circuit 130 uses an inverter to form the output signal OUT.

[0038] When the input signal A is high, transistors N2 and P3 are turned on, the voltage of the first node W1 is pulled down to the reference ground voltage, the voltage of the second node W2 is pulled up to the high voltage source V2, and at the same time transistor P4 is turned on, the voltage of the output signal OUT is pulled up to the high power supply V2.

[0039] However, during the process of transistor N2 gradually turning on and transistor N3 gradually turning off, the positive feedback effect of the cross-coupled transistor is triggered only when the voltage of the first node W1 drops below V2-Vthp (where Vthp is the threshold voltage of the P-type MOS transistor), and transistor P3 turns on, thus realizing the level conversion function.

[0040] In other words, for the circuit conversion circuit 100 in the related technology, the pull-up and pull-down capabilities must be equal. Otherwise, the pull-up transistor and the pull-down transistor will compete, resulting in increased delay and power consumption. When the input signal A is close to or even below the threshold voltage, the subthreshold current through transistor N2 is very small. The pull-down capability of transistor N2 cannot overcome the pull-up capability of transistor P2, causing the first node W1 to be unable to be pulled down to the reference ground voltage. The positive feedback cannot be triggered, and the level conversion module 120 cannot work properly.

[0041] To overcome the competition between the top and bottom sliders, in related technologies, such as... Figure 3As shown, the level conversion circuit 100 introduces transistors P5 and P6 in the pull-up branch. The gate and drain of transistors P5 and P6 are connected together, which can be equivalent to diodes, and are used to limit the pull-up capability of their respective branches.

[0042] When the level conversion circuit 100 is in a stable state, the gate-source voltages of transistors P5 and P6 are small, which is the voltage drop Vdrop (i.e., the DC voltage drop between the source and drain when the transistor is on). The transistors P1 and P2 that were originally used for pull-up are either on or off.

[0043] When the input signal A changes from 0 to 1, the voltage drop does not change quickly, but remains at the initial value, limiting the pull-up capability. When the input signal enters the logic 1 in the subthreshold region, transistor N2 operates in the subthreshold region. At the same time, due to the voltage drop across transistor P5, the pull-up current of transistor P2 is limited. Transistor N2 can pull down the first node W1 to the bottom, making transistor P3 conduct, and positive feedback begins. Transistors P5 and P6 can also work normally in the subthreshold region.

[0044] However, the voltage of the first node N1 can only reach between V2-Vdrop and V2. To ensure full swing output, transistors N4 and P4 are used as the output stage to achieve full swing. Thus, the level conversion circuit can operate over a wide voltage range, enabling low-to-high level conversion over a wider range.

[0045] However, this structure cannot operate in environments with significant voltage differences. Otherwise, such large voltage differences could lead to overvoltage issues for transistors P2 and P3 (i.e., the voltage difference between different ports of the transistors exceeds the maximum withstand voltage). This could damage the transistors due to excessively high source-drain or gate-source voltages, affecting circuit reliability and limiting the actual operating voltage range of the level shifting circuit. Furthermore, as process dimensions shrink, the maximum withstand voltage of transistors decreases (for example, there are no transistors with a withstand voltage exceeding 1.8V in processes smaller than 28nm). However, some voltage domains in I / O circuits require higher supply voltages (e.g., 3.3V). Due to size limitations, transistors with high withstand voltages cannot be used, further restricting the actual operating voltage range of the level shifting circuit.

[0046] To address the aforementioned problems, the inventors have proposed a level conversion circuit comprising: a pull-up module, a first pull-down module, a second pull-down module, and a protection module; wherein the first pull-down module is connected to a first input node, a second input node, a first output node, a mode control node, a second output node, the pull-up module, the second pull-down module, and the protection module; the second pull-down module is connected to the pull-up module, the first pull-down module, the protection module, the first output node, and the second output node; the pull-up module is connected to the protection module and the second output node, and the pull-up module is also used to receive the power supply voltage; when the mode control node receives... When the first mode signal is received, in response to the first input signal received by the first input node, the pull-up module is used to pull up the voltage of the pull-up output node to the power supply voltage, and the second pull-down module is used to pull down the voltage of the pull-down output node to the third voltage; the protection module is used to limit the voltage difference between the ports of the transistors in the pull-up module, so that the voltage difference between the ports of the same transistor is less than or equal to the maximum withstand voltage of the transistor; when the mode control node receives the second mode signal, in response to the first input signal received by the first input node, the pull-up module is used to pull up the voltage of the pull-up output node to the power supply voltage, and the second pull-down module is used to pull down the voltage of the pull-down output node to the third voltage. When the output node is a first output node, the first pull-down module is used to pull down the voltage of the pull-down output node to the reference ground voltage; when the pull-down output node is the second output node, the second pull-down module is used to pull down the voltage of the pull-down output node to the reference ground voltage; the protection module is used to limit the pull-up current of the pull-up module during the level conversion process of the first input signal, so as to speed up the level conversion process; wherein, when the first input signal is the fourth voltage, the pull-up output node is the first output node and the pull-down output node is the second output node; when the first input signal is the reference ground voltage, the pull-up output node is the second output node and the pull-down output node is the first output node. Output node; when the mode control node receives the first mode signal, the power supply voltage is the first voltage; when the mode control node receives the second mode signal, the power supply voltage is the second voltage; the first voltage is greater than the maximum withstand voltage value, the first voltage is greater than the second voltage, the second voltage is greater than the third voltage; the third voltage is greater than the fourth voltage; the second input signal input by the second input node has the opposite logic state to the first input signal. The protection module limits the voltage difference between the transistor ports in the high voltage domain to ensure the safe operation of the transistor while realizing voltage conversion beyond the withstand voltage value of the transistor and widening the operating voltage range of the level conversion circuit.

[0047] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.

[0048] Please see Figure 4 , Figure 4 A schematic diagram of a level conversion circuit provided in an embodiment of this application is shown, as follows: Figure 4As shown, the level conversion circuit 200 provided in this application embodiment includes: a pull-up module 210, a first pull-down module 220, a second pull-down module 230, and a protection module 240.

[0049] The first pull-down module 220 is connected to the first input node VINN, the second input node VINP, the first output node VOUTP, the mode control node VCON, the second output node VOUTP, the pull-up module 210, the second pull-down module 230, and the protection module 240, respectively.

[0050] The first input node VINN is used to input the first input signal, and the second input node VINP is used to input the second input signal. The first input signal and the second input signal are logically opposite. The mode control node VCON is used to input the mode control signal to switch the level conversion circuit to the corresponding operating mode.

[0051] The second pull-down module 230 is connected to the pull-up module 210, the first pull-down module 220, the protection module 240, the first output node VOUTN, and the second output node VOUTP, respectively.

[0052] In embodiments of this application, the pull-up module 210 is connected to the protection module 240 and the second output node VOUTP, respectively. The pull-up module 210 is also used to receive the power supply voltage VDDH. The pull-up module 210 includes a transistor, which pulls the pull-up output node up to the power supply voltage VDDH.

[0053] In the embodiments of this application, when the first input signal is the fourth voltage, the pull-up output node is the first output node VOUTN, and the pull-down output node is the second output node VOUTP.

[0054] When the first input signal is the reference ground voltage, the pull-up output node is the second output node VOUTP, and the pull-down output node is the first output node VOUTN.

[0055] The mode control signal includes a first mode signal, which is used to characterize the high voltage domain mode. When the mode control node VCON receives the first mode signal, the level conversion circuit 200 is used to convert the input signal into a high voltage domain output signal.

[0056] In the high-voltage domain mode, the power supply voltage VDDH is the first voltage, which is greater than the maximum withstand voltage of the transistor. Therefore, the level conversion circuit 200 provided in this embodiment can achieve a voltage output exceeding the maximum withstand voltage of the transistor. In the high-voltage domain mode, the voltage range of the output signal is from the third voltage to the first voltage. The third voltage is less than the first voltage.

[0057] The mode control signal also includes a second mode signal, which is used to characterize the low voltage domain mode. When the mode control node VCON receives the second mode signal, the level conversion circuit 200 is used to convert the input signal into a low voltage domain output signal.

[0058] In low-voltage domain mode, the power supply voltage VDDH is the second voltage, which is greater than the third voltage. In low-voltage domain mode, the output signal voltage range is from the reference ground voltage to the second voltage.

[0059] Therefore, the level conversion circuit provided in this application embodiment can realize dual-mode level conversion, has a wide operating voltage range, can be applied to various working scenarios with different requirements, and can achieve voltage conversion exceeding the withstand voltage value of transistors in the high voltage domain, further expanding the operating voltage range of the level conversion circuit.

[0060] In the embodiments of this application, when the mode control node VCON receives the first mode signal, in response to the first input signal received by the first input node VINN, the pull-up module 210 is used to pull up the voltage of the pull-up output node to the power supply voltage VDDH, and the second pull-down module 220 is used to pull down the voltage of the pull-down output node to the third voltage; the protection module 240 is used to limit the voltage difference between the ports of the transistors in the pull-up module 210, so that the voltage difference between the ports of the same transistor is less than or equal to the maximum withstand voltage of the transistor.

[0061] When the mode control node receives the second mode signal, in response to the first input signal of the first input node VINN, the pull-up module 210 is used to pull up the voltage of the pull-up output node to the power supply voltage VDDH, and when the pull-down output node is the first output node VOUTN, the first pull-down module is used to pull down the voltage of the pull-down output node to the reference ground voltage GND.

[0062] When the pull-down output node is the second output node VOUTP, the second pull-down module 230 is used to pull down the voltage of the pull-down output node to the reference ground voltage GND; the protection module 240 is used to limit the pull-up current of the pull-up module 210 during the level conversion process of the first input signal, so as to speed up the conversion speed of the level conversion process.

[0063] When the mode control node receives the first mode signal, the power supply voltage is the first voltage; when the mode control node receives the second mode signal, the power supply voltage is the second voltage; the first voltage is greater than the maximum withstand voltage value, the first voltage is greater than the second voltage, the second voltage is greater than the third voltage; the third voltage is greater than the fourth voltage; the logic state of the second input signal input by the second input node is opposite to that of the first input signal.

[0064] In the embodiments of this application, the power supply voltage can be set according to the actual application scenario. For example, the first voltage can be set to 3.3V, the second voltage can be set to 1.8V, the third voltage can be set to 1.5V, and the fourth voltage can be set to 1V. The specific voltage can be set according to the actual situation, and this application does not limit it.

[0065] In the embodiments of this application, a transistor with a suitable withstand voltage value can be selected according to the needs of the actual application scenario. For example, a transistor with a maximum withstand voltage value of 1.8V can be selected.

[0066] Please see Figure 5 , Figure 5 This illustration shows a structural diagram of a pull-up module provided in an embodiment of this application, as shown below. Figure 5 As shown, the pull-up module 210 includes: a first pull-up PMOS transistor MP1, a second pull-up PMOS transistor MP2, a first bias control unit 211, and a second bias control unit 212.

[0067] The source of the first pull-up PMOS transistor MP1 is connected to the power supply voltage VDDH, the drain of the first pull-up PMOS transistor MP1 is connected to the first terminal of the first bias control unit 211, and the gate of the first pull-up PMOS transistor MP1 is connected to the second terminal of the second bias control unit 212.

[0068] The second terminal of the first bias control unit 211 is connected to the gate of the first pull-down module 220 and the second pull-up PMOS transistor MP2, respectively; the bias terminal of the first bias control unit 211 is used to receive the bias voltage VBIAS; the third terminal of the first bias unit 211 is connected to the protection module 240.

[0069] The source of the second pull-up PMOS transistor MP2 is connected to the power supply voltage VDDH, and the drain of the second pull-up PMOS transistor MP2 is connected to the first terminal of the second bias control unit 212; the drain of the second pull-up PMOS transistor MP2 is connected to the second output node VOUTP; and the gate of the second pull-up PMOS transistor MP2 is connected to the second terminal of the second bias control unit 212.

[0070] The first terminal of the second bias control unit 212 is also connected to the first output node VOUTN via the second pull-down module 230. The second terminal of the second bias control unit 212 is connected to the first pull-down module 220; the bias terminal of the second bias control unit 212 is used to receive the bias voltage VBIAS; the third terminal of the second bias unit 212 is connected to the protection module 240 and the second pull-down module 230 respectively.

[0071] Specifically, when the mode control node VCON receives the first mode signal, the bias voltage VBIAS is the third voltage; when the mode control node VCON receives the second mode signal, the bias voltage VBIAS is the reference ground voltage.

[0072] When the mode control node VCON receives the first mode signal, the first input signal is the fourth voltage, and the bias voltage VBIAS is the third voltage, the second bias control unit 212 is used to provide a drive voltage to the gate of the first pull-up PMOS transistor MP2.

[0073] When the mode control node VCON receives the first mode signal, the first input signal is the reference ground voltage GND, and the bias voltage VBIAS is the third voltage, the first bias control unit 211 is used to provide a drive voltage to the gate of the second pull-up PMOS transistor MP2.

[0074] When the mode control node VCON receives the second mode signal, the first input signal is the fourth voltage, and the bias voltage VBIAS is the reference ground voltage GND, the second bias control unit 212 is used to provide a drive voltage to the gate of the first pull-up PMOS transistor MP2.

[0075] When the mode control node VCON receives the first mode signal, the first input signal is the reference ground voltage GND, and the bias voltage VBIAS is the reference ground voltage GND, the first bias control unit 211 is used to provide a drive voltage to the gate of the second pull-up PMOS transistor MP2.

[0076] Please see Figure 6 , Figure 6 This application provides a schematic diagram of another pull-up module structure, as shown in the embodiment. Figure 6 As shown, the first bias control unit 211 includes: a first bias PMOS transistor ZP1 and a second bias MOS transistor ZP2.

[0077] The gate of the first bias PMOS transistor ZP1 is connected to the gate of the second bias PMOS transistor ZP2, the drain of the first bias PMOS transistor ZP1 is connected to the source of the second bias PMOS transistor ZP2, the source of the first bias PMOS transistor ZP1 is connected to the drain of the first pull-up PMOS transistor MP1, and the drain of the second bias PMOS transistor ZP2 is connected to the gate of the second pull-up PMOS transistor MP2.

[0078] The second bias control unit 2112 includes a third bias PMOS transistor ZP3 and a fourth bias PMOS transistor ZP4.

[0079] The gate of the third bias PMOS transistor ZP3 is connected to the gate of the fourth bias PMOS transistor ZP4, the drain of the third bias PMOS transistor ZP3 is connected to the source of the fourth bias PMOS transistor ZP4, the source of the third bias PMOS transistor ZP3 is connected to the drain of the second pull-up PMOS transistor MP2, and the drain of the fourth bias PMOS transistor ZP4 is connected to the gate of the first pull-up PMOS transistor MP1.

[0080] The gates of the first bias PMOS transistor MP1 and the third bias PMOS transistor ZP3 are used to receive the bias voltage VBIAS, respectively; the sources of the first bias PMOS transistor ZP1 and the third bias PMOS transistor ZP3 are connected to the protection module 240, respectively.

[0081] When the mode control node VCON receives the first mode signal, and the first input signal is converted from the reference ground voltage to the fourth voltage, the fourth bias PMOS transistor ZP4 pulls the gate voltage of the first pull-up PMOS transistor MP1 to VBIAS+Vthp, ensuring that the first pull-up PMOS transistor MP1 is turned on to the maximum extent without being overvoltaged. At the same time, it pulls the gate voltage of the second pull-up PMOS transistor MP2 up to the power supply voltage VDDH, and the second pull-up PMOS transistor MP2 is turned off, forming positive feedback.

[0082] When the mode control node VCON receives the first mode signal and the first input signal is converted from the fourth voltage to the reference ground voltage, the second bias PMOS transistor ZP2 pulls the gate voltage of the second pull-up PMOS transistor MP1 to VBIAS+Vthp (Vthp is the threshold voltage of the PMOS transistor), ensuring that the second pull-up PMOS transistor MP2 is turned on to the maximum extent without being overvoltaged. At the same time, it pulls the gate voltage of the first pull-up PMOS transistor MP1 up to the power supply voltage VDDH, and the second pull-up PMOS transistor MP2 is turned off, forming positive feedback.

[0083] Please see Figure 7 , Figure 7 This application provides a schematic diagram of the structure of another pull-up module, as shown in the embodiment. Figure 7 As shown, this application provides another implementation of the first bias control unit, namely, the first bias control unit includes: a fifth bias PMOS transistor and a sixth bias PMOS transistor.

[0084] The source of the fifth bias PMOS transistor is connected to the drain of the first pull-up PMOS transistor; the source of the sixth bias PMOS transistor is connected to the gate, drain, and protection module of the fifth bias PMOS transistor; the drain of the sixth bias PMOS transistor is connected to the gate of the second pull-up PMOS transistor.

[0085] This application provides another implementation of the second bias control unit, namely, the second bias control unit includes: a seventh bias PMOS transistor and an eighth bias PMOS transistor.

[0086] The source of the seventh bias PMOS transistor is connected to the drain of the second pull-up PMOS transistor; the source of the eighth bias PMOS transistor is connected to the gate, source, and protection module of the seventh bias PMOS transistor respectively; the drain of the eighth bias PMOS transistor is connected to the gate of the first pull-up PMOS transistor.

[0087] The gates of the sixth bias PMOS transistor and the eighth bias PMOS transistor are used to receive the bias voltage VBIAS, respectively.

[0088] When the mode control node VCON receives the first mode signal, and the first input signal is converted from the reference ground voltage to the fourth voltage, the eighth bias PMOS transistor ZP8 pulls the gate voltage of the first pull-up PMOS transistor MP1 to VBIAS+Vthp, ensuring that the first pull-up PMOS transistor MP1 is turned on to the maximum extent without being overvoltaged. At the same time, it pulls the gate voltage of the second pull-up PMOS transistor MP2 up to the power supply voltage VDDH, and the second pull-up PMOS transistor MP2 is turned off, forming positive feedback.

[0089] When the mode control node VCON receives the first mode signal and the first input signal is converted from the fourth voltage to the reference ground voltage, the sixth bias PMOS transistor ZP6 pulls the gate voltage of the second pull-up PMOS transistor MP1 to VBIAS+Vthp, ensuring that the second pull-up PMOS transistor MP2 is turned on to the maximum extent without being overvoltaged. At the same time, it pulls the gate voltage of the first pull-up PMOS transistor MP1 up to the power supply voltage VDDH, and the second pull-up PMOS transistor MP2 is turned off, forming positive feedback.

[0090] Please see Figure 8 , Figure 8 This illustration shows a structural diagram of a first drop-down module provided in an embodiment of this application, as shown below. Figure 8 As shown, the first pull-down module 220 includes: a first low-voltage pull-down NMOS transistor MN1, a second low-voltage pull-down NMOS transistor MN2, a first mode switching unit 221, a second mode switching unit 222, a third mode switching unit 223, a first voltage-limiting NMOS transistor XN1, a second voltage-limiting NMOS transistor XN2, and a third voltage-limiting NMOS transistor XN3.

[0091] The gate of the first low-voltage pull-down NMOS transistor MN1 is connected to the second input node VINP, the source of the first low-voltage pull-down NMOS transistor MN1 is connected to the reference ground voltage GND, and the drain of the first low-voltage pull-down NMOS transistor MN1 is connected to the first terminal of the first mode switching unit 221.

[0092] The second terminal of the first mode switching unit 221 is connected to the source of the first voltage-limiting NMOS transistor XN1; the control terminal of the first mode switching unit 221 is used to connect to the mode control node VCON.

[0093] The gate of the first voltage-limiting NMOS transistor XN1 is used to receive the protection voltage VCCA, and the drain of the first voltage-limiting NMOS transistor is connected to the pull-up module 210.

[0094] The gate of the second low-voltage pull-down NMOS transistor MN2 is connected to the first input node VINN, the source of the second low-voltage pull-down NMOS transistor MN2 is used to connect to the reference ground voltage GND, and the drain of the second low-voltage pull-down NMOS transistor MN2 is connected to the first terminal of the second mode switching unit 222.

[0095] The second terminal of the second mode switching unit 222 is connected to the source of the second voltage-limiting NMOS transistor XN2; the control terminal of the second mode switching unit 222 is used to connect to the mode control node VCON.

[0096] The gate of the second voltage-limiting NMOS transistor XN2 is used to receive the protection voltage VCCA, and the drain of the second voltage-limiting NMOS transistor XN2 is connected to the pull-up module 210.

[0097] The first terminal of the third mode switching unit 223 is connected to the source of the third voltage-limiting NMOS transistor XN3, and the second terminal of the third mode switching unit 223 is connected to the drain of the second low-voltage pull-down NMOS transistor MN2; the control terminal of the third mode switching unit 223 is used to connect to the mode control node VCON.

[0098] The gate of the third voltage-limiting NMOS transistor XN3 is used to receive the protection voltage VCCA, and the drain of the third voltage-limiting NMOS transistor XN3 is used to connect to the second output node VOUTP.

[0099] Specifically, when the mode control node VCON receives the first mode signal, the first terminal of the first mode switching unit 221 is disconnected from the second terminal; the first terminal of the second mode switching unit 222 is disconnected from the second terminal; and the first terminal of the third mode switching unit 223 is disconnected from the second terminal.

[0100] When the mode control node receives the second mode signal, the first end of the first mode switching unit 221 is connected to the second end; the first end of the second mode switching unit 222 is connected to the second end; and the first end of the third mode switching unit 223 is connected to the second end.

[0101] Among them, the protection voltage VCCA is greater than or equal to the difference between the first voltage and the maximum withstand voltage.

[0102] In the embodiments of this application, the first mode switching unit 221, the second mode switching unit 222, and the third mode switching unit 223 can be implemented in various ways, such as using transistors, transmission gates (including parallel NMOS and PMOS), cascaded switches, or any other electronic switch structure that can achieve controlled connection and disconnection.

[0103] Please see Figure 9 , Figure 9 This application provides a schematic diagram of another first drop-down module, as shown in the embodiment. Figure 9 As shown, the first mode switching unit 221 includes a first mode switching NMOS transistor QN1; the gate of the first mode switching NMOS transistor QN1 is used to connect to the mode control node VCON, the drain of the first mode switching NMOS transistor QN1 is connected to the source of the first voltage-limiting NMOS transistor XN1; the drain of the first mode switching unit 221 is connected to the drain of the first low-voltage pull-down NMOS transistor MN1.

[0104] The second mode switching unit 222 includes a second mode switching NMOS transistor QN2; the gate of the second mode switching NMOS transistor QN2 is used to connect to the mode control node VCON, the drain of the second mode switching NMOS transistor QN2 is connected to the source of the second voltage limiting NMOS transistor XN2; the drain of the second mode switching unit 222 is connected to the drain of the second low voltage pull-down NMOS transistor MN2.

[0105] The third mode switching unit 223 includes a third mode switching NMOS transistor QN3; the gate of the third mode switching NMOS transistor QN3 is connected to the mode control node VCON, the drain of the third mode switching NMOS transistor QN3 is connected to the source of the third voltage limiting NMOS transistor XN3, and the drain of the third mode switching NMOS transistor QN3 is connected to the drain of the second low-voltage pull-down NMOS transistor MN2.

[0106] Therefore, the first mode signal is the reference ground voltage. When the mode control node receives the reference ground voltage, the first mode switching NMOS transistor QN1, the second mode switching NMOS transistor QN2, and the third mode switching NMOS transistor QN3 are turned off.

[0107] The second mode signal is the second voltage. When the mode control node receives the second voltage, the first mode switching NMOS transistor QN1, the second mode switching NMOS transistor QN2, and the third mode switching NMOS transistor QN3 are turned on.

[0108] Please see Figure 10 , Figure 10 This illustration shows a structural diagram of a second drop-down module provided in an embodiment of this application, as shown below. Figure 10As shown, the second pull-down module 230 includes: a high-voltage pull-up auxiliary unit 231, a first high-voltage pull-down unit 232, a second high-voltage pull-down unit 232, and a low-voltage pull-down unit 234.

[0109] The first end of the high-voltage pull-up auxiliary unit 231 is used to connect to the power supply voltage VDDH, the second end of the high-voltage pull-up auxiliary unit 231 is used to connect to the first output node VOUTN, and the control end of the high-voltage pull-up auxiliary unit 231 is connected to the pull-up module 210 and the second output node VOUTP respectively.

[0110] The first end of the first high voltage pull-down unit 232 is used to connect to the third voltage VP, the second end of the first high voltage pull-down unit 232 is used to connect to the second output node VOUTP, and the control end of the first high voltage pull-down unit 232 is connected to the protection module 240.

[0111] The first terminal of the low-voltage pull-down unit 234 is used to connect to the first output node VOUTN, and the second terminal of the low-voltage pull-down unit 234 is used to connect to the reference ground voltage GND; the first control terminal of the low-voltage pull-down unit is used to connect to the mode control node VCON; and the second control terminal of the low-voltage pull-down unit 234 is used to connect to the second input node VINP.

[0112] The first terminal of the second high-voltage pull-down unit 233 is used to connect to the third voltage VP, and the second terminal of the second high-voltage pull-down unit 233 is used to connect to the first output node VOUTN; the third terminal of the second high-voltage pull-down unit 233 is connected to the third terminal of the low-voltage pull-down unit 234.

[0113] When the mode control node VCON receives the first mode signal and the first input signal is the fourth voltage, the high voltage pull-up auxiliary unit 231 conducts the first and second terminals of the high voltage pull-up auxiliary unit 231 according to the signal of the pull-up module 210, thereby pulling up the voltage of the first output node VOUTN to the power supply voltage VDDH.

[0114] Furthermore, the first high voltage pull-down unit 232 conducts the first terminal and the second terminal of the first high voltage pull-down unit 232 according to the signal of the protection module 240, thereby pulling down the voltage of the second output node VOUTP to the third voltage VP; When the mode control node VCON receives the first mode signal and the first input signal is the reference ground voltage GND, the second high voltage pull-down unit 233 is used to connect the first terminal and the second terminal of the second high voltage pull-down unit; thereby causing the voltage of the first output node VOUTN to be pulled down to the third voltage VP.

[0115] When the mode control node receives the second mode signal and the second input signal is the fourth voltage, the second terminal of the low-voltage pull-down unit is connected to the third terminal, thereby pulling down the voltage of the second output node VOUTP to the reference ground voltage.

[0116] Please see Figure 11 , Figure 11 This application provides a schematic diagram of the structure of a high-voltage pull-up auxiliary unit according to an embodiment of the present application. Figure 11 As shown, the high-voltage pull-up auxiliary unit 231 includes an auxiliary PMOS transistor FP1. The source of the auxiliary PMOS transistor FP1 is used to connect to the power supply voltage VDDH; the drain of the auxiliary PMOS transistor FP1 is used to connect to the first output node VOUTN; and the gate of the auxiliary PMOS transistor FP1 is connected to the pull-up module 210 and the second output node VOUTP, respectively.

[0117] The auxiliary PMOS transistor FP1 can be turned on according to the signal output by the pull-up module 210, thereby pulling up the voltage of the first output node VOUTN to the power supply voltage VDDH.

[0118] Please see Figure 12 , Figure 12 This paper shows a schematic diagram of the structure of a first high-voltage pull-down unit provided in an embodiment of this application, as shown below. Figure 12 As shown, the first high-voltage pull-down unit 232 includes a first high-voltage pull-down PMOS transistor GP1 and a second high-voltage pull-down PMOS transistor GP2.

[0119] The source of the first high-voltage pull-down PMOS transistor GP1 is used to connect to the third voltage VP, and the gate of the first high-voltage pull-down PMOS transistor GP1 is connected to the protection module 240; the drain of the first high-voltage pull-down PMOS transistor GP1 is used to connect to the source of the second high-voltage pull-down PMOS transistor GP2.

[0120] The gate of the second high-voltage pull-down PMOS transistor GP2 is connected to the protection module 240; the drain of the second high-voltage pull-down PMOS transistor GP2 is used to connect to the second output node VOUTP.

[0121] The first high-voltage pull-down PMOS transistor GP1 and the second high-voltage pull-down PMOS transistor GP2 can be turned on according to the signal output by the protection module 240, thereby pulling down the voltage of the second output node VOUTP to the third voltage VP.

[0122] Please see Figure 13 , Figure 13 This illustration shows a structural schematic diagram of a low-voltage pull-down unit provided in an embodiment of this application, as shown below. Figure 13 As shown, the low-voltage pull-down unit 234 includes: a third low-voltage pull-down NMOS transistor MN3, a mode switching subunit 2341, and a fourth voltage-limiting NMOS transistor XN4.

[0123] The gate of the third low-voltage pull-down NMOS transistor MN3 is used to connect to the second input node VINP, the drain of the third low-voltage pull-down NMOS transistor MN3 is used to connect to the reference ground voltage GND, and the source of the third low-voltage pull-down NMOS transistor is connected to the first terminal of the mode switching subunit 2341 and the third terminal of the second high-voltage pull-down unit 233, respectively.

[0124] The control terminal of the mode switching subunit 233 is used to connect to the mode control node VCON; the second terminal of the mode switching subunit 233 is used to connect to the drain of the fourth voltage-limiting NMOS transistor XN4.

[0125] The gate of the fourth voltage-limiting NMOS transistor XN4 is used to connect to the protection voltage VCCA, and the source of the fourth voltage-limiting NMOS transistor XN4 is used to connect to the first output node VOUTN.

[0126] Among them, the protection voltage VCCA is greater than or equal to the difference between the first voltage and the maximum withstand voltage.

[0127] When the mode control node VCON receives the second mode signal, the first and second terminals of the mode switching subunit 2341 are connected.

[0128] When the second input signal is the fourth voltage, the source and drain of the third low-voltage pull-down NMOS transistor MN3 are connected.

[0129] In the embodiments of this application, the mode switching subunit 233 can be implemented in various ways, such as using transistors, transmission gates (including parallel NMOS and PMOS), cascaded switches, or any other electronic switch structure capable of controlled connection and disconnection.

[0130] Please see Figure 14 , Figure 14 This paper shows a schematic diagram of the structure of a second high-voltage pull-down unit provided in an embodiment of this application, as shown below. Figure 14 As shown, the second high-voltage pull-down unit 233 includes: a ninth bias PMOS transistor ZP9, a third high-voltage pull-down PMOS transistor GP3, a fifth voltage-limiting NMOS transistor XN5, and a dynamic adjustment subunit 2331.

[0131] Among them, the drain of the ninth bias PMOS transistor ZP9 is used to connect to the first output node VOUTN; the gate of the ninth bias PMOS transistor ZP9 is used to receive the bias voltage VBIAS; and the source of the ninth bias PMOS transistor ZP9 is connected to the drain of the third high-voltage pull-down PMOS transistor GP3.

[0132] The source of the third high-voltage pull-down PMOS transistor GP3 is connected to the first detection terminal of the dynamic voltage drop adjustment subunit 2331, and the gate of the third high-voltage pull-down PMOS transistor GP3 is connected to the second detection terminal of the dynamic voltage drop adjustment subunit 2331.

[0133] The source of the fifth voltage-limiting NMOS transistor XN5 is connected to the third terminal of the low-voltage pull-down unit 234, and the drain of the fifth voltage-limiting NMOS transistor XN5 is connected to the third detection terminal of the dynamic adjustment subunit 2331.

[0134] The dynamic adjustment subunit 2331 is used to adjust the voltage input to the gate of the third high-voltage pull-down PMOS transistor GP3 according to the voltage changes of the first and second detection terminals during the level conversion of the second input signal, so that the voltage difference between the ports of the third high-voltage pull-down PMOS transistor GP3 is less than or equal to the maximum withstand voltage value.

[0135] When the mode control node VCON receives the first mode signal, the bias voltage VBIAS is the third voltage; when the mode control node VCON receives the second mode signal, the bias voltage VBIAS is the reference ground voltage.

[0136] Please see Figure 15 , Figure 15 This illustration shows a structural schematic diagram of a dynamically adjustable subunit provided in an embodiment of this application, as shown below. Figure 15 As shown, the dynamic adjustment subunit 2331 includes: a first adjustment NMOS transistor TN1, a second adjustment NMOS transistor TN2, a third adjustment NMOS transistor TN3, a first adjustment PMOS transistor TP1, and a second adjustment PMOS transistor TP2.

[0137] In this configuration, the source of the first adjusting NMOS transistor TN1 is connected to the source of the third high-voltage pull-down PMOS transistor, the gate of the first adjusting NMOS transistor TN1 is used to receive the bias voltage VBIAS, and the drain of the first adjusting NMOS transistor TN1 is connected to the source of the second adjusting NMOS transistor TN2.

[0138] The gate of the second regulating NMOS transistor TN2 is connected to the drain of the third regulating NMOS transistor TN3; the drain of the second regulating NMOS transistor TN2 is used to receive the third voltage VP.

[0139] The source of the third adjusting NMOS transistor TN3 is connected to the drain of the fifth limiting NMOS transistor XN5; the gate of the third adjusting NMOS transistor TN3 is connected to the source of the first adjusting PMOS transistor TN1; and the drain of the third adjusting NMOS transistor TN3 is connected to the drain of the first adjusting PMOS transistor TP1.

[0140] The gate of the first regulating PMOS transistor TP1 is used to receive the protection voltage VCCA; the source of the first regulating PMOS transistor TP1 is connected to the drain of the second regulating PMOS transistor TP2.

[0141] The gate of the second regulating PMOS transistor TP2 is connected to the drain of the third regulating NMOS transistor TN3, and the source of the second regulating PMOS transistor TP2 is used to receive the protection voltage VCCA.

[0142] Among them, the protection voltage VCCA is greater than or equal to the difference between the first voltage and the maximum withstand voltage.

[0143] Please see Figure 16 , Figure 16 This paper illustrates a schematic diagram of the structure of a protection module provided in an embodiment of this application, as shown below. Figure 16 As shown, the protection module 240 includes a first protection unit 241 and a second protection unit 242.

[0144] The first end of the first protection unit 241 is connected to the third end of the first bias control unit 211, and the second end of the first protection unit 241 is connected to the first pull-down module 220. When the second input signal is the first voltage, the first pull-down module 220 is used to connect the second end of the first protection unit 241 to the reference ground voltage GND.

[0145] The first end of the second protection unit 242 is connected to the third end of the second bias control unit 212, and the first end of the second protection unit 242 is also connected to the second pull-down module 230; the second end of the second protection unit 242 is used to connect to the mode control node VCON.

[0146] Please see Figure 17 , Figure 17 This illustration shows a structural schematic diagram of a first protection unit provided in an embodiment of this application, as shown below. Figure 17 As shown, the first protection unit 241 includes a first protection NMOS transistor HN1, a first protection PMOS transistor HP1, and a sixth voltage-limiting NMOS transistor XN6.

[0147] The gate of the first protection NMOS transistor HN1 is connected to the third terminal of the first bias control unit 211; the drain of the first protection NMOS transistor HN1 is connected to the drain of the first protection PMOS transistor HP1; and the source of the first protection NMOS transistor HN1 is connected to the gate of the first protection PMOS transistor HP1 and the source of the sixth voltage-limiting NMOS transistor.

[0148] The source of the first protection PMOS transistor is connected to the third terminal of the first bias control unit 211.

[0149] The gate of the sixth voltage-limiting NMOS transistor is used to receive the protection voltage, and the drain of the sixth voltage-limiting NMOS transistor is connected to the first pull-down module.

[0150] Among them, the protection voltage is greater than or equal to the difference between the first voltage and the maximum withstand voltage.

[0151] Please see Figure 18 , Figure 18 This paper shows a schematic diagram of the structure of a second protection unit provided in an embodiment of this application, as shown below. Figure 18 As shown, the second protection unit 242 includes a second protection NMOS transistor HN2, a second protection PMOS transistor HP2, and a seventh voltage-limiting NMOS transistor XN7.

[0152] The gate of the second protection NMOS transistor HN2 is connected to the third terminal of the second bias control unit, the drain of the second protection NMOS transistor HN2 is connected to the drain of the second protection PMOS transistor HP2, and the source of the second protection NMOS transistor HN2 is connected to the gate of the second protection PMOS transistor HP2 and the source of the seventh voltage-limiting NMOS transistor XN7.

[0153] The source of the second protection PMOS transistor HN2 is connected to the third terminal of the second bias control unit 212 and the second pull-down module 230, respectively.

[0154] The gate of the seventh voltage-limiting NMOS transistor XN7 is used to receive the protection voltage VCCA, and the drain of the seventh voltage-limiting NMOS transistor XN7 is used to connect to the mode control node VCON; wherein, the protection voltage VCCA is greater than or equal to the difference between the first voltage and the maximum withstand voltage value.

[0155] The following specific embodiment will describe in detail the operation of the level conversion circuit provided in this application. Please refer to... Figure 19 , Figure 19 The diagram shows another level conversion circuit provided in the embodiment of this application. In the embodiment of this application, the mode switching subunit adopts a fourth mode switching NMOS transistor QN4. The gate of the fourth mode switching NMOS transistor QN4 is used to connect to the mode control node VCON. The source of the fourth mode switching NMOS transistor QN4 is connected to the drain of the third pull-down NMOS transistor MN3. The drain of the fourth mode switching NMOS transistor QN4 is connected to the source of the fourth voltage-limiting NMOS transistor XN4.

[0156] In this embodiment, the transistor used in the level conversion circuit 200 has a maximum withstand voltage of 1.8V.

[0157] When the mode control node VCON receives the first mode control signal (1.8V), the level conversion circuit is in the high voltage domain mode. At this time, the power supply voltage VDDH is the first level (3.3V), the third voltage VP is 1.5V, the protection voltage VCCA is 1.8V, and the bias voltage VBIAS is 1.5V.

[0158] Since the mode control node VCON receives a first mode control signal of 1.8V, the first mode switching NMOS transistor QN1, the second mode switching NMOS transistor QN2, the third mode switching NMOS transistor QN3, and the fourth mode switching NMOS transistor QN4 are in the off state.

[0159] When the first input signal is the reference ground voltage GND and the second input signal is the fourth voltage (1V), the second low-voltage pull-down NMOS transistor MN2 is turned off; the first low-voltage pull-down NMOS transistor MN1 is turned on, pulling the drain voltage of the sixth voltage-limiting NMOS transistor XN6 to the reference ground voltage GND, thereby turning on the sixth voltage-limiting NMOS transistor XN6.

[0160] The source of the second bias PMOS transistor is pulled to the threshold voltage Vthp by the first protection NMOS transistor HN1 and the first protection PMOS transistor HP1. The second bias PMOS transistor ZP2 pulls the gate voltage of the second pull-up PMOS transistor MP2 to VBIAS+Vthp, thereby ensuring that the second pull-up PMOS transistor MP2 does not exceed the voltage while maximizing its conduction.

[0161] The second pull-up PMOS transistor MP2 is turned on, pulling the voltage of the second output node VOUTP to the first level. At the same time, the gate voltage of the auxiliary PMOS transistor FP1 is pulled to the first level, thereby turning off the auxiliary PMOS transistor FP1 and disconnecting the pull-up path of the second output node VOUTP.

[0162] Since the second input signal is the fourth voltage, the third low-voltage pull-down NMOS transistor MN3 and the fifth voltage-limiting NMOS transistor XN5 are turned on. The second regulating NMOS transistor TN2, the first regulating NMOS transistor TN1, the third high-voltage pull-down PMOS transistor GP3, and the ninth bias PMOS transistor ZP9 pull the voltage of the first output node VOUTN to VP+Vthp. At the same time, the second regulating PMOS transistor TP2, the first regulating PMOS transistor TP1, and the third regulating NMOS transistor TN3 perform overvoltage protection, pulling the source voltage of the third high-voltage pull-down PMOS transistor GP3 to the reference ground voltage and the drain voltage to the threshold voltage Vthp, thus preventing overvoltage of the third high-voltage pull-down PMOS transistor GP3.

[0163] During the level transition process of the first input signal from the fourth voltage to the reference ground voltage, the diode-coupled MOS transistor composed of the first protection PMOS transistor HP1 and the first protection NMOS transistor HN1 limits the source voltage of the second bias PMOS transistor ZP2 to the threshold voltage Vthp, reduces the drain voltage of the first pull-up PMOS transistor MP1, weakens the pull-up capability of the first pull-up PMOS transistor MP1, and alleviates the competition between pull-up and pull-down during the level transition process. At the same time, the second bias PMOS transistor ZP2 pulls the gate voltage of the second pull-up PMOS transistor MP2 to VBIAS+Vthp, forming positive feedback.

[0164] The dynamic adjustment subunit (including the first adjustment NMOS transistor TN1, the second adjustment NMOS transistor TN2, the third adjustment NMOS transistor TN3, the first adjustment PMOS transistor TP1, and the second adjustment PMOS transistor TP2, etc.) dynamically adjusts the gate voltage of the third high-voltage pull-down PMOS transistor GP3 according to the voltage change of the second output node VOUTN. As the drain voltage of the third high-voltage pull-down PMOS transistor GP3 decreases, the drain-source voltage of GP13 increases. The dynamic adjustment subunit pulls down the gate voltage of the third high-voltage pull-down PMOS transistor GP3, thereby reducing the drain-source voltage of the third high-voltage pull-down PMOS transistor GP3 and ensuring that the transistor does not overvoltage. When stable, the source and drain of the third high-voltage pull-down PMOS transistor GP3 are pulled to the reference ground voltage GND and the threshold voltage Vthp of the PMOS transistor, respectively, to avoid overvoltage.

[0165] When the first input signal is the fourth voltage (1V) and the second input signal is the reference ground voltage GND, the first low-voltage pull-down NMOS transistor MN1 is turned off and the second low-voltage pull-down NMOS transistor MN2 is turned on, pulling the drain voltage of the seventh voltage-limiting NMOS transistor XN7 to the reference ground voltage GND, thereby turning on the seventh voltage-limiting NMOS transistor XN7.

[0166] The source voltage of the fourth bias PMOS transistor is pulled to the threshold voltage Vthp by the second protection NMOS transistor HN2 and the second protection PMOS transistor HP2. The fourth bias PMOS transistor ZP4 pulls the gate voltage of the first pull-up PMOS transistor MP1 to VBIAS+Vthp, thereby ensuring that the first pull-up PMOS transistor MP1 does not exceed the voltage while maximizing its conduction.

[0167] Since the source voltage of the fourth bias PMOS transistor is the threshold voltage Vthp, the first high-voltage pull-down PMOS transistor GP1 and the second high-voltage pull-down PMOS transistor GP2 connect the pull-down path from the second output node VOUTP to the third voltage. The second output node VOUTP is pulled down to the third voltage, which in turn assists PMOS transistor FP1 to turn on, connecting the pull-up path from the first output node VOUTN to the power supply voltage VDDH. The voltage of the first output node VOUTN is pulled up to the power supply voltage VDDH.

[0168] During the level transition process of the first input signal from the reference ground voltage to the fourth voltage: the diode-coupled MOS transistor composed of the second protection PMOS transistor HP2 and the second protection NMOS transistor HN2 limits the source voltage of the fourth bias PMOS transistor ZP4 to the threshold voltage Vthp, reduces the drain voltage of the second pull-up PMOS transistor MP2, weakens the pull-up capability of the second pull-up PMOS transistor MP2, and slows down the competition between pull-up and pull-down during the level transition process. At the same time, the fourth bias PMOS transistor ZP4 pulls the gate voltage of the first pull-up PMOS transistor MP1 to VBIAS+Vthp, forming positive feedback.

[0169] The dynamic adjustment subunit (including the first adjusting NMOS transistor TN1, the second adjusting NMOS transistor TN2, the third adjusting NMOS transistor TN3, the first adjusting PMOS transistor TP1, and the second adjusting PMOS transistor TP2, etc.) dynamically adjusts the gate voltage of the third high-voltage pull-down PMOS transistor GP3 according to the voltage change of the second output node VOUTN. As the drain voltage of the third high-voltage pull-down PMOS transistor GP3 increases, the drain-source voltage of GP13 decreases. The dynamic adjustment subunit then raises the gate voltage of the third high-voltage pull-down PMOS transistor GP3, thereby increasing the drain-source voltage of GP3 and ensuring that the transistor does not overvoltage. When stable, the source and drain of the third high-voltage pull-down PMOS transistor GP3 are pulled to the first voltage and the first voltage -Vthn (the threshold voltage of the NMOS transistor), respectively, to avoid overvoltage.

[0170] In high-voltage domain mode, the waveforms of the second input node VINN and the second output node VOUTP are as follows: Figure 20 As shown, by Figure 20 It can be seen that the level conversion circuit provided in this application embodiment has a rise delay of approximately 115ps and a fall delay of approximately 210ps in the high voltage domain mode.

[0171] In the embodiments of this application, the dynamic adjustment subunit provides a dynamic gate voltage bias through diode coupling connection to keep all transistors charging and discharging consistently, thus avoiding overvoltage during the level transition process.

[0172] When the mode control node VCON receives the second mode control signal (reference ground voltage), the level conversion circuit is in the low voltage domain mode. At this time, the power supply voltage VDDH is the second level (1.8V), the third voltage VP is 300mV, the protection voltage VCCA is 1.8V, and the bias voltage VBIAS is the reference ground voltage.

[0173] Since the mode control node VCON receives the first mode control signal as the reference ground voltage GND, the first mode switching NMOS transistor QN1, the second mode switching NMOS transistor QN2, the third mode switching NMOS transistor QN3, and the fourth mode switching NMOS transistor QN4 are in the on state.

[0174] When the first input signal is the reference ground voltage GND and the second input signal is the fourth voltage (1V), the second low-voltage pull-down NMOS transistor MN2 is turned off; the first low-voltage pull-down NMOS transistor MN1 is turned on, and the first voltage-limiting NMOS transistor XN1 is turned on, pulling the gate voltage of the second pull-up PMOS transistor MP2 down to the reference ground voltage. The second pull-up PMOS transistor MP2 is turned on, thereby connecting the pull-up path between the second output node VOUTP and the reference power supply VDDH. The voltage of the second output node VOUTP is pulled to the second level.

[0175] As the second pull-up PMOS transistor MP2 is turned on, the gate of the auxiliary PMOS transistor FP1 is pulled high to the power supply voltage. The auxiliary PMOS transistor FP1 is in the off state, disconnecting the pull-up path between the first output node VOUTN and the reference power supply VDDH.

[0176] Since the second input signal is the fourth voltage, the third low-voltage pull-down NMOS transistor MN3 is turned on, the fourth mode switching NMOS transistor QN4 is turned on, the source voltage of the fourth voltage-limiting NMOS transistor XN4 is pulled to the reference ground voltage GND, the fourth voltage-limiting NMOS transistor XN4 is turned on, connecting the pull-down path of the first output node VOUTN and the reference ground voltage GND, and the first output node VOUTN is pulled to the reference ground voltage.

[0177] In the process of level transition from the fourth voltage to the reference ground voltage of the first input signal, the diode-coupled MOS transistor composed of the first protection PMOS transistor HP1 and the first protection NMOS transistor HN1 limits the source voltage of the second bias PMOS transistor ZP2 to the threshold voltage Vthp, reduces the drain voltage of the first pull-up PMOS transistor MP1, weakens the pull-up capability of the first pull-up PMOS transistor MP1, and alleviates the competition between pull-up and pull-down during the level transition. At the same time, the diode-coupled MOS transistor composed of the first protection PMOS transistor HP1 and the first protection NMOS transistor HN1 is also the main charge transport path, which can reduce the rise delay, greatly reduce the time required for the level transition process, and ensure the normal operation of the circuit.

[0178] When the first input signal is the fourth voltage and the second input signal is the reference ground voltage, the first low-voltage pull-down NMOS transistor MN1 is turned off; the second low-voltage pull-down NMOS transistor MN2 is turned on, and the second voltage-limiting NMOS transistor XN2 is turned on, pulling down the gate voltage of the first pull-up PMOS transistor MP1 and the gate voltage of the auxiliary PMOS transistor FP1 to the reference ground voltage, and the first pull-up PMOS transistor MP1 and the auxiliary PMOS transistor FP1 are turned on.

[0179] When the auxiliary PMOS transistor FP1 is turned on, the pull-up path between the first output node VOUTN and the power supply voltage VDDH is connected, and the voltage of the first output node VOUTN is pulled up to the second voltage.

[0180] Since the first input signal is the fourth voltage, the second low-voltage pull-down NMOS transistor MN2 is turned on, and the third mode switching NMOS transistor QN3 is turned on, pulling the source voltage of the third voltage-limiting NMOS transistor XN6 down to the reference ground voltage GND. Thus, the third voltage-limiting NMOS transistor XN6 is turned on, connecting the pull-down path between the second output node VOUTP and the reference ground voltage GND, and the voltage of the second output node VOUTP is pulled down to the reference ground voltage GND.

[0181] In the process of level transition from the reference ground voltage to the fourth voltage of the first input signal, the diode-coupled MOS transistor composed of the second protection PMOS transistor HP2 and the second protection NMOS transistor HN2 limits the source voltage of the fourth bias PMOS transistor ZP4 to the threshold voltage Vthp, reduces the drain voltage of the second pull-up PMOS transistor MP2, weakens the pull-up capability of the second pull-up PMOS transistor MP2, and alleviates the competition between pull-up and pull-down during the level transition. At the same time, the diode-coupled MOS transistor composed of the second protection PMOS transistor HP2 and the second protection NMOS transistor HN2 is also the main charge transport path, which can reduce the rise delay, greatly reduce the time required for the level transition process, and ensure the normal operation of the circuit.

[0182] In low-voltage domain mode, the waveforms of the second input node VINN and the second output node VOUTP are as follows: Figure 21 As shown, by Figure 21 It can be seen that the level conversion circuit provided in this application embodiment has a rise delay of approximately 270ps and a fall delay of approximately 195ps in the low voltage domain mode.

[0183] In summary, the level conversion circuit provided in this application includes: a pull-up module, a first pull-down module, a second pull-down module, and a protection module; wherein, the first pull-down module is connected to a first input node, a second input node, a first output node, a mode control node, a second output node, the pull-up module, the second pull-down module, and the protection module respectively; the second pull-down module is connected to the pull-up module, the first pull-down module, the protection module, the first output node, and the second output node respectively; the pull-up module is connected to the protection module and the second output node respectively, and the pull-up module is also used to receive power supply voltage; when the mode control node receives the first mode signal... When the first input signal is received by the first input node, the pull-up module is used to pull up the voltage of the pull-up output node to the power supply voltage, and the second pull-down module is used to pull down the voltage of the pull-down output node to the third voltage; the protection module is used to limit the voltage difference between the ports of the transistors in the pull-up module, so that the voltage difference between the ports of the same transistor is less than or equal to the maximum withstand voltage of the transistor; when the mode control node receives the second mode signal, in response to the first input signal received by the first input node, the pull-up module is used to pull up the voltage of the pull-up output node to the power supply voltage, and the pull-down output node is the first output node. When the first input signal is a fourth voltage, the first pull-down module is used to pull down the voltage of the pull-down output node to the reference ground voltage; when the pull-down output node is the second output node, the second pull-down module is used to pull down the voltage of the pull-down output node to the reference ground voltage; the protection module is used to limit the pull-up current of the pull-up module during the level conversion process of the first input signal, so as to speed up the level conversion process; wherein, when the first input signal is a fourth voltage, the pull-up output node is the first output node and the pull-down output node is the second output node; when the first input signal is the reference ground voltage, the pull-up output node is the second output node and the pull-down output node is the first output node. Point; when the mode control node receives the first mode signal, the power supply voltage is the first voltage; when the mode control node receives the second mode signal, the power supply voltage is the second voltage; the first voltage is greater than the maximum withstand voltage value, the first voltage is greater than the second voltage, the second voltage is greater than the third voltage; the third voltage is greater than the fourth voltage; the second input signal input by the second input node has the opposite logic state to the first input signal. The protection module limits the voltage difference between the transistor ports in the high voltage domain to ensure the safe operation of the transistor while realizing voltage conversion beyond the withstand voltage value of the transistor and widening the operating voltage range of the level conversion circuit.

[0184] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A level conversion circuit, characterized in that, The level conversion circuit includes: a pull-up module, a first pull-down module, a second pull-down module, and a protection module; The first pull-down module is connected to the first input node, the second input node, the first output node, the mode control node, the second output node, the pull-up module, the second pull-down module, and the protection module, respectively. The second pull-down module is connected to the pull-up module, the first pull-down module, the protection module, the first output node, and the second output node, respectively. The pull-up module is connected to the protection module and the second output node, and the pull-up module is also used to receive power supply voltage. When the mode control node receives the first mode signal, in response to the first input signal received by the first input node, the pull-up module is used to pull up the voltage of the pull-up output node to the power supply voltage, and the second pull-down module is used to pull down the voltage of the pull-down output node to the third voltage; the protection module is used to limit the voltage difference between the ports of the transistors in the pull-up module, so that the voltage difference between the ports of the same transistor is less than or equal to the maximum withstand voltage of the transistor. When the mode control node receives the second mode signal, in response to the first input signal received by the first input node, the pull-up module is used to pull up the voltage of the pull-up output node to the power supply voltage, and when the pull-down output node is the first output node, the first pull-down module is used to pull down the voltage of the pull-down output node to the reference ground voltage; when the pull-down output node is the second output node, the second pull-down module is used to pull down the voltage of the pull-down output node to the reference ground voltage; the protection module is used to limit the pull-up current of the pull-up module during the level conversion process of the first input signal, so as to accelerate the conversion speed of the level conversion process; Wherein, when the first input signal is the fourth voltage, the pull-up output node is the first output node and the pull-down output node is the second output node; when the first input signal is the reference ground voltage, the pull-up output node is the second output node and the pull-down output node is the first output node; When the mode control node receives the first mode signal, the power supply voltage is the first voltage; when the mode control node receives the second mode signal, the power supply voltage is the second voltage; the first voltage is greater than the maximum withstand voltage value, the first voltage is greater than the second voltage, the second voltage is greater than the third voltage; the third voltage is greater than the fourth voltage; the second input signal input by the second input node has the opposite logic state to the first input signal.

2. The level conversion circuit according to claim 1, characterized in that, The pull-up module includes: a first pull-up PMOS transistor, a second pull-up PMOS transistor, a first bias control unit, and a second bias control unit; Wherein, the source of the first pull-up PMOS transistor is used to connect to the power supply voltage, the drain of the first pull-up PMOS transistor is connected to the first terminal of the first bias control unit, and the gate of the first pull-up PMOS transistor is connected to the second terminal of the second bias control unit; The second terminal of the first bias control unit is connected to the gate of the first pull-down module and the second pull-up PMOS transistor, respectively; the bias terminal of the first bias control unit is used to receive the bias voltage; the third terminal of the first bias unit is connected to the protection module. The source of the second pull-up PMOS transistor is connected to the power supply voltage, and the drain of the second pull-up PMOS transistor is connected to the first terminal of the second bias control unit; the drain of the second pull-up PMOS transistor is connected to the second output node; the gate of the second pull-up PMOS transistor is connected to the second terminal of the first bias control unit. The first terminal of the second bias control unit is also connected to the first output node through the second pull-down module; the second terminal of the second bias control unit is connected to the first pull-down module; the bias terminal of the second bias control unit is used to receive the bias voltage; the third terminal of the second bias unit is connected to the protection module. When the mode control node receives a first mode signal, the first input signal is the fourth voltage, and the bias voltage is the third voltage, the second bias control unit is used to provide a drive voltage to the gate of the first pull-up PMOS transistor; When the mode control node receives a first mode signal, the first input signal is the reference ground voltage, and the bias voltage is the third voltage, the first bias control unit is used to provide a drive voltage to the gate of the second pull-up PMOS transistor.

3. The level conversion circuit according to claim 2, characterized in that, The first bias control unit includes: a first bias PMOS transistor and a second bias PMOS transistor; The gate of the first biased PMOS transistor is connected to the gate of the second biased PMOS transistor, the drain of the first biased PMOS transistor is connected to the source of the second biased PMOS transistor, the source of the first biased PMOS transistor is connected to the drain of the first pull-up PMOS transistor, and the drain of the second biased PMOS transistor is connected to the gate of the second pull-up PMOS transistor. The second bias control unit includes: a third bias PMOS transistor and a fourth bias PMOS transistor; The gate of the third bias PMOS transistor is connected to the gate of the fourth bias PMOS transistor, the drain of the third bias PMOS transistor is connected to the source of the fourth bias PMOS transistor, the source of the third bias PMOS transistor is connected to the drain of the second pull-up PMOS transistor, and the drain of the fourth bias PMOS transistor is connected to the gate of the first pull-up PMOS transistor. The gates of the first bias PMOS transistor and the third bias PMOS transistor are respectively used to receive bias voltages; the drains of the first bias PMOS transistor and the third bias PMOS transistor are respectively connected to the protection module.

4. The level conversion circuit according to claim 2, characterized in that, The first bias control unit includes: a fifth bias PMOS transistor and a sixth bias PMOS transistor; The source of the fifth bias PMOS transistor is connected to the drain of the first pull-up PMOS transistor; the source of the sixth bias PMOS transistor is connected to the gate and drain of the fifth bias PMOS transistor and the protection module, respectively; the drain of the sixth bias PMOS transistor is connected to the gate of the second pull-up PMOS transistor. The second bias control unit includes: a seventh bias PMOS transistor and an eighth bias PMOS transistor; The source of the seventh bias PMOS transistor is connected to the drain of the second pull-up PMOS transistor; the source of the eighth bias PMOS transistor is connected to the gate and drain of the seventh bias PMOS transistor and the protection module, respectively; the drain of the eighth bias PMOS transistor is connected to the gate of the first pull-up PMOS transistor. The gates of the sixth bias PMOS transistor and the eighth bias PMOS transistor are respectively used to receive the bias voltage.

5. The level conversion circuit according to claim 1, characterized in that, The first pull-down module includes: a first low-voltage pull-down NMOS transistor, a second low-voltage pull-down NMOS transistor, a first mode switching unit, a second mode switching unit, a third mode switching unit, a first voltage-limiting NMOS transistor, a second voltage-limiting NMOS transistor, and a third voltage-limiting NMOS transistor; Wherein, the gate of the first low-voltage pull-down NMOS transistor is connected to the second input node, the source of the first low-voltage pull-down NMOS transistor is used to connect to the reference ground voltage, and the drain of the first low-voltage pull-down NMOS transistor is connected to the first terminal of the first mode switching unit; The second terminal of the first mode switching unit is connected to the source of the first voltage-limiting NMOS transistor; the control terminal of the first mode switching unit is used to connect to the mode control node; The gate of the first voltage-limiting NMOS transistor is used to receive the protection voltage, and the drain of the first voltage-limiting NMOS transistor is connected to the pull-up module; The gate of the second low-voltage pull-down NMOS transistor is connected to the first input node, the source of the second low-voltage pull-down NMOS transistor is used to connect to the reference ground voltage, and the drain of the second low-voltage pull-down NMOS transistor is connected to the first terminal of the second mode switching unit; The second terminal of the second mode switching unit is connected to the source of the second voltage-limiting NMOS transistor; the control terminal of the second mode switching unit is used to connect to the mode control node; The gate of the second voltage-limiting NMOS transistor is used to receive the protection voltage, and the drain of the second voltage-limiting NMOS transistor is connected to the pull-up module; The first terminal of the third mode switching unit is connected to the source of the third voltage-limiting NMOS transistor, and the second terminal of the third mode switching unit is connected to the drain of the second low-voltage pull-down NMOS transistor; the control terminal of the third mode switching unit is used to connect to the mode control node. The gate of the third voltage-limiting NMOS transistor is used to receive the protection voltage, and the drain of the third voltage-limiting NMOS transistor is used to connect to the second output node; Specifically, when the mode control node receives the first mode signal, the first terminal of the first mode switching unit is disconnected from the second terminal; the first terminal of the second mode switching unit is disconnected from the second terminal; and the first terminal of the third mode switching unit is disconnected from the second terminal. When the mode control node receives the second mode signal, the first end of the first mode switching unit is connected to the second end; the first end of the second mode switching unit is connected to the second end; and the first end of the third mode switching unit is connected to the second end. The protection voltage is greater than or equal to the difference between the first voltage and the maximum withstand voltage.

6. The level conversion circuit according to claim 5, characterized in that, The first mode switching unit includes a first mode switching NMOS transistor; the gate of the first mode switching NMOS transistor is used to connect to the mode control node, and the drain of the first mode switching NMOS transistor is connected to the source of the first voltage-limiting NMOS transistor; the drain of the first mode switching unit is connected to the drain of the first low-voltage pull-down NMOS transistor. The second mode switching unit includes a second mode switching NMOS transistor; the gate of the second mode switching NMOS transistor is used to connect to the mode control node, and the drain of the second mode switching NMOS transistor is connected to the source of the second voltage-limiting NMOS transistor; the drain of the second mode switching unit is connected to the drain of the second low-voltage pull-down NMOS transistor. The third mode switching unit includes a third mode switching NMOS transistor; the gate of the third mode switching NMOS transistor is used to connect to the mode control node, the drain of the third mode switching NMOS transistor is connected to the source of the third voltage-limiting NMOS transistor, and the drain of the third mode switching NMOS transistor is connected to the drain of the second low-voltage pull-down NMOS transistor.

7. The level conversion circuit according to claim 1, characterized in that, The second pull-down module includes: a high-voltage pull-up auxiliary unit, a first high-voltage pull-down unit, a second high-voltage pull-down unit, and a low-voltage pull-down unit; The first end of the high-voltage pull-up auxiliary unit is used to connect to the power supply voltage, the second end of the high-voltage pull-up auxiliary unit is used to connect to the first output node, and the control end of the high-voltage pull-up auxiliary unit is connected to the pull-up module and the second output node respectively. The first end of the first high-voltage pull-down unit is used to connect to the third voltage, the second end of the first high-voltage pull-down unit is used to connect to the second output node, and the control end of the first high-voltage pull-down unit is connected to the protection module. The first terminal of the low-voltage pull-down unit is used to connect to the first output node, and the second terminal of the low-voltage pull-down unit is used to connect to the reference ground voltage; the first control terminal of the low-voltage pull-down unit is used to connect to the mode control node; the second control terminal of the low-voltage pull-down unit is used to connect to the second input node. The first terminal of the second high-voltage pull-down unit is used to connect to the third voltage, and the second terminal of the second high-voltage pull-down unit is used to connect to the first output node; the third terminal of the second high-voltage pull-down unit is connected to the third terminal of the low-voltage pull-down unit. When the mode control node receives the first mode signal and the first input signal is the fourth voltage, the high voltage pull-up auxiliary unit turns on the first and second terminals of the high voltage pull-up auxiliary unit according to the signal of the pull-up module, and the first high voltage pull-down unit turns on the first and second terminals of the first high voltage pull-down unit according to the signal of the protection module. When the mode control node receives the first mode signal and the first input signal is the reference ground voltage, the second high voltage pull-down unit is used to connect the first terminal and the second terminal of the second high voltage pull-down unit. When the mode control node receives the second mode signal and the second input signal is the fourth voltage, the second terminal of the low-voltage pull-down unit is connected to the third terminal.

8. The level conversion circuit according to claim 7, characterized in that, The high-voltage pull-up auxiliary unit includes an auxiliary PMOS transistor, the source of which is connected to the power supply voltage; the drain of which is connected to the first output node; and the gate of which is connected to the pull-up module and the second output node.

9. The level conversion circuit according to claim 7, characterized in that, The first high-voltage pull-down unit includes a first high-voltage pull-down PMOS transistor and a second high-voltage pull-down PMOS transistor; The source of the first high-voltage pull-down PMOS transistor is connected to the third voltage, and the gate of the first high-voltage pull-down PMOS transistor is connected to the protection module; the drain of the first high-voltage pull-down PMOS transistor is connected to the source of the second high-voltage pull-down PMOS transistor. The gate of the second high-voltage pull-down PMOS transistor is connected to the protection module; the drain of the second high-voltage pull-down PMOS transistor is used to connect to the second output node.

10. The level conversion circuit according to claim 7, characterized in that, The low-voltage pull-down unit includes: a third low-voltage pull-down NMOS transistor, a mode switching subunit, and a fourth voltage-limiting NMOS transistor; The gate of the third low-voltage pull-down NMOS transistor is used to connect to the second input node, the drain of the third low-voltage pull-down NMOS transistor is used to connect to the reference ground voltage, and the source of the third low-voltage pull-down NMOS transistor is connected to the first terminal of the mode switching subunit and the third terminal of the second high-voltage pull-down unit, respectively. The control terminal of the mode switching subunit is used to connect to the mode control node; the second terminal of the mode switching subunit is used to connect to the drain of the fourth voltage-limiting NMOS transistor. The gate of the fourth voltage-limiting NMOS transistor is used to connect to the protection voltage, and the source of the fourth voltage-limiting NMOS transistor is used to connect to the first output node; The protection voltage is greater than or equal to the difference between the first voltage and the maximum withstand voltage value; When the mode control node receives the second mode signal, the first and second terminals of the mode switching subunit are connected. When the second input signal is the fourth voltage, the source and drain of the third low-voltage pull-down NMOS transistor are connected.

11. The level conversion circuit according to claim 7, characterized in that, The second high-voltage pull-down unit includes: a ninth bias PMOS transistor, a third high-voltage pull-down PMOS transistor, a fifth voltage-limiting NMOS transistor, and a dynamic adjustment subunit; The drain of the ninth bias PMOS transistor is used to connect to the first output node; the gate of the ninth bias PMOS transistor is used to receive the bias voltage; and the source of the ninth bias PMOS transistor is connected to the drain of the third high-voltage pull-down PMOS transistor. The source of the third high-voltage pull-down PMOS transistor is connected to the first detection terminal of the dynamic voltage drop adjustment subunit, and the gate of the third high-voltage pull-down PMOS transistor is connected to the second detection terminal of the dynamic voltage drop adjustment subunit. The source of the fifth voltage-limiting NMOS transistor is connected to the third terminal of the low-voltage pull-down unit, and the drain of the fifth voltage-limiting NMOS transistor is connected to the third detection terminal of the dynamic adjustment subunit. The dynamic adjustment subunit is used to adjust the voltage input to the gate of the third high-voltage pull-down PMOS transistor according to the voltage changes of the first detection terminal and the second detection terminal during the level conversion of the second input signal, so that the voltage difference between the ports of the third high-voltage pull-down PMOS transistor is less than or equal to the maximum withstand voltage value. When the mode control node receives the first mode signal, the bias voltage is the third voltage.

12. The level conversion circuit according to claim 11, characterized in that, The dynamic adjustment subunit includes: a first adjustment NMOS transistor, a second adjustment NMOS transistor, a third adjustment NMOS transistor, a first adjustment PMOS transistor, and a second adjustment PMOS transistor; Wherein, the source of the first adjusting NMOS transistor is connected to the source of the third high-voltage pull-down PMOS transistor, the gate of the first adjusting NMOS transistor is used to receive the bias voltage, and the drain of the first adjusting NMOS transistor is connected to the source of the second adjusting NMOS transistor. The gate of the second adjusting NMOS transistor is connected to the drain of the third adjusting NMOS transistor; the drain of the second adjusting NMOS transistor is used to receive the third voltage. The source of the third adjusting NMOS transistor is connected to the drain of the fifth limiting NMOS transistor; the gate of the third adjusting NMOS transistor is connected to the source of the first adjusting PMOS transistor; and the drain of the third adjusting NMOS transistor is connected to the drain of the first adjusting PMOS transistor. The gate of the first regulating PMOS transistor is used to receive the protection voltage; the source of the first regulating PMOS transistor is connected to the drain of the second regulating PMOS transistor. The gate of the second adjusting PMOS transistor is connected to the drain of the third adjusting NMOS transistor, and the source of the second adjusting PMOS transistor is used to receive the protection voltage. Wherein, the protection voltage is greater than or equal to the difference between the first voltage and the maximum withstand voltage value.

13. The level conversion circuit according to claim 2, characterized in that, The protection module includes a first protection unit and a second protection unit; The first terminal of the first protection unit is connected to the third terminal of the first bias control unit, and the second terminal of the first protection unit is connected to the first pull-down module; when the second input signal is the first voltage, the first pull-down module is used to connect the second terminal of the first protection unit to the reference ground voltage. The first end of the second protection unit is connected to the third end of the second bias control unit, and the first end of the second protection unit is also connected to the second pull-down module; the second end of the second protection unit is used to connect to the mode control node.

14. The level conversion circuit according to claim 13, characterized in that, The first protection unit includes a first protection NMOS transistor, a first protection PMOS transistor, and a sixth voltage-limiting NMOS transistor; The gate of the first protection NMOS transistor is connected to the third terminal of the first bias control unit, the drain of the first protection NMOS transistor is connected to the drain of the first protection PMOS transistor, and the source of the first protection NMOS transistor is connected to the gate of the first protection PMOS transistor and the source of the sixth voltage-limiting NMOS transistor. The source of the first protection PMOS transistor is connected to the third terminal of the first bias control unit; The gate of the sixth voltage-limiting NMOS transistor is used to receive the protection voltage, and the drain of the sixth voltage-limiting NMOS transistor is connected to the first pull-down module. Wherein, the protection voltage is greater than or equal to the difference between the first voltage and the maximum withstand voltage value.

15. The level conversion circuit according to claim 13, characterized in that, The second protection unit includes a second protection NMOS transistor, a second protection PMOS transistor, and a seventh voltage-limiting NMOS transistor; The gate of the second protection NMOS transistor is connected to the third terminal of the second bias control unit, the drain of the second protection NMOS transistor is connected to the drain of the second protection PMOS transistor, and the source of the second protection NMOS transistor is connected to the gate of the second protection PMOS transistor and the source of the seventh voltage-limiting NMOS transistor, respectively. The source of the second protection PMOS transistor is connected to the third terminal of the second bias control unit and the second pull-down module, respectively. The gate of the seventh voltage-limiting NMOS transistor is used to receive the protection voltage, and the drain of the seventh voltage-limiting NMOS transistor is used to connect to the mode control node; wherein, the protection voltage is greater than or equal to the difference between the first voltage and the maximum withstand voltage value.

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