A GaN HEMT device with integrated reverse conduction function and its fabrication method

Abstract

The application discloses a GaN HEMT device integrated with a reverse conduction function and a preparation method thereof, and belongs to the technical field of semiconductor devices. The device comprises a substrate and a buffer layer, a first channel layer, a first barrier layer, an isolation layer, a second channel layer, a second barrier layer and a p-GaN layer which are sequentially stacked; wherein a first recess is formed in the second barrier layer and penetrates to the first channel layer, the bottom of the recess is provided with an anode which forms a Schottky contact with the first channel layer, and a source electrode covers the anode and the first recess; a second recess is formed and penetrates to the first barrier layer, and a cathode which forms an ohmic contact with the first barrier layer is arranged in the recess. The application integrates an independent reverse conduction diode channel in the GaN HEMT device by constructing a double heterojunction structure and a specific recess electrode design, realizes single-chip integration of forward switching and reverse current flow, effectively reduces a reverse conduction voltage drop, eliminates parasitic parameters of an externally-mounted diode, and significantly improves the power density and reliability of a system.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and more specifically, to a GaNHEMT device with integrated reverse conduction function and its fabrication method. Background Technology

[0002] Gallium nitride (GaN), a wide-bandgap semiconductor material, has become an ideal material for developing next-generation high-efficiency, high-power-density power electronic devices due to its high critical breakdown electric field, high electron saturation drift velocity, and excellent two-dimensional electron gas (2DEG) mobility. High electron mobility transistors (HEMTs) based on GaN utilize the two-dimensional electron gas formed at the heterojunction interface as a conductive channel, achieving extremely low on-resistance and extremely high switching speeds, demonstrating enormous application potential in switching power supplies, inverters, and RF power amplifiers.

[0003] In typical bridge power conversion circuits (such as half-bridge, full-bridge topologies, and DC-DC converters), a freewheeling diode (FWD) is required in parallel with the power switching device to provide a reverse freewheeling path for the inductive load current. This prevents excessively high voltage spikes caused by sudden changes in inductor current when the switch is turned off, thus protecting the device and maintaining normal circuit operation. For traditional silicon-based power MOSFETs, their inherent body diode can perform the freewheeling function. However, conventional GaN HEMTs, as lateral devices, do not have a vertical body diode structure similar to that of MOSFETs. Therefore, existing technologies commonly employ a scheme of connecting an independent silicon-based fast recovery diode (FRD) or Schottky barrier diode (SBD) in parallel with the GaN HEMT device to construct the freewheeling circuit.

[0004] This discrete solution has significant inherent drawbacks: First, the additional diode components increase the system's material cost, packaging complexity, and overall size, hindering the achievement of high power density and miniaturized integration. Second, the package leads of discrete devices and the traces on the printed circuit board introduce significant parasitic inductance and capacitance, leading to severe voltage overshoot and ringing during high-speed switching. This not only increases switching losses but may also cause overvoltage breakdown of the devices, threatening circuit reliability. Furthermore, the recovery characteristics of the external diode may not match the fast switching characteristics of GaN HEMTs, limiting the optimization of overall system performance.

[0005] To overcome the drawbacks of external discrete diodes, the industry has explored utilizing the inherent bidirectional conductivity of GaN HEMT devices to achieve reverse conduction. A common approach is to use the gate of the HEMT to open the two-dimensional electron gas channel beneath it under reverse bias, thereby achieving reverse conduction. However, this conduction method suffers from a high on-state voltage drop. Physically, the reverse conduction turn-on voltage is equal to the difference between its threshold voltage and the gate-source voltage. To ensure reliable system operation and prevent false turn-on, the circuit typically applies a negative bias voltage to the gate, which further increases the already high on-state voltage drop, resulting in a significant voltage drop and power loss during reverse conduction. Furthermore, the threshold voltage of GaN HEMTs may exhibit dynamic shifts, making the reverse conduction characteristics unstable and unpredictable. The high reverse conduction voltage drop not only directly reduces system efficiency but also leads to significant heat generation, posing a serious challenge to device reliability. Another approach is to try integrating Schottky diodes into GaN epitaxial structures. However, how to achieve low-loss, high-performance reverse conduction without degrading the forward performance of HEMTs or significantly increasing process complexity remains a technical challenge that needs to be solved in this field.

[0006] Therefore, there is an urgent need in this field for a novel GaN HEMT device structure that can significantly reduce the reverse conduction voltage drop while maintaining or even optimizing the device's forward blocking capability and low on-resistance, achieving monolithic integration of forward switching and reverse freewheeling functions, thereby eliminating the drawbacks of external discrete components and meeting the stringent requirements of modern power electronic systems for high efficiency, high power density, and high reliability. Summary of the Invention

[0007] To address the problems of high reverse conduction voltage drop, high loss, and parasitic parameters introduced by external freewheeling diodes in existing GaN HEMT devices, this invention provides a GaN HEMT device with integrated reverse conduction function and its fabrication method. By constructing a double-layer heterojunction structure and a specific electrode layout, an independent reverse conduction diode channel is integrated inside the GaN HEMT device, realizing monolithic integration of low-loss reverse freewheeling and high-efficiency forward switching, effectively solving the problem that the reverse conduction voltage drop is limited by the threshold voltage.

[0008] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0009] A GaN HEMT device with integrated reverse conduction function includes:

[0010] Substrate;

[0011] A buffer layer is formed on the substrate;

[0012] The first channel layer is formed on the buffer layer;

[0013] A first barrier layer is formed on the first channel layer;

[0014] An isolation layer is formed on the first barrier layer;

[0015] The HEMT device structure is formed on the isolation layer, including a second channel layer and a second barrier layer formed sequentially on the isolation layer, a p-GaN layer formed on the second barrier layer, a gate formed on the p-GaN layer, and a source and drain formed on the second barrier layer on both sides of the gate, respectively.

[0016] The first and second grooves are formed on the second barrier layer;

[0017] The first groove penetrates the second barrier layer, the second channel layer, the isolation layer and the first barrier layer and extends to the first channel layer. The first groove is filled with Schottky contact metal and Ohmic contact metal to form an anode and a source, respectively. The anode is located at the bottom of the first groove and is electrically connected to the first channel layer. The source covers the first groove and is electrically connected to the second channel layer.

[0018] The second groove penetrates the second barrier layer, the second channel layer, and the isolation layer and extends to the first barrier layer. The second groove is filled with ohmic contact metal to form a cathode. The cathode is electrically connected to the first barrier layer, and the second groove is located on the side of the drain away from the gate.

[0019] Specifically, the material of the isolation layer includes AlN or AlGaN, and the thickness of the isolation layer is 50nm~150nm, which is used to suppress carrier tunneling between the first channel layer and the second channel layer.

[0020] Specifically, the materials of the first channel layer and the second channel layer both include GaN, the materials of the first barrier layer and the second barrier layer both include AlGaN, the first channel layer and the first barrier layer form a first heterojunction, and the second channel layer and the second barrier layer form a second heterojunction.

[0021] Specifically, the first channel layer is replaced with an n-type doped layer, the first barrier layer is replaced with a p-type doped layer, and the n-type doped layer and the p-type doped layer form a PN junction structure;

[0022] The first groove penetrates the second barrier layer, the second channel layer, and the isolation layer and extends to the p-type doped layer. The first groove is filled with ohmic contact metal to form the source electrode, and the source electrode is electrically connected to the p-type doped layer.

[0023] The second groove extends through the second barrier layer, the second channel layer, the isolation layer, and the p-type doped layer. The sidewalls of the second groove are covered with a dielectric layer. The cathode covers the dielectric layer and the bottom of the second groove and is electrically connected to the n-type doped layer.

[0024] Specifically, the material of the dielectric layer includes at least one of AlN, Al2O3, SiO2, and Si3N4, and the thickness of the dielectric layer is 20nm to 50nm.

[0025] Specifically, the substrate is a silicon substrate, a silicon carbide substrate, or a sapphire substrate; the material of the buffer layer includes at least one of AlN, AlGaN, InGaN, or GaN, and the thickness of the buffer layer is 1000nm~4000nm.

[0026] Specifically, the source, drain, and cathode are all ohmic contacts, and the gate and anode are all Schottky contacts; the gaps between the source, gate, and drain are filled with a passivation layer, the material of which includes Al2O3.

[0027] Specifically, the anode forms a Schottky contact with the two-dimensional electron gas at the bottom of the first channel layer, the cathode forms an ohmic contact with the two-dimensional electron gas below the first barrier layer, and the source forms an ohmic contact with the two-dimensional electron gas above the second channel layer.

[0028] Furthermore, the present invention also provides a method for fabricating the above-mentioned GaN HEMT device with integrated reverse conduction function, comprising the following steps:

[0029] S1. A substrate is provided, and a buffer layer, a first channel layer, a first barrier layer, an isolation layer, a second channel layer, a second barrier layer and a p-GaN layer are epitaxially grown sequentially on the substrate as a device epitaxial layer;

[0030] S2. Etch the p-GaN layer down to the second barrier layer, retaining the p-GaN layer in the gate region;

[0031] S3. A first groove and a second groove are etched on the second barrier layer, wherein the first groove is etched above the first channel layer and the second groove is etched above the first barrier layer.

[0032] S4. A Schottky contact metal is deposited at the bottom of the first groove to form an anode, and the anode forms a Schottky contact with the first channel layer;

[0033] S5. Source trench and drain trench are etched on the second barrier layer, and the etching depth does not exceed the thickness of the second barrier layer.

[0034] S6. Deposit ohmic contact metal at the first groove, the source groove, the drain groove and the second groove to form a source, a drain and a cathode. The source and drain form ohmic contact with the upper two-dimensional electron gas and the cathode forms ohmic contact with the lower two-dimensional electron gas.

[0035] S7. Deposit gate metal on the retained p-GaN layer to form the gate.

[0036] Specifically, in step S4, the Schottky contact metal adopts a Ni / Au stacked structure; in step S6, the ohmic contact metal adopts a Ti / Al / Ni / Au stacked structure.

[0037] Compared with the prior art, the present invention has the following beneficial effects:

[0038] (1) This invention constructs two independent upper and lower conduction paths in the HEMT epitaxial structure and integrates a Schottky diode monolithically inside the GaN HEMT device using a through-type groove electrode design. In reverse conduction mode, current flows through the anode, the first channel layer, and the cathode. Since this path is independent of the gate control region of the HEMT, its on-state voltage drop is determined only by the characteristics of the integrated diode and is not affected by the HEMT threshold voltage and the gate negative bias voltage, thereby significantly reducing reverse conduction loss and improving system efficiency.

[0039] (2) By setting an isolation layer, the present invention effectively suppresses the coupling interference between the upper HEMT channel and the lower diode channel, ensuring the independence and stability of the device's forward blocking capability and reverse freewheeling capability, and avoiding the influence of threshold voltage drift on the reverse characteristics.

[0040] (3) Compared with the external discrete diode solution, the monolithic integrated solution of the present invention eliminates the parasitic inductance and parasitic capacitance caused by the package leads, reduces switching losses and electromagnetic interference, which is beneficial to improving the power density and switching frequency of the system, while reducing the system size and cost. Attached Figure Description

[0041] Figure 1 This is a schematic diagram of the device structure of Embodiment 1 of the present invention.

[0042] Figure 2 for Figure 1 Schematic diagram of the cross-sectional structure of the device A-A'.

[0043] Figure 3 for Figure 1 Schematic diagram of the cross-sectional structure of the device B-B'.

[0044] Figure 4 This is a schematic diagram of a partial cross-sectional structure of the device in Embodiment 2 of the present invention.

[0045] In the above figures, the component names corresponding to the reference numerals are as follows:

[0046] 101-Substrate, 102-Buffer layer, 103-First channel layer, 104-First barrier layer, 105-Isolation layer, 106-Second channel layer, 107-Second barrier layer, 108-p-GaN layer, 109-Gate, 110-Drain, 111-Source, 112-First trench, 113-Anode, 114-Second trench, 115-Cathode; 203-n-type doped layer, 204-p-type doped layer, 205-Dielectric layer. Detailed Implementation

[0047] The present invention will be further described below with reference to the accompanying drawings and embodiments. The embodiments of the present invention include, but are not limited to, the following embodiments.

[0048] Example 1

[0049] like Figures 1 to 3 As shown, this embodiment provides a GaN HEMT device with integrated reverse conduction function, which mainly includes an epitaxial structure stacked vertically from bottom to top and an electrode structure formed on the epitaxial structure.

[0050] The epitaxial structure specifically includes: a substrate 101, preferably made of silicon, silicon carbide, or sapphire, used to support the entire device structure; a buffer layer 102, formed on the substrate 101, made of one or more combinations of AlN, AlGaN, InGaN, or GaN, with a thickness preferably of 1000 nm to 4000 nm, used to alleviate lattice mismatch between the substrate and GaN and reduce defects; a first channel layer 103, formed on the buffer layer 102, preferably made of undoped GaN, with a thickness of 100 nm to 300 nm; and a first barrier layer 104, formed on the first channel layer 103, preferably made of AlGaN, with an Al content of approximately 25%, and a thickness of 15 nm to 30 nm. The first channel layer 103 and the first barrier layer 104 form a first heterojunction, and a lower two-dimensional electron gas (2DEG) is generated at the interface.

[0051] An isolation layer 105 is formed on the first barrier layer 104. The material of the isolation layer is preferably AlN or AlGaN with a high aluminum content (Al>40%), and its thickness is 50nm~150nm. The isolation layer 105 can effectively suppress quantum tunneling of charge carriers between the upper and lower layers, thereby achieving electrical isolation.

[0052] The main structure of the HEMT device is formed on the isolation layer 105, including: a second channel layer 106, preferably made of undoped GaN, with a thickness of 100nm~300nm; a second barrier layer 107, preferably made of AlGaN, with an Al content of approximately 25%, and a thickness of 15nm~30nm; and a p-GaN layer 108, formed on the gate region of the second barrier layer 107, which is a p-GaN layer doped with Mg, Zn, or Ca. The second channel layer 106 and the second barrier layer 107 form a second heterojunction, and an upper two-dimensional electron gas (2DEG) is generated at the interface.

[0053] The electrode structure specifically includes: gate 109, drain 110, source 111, anode 113, and cathode 115. Gate 109 is formed on a p-GaN layer 108, typically using a Schottky contact metal (such as Ni / Au). The p-GaN layer provides enhancement-mode characteristics, meaning the device is in a turn-off state at zero gate-source voltage, meeting the safety requirements of power electronic applications. Source 111 and drain 110 are located on either side of gate 109 and form ohmic contacts with the upper two-dimensional electron gas layer.

[0054] Specifically, this embodiment integrates a reverse conduction function into the above structure. Specifically, a first groove 112 is formed below the source electrode 111, penetrating the second barrier layer 107, the second channel layer 106, the isolation layer 105, and the first barrier layer 104, and extending to the first channel layer 103. A Schottky contact metal is filled at the bottom of the first groove 112 to form an anode 113, which forms a Schottky contact with the lower two-dimensional electron gas in the first channel layer 103. The source electrode 111 covers the first groove 112, fills the first groove 112, and contacts the upper surfaces of the second barrier layer 107 and the anode 113, achieving ohmic contact between the source electrode 111 and the upper two-dimensional electron gas, while simultaneously achieving a physical connection between the source electrode 111 and the anode 113. A second groove 114 is formed on the side of the drain 110 away from the gate 109, which penetrates the second barrier layer 107, the second channel layer 106 and the isolation layer 105 and extends to the first barrier layer 104; the second groove 114 is filled with ohmic contact metal to form a cathode 115, and the cathode 115 forms an ohmic contact with the lower two-dimensional electron gas in the first barrier layer 104.

[0055] For example, the Schottky contact metal and the ohmic contact metal may specifically include, but are not limited to, Al, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, Si, metal alloys or compounds thereof, or other metal compounds.

[0056] The working principle of the device in this embodiment is as follows:

[0057] During forward conduction, a positive voltage is applied to the gate 109, which opens the upper two-dimensional electron gas channel at the interface between the second channel layer 106 and the second barrier layer 107, allowing current to flow from the drain 110 to the source 111. At this time, since the anode is connected to the source at a low potential and the cathode is connected to the drain at a high potential, the lower diode structure between the anode 113 and the cathode 115 is in a reverse blocking state, which does not affect forward conduction.

[0058] During reverse freewheeling, a negative or zero voltage (off state) is applied to the gate 109, and the HEMT channel is turned off. Due to the inductive load, the source 111 potential is higher than the drain 110 potential. At this time, current flows from the source 111 to the anode 113. Since the anode 113 has a Schottky contact with the lower two-dimensional electron gas, it quickly conducts under forward bias. The current flows through the first channel layer 103 to the cathode 115 and finally to the drain 110 side. Because this path utilizes the low on-state voltage drop characteristic of the Schottky junction and is independent of the gate channel of the HEMT, the reverse voltage drop is determined only by the characteristics of the Schottky junction, typically 0.7V-1.5V, which is much lower than the high voltage drop (>2V) during reverse conduction in traditional HEMTs, significantly reducing losses.

[0059] This embodiment also provides a method for fabricating the above-mentioned device, the specific steps of which are as follows:

[0060] S1. Epitaxial Structure Growth: A substrate is provided, and a buffer layer, a first channel layer, a first barrier layer, an isolation layer, a second channel layer, a second barrier layer, and a p-GaN layer are sequentially epitaxially grown on the substrate using metal-organic chemical vapor deposition (MOCVD) technology, serving as the device epitaxial layer. During the growth process, process parameters such as temperature, pressure, and gas flow rate are strictly controlled to ensure crystal quality.

[0061] S2. Gate mesa etching: The p-GaN layer is etched away using inductively coupled plasma (ICP) etching process, leaving only the p-GaN layer in the gate region. The etching endpoint is on the surface of the second barrier layer to avoid damaging the barrier layer.

[0062] S3. Etching the first and second grooves: Continuing with the ICP process, etch the first and second grooves at predetermined locations. The first groove has a greater etching depth, penetrating the upper structure to the first channel layer, while the second groove is etched down to the first barrier layer. The etching process precisely controls the depth to avoid over-etching and damaging the underlying channel.

[0063] S4. Anode deposition: The anode region is defined by photolithography, and Schottky contact metal is deposited using electron beam evaporation technology. The preferred material is a Ni / Au stack with a thickness of 50nm / 100nm. The anode located at the bottom of the first groove is retained by a lift-off process.

[0064] S5. Etching source and drain trenches: The source and drain trench areas on the barrier layer are defined using photolithography. Shallow source and drain trenches are etched on the second barrier layer using ICP process. The etching depth does not exceed the thickness of the second barrier layer, which is used to form good ohmic contacts in the future.

[0065] S6. Deposition of Source, Drain, and Cathode: The source, drain, and cathode regions are defined using photolithography. Ohmic contact metals for the source, drain, and cathode are deposited using electron beam evaporation. The preferred material is a Ti / Al / Ni / Au stack with thicknesses of 20nm / 100nm / 50nm / 100nm. The corresponding electrodes are formed through a lift-off process and then placed in a rapid thermal annealing furnace for annealing in a nitrogen or oxygen atmosphere at a temperature of 400℃~800℃ for 30s~200s. This allows the metal and semiconductor material to undergo an alloying reaction, forming a low-resistance ohmic contact.

[0066] S7. Deposited gate: The gate area is lithographically etched using photolithography, and the gate metal Ni / Au is deposited by electron beam evaporation with a thickness of 50nm / 100nm. After peeling, the gate is formed.

[0067] S8. Passivation treatment: Atomic layer deposition (ALD) or plasma-enhanced chemical vapor deposition (PECVD) processes are used to grow an aluminum oxide or other dielectric layer on the device surface as a passivation layer to fill the gaps between electrodes, protect the device surface from environmental pollution, and suppress current collapse effect.

[0068] Example 2

[0069] like Figure 4 As shown, this embodiment provides another GaN HEMT device with a different structure. The difference from Embodiment 1 is that the first channel layer 103 in the epitaxial structure is replaced with an n-type doped layer 203, and the first barrier layer 104 is replaced with a p-type doped layer 204, forming a PN junction structure. The material of the n-type doped layer 203 may include, but is not limited to, n-doped III-V group nitride semiconductor materials, such as n-type GaN, n-type AlGaN, n-type InN, n-type AlInN, n-type InGaN, and n-type AlInGaN. The n-type doped material is achieved by using n-type impurities such as Si, Ge, Sn, O, and Se. The p-type doped layer 204 may include, but is not limited to, p-doped III-V group nitride semiconductor materials, such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type InGaN, and p-type AlInGaN. The p-type doped material is achieved by using p-type impurities such as Be, Mg, Zn, Cd, and Mg.

[0070] In this structure, the first groove 112 penetrates the second barrier layer 107, the second channel layer 106, and the isolation layer 105, and extends to the p-type doped layer 204. The first groove 112 is filled with ohmic contact metal to form a source 111, which is electrically connected to the p-type doped layer 204.

[0071] The second groove 114 penetrates the second barrier layer 107, the second channel layer 106, the isolation layer 105, and the p-type doped layer 204, extending into the n-type doped layer 203. A dielectric layer 205 is first deposited on the sidewalls and bottom of the second groove 114. The preferred material is at least one of AlN, Al2O3, SiO2, Si3N4, AlON, and SiON, with a thickness of 20 nm to 50 nm, used for sidewall passivation and isolation. Subsequently, a metal is deposited on the dielectric layer 205 and at the bottom of the groove to form a cathode 115. The cathode 115 penetrates the p-type doped layer 204 and forms an ohmic contact with the n-type doped layer 203.

[0072] In this embodiment, a PN junction is used instead of a heterojunction as the underlying conductive channel. During reverse freewheeling, the source 111 is connected to the p-type layer, and the cathode 115 is connected to the n-type layer, forming a PN diode structure integrated inside the chip. Although the turn-on voltage of the PN junction is slightly higher than that of the Schottky junction, its reverse leakage current is lower, and the PN junction structure exhibits superior voltage withstand capability. Furthermore, by introducing a dielectric layer 205 on the cathode sidewall, the electric field concentration effect at the mesa edge is effectively suppressed, further improving the reverse voltage withstand capability and reliability of the device.

[0073] The above embodiments are merely preferred embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any changes made based on the design principles of the present invention, or any non-creative modifications made thereon, shall fall within the scope of protection of the present invention.

Claims

1. A GaN HEMT device integrating reverse conduction function, characterized in that, include: Substrate; A buffer layer is formed on the substrate; The first channel layer is formed on the buffer layer; A first barrier layer is formed on the first channel layer; An isolation layer is formed on the first barrier layer; The HEMT device structure is formed on the isolation layer, including a second channel layer and a second barrier layer formed sequentially on the isolation layer, a p-GaN layer formed on the second barrier layer, a gate formed on the p-GaN layer, and a source and drain formed on the second barrier layer on both sides of the gate, respectively. The first and second grooves are formed on the second barrier layer; The first groove penetrates the second barrier layer, the second channel layer, the isolation layer and the first barrier layer and extends to the first channel layer. The first groove is filled with Schottky contact metal and Ohmic contact metal to form an anode and a source, respectively. The anode is located at the bottom of the first groove and is electrically connected to the first channel layer. The source covers the first groove and is electrically connected to the second channel layer. The second groove penetrates the second barrier layer, the second channel layer, and the isolation layer and extends to the first barrier layer. The second groove is filled with ohmic contact metal to form a cathode. The cathode is electrically connected to the first barrier layer, and the second groove is located on the side of the drain away from the gate. The material of the isolation layer includes AlN or AlGaN, and the thickness of the isolation layer is 50nm~150nm, which is used to suppress carrier tunneling between the first channel layer and the second channel layer. The materials of the first channel layer and the second channel layer both include GaN, and the materials of the first barrier layer and the second barrier layer both include AlGaN. The first channel layer and the first barrier layer form a first heterojunction, and the second channel layer and the second barrier layer form a second heterojunction.

2. The GaN HEMT device with integrated reverse conduction function according to claim 1, characterized in that, The first channel layer is replaced with an n-type doped layer, the first barrier layer is replaced with a p-type doped layer, and the n-type doped layer and the p-type doped layer form a PN junction structure; The first groove penetrates the second barrier layer, the second channel layer, and the isolation layer and extends to the p-type doped layer. The first groove is filled with ohmic contact metal to form the source electrode, and the source electrode is electrically connected to the p-type doped layer. The second groove extends through the second barrier layer, the second channel layer, the isolation layer, and the p-type doped layer. The sidewalls of the second groove are covered with a dielectric layer. The cathode covers the dielectric layer and the bottom of the second groove and is electrically connected to the n-type doped layer.

3. The GaN HEMT device with integrated reverse conduction function according to claim 2, characterized in that, The material of the dielectric layer includes at least one of AlN, Al2O3, SiO2, and Si3N4, and the thickness of the dielectric layer is 20nm to 50nm.

4. The GaN HEMT device with integrated reverse conduction function according to claim 1, characterized in that, The substrate is a silicon substrate, a silicon carbide substrate, or a sapphire substrate; the material of the buffer layer includes at least one of AlN, AlGaN, InGaN, or GaN, and the thickness of the buffer layer is 1000nm~4000nm.

5. The GaN HEMT device with integrated reverse conduction function according to claim 1, characterized in that, The source, drain, and cathode are all ohmic contacts, and the gate and anode are all Schottky contacts. The gaps between the source, gate, and drain are filled with a passivation layer, the material of which includes Al2O3.

6. The GaN HEMT device with integrated reverse conduction function according to any one of claims 1 to 5, characterized in that, The anode forms a Schottky contact with the two-dimensional electron gas at the bottom of the first channel layer, the cathode forms an ohmic contact with the two-dimensional electron gas below the first barrier layer, and the source forms an ohmic contact with the two-dimensional electron gas above the second channel layer.

7. A method for fabricating a GaN HEMT device with integrated reverse conduction function as described in any one of claims 1-6, characterized in that, Includes the following steps: S1. A substrate is provided, and a buffer layer, a first channel layer, a first barrier layer, an isolation layer, a second channel layer, a second barrier layer and a p-GaN layer are epitaxially grown sequentially on the substrate. S2. Etch the p-GaN layer down to the second barrier layer, retaining the p-GaN layer in the gate region; S3. A first groove and a second groove are etched on the second barrier layer, wherein the first groove is etched above the first channel layer and the second groove is etched above the first barrier layer. S4. A Schottky contact metal is deposited at the bottom of the first groove to form an anode, and the anode forms a Schottky contact with the first channel layer; S5. Source trench and drain trench are etched on the second barrier layer, and the etching depth does not exceed the thickness of the second barrier layer. S6. Deposit ohmic contact metal at the first groove, the source groove, the drain groove and the second groove to form a source, a drain and a cathode. The source and drain form ohmic contact with the upper two-dimensional electron gas and the cathode forms ohmic contact with the lower two-dimensional electron gas. S7. Deposit gate metal on the retained p-GaN layer to form the gate.

8. The method for fabricating a GaN HEMT device with integrated reverse conduction function according to claim 7, characterized in that, In step S4, the Schottky contact metal adopts a Ni / Au stacked structure; in step S6, the ohmic contact metal adopts a Ti / Al / Ni / Au stacked structure with a thickness of 20nm / 100nm / 50nm / 100nm.

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