Graphical processing method and system, computing device, and storage medium

Abstract

The application provides a graphics processing system, including at least two enabled graphics processing cores, and each graphics processing core includes a vertex splitting module, a vertex processing pipeline module, a primitive assembling pipeline module, a primitive processing pipeline module and a pixel processing pipeline module. The vertex splitting module of the target graphics processing core is configured to obtain a primitive packet to be processed from vertex index data; the vertex processing pipeline module is configured to perform shading processing on the vertex corresponding to the index in the primitive packet to obtain a shading processing result; the primitive assembling pipeline module is configured to obtain a primitive splitting initial state and split the primitive packet into primitives based on the primitive splitting initial state; the primitive processing pipeline module is configured to perform primitive processing on the shading processing result and the split primitives to obtain a primitive processing result; and the pixel processing pipeline module is configured to process the primitive processing result to obtain a visualized graphics.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to graphics processing methods, apparatus and systems, computing devices and storage media, and computer program products. Background Technology

[0002] In the field of computer science, graphics processing units (GPUs) are used to process various types of graphics data. The rendering pipeline is a key concept in computer graphics processing; it's a stage within the GPU responsible for processing and transforming graphics data. The main task of the rendering pipeline is to convert the geometric primitives (such as points, lines, and triangles) included in the input graphics data into pixels visible on the screen, thereby achieving graphics rendering. With continuous technological advancements, there is an urgent need to improve GPU throughput to increase processing speed and achieve high-quality, high-resolution rendering in real time. However, this poses a significant challenge to the current data processing capabilities of conventional GPUs. Summary of the Invention

[0003] In view of the above, this disclosure provides graphics processing methods and systems, computing devices and storage media, and computer program products, which are intended to address some or all of the defects mentioned above, as well as other possible defects.

[0004] According to a first aspect of this disclosure, a graphics processing system is provided, characterized in that the graphics processing system includes at least two enabled graphics processing cores, and each of the at least two enabled graphics processing cores includes a vertex splitting module, a vertex processing pipeline module, a primitive assembly pipeline module, a primitive processing pipeline module, and a pixel processing pipeline module; wherein the at least two enabled graphics processing cores include a target graphics processing core. The vertex splitting module of the target graphics processing core is configured to obtain a primitive package to be processed by the target graphics processing core from the vertex index data; the vertex processing pipeline module of the target graphics processing core is configured to perform coloring processing on the vertices corresponding to the indices in the primitive package to obtain the coloring processing result; the primitive assembly pipeline module of the target graphics processing core is configured to obtain the primitive splitting initial state and split the primitive package into primitives based on the primitive splitting initial state, wherein the primitive splitting initial state represents the information of the primitives composed of the vertices corresponding to the indices included in the primitive package; the primitive processing pipeline module of the target graphics processing core is configured to perform primitive processing on the coloring processing result and the split primitives to obtain the primitive processing result; the pixel processing pipeline module of the target graphics processing core is configured to process the primitive processing result to obtain the visualization graphics.

[0005] In some embodiments, the vertex splitting module of the target graphics processing core is configured to: obtain target vertex index data from vertex index data, and determine the primitive package based on the target vertex index data, the primitive package including vertex index fragments and suffix vertex indices, wherein the vertex index data includes indices of vertices of a graph of a specified topology to be drawn, and the suffix vertex indices are indices that are consecutively located after the vertex index fragments in the index order of the vertex index data.

[0006] In some embodiments, the vertex index fragments included in the primitive package to be processed by the at least two enabled graphics processing cores all include the same predetermined number of vertex indices, and the number of suffix vertex indices depends on the specified topology type.

[0007] In some embodiments, the shading process performed by the vertex processing pipeline module of the target graphics processing core and the primitive assembly pipeline module of the target graphics processing core are separated into parallel operations.

[0008] In some embodiments, the primitive assembly pipeline modules of the at least two enabled graphics processing cores are unidirectionally connected in the order of the graphics processing core serial numbers 0 to N-1, and the primitive assembly pipeline module of the graphics processing core with serial number N-1 is unidirectionally connected to the primitive assembly pipeline module of the graphics processing core with serial number 0, so that the communication connection is in a ring shape, where N is a positive integer greater than 1.

[0009] In some embodiments, the sequence number of the target graphics processing core is n, where n is an integer greater than or equal to 0 and less than or equal to N-1, and the primitive assembly pipeline module of the target graphics processing core is further configured to: in response to the sequence number n being 0 and the target graphics processing core being in its first primitive splitting initial state, acquire a pre-configured initial state as the primitive splitting initial state of the target graphics processing core; in response to the sequence number n being non-0 or the target graphics processing core being in its non-first primitive splitting initial state, acquire the primitive splitting initial state sent by the primitive assembly pipeline module of the preceding graphics processing core in the ring communication connection as the primitive splitting initial state of the target graphics processing core.

[0010] In some embodiments, the primitive assembly pipeline module of the target graphics processing core is further configured to: generate a primitive splitting initial state of the subsequent graphics processing core of the target graphics processing core in the ring communication connection, and send it to the primitive assembly pipeline module of the subsequent graphics processing core.

[0011] In some embodiments, the vertex splitting module of the target graphics processing core is configured to: obtain a graphics drawing command, the graphics drawing command indicating that a graphics with a specified topology type should be drawn; determine the number sequence corresponding to the indexes of a predetermined number of vertices to be processed by the target graphics processing core; and obtain, according to the number sequence, vertex index fragments and suffix vertex indices to be processed by the target graphics processing core from the vertex index data, which serve as target vertex index data, to determine the primitive package to be processed by the target graphics processing core.

[0012] In some embodiments, the primitive splitting initial state of the subsequent graphics processing core includes the number of the starting vertex, the valid state of the starting vertex, the number of the starting primitive, the offset of the starting vertex, and the winding order of the starting primitive, wherein the winding order of the starting primitive indicates the connection order of the vertices of the starting primitive when forming the starting primitive, the connection order including one of clockwise and counterclockwise, and the primitive assembly pipeline module of the target graphics processing core is further configured to: in response to the specified topology type being a point list, a line strip, and a line strip with adjacent points, determine the primitive splitting initial state to include: the valid state of the starting vertex being invalid, and the number of the starting primitive being the target graphics processing core. The sum of the final primitive number processed by the target graphics processing core and one, and the offset of the starting vertex are zero; in response to the specified topology type being a control packet list with K points, a line list, a line list with adjacency information, a triangle list, or a triangle list with adjacency information, the initial state of primitive splitting is determined as follows: the valid state of the starting vertex is invalid, the number of the starting primitive is the sum of the final primitive number processed by the target graphics processing core and one, and the offset of the starting vertex depends on the position of the virtual clipping point in the vertex index segment of the target graphics processing core, wherein the position of the virtual clipping point includes the position of the reset point and the position of the primitive end, and the reset point indicates the reset. There are no common vertices between the primitive containing the vertex preceding the reset point and the primitive containing the vertex following the reset point; in response to the specified topology type being triangle band, the initial state of primitive splitting is determined as follows: the valid state of the starting vertex is invalid, the number of the starting primitive is the sum of the last primitive number processed by the target graphics processing core and one, the offset of the starting vertex is zero, the winding order of the starting primitive is the opposite of the winding order of the last primitive processed by the target processing core, and the winding order of the starting primitive indicates the connection order of the vertices of the starting primitive when forming the starting primitive, the connection order including one of clockwise and counterclockwise; in response to the specified topology type being band neighbor The triangular band at the junction determines the initial state of primitive splitting as follows: the effective state of the starting vertex is invalid; the number of the starting primitive is the sum of the number of the last primitive processed by the target graphics processing core and one; the offset of the starting vertex is one when the last primitive processed by the target graphics processing core uses an odd number of suffix vertex indices and zero when the last primitive processed by the target graphics processing core uses an even number of suffix vertex indices; the winding order of the starting primitive is the opposite of the winding order of the last primitive processed by the target processing core; the winding order of the starting primitive indicates the connection order of the vertices of the starting primitive when forming the starting primitive, and the connection order includes one of clockwise and counterclockwise.In response to the specified topology type being a loop line or a triangle fan, the initial state of primitive splitting is determined as follows: the starting vertex is valid when the last vertex index of the vertex index segment to be processed by the target graphics processing core is not a reset point, and the starting vertex number is the starting vertex number of the last primitive in the vertex index segment processed by the target graphics processing core; the starting primitive number is the sum of the last primitive number processed by the target graphics processing core and one; and the offset of the starting vertex is zero.

[0013] In some embodiments, the at least two enabled graphics processing cores include a central graphics processing core and at least one non-central graphics processing core. When the target graphics processing core is a central graphics processing core, the primitive assembly pipeline module of the target graphics processing core is configured to generate a primitive splitting initial state for each of the at least two enabled graphics processing cores. When the target graphics processing core is a non-central graphics processing core, the primitive assembly pipeline module of the target graphics processing core is configured to obtain the primitive splitting initial state from the primitive assembly pipeline module of the central graphics processing core.

[0014] In some embodiments, when the target graphics processing core is a central graphics processing core, the primitive assembly pipeline module of the target graphics processing core is configured to generate a primitive splitting initial state for each of the at least two enabled graphics processing cores based on all vertex index data.

[0015] In some embodiments, the vertex splitting module of the target graphics processing core is further configured to: in response to the target graphics processing core being a non-central graphics processing core, perform the following steps. These steps include: obtaining a graphics drawing command, the graphics drawing command indicating that a graph with a specified topology type should be drawn; determining a sequence of indexes corresponding to a predetermined number of vertices to be processed by the target graphics processing core; and obtaining, based on the sequence of indexes, vertex index fragments and suffix vertex indices to be processed by the target graphics processing core from the vertex index data, to determine the primitive package to be processed by the target graphics processing core.

[0016] In some embodiments, the vertex splitting module of the target graphics processing core is further configured to perform the following steps in response to the target graphics processing core being a central graphics processing core. The steps include: obtaining a graphics drawing command indicating that a graph with a specified topology type should be drawn; determining a sequence of numbers corresponding to the indices of a predetermined number of vertices to be processed by the target graphics processing core; obtaining all vertex index data required for drawing the graph, which serves as target vertex index data; and determining vertex index fragments and suffix vertex indices to be processed by the target graphics processing core from the target vertex index data based on the number sequence, to determine the primitive package to be processed by the target graphics processing core.

[0017] In some embodiments, the vertex index data is pre-generated by the application that issues the graphics drawing command or generated by the vertex splitting module itself.

[0018] In some embodiments, the vertex splitting module of the target graphics processing core is further configured to determine the number of suffix vertex indices in the following ways: In response to the specified topology type being a point list, the number of suffix vertex indices is zero; in response to the specified topology type being a line list, loop line, or line strip, the number of suffix vertex indices is one; in response to the specified topology type being a triangle list, triangle strip, or triangle fan, the number of suffix vertex indices is two; in response to the specified topology type being a line list with adjacency information or a line strip with adjacency information, the number of suffix vertex indices is three; in response to the specified topology type being a triangle list with adjacency information, the number of suffix vertex indices is five; in response to the specified topology type being a triangle strip with adjacency information, the number of suffix vertex indices is seven; in response to the specified topology type being a control packet list with K points, the number of suffix vertex indices is K-1, where K is a positive integer.

[0019] In some embodiments, the vertex splitting module of the target graphics processing core is further configured to: divide consecutive numbers into number sequences based on the number of vertex index segments, and number the obtained number sequences sequentially; determine the sequence number of the target graphics processing core among the at least two enabled graphics processing cores during the current graphics processing; and, in response to the remainder obtained by dividing the number of the obtained target number sequence by the number of the at least two enabled graphics processing cores being the same as the sequence number of the target graphics processing core, determine the target number sequence as the number sequence corresponding to the index of a predetermined number of vertices to be processed by the target graphics processing core.

[0020] In some embodiments, the graphics processing core further includes a vertex cache module with a vertex index cache and vertex storage.

[0021] The vertex cache module of the target graphics processing core is configured to: perform a hit test on multiple indexes included in the primitive package based on the vertex index cache, add the missing indexes to the vertex index cache, and send the indexes in the vertex index cache to the vertex processing pipeline module of the target graphics processing core.

[0022] The vertex processing pipeline module of the target graphics processing core is configured to: perform color processing on the vertex corresponding to the received index, and store the color processing result in the vertex storage.

[0023] In some embodiments, the primitive assembly pipeline module of the target graphics processing core is configured to: obtain the mapping relationship between the index in the primitive package and the shading result index, wherein the shading result index is used to identify the shading result of the vertex corresponding to the index in the primitive package.

[0024] In some embodiments, the vertex cache module of the target graphics processing core is further configured to: generate vertex shader tasks and shading result indexes based on the missing indexes in the vertex index cache, send the vertex shader tasks and shading result indexes to the vertex processing pipeline module of the target graphics processing core, and send the mapping relationship between the indexes in the primitive package and the shading result indexes to the primitive assembly pipeline module of the target graphics processing core.

[0025] In some embodiments, the primitive assembly pipeline module of the target graphics processing core is configured to: perform a hit test on multiple indexes included in the primitive package based on the shadow cache, add the missing indexes to the shadow cache; and determine the shading processing result index corresponding to each index according to the order in which each index is added to the shadow cache, so as to determine the mapping relationship.

[0026] In some embodiments, the primitive assembly pipeline module of the target graphics processing core is further configured to: determine the shading result index corresponding to each index included in the split primitive based on the mapping relationship, and send the shading result index corresponding to the split primitive to the primitive processing pipeline module of the target graphics processing core;

[0027] The primitive processing pipeline module of the target graphics processing core is configured to: obtain the shading result corresponding to the primitive from the vertex storage based on the shading result index corresponding to the split primitive, and perform primitive processing.

[0028] In some embodiments, the primitive assembly pipeline module of the target graphics processing core is further configured to: send the mapping relationship and the indexes included in the split primitives to the primitive processing pipeline module of the target graphics processing core;

[0029] The primitive processing pipeline module of the target graphics processing core is configured to: determine the shading result index corresponding to the split primitive based on the mapping relationship and the index included in the split primitive, and obtain the shading result corresponding to the primitive from the vertex storage based on the shading result index corresponding to the split primitive, and perform primitive processing.

[0030] In some embodiments, the vertex cache module of the target graphics processing core is configured to send the index in the vertex index cache to the vertex processing pipeline module of the target graphics processing core when any of the following conditions are met:

[0031] The number of unsent vertices in the vertex index cache reaches the trigger threshold;

[0032] The vertex index cache is full;

[0033] The primitive packet includes multiple vertices, none of which are remaining vertices that have not been hit-tested.

[0034] According to a second aspect of this disclosure, a graphics processing method is provided, characterized in that the method is executed by a target graphics processing core, the target graphics processing core being one of at least two enabled graphics processing cores included in a graphics processing system, each of the at least two enabled graphics processing cores including a vertex splitting module, a vertex processing pipeline module, a primitive assembly pipeline module, a primitive processing pipeline module, and a pixel processing pipeline module. The method includes: using the vertex splitting module of the target graphics processing core to obtain a primitive package to be processed by the target graphics processing core from the vertex index data; using the vertex processing pipeline module of the target graphics processing core to perform coloring processing on the vertices corresponding to the indices in the primitive package to be processed by the target graphics processing core to obtain a coloring processing result; using the primitive assembly pipeline module of the target graphics processing core to obtain the primitive splitting initial state of the target graphics processing core, and splitting the primitive package determined from the target vertex index data into primitives based on the primitive splitting initial state, wherein the primitive splitting initial state represents the information of primitives composed of vertices corresponding to the indices included in the primitive package to be processed by the target graphics processing core; using the primitive processing pipeline module of the target graphics processing core to perform primitive processing on the coloring processing result and the split primitives to obtain a primitive processing result; and using the pixel processing pipeline module of the target graphics processing core to process the primitive processing result to obtain a visualization graphic.

[0035] According to a third aspect of this disclosure, a computing device is provided, including a processor; and a memory configured to store computer-executable instructions thereon, which, when executed by the processor, perform any of the methods described above.

[0036] According to a fourth aspect of this disclosure, a computer-readable storage medium is provided that stores computer-executable instructions that, when executed, perform any of the methods described above.

[0037] The graphics processing method and system claimed in this disclosure employ a parallel geometry processing pipeline, allowing vertex processing and primitive assembly to be processed in parallel. This significantly expands the data processing throughput of the geometry stage, improves the processing speed of the graphics processing system, enables real-time high-quality and high-resolution rendering, and possesses excellent scalability. Users can easily add or remove (or dynamically configure as needed) the corresponding GPU units (e.g., enabled graphics processing cores) according to the usage scenario to meet the performance and power consumption requirements of different scenarios.

[0038] These and other advantages of this disclosure will become clear from the embodiments described below, and will be illustrated with reference to the embodiments described below. Attached Figure Description

[0039] Embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings, in which:

[0040] Figure 1 An exemplary architecture diagram of a graphics processing system according to an embodiment of the present disclosure is shown;

[0041] Figure 2 The figure illustrates a schematic diagram of a first type of connection of a primitive assembly pipeline module in a graphics processing system according to an embodiment of the present disclosure.

[0042] Figure 3 The illustration shows a schematic diagram of the primitive packet obtained by the vertex splitting module according to an embodiment of the present disclosure in the case of a first connection.

[0043] Figure 4 The illustration shows an exemplary flowchart of a vertex processing pipeline module and a primitive assembly pipeline module that are executed in parallel in the case of a first connection, according to an embodiment of the present disclosure.

[0044] Figure 5 The figure illustrates a second type of connection of a primitive assembly pipeline module in a graphics processing system according to an embodiment of the present disclosure.

[0045] Figure 6 The illustration shows a schematic diagram of the primitive packet obtained by the vertex splitting module in a second connection case according to an embodiment of the present disclosure;

[0046] Figure 7 The illustration shows an exemplary flowchart of a vertex processing pipeline module and a primitive assembly pipeline module that are executed in parallel in the case of a second connection, according to an embodiment of the present disclosure.

[0047] Figure 8 An exemplary flowchart of a graphics processing method according to an embodiment of the present disclosure is shown;

[0048] Figures 9A-9D The illustration shows an exemplary schematic diagram of a primitive packet divided in a first connection case according to an embodiment of the present disclosure;

[0049] Figure 10 An example system is illustrated, which includes an example computing device representing one or more systems and / or devices that can implement the various technologies described herein. Detailed Implementation

[0050] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this application will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted.

[0051] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0052] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0053] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily have to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0054] It should be understood that although the terms first, second, third, etc., may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another. Therefore, the first component discussed below may be referred to as the second component without departing from the teachings of this application. As used herein, the terms "and / or" and similar terms include all combinations of any, multiple, and all of the associated listed items.

[0055] Those skilled in the art will understand that the accompanying drawings are merely schematic diagrams of exemplary embodiments, and the modules or processes in the drawings are not necessarily essential for implementing this application, and therefore cannot be used to limit the scope of protection of this application.

[0056] Before detailing the embodiments of this application, some related concepts will be explained for clarity.

[0057] Geometric primitives, also known as graphic primitives, refer to the basic geometric shapes that make up a graphic, including points, lines, triangles, etc. For example, a graphic drawn by an application can be represented in the computer by a large number of triangles. After breaking down graphic data into corresponding basic geometric shapes, these basic geometric shapes can be used to determine the pixels of the drawn graphic.

[0058] Topology types: also known as primitive topology types, typically include point lists, line lists, triangle lists, line bands, triangle bands, line lists with adjacency information, triangle lists with adjacency information, line bands with adjacency information, triangle bands with adjacency information, loop lines, etc. The definitions of these topologies are the same as those in Microsoft DirectX 11.3.

[0059] As mentioned earlier, the GPU rendering pipeline is a key concept in computer graphics. It's a stage within the graphics processing unit (GPU) responsible for processing and transforming graphics data for rendering. The primary task of the rendering pipeline is to convert input geometric primitives (such as points, lines, triangles, etc.) into pixels visible on the screen. The goal of the rendering pipeline is to process graphics efficiently and generate the final image. Through parallel processing and specialized hardware support, the GPU can perform these calculations rapidly to achieve real-time graphics rendering.

[0060] In related technologies, the rendering pipeline can generally be divided into two parts: the geometry processing part (also known as the geometry pipeline) and the pixel processing part (also known as the fragment pipeline).

[0061] The geometry processing section includes the vertex input stage, vertex shading stage, primitive assembly stage, geometry shading stage, clipping stage, and screen mapping stage. The geometry pipeline primarily focuses on the processing and transformation of geometric data. It receives input geometric primitives (such as points, lines, triangles, etc.) and, after a series of stages, transforms them into geometric processing results mapped to pixel coordinates in screen space. The geometry processing section is responsible for performing geometric calculations such as model transformation, view transformation, and projection transformation, as well as generating new geometric primitives and changing their shape, size, and position.

[0062] The pixel processing section generally includes the rasterization stage, the fragment shading stage, and the pixel manipulation stage. The fragment pipeline focuses on pixel-level processing. It receives the pixels on the screen generated by the rasterization stage and processes each pixel through a series of stages. The pixel processing section is responsible for performing pixel-level lighting calculations, texture sampling, depth testing, and other operations to determine the final color and attributes of each pixel.

[0063] Specifically, the vertex input phase passes vertex data from the application to the geometry pipeline. Vertex data includes attributes such as position, color, and normals. In the vertex shading phase, the vertex shader calculates for each input vertex and can perform various transformations and operations, such as model transformations, view transformations, and projection transformations. It can also calculate vertex lighting and texture coordinates. In the primitive assembly phase, the primitive assembler converts vertices into complete geometric primitives, such as points, line segments, and triangles. In the geometry shading phase, the geometry shader can manipulate and generate geometric primitives. It can create new primitives and change their shape, size, and position. In the clipping phase, the clipper compares primitives to the screen boundary and discards portions outside the view volume. The screen mapping phase maps the clipped primitives to pixel coordinates in screen space. The rasterization phase converts the transformed geometry into pixels on the screen and determines the position, color, and other attributes of each pixel. In the fragment shading phase, the fragment shader calculates for each rasterized pixel, performing pixel-level lighting calculations, texture sampling, depth testing, and other operations. Pixel operations are used to perform final pixel processing, such as blending, dithering, and anti-aliasing.

[0064] It should be noted that these two pipelines are consecutive stages in the rendering pipeline; they are interdependent and work closely together to ultimately generate a visualized image. The geometry pipeline transforms geometric data into geometric processing results corresponding to pixel coordinates, while the fragment pipeline performs final processing and computation on the geometric processing results and the corresponding pixel data. Through parallel processing and dedicated hardware support, the GPU can efficiently execute these pipeline stages to achieve real-time graphics rendering.

[0065] With the development of GPUs, there is an urgent need to improve GPU throughput to increase processing speed and achieve high-quality, high-resolution rendering in real time. However, this poses a significant challenge to the data processing capabilities of current conventional GPUs. This disclosure proposes a graphics processing method and system that allows vertex processing and primitive assembly to be processed in parallel, significantly expanding the data processing throughput of the geometry stage and thus improving GPU speed. The following sections will illustrate in detail how to implement this graphics processing method and apparatus using several embodiments.

[0066] Figure 1 An exemplary architecture diagram of a graphics processing system 100 according to an embodiment of the present disclosure is shown. Figure 1 As shown, the graphics processing system includes multiple graphics processing cores. Figure 1The diagram shows three graphics processing cores 110, 120, and 130. Two or more of these cores can be enabled as needed; for example, cores 110 and 120 can be enabled while core 130 is disabled. Here, "enable" means "start" or "activate." Each core may include a vertex splitting module, a vertex processing pipeline module, a primitive assembly pipeline module, a primitive processing pipeline module, and a pixel processing pipeline module. Figure 1 As shown, the graphics processing core 110 includes a vertex splitting module 111, a vertex processing pipeline module 112, a primitive assembly pipeline module 113, a primitive processing pipeline module 114, and a pixel processing pipeline module 115. The graphics processing core 120 includes a vertex splitting module 121, a vertex processing pipeline module 122, a primitive assembly pipeline module 123, a primitive processing pipeline module 124, and a pixel processing pipeline module 125. The graphics processing core 130 includes a vertex splitting module 131, a vertex processing pipeline module 132, a primitive assembly pipeline module 133, a primitive processing pipeline module 134, and a pixel processing pipeline module 135.

[0067] For each enabled graphics processing core, taking graphics processing core 110 as an example, the vertex splitting module 111 can be configured to obtain a primitive package to be processed by the target graphics processing core from the vertex index data; the vertex processing pipeline module 112 can be configured to perform shading processing on the vertices corresponding to the indices in the primitive package to obtain the shading processing result; the primitive assembly pipeline module 113 can be configured to obtain the primitive splitting initial state and split the primitive package into primitives based on the primitive splitting initial state, wherein the primitive splitting initial state represents the information of the primitives constituted by the vertices corresponding to the indices included in the primitive package; the primitive processing pipeline module 114 can be configured to perform primitive processing on the shading processing result and the split primitives to obtain the primitive processing result; the pixel processing pipeline module 115 can be configured to process the primitive processing result to obtain the visualization graphics.

[0068] In this way, the shading processing performed by the vertex processing pipeline module of the graphics processing core 110 and the primitive splitting operation performed by the primitive assembly pipeline module are parallel operations, realizing parallel processing of vertex processing and primitive assembly. This can make full use of the parallelism of vertex shading and primitive assembly in graphics processing, reduce the number of processing events, and improve the geometric processing throughput of the system.

[0069] Vertex splitting module 111 can be configured to obtain target vertex index data from vertex index data and determine the primitive package based on the target vertex index data. The target vertex index data is the vertex index data to be processed by the target graphics processing core. The primitive package described herein may include vertex index fragments and suffix vertex indices, wherein the vertex index data includes indices of vertices of a graph with a specified topology to be drawn, and the suffix vertex indices are indices that are consecutively located after the vertex index fragments in the vertex index data according to the index order in the vertex index data. In some embodiments, the vertex index fragments included in the primitive package to be processed by the at least two enabled graphics processing cores all include the same predetermined number of vertex indices, and the number of suffix vertex indices depends on the specified topology. For example, each vertex index fragment includes indices of 8 vertices.

[0070] Optionally, the graphics processing system 100 may further include a system configuration module 140, which can be configured to generate configuration information and send the configuration information to the vertex splitting module of each graphics processing core for configuration. The configuration information may include the number of vertex indices included in each vertex index fragment, information indicating at least two enabled graphics processing cores among the plurality of graphics processing cores included in the graphics processing system, and the sequence numbers of the at least two enabled graphics processing cores in the current graphics processing process.

[0071] Optionally, the graphics processing system 100 may further include a system bus 150, a storage unit 160, and a graphics processing core that may also include a storage access arbitrator. For example, graphics processing cores 110, 120, and 130 may also include storage access arbitrators 116, 126, and 136. The graphics processing core may obtain the required data from the storage unit via the system bus, or store the generated data in the storage unit via the system bus after arbitration processing by the storage access arbitrator. The system bus may be an on-chip bus or an on-chip bus. The storage unit may be SRAM (Static Random-Access Memory), DRAM (Dynamic Random-Access Memory), etc., and is not limited here. In some implementations, the system bus 150, storage unit 160, and storage access arbitrator may not be included in the graphics processing system and may exist as independent components outside the graphics processing system.

[0072] In embodiments of this disclosure, the graphics processing system 100 can be implemented as a complete GPU system (i.e., GPU) as a chip module. Each graphics processing core can be implemented as a smaller module or chip unit as a GPU unit. A GPU system may have only one GPU unit, suitable for applications with low performance and low power consumption requirements, such as PDAs (Personal Digital Assistants) and automotive chips. A GPU system may also include multiple GPU units to provide solutions for high-performance applications. This disclosure does not limit the number of GPU units.

[0073] Chip modules are a novel integrated circuit design approach that breaks down a complex chip into multiple smaller modules or chip units, which are then combined to form a complete system-on-a-chip (SoC). Each smaller module typically contains a specific function or subsystem and can be designed, tested, and manufactured independently. These modules can be implemented using different manufacturing processes, technologies, or suppliers. Finally, these modules can be assembled in a single package to form a fully functional SoC.

[0074] As can be seen from the above, the graphics processing system disclosed herein adopts a distributed parallel geometry processing pipeline, in which vertex processing and primitive assembly can be processed in parallel, which fully expands the data processing throughput of the geometry stage, improves the processing speed of the graphics processing system, realizes high-quality and high-resolution rendering in real time, and has good scalability. Users can easily add or reduce (or dynamically configure as needed) the corresponding GPU units (e.g., enabled graphics processing cores) according to the usage scenario to meet the performance and power consumption requirements of different scenarios.

[0075] To facilitate understanding of this solution, the technical details will be described in detail below using the enabled graphics processing core 110 as an example of the target graphics processing core. It should be noted that any enabled graphics processing core can serve as the target graphics processing core.

[0076] As described above, the vertex splitting module 111 can be configured to determine the primitive package to be processed by the target graphics processing core from the vertex index data. The vertex index data includes indexes of the vertices of the graphic to be drawn. The vertices described herein are represented by the vertex data as described above; therefore, the vertex index data can also be understood as an index of the vertex data. The vertex index data can be in the form of numbers or letters, for example, without limitation. Numerical numbers are, for example, 0, 1, 2, etc., and letter numbers are, for example, A, B, C, etc. In some embodiments, the vertex index data required for drawing the graphic can be obtained from an index buffer memory, or the vertex index data required for drawing the graphic can be automatically generated.

[0077] In some embodiments, the primitive package includes vertex index fragments and suffix vertex indices, wherein the vertex index data includes indices of vertices of a graph of a specified topology to be drawn, and the suffix vertex indices are indices that are consecutively located after the vertex index fragments in the vertex index data. The vertex index fragments included in the primitive package to be processed by the at least two enabled graphics processing cores all include the same predetermined number of vertex indices, and the number of suffix vertex indices depends on the specified topology. In this embodiment, each primitive comprises two parts: a vertex index fragment and a suffix vertex index. The number of vertex indices included in the vertex index fragment of each primitive is the same and can be pre-specified.

[0078] As described above, the number of vertex indices included in each vertex index fragment (e.g., Z, where Z is a positive integer) can be pre-specified or configured by the system configuration module. That is, each vertex index fragment includes a fixed number of Z vertex indices, and these vertex index fragments are non-repeating and have no gaps (i.e., no skipped vertex indices). The number Z can optionally be aligned with the bandwidth of the access interface of the memory where the geometry processing results are to be stored. Vertex index fragments may not be sufficient to represent complete primitives; therefore, the vertex splitting module needs to add a certain number of suffix vertex indices to each vertex index fragment according to the topology type specified by the drawing instructions, so that the vertex index fragments, after adding the suffix vertex indices, can represent complete primitive information.

[0079] The number of suffix vertex indices depends on the specified topology type. In some embodiments, the vertex splitting module is further configured to determine the number of suffix vertex indices as follows: zero suffix vertex indices in response to the specified topology type being a point list; one suffix vertex indices in response to the specified topology type being a line list, loop line, or line strip; two suffix vertex indices in response to the specified topology type being a triangle list, triangle strip, or triangle fan; three suffix vertex indices in response to the specified topology type being a line list with adjacency information or a line strip with adjacency information; five suffix vertex indices in response to the specified topology type being a triangle list with adjacency information; seven suffix vertex indices in response to the specified topology type being a triangle strip with adjacency information; and K-1 suffix vertex indices in response to the specified topology type being a control packet list with K points, where K is a positive integer.

[0080] It should be noted that the graphic to be drawn may or may not have a reset point, which can be explicitly specified in the drawing command. A reset point is a point where there are no common vertices between the geometric primitive containing the vertex before the reset point and the geometric primitive containing the vertex after the reset point. For example, in the vertex index data A, B, C, (CT), D, E, F of a triangle band, ABC constitutes the first triangle primitive, and DEF constitutes the second triangle primitive. CT represents a reset point, indicating that there are no common vertices between the first and second triangle primitives, that is, A, B, C, D, E, F are divided into two primitives, while B, C, and D do not constitute a triangle primitive.

[0081] In some cases, the primitive assembly pipeline modules of each graphics processing core in a graphics processing system are connected sequentially via a certain communication protocol (including, but not limited to, direct connection). In some embodiments, the primitive assembly pipeline modules of at least two enabled graphics processing cores are unidirectionally connected in the order of their serial numbers 0 to N-1, and the primitive assembly pipeline module of the graphics processing core with serial number N-1 is unidirectionally connected to the primitive assembly pipeline module of the graphics processing core with serial number 0, so that the communication connection is circular, where N is a positive integer greater than 1.

[0082] Figure 2 The illustration shows a schematic diagram of a first type of connection of a primitive assembly pipeline module in a graphics processing system 100 according to an embodiment of the present disclosure. For example... Figure 2As shown, in a system with three graphics processing cores (assuming all three are enabled), graphics processing cores 110 to 130 are configured by the system configuration module with serial numbers 0-2, respectively. Following the sequential order of their serial numbers 0 to 2, the primitive assembly pipeline module of graphics processing core 110 (serial number 0) is unidirectionally connected to the primitive assembly pipeline module of graphics processing core 120 (serial number 1) (the communication connection is unidirectional, i.e., from graphics processing core 110 to graphics processing core 120). The primitive assembly pipeline module of graphics processing core 120 is then unidirectionally connected to the primitive assembly pipeline module of graphics processing core 130 (serial number 2), and so on, until the primitive assembly pipeline module of graphics processing core 130 is unidirectionally connected to the primitive assembly pipeline module of graphics processing core 110. Thus, the communication connections of all primitive assembly pipeline modules of graphics processing cores 110 to 130 form a ring structure.

[0083] In the first connection scenario, the vertex splitting module 111 of the target graphics processing core can be configured to: acquire a graphics drawing command indicating that a graph with a specified topology type should be drawn; determine a sequence of numbers corresponding to the indices of a predetermined number of vertices to be processed by the target graphics processing core; and, based on the sequence of numbers, acquire vertex index fragments and suffix vertex indices to be processed by the target graphics processing core from the vertex index data, which serve as target vertex index data, to determine the primitive package to be processed by the target graphics processing core. For example, if the sequence of numbers is (0,1,2,3,4,5), then target vertex index data is acquired from the vertex index data based on the sequence of numbers. The target vertex index data consists of vertex index fragments to be processed by the target graphics processing core (which, for example, includes vertex indices 0,1,2,3,4,5, which is not limited) and suffix vertex indices (indices 6,7, which depend on the specified topology type). Typically, the sequence of numbers and the indices in the vertex index data can have a one-to-one correspondence, and the corresponding vertex index can be obtained based on the sequence of numbers.

[0084] It should be noted that the vertex index data mentioned above can be pre-generated by the application that issues the graphics drawing command and, for example, stored in an index buffer. The vertex splitting module can obtain the vertex index fragments and suffix vertex indices to be processed by the target graphics processing core from the vertex index data in the index buffer, or the vertex index data can be generated by the vertex index data itself, without any limitation.

[0085] The process by which the vertex splitting module 111 determines the number sequence corresponding to the indexes of the predetermined number of vertices to be processed by the target graphics processing core can be understood as a process of splitting the vertex index data. This is because the resulting number sequence can be used to determine the vertex index fragments and suffix vertex indices to be processed by the target graphics processing core from the vertex index data. The vertex splitting module 111 can be configured to execute various vertex splitting methods to determine the number sequence corresponding to the indexes of the predetermined number of vertices to be processed by the target graphics processing core.

[0086] In some embodiments, the vertex splitting module 111 can be configured to first divide the consecutive numbers into number sequences based on the number of vertex index fragments, and then number the resulting number sequences sequentially; then, determine the sequence number of the target graphics processing core among the at least two enabled graphics processing cores in this graphics processing process; finally, in response to the remainder obtained by dividing the number of the target number sequence by the number of the at least two enabled graphics processing cores being the same as the sequence number of the target graphics processing core, the target number sequence is determined as the number sequence corresponding to the indexes of a predetermined number of vertices to be processed by the target graphics processing core. Here, the number of consecutive numbers can be the same as the total number of vertex index data. After the vertex splitting module in each graphics processing core obtains the position of the vertex index fragment it needs to process, it only needs to access this part of the vertex index fragment from the storage unit (or only generate the corresponding vertex index fragment). In this way, the total number of vertex indexes accessed by all graphics processing cores is equal to the total number of original vertex indexes, thereby reducing the amount of access to vertex index data.

[0087] As an example, Figure 3 The illustration shows a schematic diagram of a primitive packet (including vertex index fragments and suffix vertex indices) obtained by a vertex splitting module according to an embodiment of the present disclosure in the case of a first connection. Figure 3 As shown, assuming graphics processing core 110 is mapped to serial number 1, graphics processing core 120 is mapped to serial number 2, and graphics processing core 130 is mapped to serial number 0, then graphics processing core 130 processes... Figure 3 The primitive packets 0, 3, and 6 extracted from the graphics core are processed by graphics processing core 110, while primitive packets 1, 4, and 7 are processed by graphics processing core 120, and primitive packets 2, 5, and 8 are processed by graphics processing core 120.

[0088] Furthermore, in the first connection scenario, assuming the target graphics processing core's serial number is n, and n is an integer greater than or equal to 0 and less than or equal to N-1, the primitive assembly pipeline module of the target graphics processing core can be configured to: in response to the serial number n being 0 and the target graphics processing core being in its first primitive splitting initial state, acquire a pre-configured initial state as the target graphics processing core's primitive splitting initial state; in response to the serial number n not being 0 or the target graphics processing core being in a non-first primitive splitting initial state, acquire the primitive splitting initial state sent by the primitive assembly pipeline module of the preceding graphics processing core in the ring communication connection as the target graphics processing core's primitive splitting initial state. The first primitive splitting state mentioned here refers to the first primitive splitting initial state acquired when considering the graphics processing system as a whole, not the first primitive splitting initial state acquired when considering the target graphics processing core itself. The graphics processing core with serial number 0 uses the pre-configured initial state as its primitive splitting initial state when it first acquires the primitive splitting initial state. The preceding graphics processing core of the target graphics processing core is the previous graphics processing core in the ring communication connection. For example, the preceding graphics processing core of graphics processing core 120 is graphics processing core 110, the preceding graphics processing core of graphics processing core 110 is graphics processing core 130, and so on. Furthermore, the primitive assembly pipeline module of the target graphics processing core can also generate the initial primitive decomposition state of the subsequent graphics processing core in the ring communication connection and send it to the primitive assembly pipeline module of the subsequent graphics processing core.

[0089] Vertex splitting module 111 sends the primitive packets handled by the target graphics processing core to vertex processing pipeline module 112. After obtaining the vertex data, vertex processing pipeline module 112 only runs the vertex shading program, processing each input vertex and outputting the shading result for each vertex. Additionally, vertex splitting module 111 also sends the primitive packets to primitive assembly pipeline module 113. Primitive assembly pipeline module 113, based on the received primitive packets and the initial primitive splitting state sent from the previous graphics processing core's primitive assembly pipeline module 113, splits these primitives into corresponding primitives. The results obtained from the primitive assembly pipeline module's splitting are then sent to the downstream primitive processing pipeline module 114. Primitive processing pipeline module 114 receives the shading results of each vertex from vertex processing pipeline module 112, as well as primitives (specifically, the specific way these vertices are composed of primitives) from primitive assembly pipeline module 113. It then assembles the primitives and performs subsequent primitive operations such as geometric shading, tessellation, clipping, and culling to obtain the primitive processing results. The primitive processing results are written to the storage unit via a storage access arbitrator. Pixel processing pipeline 115 reads the primitive processing results from the storage unit, rasterizes and shades them, and finally outputs the rendered result, i.e., the visual graphics. After processing a primitive package, primitive assembly pipeline module 113 needs to generate a new primitive decomposition initial state and send it to the primitive assembly pipeline in the next (i.e., the subsequent) graphics processing core.

[0090] As an example, Figure 4 An exemplary flowchart illustrating a vertex processing pipeline module and a primitive assembly pipeline module according to an embodiment of the present disclosure are executed in parallel in a first connection scenario, showing the processing of five primitive packets (including vertex index fragments and suffix vertex indexes) by three graphics processing cores.

[0091] For graphics processing core 0, vertex processing (i.e., shading) is first performed on primitive package 0. Simultaneously, the primitive assembly pipeline module performs primitive assembly on primitive package 0 (i.e., splitting primitive package 0 into primitives based on the primitive splitting initial state). At the same time, graphics processing cores 1 and 2 can also simultaneously begin vertex processing on primitive packages 1 and 2, respectively. However, graphics processing core 1 must wait for graphics processing core 0 to complete its primitive assembly and receive the primitive splitting initial state before it can begin assembling primitives. Similarly, graphics processing core 2 must wait for graphics processing core 1 to complete its primitive assembly and receive the primitive splitting initial state before it can begin assembling primitives. In graphics processing core 0, primitive processing can begin once vertex processing and primitive assembly of primitive package 0 are complete. The same applies to graphics processing core 1. However, for graphics processing core 2, its primitive assembly for primitive packet 2 requires graphics processing core 1 to complete its primitive assembly for primitive packet 1 and send over the initial primitive decomposition state before it can begin. Therefore, primitive processing by graphics processing core 2 cannot start immediately after vertex processing ends; there is a small delay. Note that this is just an illustrative example and is not always the case. Similarly, when graphics processing core 0 starts processing primitive packet 3, its primitive assembly requires graphics processing core 2 to complete its primitive assembly for primitive packet 2 and send over the initial primitive decomposition state before it can begin.

[0092] This example demonstrates that if vertex processing takes a considerable amount of time, enough to cover the time required for each graphics processing core to process primitive assembly once, then vertex processing across all graphics processing cores is completely parallel. In this case, although the primitive assembly pipeline modules within each graphics processing core are interdependent (i.e., the primitive assembly pipeline module in the next graphics processing core needs to wait for the primitive assembly pipeline module in the previous graphics processing core to send the initial primitive splitting state), this dependency is completely covered by the vertex processing flow of each primitive packet. In this scenario, the graphics processing system achieves maximum throughput.

[0093] In some embodiments, the generated initial state of subsequent primitive splitting includes the number of the starting vertex, the valid state of the starting vertex, the number of the starting primitive, the offset of the starting vertex, and the winding order of the starting primitive, wherein the winding order of the starting primitive indicates the connection order of the vertices of the starting primitive when forming the starting primitive, and the connection order includes one of clockwise and counterclockwise. In this configuration, the primitive assembly pipeline module of the target graphics processing core can be configured such that, in response to the specified topology type being a point list, a line strip, or a line strip with adjacent points, the initial state of primitive splitting is determined to include: the valid state of the starting vertex is invalid, the number of the starting primitive is the sum of the last primitive number processed by the target graphics processing core and one, and the offset of the starting vertex is zero; in response to the specified topology type being a control packet list with K points, a line list, a line list with adjacency information, a triangle list, or a triangle list with adjacency information, the initial state of primitive splitting is determined to include: the valid state of the starting vertex is invalid, the number of the starting primitive is the sum of the last primitive number processed by the target graphics processing core and one, and the offset of the starting vertex depends on the position of the virtual clipping point in the vertex index segment processed by the target graphics processing core, wherein the position of the virtual clipping point includes the position of the reset point and the position of the primitive end, and the reset point indicates that there are no common vertices between the primitive containing the vertex before the reset point and the primitive containing the vertex after the reset point.In response to the specified topology type being a triangle strip, the initial state of primitive splitting is determined as follows: the valid state of the starting vertex is invalid; the number of the starting primitive is the sum of the last primitive number processed by the target graphics processing core and one; the offset of the starting vertex is zero; the winding order of the starting primitive is the opposite of the winding order of the last primitive processed by the target processing core; the winding order of the starting primitive indicates the connection order of the vertices of the starting primitive when forming the starting primitive, and the connection order includes one of clockwise and counterclockwise. In response to the specified topology type being a triangle strip with adjacent vertices, the initial state of primitive splitting is determined as follows: the valid state of the starting vertex is invalid; the number of the starting primitive is the sum of the last primitive number processed by the target graphics processing core and one; the offset of the starting vertex is zero when the last primitive processed by the target graphics processing core uses an odd number of suffix vertex indices. The initial state of the primitive splitting is determined as follows: when the last primitive processed by the target graphics processing core uses an even number of suffix vertex indices, the initial state is zero; the winding order of the starting primitive is the reverse of the winding order of the last primitive processed by the target graphics processing core; the winding order of the starting primitive indicates the connection order of the vertices of the starting primitive when forming the starting primitive; the connection order includes one of clockwise and counterclockwise. In response to the specified topology type being a loop line or a triangle fan, the initial state of the primitive splitting is determined as follows: the starting vertex is valid when the last vertex index of the vertex index segment to be processed by the target graphics processing core is a reset point, and the number of the starting vertex is the number of the starting vertex of the last primitive of the vertex index segment processed by the target graphics processing core; the number of the starting primitive is the sum of the number of the last primitive processed by the target graphics processing core and one; and the offset of the starting vertex is zero.

[0094] Specifically, for the point list, the valid state of the starting vertex is determined to be invalid, the offset of the starting vertex is 0, and the number of the starting primitive is the sum of the last primitive number in this primitive package and one. The winding order of the starting primitive and the number of the starting vertex are meaningless at this time and do not need to be set. The initial state of the generated primitive splitting is shown in Table 1 below. Note that the initial state below refers to the initial state of the primitive assembly pipeline when the drawing command starts. The last primitive number here refers to the primitive number of the last primitive when the current primitive assembly pipeline module processes the primitive package.

[0095] Table 1

[0096] information Initial state of generated primitive splitting The initial state Number of the starting vertex 0 0 Valid state of the starting vertex invalid invalid Numbering of the starting element Add 1 to the last element number 0 offset of the starting vertex 0 0 Winding order of the starting primitive clockwise clockwise .

[0097] For a control packet list with K points (including an equivalent line list, a line list with adjacency information, a triangle list, and a triangle list with adjacency information), the initial state of the generated primitive splitting is shown in Table 2 below.

[0098] Table 2

[0099]

[0100] For a list of control packets with K points, it involves the position of a virtual cutting point. The position of the virtual cutting point includes the position of the reset point and the end position of the primitive. The primitive processing pipeline module needs to find the position of the last virtual cutting point. Suppose there are still M vertices (M < K) from it to the end of the vertex index segment (excluding the suffix vertex part), then the offset of the starting vertex should be determined as (K - M) mod K at this time. The mod operation refers to finding the remainder after dividing two numbers. For example, if M = 0, then the offset of the starting vertex is 0, and the next vertex segment will split the primitive starting from position 0. If M = 1, it indicates that M0 - S0 - S1 - … - S(K - 2) forms the primitive, and the next vertex segment will split the primitive starting from the offset position of K - 1.

[0101] For a line strip with adjacent vertices, the initial state of the generated primitive splitting is shown in Table 3 below.

[0102] Table 3

[0103]

[0104]

[0105] For a triangle strip, the initial state of the generated primitive splitting is shown in Table 4 below.

[0106] Table 4

[0107] information Initial state of generated primitive splitting The initial state Number of the starting vertex 0 0 Valid state of the starting vertex invalid invalid Numbering of the starting element Add 1 to the last element number 0 offset of the starting vertex 0 0 Winding order of the starting primitive Invert the orientation of the final primitive. clockwise

[0108] For a triangle strip, the winding order of the starting primitive in the initial state of the generated primitive splitting needs to be reversed according to the orientation of the last primitive in the current vertex segment. If the last primitive is in the clockwise direction, then the winding order of the starting primitive in the initial state of the primitive splitting is set to the counterclockwise direction. If the last primitive is in the counterclockwise direction, then the winding order of the starting primitive in the initial state of the primitive splitting is set to the clockwise direction.

[0109] For a triangle strip with adjacent vertices, the initial state of the generated primitive splitting is shown in Table 5 below.

[0110] Table 5

[0111]

[0112] The winding order of the starting primitives in the initial state of primitive splitting for a triangle strip with adjacent vertices is determined in the same way as in the triangle strip: by reversing the orientation of the last primitive. In the initial state of primitive splitting for a triangle strip with adjacent vertices, the offset of the starting vertex depends on the number of suffix vertex indices used by the last primitive. When the last primitive uses an odd number of suffix vertex indices, the offset of the starting vertex is 1. When the subsequent primitive uses an even number of suffix vertices, the offset of the starting vertex is 0.

[0113] For the loop line, the initial state of the generated primitive split is shown in Table 6 below.

[0114] Table 6

[0115]

[0116]

[0117] For a loop, the starting vertex number needs to be determined based on the current vertex index segment. When the last vertex of the current vertex index segment is a reset point, the valid state of the starting vertex in the generated primitive split initial state is invalid. When the last vertex of the current vertex index segment is not a reset point, the valid starting vertex in the generated primitive split initial state is valid, and the starting vertex number is the number of the starting vertex of the last primitive when processing the current vertex index segment.

[0118] For a triangular sector, the initial state of the generated primitive split is shown in Table 7 below.

[0119] Table 7

[0120] information Initial state of generated primitive splitting The initial state Number of the starting vertex Determined based on the current vertex fragment 0 Valid state of the starting vertex Determined based on the current vertex fragment invalid Numbering of the starting element Final element number + 1 0 offset of the starting vertex 0 0 Winding order of the starting primitive clockwise clockwise

[0121] For a triangular sector, the starting vertex number needs to be determined based on the current vertex index segment. When the last vertex of the current vertex index segment is a reset point, the valid state of the starting vertex in the generated primitive split initial state is invalid. When the last vertex of the current vertex index segment is not a reset point, the valid starting vertex in the generated primitive split initial state is valid, and the starting vertex number is the number of the starting vertex of the last primitive when processing the current vertex index segment.

[0122] For cyclic lines and triangle fans, there is information about the starting vertex number (and whether it is valid). When the primitive assembly pipeline module receives the primitive split initial state, and the starting vertex number is valid, the primitive assembly pipeline module needs to check whether the sent starting vertex number exists in the current vertex index fragment and the suffix vertex index. If it does not exist, then the primitive assembly pipeline module needs to send an additional vertex task to the vertex processing pipeline, sending the vertex represented by the starting vertex number to the vertex processing pipeline module to obtain its corresponding vertex shading result.

[0123] In some cases, the primitive assembly pipeline modules of other graphics processing cores in the graphics processing system are connected to the primitive assembly pipeline of a central graphics processing core configured by the system configuration module through a certain communication protocol (the communication protocol used includes, but is not limited to, direct connection).

[0124] Figure 5 The illustration shows a schematic diagram of a second connection of a primitive assembly pipeline module in a graphics processing system 100 according to an embodiment of the present disclosure. As described above, the graphics processing system 100 includes at least two enabled graphics processing cores, and each of the at least two enabled graphics processing cores includes a vertex splitting module, a vertex processing pipeline module, a primitive assembly pipeline module, a primitive processing pipeline module, and a pixel processing pipeline module. The at least two enabled graphics processing cores include a target graphics processing core. Figure 5 As shown, in a system with three graphics processing cores (assuming all three are enabled), graphics processing cores 110 to 130 are configured by the system configuration module with serial numbers 0-2, respectively. Graphics processing core 110 is configured as the central graphics processing core, and the primitive assembly pipeline modules in graphics processing cores 120 and 130 are connected to the primitive assembly pipeline module of graphics processing core 110 via a protocol. Thus, all primitive assembly pipelines of graphics processing cores 110-130 have a radial structure. Of course, the number of graphics processing cores here is exemplary and not limiting.

[0125] In the second connection scenario, if the target graphics processing core is a non-central graphics processing core, the vertex splitting module of the target graphics processing core is configured to: obtain a graphics drawing command indicating that a graph with a specified topology type should be drawn; determine a sequence of numbers corresponding to the indices of a predetermined number of vertices to be processed by the target graphics processing core; and, based on the sequence of numbers, obtain vertex index fragments and suffix vertex indices to be processed by the target graphics processing core from the vertex index data, which serve as target vertex index data, to determine the primitive package to be processed by the target graphics processing core. For example, if the sequence of numbers is (0,1,2,3,4,5), then target vertex index data is obtained from the vertex index data based on the sequence of numbers. The target vertex index data consists of vertex index fragments to be processed by the target graphics processing core (which, for example, includes vertex indices 0,1,2,3,4,5, which is not limited) and suffix vertex indices (indices 6,7, which depend on the specified topology type). Typically, the sequence of numbers and the indices in the vertex index data can have a one-to-one correspondence, and the corresponding vertex index can be obtained based on the sequence of numbers.

[0126] If the target graphics processing core is a central graphics processing core, then the vertex splitting module of the target graphics processing core is further configured to: acquire a graphics drawing command, the graphics drawing command indicating that a graphics with a specified topology type should be drawn; determine the number sequence corresponding to the indices of a predetermined number of vertices to be processed by the target graphics processing core; acquire all vertex index data required for drawing the graphics, which serves as target vertex index data; and determine the vertex index fragments and suffix vertex indices to be processed by the target graphics processing core from the target vertex index data according to the number sequence, so as to determine the primitive package to be processed by the target graphics processing core. The vertex splitting module of the central graphics processing core needs to access the complete vertex index data to perform vertex splitting.

[0127] It should be noted that the vertex index data mentioned above can be pre-generated by the application that issues the graphics drawing command and, for example, stored in an index buffer. The vertex splitting module can obtain the vertex index fragments and suffix vertex indices to be processed by the target graphics processing core from the vertex index data in the index buffer, or the vertex index data can be generated by the vertex index data itself, without any limitation.

[0128] Similar to the first connection, in the second connection, the process by which the vertex splitting module of the target graphics processing core determines the number sequence corresponding to the indices of the predetermined number of vertices to be processed by the target graphics processing core can be understood as a process of splitting the vertex index data. This is because the resulting number sequence can be used to determine the vertex index fragments and suffix vertex indices to be processed by the target graphics processing core from the vertex index data. The vertex splitting module can be configured to execute various vertex splitting methods to determine the number sequence corresponding to the indices of the predetermined number of vertices to be processed by the target graphics processing core.

[0129] In some embodiments, the vertex splitting module of the target graphics processing core can be configured to first divide consecutive numbers into number sequences based on the number of vertex index fragments, and then number the resulting number sequences sequentially; then, determine the sequence number of the target graphics processing core among the at least two enabled graphics processing cores during the current graphics processing; finally, in response to the remainder obtained by dividing the number of the target number sequence by the number of the at least two enabled graphics processing cores being the same as the sequence number of the target graphics processing core, the target number sequence is determined as the number sequence corresponding to the indexes of a predetermined number of vertices to be processed by the target graphics processing core. Here, the number of consecutive numbers can be the same as the number of all vertex index data. Besides the central graphics processing core, the vertex splitting modules in other non-central graphics processing cores, after obtaining the position of the vertex index fragments they need to process, only need to access these vertex index fragments from the storage unit (or only generate the corresponding vertex index fragments). In this way, the total number of vertex indexes accessed by all graphics processing cores is equal to (2N-1) / N of the original total number of vertex indexes, where N is the number of graphics processing cores in the image processing system, thereby reducing the amount of access to vertex index data.

[0130] As an example, Figure 6 The illustration shows a schematic diagram of a primitive packet (including vertex index fragments and suffix vertex indices) obtained by the vertex splitting module in a second connectivity case according to an embodiment of the present disclosure. Figure 6 As shown, assuming graphics processing core 110 is mapped to sequence number 0 and is the central image processing core, graphics processing core 120 is mapped to sequence number 1, and graphics processing core 130 is mapped to sequence number 2. Graphics processing core 0 accesses all vertex index data, splits out all primitive packets, and... Figure 6 Primitive packets 0, 3, and 6 extracted from the graph are sent to the vertex processing pipeline module for processing, while the graphics processing core 1 processes them. Figure 6 The extracted primitive packages 1, 4, and 7 are processed by the graphics processing core 2. Figure 6The extracted primitives are packages 2, 5, and 8.

[0131] Furthermore, in the second connection scenario, the at least two enabled graphics processing cores include a central graphics processing core and at least one non-central graphics processing core. When the target graphics processing core is a central graphics processing core, the primitive assembly pipeline module of the target graphics processing core is configured to generate a primitive splitting initial state for each of the at least two enabled graphics processing cores. When the target graphics processing core is a non-central graphics processing core, the primitive assembly pipeline module of the target graphics processing core is configured to obtain the primitive splitting initial state from the primitive assembly pipeline module of the central graphics processing core. In some embodiments, when the target graphics processing core is a central graphics processing core, the primitive assembly pipeline module of the target graphics processing core is configured to generate a primitive splitting initial state for each of the at least two enabled graphics processing cores based on all vertex index data.

[0132] The vertex splitting module outside the central graphics processing core sends the vertex index fragments and corresponding suffix vertex data handled by that graphics processing core to the vertex processing pipeline module. The central graphics processing core sends the vertex index fragments and suffix vertex indices handled by that graphics processing core to the vertex processing pipeline module for processing, and sends all vertex index fragments and suffix vertex indices to the primitive assembly pipeline module in the central graphics processing core for processing.

[0133] The vertex processing pipeline module only runs the vertex shading program, processing each input vertex and outputting the shading result for each vertex. The vertex splitting module (not part of the central graphics processing core) also sends primitive packets to the primitive assembly pipeline module. The primitive assembly pipeline module, based on the received primitive packets and the initial primitive splitting state from the central graphics processing core's primitive assembly pipeline module, splits these primitive packets into corresponding primitives. The results from the primitive assembly pipeline module are sent to the downstream primitive processing pipeline module. The primitive processing pipeline module receives the shading results for each vertex output from the vertex processing pipeline module, as well as the primitives from the primitive assembly pipeline module (specifically, the way these vertices are composed of primitives), assembles the primitives, and performs subsequent primitive operations such as geometric shading, tessellation, clipping, and culling to obtain the primitive processing result. The primitive processing result is written to the storage unit via a storage access arbitrator. The pixel processing pipeline reads the primitive processing results from the storage unit, rasterizes and colors them into pixels, and finally outputs the rendering result, i.e., the visual graphics.

[0134] For the central graphics processing core (GPU), its primitive assembly pipeline module receives all primitive packets (including those processed by vertex processing pipeline modules outside the GPU), generates primitive splitting initial states for these packets, and sends these initial states to the primitive assembly pipeline modules outside the GPU. For the GPU, the primitive assembly pipeline modules outside the GPU receive the primitive splitting initial states from the GPU's primitive assembly pipeline module, and parse the primitive packets sent by their respective vertex splitting modules into basic primitives. The primitive processing pipeline modules then perform further primitive processing based on the specific way these vertices compose primitives, combined with the output of the vertex processing pipeline modules.

[0135] As an example, Figure 7 An exemplary flowchart illustrating a vertex processing pipeline module and a primitive assembly pipeline module according to an embodiment of the present disclosure are executed in parallel in a second connection scenario, showing the processing of five primitive packets (including vertex index fragments and suffix vertex indexes) by three graphics processing cores.

[0136] Graphics processing core 0 is the central graphics processing core. For graphics processing core 0, vertex processing (i.e., shading) is first performed on primitive package 0. Simultaneously, its primitive assembly pipeline module performs primitive assembly on primitive package 0 (i.e., splitting primitive package 0 into primitives based on the primitive splitting initial state). At the same time, graphics processing cores 1 and 2 can also simultaneously begin vertex processing on primitive packages 1 and 2, respectively. However, graphics processing core 1's primitive assembly of primitive package 1 must wait for graphics processing core 0 to complete its primitive assembly and receive the primitive splitting initial state before it can begin assembling primitives. Similarly, graphics processing core 2's primitive assembly of primitive package 2 also needs to wait for graphics processing core 0 to complete its primitive assembly of primitive package 1 and receive the primitive splitting initial state before it can begin assembling primitives. In graphics processing core 0, primitive processing can begin once vertex processing and primitive assembly of primitive package 0 are completed. The same applies to graphics processing core 1. However, for graphics processing core 2, its primitive assembly for primitive packet 2 requires graphics processing core 0 to complete primitive assembly for primitive packet 1 and send the initial primitive decomposition state before it can begin. Therefore, primitive processing of graphics processing core 2 cannot start immediately after vertex processing is completed; there is a small delay. Note that this is just an illustrative example and is not always the case.

[0137] This example demonstrates that if vertex processing takes a considerable amount of time, enough to cover the time required for each graphics processing core to process primitive assembly once, then vertex processing across all graphics processing cores is completely parallel. In this case, although the primitive assembly pipeline modules in each graphics processing core depend on the primitive assembly pipeline module of the central graphics processing core, this dependency is entirely covered by the vertex processing flow of each primitive package. In this scenario, the graphics processing system achieves maximum throughput.

[0138] In this scenario, the primitive assembly pipeline module of the central graphics processing core can generate primitive splitting initial states for all primitive packets and send these initial states to the primitive assembly pipeline modules of each non-central graphics processing core. The primitive splitting initial states can be represented in various suitable forms. Optionally, the generated primitive splitting initial states may also include the starting vertex number, the valid state of the starting vertex, the starting primitive number, the offset of the starting vertex, and the winding order of the starting primitive, wherein the winding order of the starting primitive indicates the connection order of the vertices of the starting primitive when forming the starting primitive, and the connection order includes either clockwise or counterclockwise. Because primitive splitting initial states have already been generated for all primitives, it is not necessary to consider information such as primitive or vertex index fragments processed by the target graphics processing core; the relevant information can be directly determined.

[0139] Accordingly, Figure 8 An exemplary flowchart of a graphics processing method 800 according to an embodiment of the present disclosure is shown. The method 800 can be executed by a target graphics processing core, which is one of at least two enabled graphics processing cores included in a graphics processing system. Each of the at least two enabled graphics processing cores includes a vertex splitting module, a vertex processing pipeline module, a primitive assembly pipeline module, a primitive processing pipeline module, and a pixel processing pipeline module. The target graphics processing core may, for example, be a reference... Figure 1 The enabled graphics processing core 110 is described. The method 800 may include the following steps.

[0140] In step 810, the vertex splitting module of the target graphics processing core obtains the primitive package to be processed by the target graphics processing core from the vertex index data. The vertex index data includes indices of the vertices of the graphics to be drawn. Further, target vertex index data can be obtained from the vertex index data, and the primitive package is determined based on the target vertex index data. The primitive package includes vertex index fragments and suffix vertex indices, wherein the vertex index data includes indices of the vertices of the graphics to be drawn having a specified topology, and the suffix vertex indices are indices that are consecutively located after the vertex index fragments in the vertex index data according to the index order in the vertex index data. In some embodiments, the vertex index fragments included in the primitive package to be processed by the at least two enabled graphics processing cores all include the same predetermined number of vertex indices, and the number of suffix vertex indices depends on the specified topology.

[0141] In step 820, the vertex processing pipeline module of the target graphics processing core is used to perform shading processing on the vertices corresponding to the indices in the primitive package to be processed by the target graphics processing core, so as to obtain the shading processing result. This shading processing calculates for each vertex and can perform various transformations and operations, such as model transformation, view transformation, projection transformation, etc., and can also calculate vertex lighting, texture coordinates, etc.

[0142] In step 830, the primitive assembly pipeline module of the target graphics processing core is used to obtain the primitive splitting initial state of the target graphics processing core, and the primitive package determined from the target vertex index data is split into primitives based on the primitive splitting initial state. The primitive splitting initial state represents the information of primitives composed of vertices corresponding to the indices included in the primitive package to be processed by the target graphics processing core.

[0143] In step 840, the primitive processing pipeline module of the target graphics processing core is used to perform primitive processing on the coloring processing result and the split primitives to obtain the primitive processing result.

[0144] In step 850, the pixel processing pipeline module of the target graphics processing core is used to process the primitive processing results to obtain a visualized graphic. The pixel processing pipeline module mainly obtains the visualized graphic by executing the various stages of the pixel processing part of the rendering pipeline as described above. These stages are similar to those described in related technologies and will not be described in detail here.

[0145] The graphics processing method disclosed herein enables parallel processing of vertex processing and primitive assembly, significantly expanding the data processing throughput of the geometry stage, improving the processing speed of the graphics processing system, achieving high-quality and high-resolution rendering in real time, and possessing good scalability. Users can easily add or remove (or dynamically configure as needed) the corresponding GPU units (e.g., enabled graphics processing cores) according to the usage scenario to meet the performance and power consumption requirements of different scenarios.

[0146] As an example, Figures 9A-9D The illustration shows an exemplary schematic diagram of primitive packets divided in a first connection scenario according to an embodiment of the present disclosure, wherein the topology type is described as a triangular strip. Figure 9A As shown, all vertex index data is v0-v31, where v14 and v19 are reset points, which can form as follows: Figure 9A The triangle strip shown is an example. Assume the system configuration module is configured with Z = 8 vertex indices in each vertex index segment, meaning each vertex slice index segment has 8 vertex indices. In this way, all the vertex and bottom index data is split into four vertex slices: v0-v7, v8-v15, v16-v23, and v24-v31. Simultaneously, based on the topology of the triangle strip, the number of suffix vertex indices is determined to be 2.

[0147] like Figure 9B As shown, the partitioned primitive package 0 contains vertex index fragments v0-v7, and two suffix vertex indices v8 and v9. The vertex splitting module of the graphics processing core 0 sends v0-v7 and v8v9 to the vertex processing pipeline module to obtain the processing results of vertices v0-v9. These vertices are also sent to the primitive assembly pipeline module, which assembles them into a total of 9 triangles: v0-v1-v2(CW), v1-v2-v3(CCW), v2-v3-v4(CW), v3-v4-v5(CCW), v4-v5-v6(CW), v5-v6-v7(CCW), v6-v7-v8(CW), and v7-v8-v9(CCW). The primitives are numbered from 0 to 8, CW indicates that the winding order of the primitives is clockwise, and CCW indicates that the winding order of the primitives is counterclockwise. The primitive assembly pipeline module also generates the following primitive splitting initial state data:

[0148] information Initial state of generated primitive splitting Number of the starting vertex 0 Valid state of the starting vertex invalid Numbering of the starting element 9 offset of the starting vertex 0 Winding order of the starting primitive clockwise .

[0149] like Figure 9CAs shown, primitive package 1 contains vertex index fragments v8-v15, and two suffix vertex indices v16 and v17. The vertex splitting module in another graphics processing core sends v8-v15, as well as v16 and v17, to the vertex processing pipeline module, which then processes the vertices v8-v17. These vertices are also sent to the primitive assembly pipeline module. Once the primitive assembly pipeline module receives the initial split state, it can split the primitives into five triangles: v8-v9-v10 (CW), v9-v10-v11 (CCW), v10-v11-v12 (CW), v11-v12-v13 (CCW), and v15-v16-v17 (CW), numbered from 9 to 13. The primitive assembly pipeline module simultaneously generates the following initial primitive split state data:

[0150] information Initial state of generated primitive splitting Number of the starting vertex 0 Valid state of the starting vertex invalid Numbering of the starting element 14 offset of the starting vertex 0 Winding order of the starting primitive counterclockwise .

[0151] At the same time, such as Figure 9D As shown, primitive package 2 contains vertex index fragments v16-v23, and two suffix vertex indices v24 and v25. The vertex splitting module in another graphics processing core sends v16-v23, as well as v24 and v25, to the vertex processing pipeline module, which then processes the vertices v16-v25. These vertices are also sent to the primitive assembly pipeline module. Once the primitive assembly pipeline module receives the initial primitive splitting state, it can split the primitives into five primitives: v16-v17-v18 (CCW), v20-v21-v22 (CW), v21-v22-v23 (CCW), v22-v23-v24 (CW), and v23-v24-v25 (CCW), numbered from 14 to 18. The primitive assembly pipeline module simultaneously generates the following initial primitive splitting state data:

[0152] information Initial state of generated primitive splitting Number of the starting vertex 0 Valid state of the starting vertex invalid Numbering of the starting element 19 offset of the starting vertex 0 Winding order of the starting primitive clockwise

[0153] In some optional embodiments, the graphics processing core further includes a vertex cache module with a vertex index cache and vertex storage.

[0154] The vertex cache module of the target graphics processing core is configured to: perform a hit test on multiple indexes included in the primitive package based on the vertex index cache, add the missing indexes to the vertex index cache, and send the indexes in the vertex index cache to the vertex processing pipeline module of the target graphics processing core.

[0155] The vertex processing pipeline module of the target graphics processing core is configured to: perform color processing on the vertex corresponding to the received index, and store the color processing result in the vertex storage.

[0156] For example, the vertex caching module receives multiple indices included in the primitive packet. For instance, it receives multiple indices arranged in sequence, where each index indicates a vertex, and there is a one-to-one correspondence between the indices and the vertices. For example, "multiple indices arranged in sequence" means that the indices are arranged according to the order in which the vertices are located within the primitive. For instance, the indices corresponding to multiple vertices within each primitive are consecutive, and the indices are arranged in either a clockwise or counter-clockwise order within the primitive.

[0157] Optionally, the vertex cache module, based on the vertex index cache, performs a hit test on multiple indices included in the primitive packet, adds the missing indices to the vertex index cache, and sends the indices in the vertex index cache to the vertex processing pipeline module of the target graphics processing core. A vertex cache hit means that the vertex index is already stored in the vertex index cache; a vertex cache miss means that the vertex index does not exist in the vertex index cache. The vertex processing pipeline module of the target graphics processing core performs shading processing on the vertices corresponding to the received indices and stores the shading results in vertex storage. The missing indices can be added to the vertex index cache in order.

[0158] In this way, primitive assembly and vertex shading can be performed in parallel, allowing vertex shading to be done even without primitive assembly or primitive information. Furthermore, vertex index caching reduces the number of times the vertex shading procedure runs.

[0159] In some optional embodiments, the vertex cache module of the target graphics processing core is configured to send the index in the vertex index cache to the vertex processing pipeline module of the target graphics processing core if any of the following conditions are met:

[0160] The number of unsent vertices in the vertex index cache reaches the trigger threshold;

[0161] The vertex index cache is full;

[0162] The primitive packet includes multiple vertices, none of which are remaining vertices that have not been hit-tested.

[0163] For example, the vertex processing pipeline module executes vertex shader tasks, which include the vertices processed each time the vertex shader program starts. That is, to improve hardware performance and efficiency, the vertex shader program is not started immediately for each input vertex. Instead, it is started only for a certain number of vertices after they have been collected. Thus, a batch of started vertices constitutes one vertex shader task (or simply shader task).

[0164] If the number of unsent vertices in the vertex index cache reaches the trigger threshold, or the vertex index cache is full, or there are no remaining vertices in the primitive package that have not been hit tested, the index in the vertex index cache can be sent to the vertex processing pipeline module of the target graphics processing core so that the vertex processing pipeline module can start and execute the vertex shading program.

[0165] This can improve hardware performance and efficiency.

[0166] In some optional embodiments, the primitive assembly pipeline module of the target graphics processing core is configured to: obtain the mapping relationship between the index in the primitive package and the shading result index, wherein the shading result index is used to identify the shading result of the vertex corresponding to the index in the primitive package.

[0167] The mapping relationship can be generated by the vertex cache module and sent to the primitive assembly pipeline module, or it can be generated by the primitive assembly pipeline module based on the same hit test logic as the vertex cache module. For example, the vertex cache module adds the missing indices to the vertex index cache in order, and the primitive assembly pipeline module performs a hit test on the indices included in the primitive package based on the shadow cache according to the same hit test logic, and adds the missing indices to the shadow cache in order, thereby obtaining the mapping relationship. This disclosure does not limit this.

[0168] In this way, the mapping relationship between the index in the primitive package and the index of the shading result can be used to determine the shading result of the vertex corresponding to the index in the primitive package. This allows for vertex shading even without primitive information. Furthermore, once the primitive assembly is complete, the shading result of the vertices included in each primitive can be determined based on the mapping relationship. This realizes the dependency relationship between vertex shading and primitive assembly, thereby improving hardware performance and efficiency.

[0169] In some optional embodiments, the vertex cache module of the target graphics processing core is further configured to: generate vertex shader tasks and shading result indexes based on the missing indexes in the vertex index cache, send the vertex shader tasks and shading result indexes to the vertex processing pipeline module of the target graphics processing core, and send the mapping relationship between the indexes in the primitive package and the shading result indexes to the primitive assembly pipeline module of the target graphics processing core.

[0170] For example, the vertex cache module can generate vertex shader tasks and shading result indices based on missed indices in the vertex index cache. For instance, it can generate shading result indices based on the shader task identifier and the vertex index. The vertex cache module can also send the mapping relationship between the indices in the primitive package and the shading result indices to the primitive assembly pipeline module of the target graphics processing core.

[0171] In some optional embodiments, the vertex cache module may further include a hit test control subunit, a shader task assembly subunit, and a shader task mapping subunit; the hit test control subunit is configured to perform a vertex hit test on each of a plurality of indices of the primitive package; add the index of the vertex that is not hit in the vertex index cache to the vertex index cache; generate a vertex shader task to which the vertex corresponding to the missed index belongs; generate a shading result index of the vertex; and send the shading result index of the vertex to the shader task assembly subunit;

[0172] The shader task assembly subunit is used to send the vertex shader task to which the vertex belongs and the shader processing result index to the vertex processing pipeline to perform vertex processing;

[0173] The shader task mapping subunit is used to send the mapping relationship between the vertex index and the shader processing result index to the primitive assembly pipeline module.

[0174] In this way, vertex shading is achieved without primitive assembly, enabling vertex-level hit testing. Specifically, a shading result index for internal use within the geometry pipeline is generated by the vertex caching module. After the vertex shading program processes the vertex, the shading result and its corresponding index are stored in the vertex storage. This allows the vertex shading program to process the vertex without needing to confirm its primitive position, thus decoupling vertex shading and hit testing, as well as different geometry processing pipelines. Consequently, the geometry processing pipeline shown in this embodiment is applicable to processors with distributed architectures. Furthermore, the geometry processing pipeline provided in this embodiment improves processing efficiency compared to related technologies that use primitives as the granularity for hit testing. This means the vertex caching module can perform hit testing without obtaining primitive assembly information, allowing hit testing and vertex shading to proceed in parallel, thereby improving the processing performance of the geometry processing pipeline.

[0175] In some optional embodiments, the primitive assembly pipeline module of the target graphics processing core is configured to: perform a hit test on multiple indexes included in the primitive package based on the shadow cache, add the missing indexes to the shadow cache; and determine the shading processing result index corresponding to each index according to the order in which each index is added to the shadow cache, so as to determine the mapping relationship.

[0176] For example, the mapping relationship can be determined by the primitive assembly pipeline module based on the same hit test logic as the vertex cache module. For instance, based on the shadow cache, a hit test can be performed on multiple indices included in the primitive package, and the missing indices can be added to the shadow cache; according to the order in which each index is added to the shadow cache, the shading result index corresponding to each index can be determined to determine the mapping relationship.

[0177] For example, the vertex caching module includes a first hit test control module and a task assembly module.

[0178] The first hit test control module is configured to, for each index in the primitive packet, in response to the index not hitting the vertex index cache and the cache not being full, store the index in the vertex index cache; or, in response to the index not hitting the vertex index cache and the vertex index cache being full, send at least a portion of the indexes in the vertex index cache to the task assembly module, clear the sent indexes in the vertex index cache, and store the indexes in the vertex index cache after the clearing operation.

[0179] The task assembly module is configured to assemble tasks based on the indexes received from the first hit test control module, wherein each vertex shader task includes a preset number of indexes and corresponds to a vertex shader task index.

[0180] For example, the primitive processing pipeline module may include a second hit test control module, which is used to perform a hit test based on the shadow cache for each index and store the indexes that are not hit into the shadow cache; and to determine the shading processing result index corresponding to each index according to the order in which each index is stored into the shadow cache, so as to determine the mapping relationship.

[0181] In some optional embodiments, in response to the index not being hit by the shadow cache and the shadow cache not being full, the index is stored in the shadow cache;

[0182] In response to the vertex index not being hit in the shadow cache and the shadow cache being full, at least a portion of the indexes in the shadow cache are cleared, and the indexes are stored in the shadow cache after the clearing operation is performed.

[0183] The second hit test control module of the vertex cache module can perform similar functions to the first hit test control module within the vertex cache module. The second hit test control module can perform hit tests on each index and cache missed indexes based on the shadow cache. The shadow cache can be considered a shadow of the vertex index cache in the vertex cache module. Since the hit test logic executed by the second hit test control module can be consistent with that of the first hit test control module, and both process the same primitive package, the caching and changes of the indexes in the shadow cache can remain consistent with those in the vertex index cache. Therefore, with the help of the second hit test control module and the shadow cache, the mapping relationship between each index and the shading result index existing in the vertex cache module and the vertex processing pipeline can be reconstructed. This mapping relationship can, for example, be filled into a reconstructed mapping table and can be used by other modules to obtain the shading result index corresponding to each index, and then locate the corresponding shading result in the vertex storage. It should be noted that although the execution logic of the hit test in the second hit test control module is similar to that of the hit test in the first hit test control module, and the results are the same, the two are executed independently of each other, and they can be executed synchronously or asynchronously.

[0184] Unlike the first hit test control module, the second hit test control module does not need to perform operations such as sending indexes, nor does it need to perform operations such as sending control information to start downstream task assembly and vertex shader task execution.

[0185] In this way, the remapped vertex shading results corresponding to the vertices included in the primitive package and their positions in vertex storage can be determined, and then primitive processing can be performed.

[0186] In some optional embodiments, the primitive assembly pipeline module of the target graphics processing core is further configured to: determine the shading result index corresponding to each index included in the split primitive based on the mapping relationship, and send the shading result index corresponding to the split primitive to the primitive processing pipeline module of the target graphics processing core;

[0187] The primitive processing pipeline module of the target graphics processing core is configured to: obtain the shading result corresponding to the primitive from the vertex storage based on the shading result index corresponding to the split primitive, and perform primitive processing.

[0188] For example, the primitive assembly pipeline module can determine the shading result index corresponding to each index of the primitive based on the index of the vertices included in the assembled primitive and the mapping relationship, and send the shading result index corresponding to each index of the primitive to the primitive processing pipeline module of the target graphics processing core. The primitive processing pipeline module retrieves the shading result corresponding to the primitive from the vertex storage and performs primitive processing.

[0189] In this way, vertex shading is achieved without primitive assembly, enabling vertex-level hit testing. This allows the vertex shading program to process the vertex without needing to confirm its primitive position, thus decoupling vertex shading and hit testing, as well as different geometry processing pipelines. This makes the geometry processing pipeline shown in this embodiment applicable to distributed processor architectures. Furthermore, the geometry processing pipeline provided in this embodiment improves processing efficiency compared to related technologies that use primitives as the granularity for hit testing. Specifically, the vertex caching module can perform hit testing without obtaining primitive assembly information, allowing hit testing and vertex shading to proceed in parallel, thereby improving the processing performance of the geometry processing pipeline.

[0190] In some optional embodiments, the primitive assembly pipeline module of the target graphics processing core is further configured to send the mapping relationship and the indexes included in the split primitives to the primitive processing pipeline module of the target graphics processing core.

[0191] The primitive processing pipeline module of the target graphics processing core is configured to: determine the shading result index corresponding to the split primitive based on the mapping relationship and the index included in the split primitive, and obtain the shading result corresponding to the primitive from the vertex storage based on the shading result index corresponding to the split primitive, and perform primitive processing.

[0192] For example, the primitive assembly pipeline module sends the mapping relationship and the indexes included in the split primitives to the primitive processing pipeline module of the target graphics processing core. The primitive processing pipeline module determines the shading result index corresponding to the split primitive based on the mapping relationship and the indexes included in the split primitives, and retrieves the shading result corresponding to the primitive from the vertex storage based on the shading result index corresponding to the split primitive, and performs primitive processing.

[0193] This achieves decoupling of vertex shading and hit testing, as well as decoupling between different geometry processing pipelines, thereby enabling the geometry processing pipeline shown in the embodiments of this application to be applicable to processors with distributed architectures.

[0194] Figure 10 The illustration depicts an example system 1000, which includes an example computing device 1010 representing one or more systems and / or devices that can implement the various technologies described herein. The computing device 1010 may be, for example, a server of a service provider, a device associated with a server, a system-on-a-chip, and / or any other suitable computing device or computing system. (Refer to above) Figure 1 The described graphics processing system 100 can take the form of a computing device 1010. Alternatively, the graphics processing method 800 can be implemented as a computer program in the form of an application 1016.

[0195] The example computing device 1010 shown includes a processing system 1011, one or more computer-readable media 1012, and one or more I / O interfaces 1013, all communicatively coupled to each other. Although not shown, the computing device 1010 may also include a system bus or other data and command transfer system that couples the various components to each other. The system bus may include any or a combination of different bus architectures, such as a memory bus or memory controller, a peripheral bus, a universal serial bus, and / or a processor or local bus utilizing any of these various bus architectures. Various other examples, such as control and data lines, are also conceived.

[0196] Processing system 1011 represents the functionality of performing one or more operations using hardware. Therefore, processing system 1011 is illustrated as including hardware elements 1014 that can be configured as processors, function blocks, etc. This may include application-specific integrated circuits (ASICs) or other logic devices formed using one or more semiconductors in the hardware. Hardware element 1014 is not limited by the materials in which it is formed or the processing mechanism employed therein. For example, a processor may consist of semiconductors and / or transistors (e.g., integrated circuits (ICs)). In such a context, processor-executable instructions may be electronically executable instructions.

[0197] Computer-readable medium 1012 is illustrated as including memory / storage device 1015. Memory / storage device 1015 represents a memory / storage capacity associated with one or more computer-readable media. Memory / storage device 1015 may include volatile media (such as random access memory (RAM)) and / or non-volatile media (such as read-only memory (ROM), flash memory, optical disk, magnetic disk, etc.). Memory / storage device 1015 may include fixed media (e.g., RAM, ROM, fixed hard disk drive, etc.) and removable media (e.g., flash memory, removable hard disk drive, optical disk, etc.). Computer-readable medium 1012 may be configured in various other ways as further described below.

[0198] One or more I / O interfaces 1013 represent functions that allow users to input commands and information to the computing device 1010 using various input devices and optionally also allow information to be presented to the user and / or other components or devices using various output devices. Examples of input devices include keyboards, cursor control devices (e.g., mice), microphones (e.g., for voice input), scanners, touch functionality (e.g., capacitive or other sensors configured to detect physical touch), cameras (e.g., capable of detecting non-touch-related motion as gestures using visible or invisible wavelengths (such as infrared frequencies), etc. Examples of output devices include display devices (e.g., monitors or projectors), speakers, printers, network interface cards, haptic-responsive devices, etc. Therefore, the computing device 1010 can be configured to support user interaction in various ways as further described below.

[0199] The computing device 1010 also includes an application 1016. The application 1016 may be, for example, a software instance of a graphics processing method, and implements the techniques described herein in combination with other elements in the computing device 1010.

[0200] This document describes various technologies within the general context of software and hardware components or program modules. Generally, these modules include routines, programs, objects, elements, components, data structures, etc., that perform specific tasks or implement specific abstract data types. As used herein, the terms "module," "function," and "component" generally refer to software, firmware, hardware, or a combination thereof. The technologies described herein are characterized as platform-independent, meaning that these technologies can be implemented on a variety of computing platforms with various processors.

[0201] Implementations of the described modules and technologies may be stored on or transmitted across some form of computer-readable medium. The computer-readable medium may include a variety of media accessible by the computing device 1010. By way of example and not limitation, the computer-readable medium may include "computer-readable storage media" and "computer-readable signal media".

[0202] In contrast to simple signal transmission, carrier waves, or signals themselves, a "computer-readable storage medium" refers to a medium and / or device capable of persistently storing information, and / or a tangible storage device. Therefore, a computer-readable storage medium refers to a non-signal-bearing medium. Computer-readable storage media include hardware such as volatile and non-volatile, removable and non-removable media and / or storage devices implemented using methods or techniques suitable for storing information (such as computer-readable instructions, data structures, program modules, logic elements / circuits, or other data). Examples of computer-readable storage media may include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, DVD or other optical storage devices, hard disks, magnetic tape cassettes, magnetic tapes, disk storage devices or other magnetic storage devices, or other storage devices, tangible media, or articles of art suitable for storing desired information and accessible by a computer.

[0203] "Computer-readable signal medium" refers to a signal-bearing medium configured to transmit instructions, such as via a network, to computing device 1010. A signal medium typically embodies computer-readable instructions, data structures, program modules, or other data in a modulated data signal, such as a carrier wave, data signal, or other transmission mechanism. Signal media also include any information transmission medium. The term "modulated data signal" refers to a signal in which one or more of its characteristics are set or altered to encode information. By way of example and not limitation, communication media include wired media such as wired networks or direct connections, and wireless media such as acoustic, RF, infrared, and other wireless media.

[0204] As previously described, hardware element 1014 and computer-readable medium 1012 represent instructions, modules, programmable device logic, and / or fixed device logic implemented in hardware, which in some embodiments can be used to implement at least some aspects of the techniques described herein. Hardware elements may include components of integrated circuits or systems-on-a-chip, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), and other implementations or other hardware devices in silicon. In this context, hardware elements can serve as processing devices for executing program tasks defined by instructions, modules, and / or logic embodied by the hardware element, and as hardware devices for storing instructions for execution, such as the previously described computer-readable storage medium.

[0205] The foregoing combinations can also be used to implement the various techniques and modules described herein. Therefore, software, hardware, or program modules and other program modules can be implemented as one or more instructions and / or logic embodied on some form of computer-readable storage medium and / or by one or more hardware elements 1014. The computing device 1010 can be configured to implement specific instructions and / or functions corresponding to the software and / or hardware modules. Thus, for example, by using the computer-readable storage medium and / or hardware elements 1014 of the processing system, modules can be implemented at least partially in hardware as modules executable as software by the computing device 1010. Instructions and / or functions can be executable / operable by one or more articles of art (e.g., one or more computing devices 1010 and / or processing systems 1011) to implement the techniques, modules, and examples described herein.

[0206] In various embodiments, the computing device 1010 can be configured in various ways. For example, the computing device 1010 can be implemented as a computer-type device, including personal computers, desktop computers, multi-screen computers, laptop computers, netbooks, etc. The computing device 1010 can also be implemented as a mobile device, including mobile devices such as mobile phones, portable music players, portable gaming devices, tablet computers, multi-screen computers, etc. The computing device 1010 can also be implemented as a television-type device, including devices with or connected to a generally large screen in a leisure viewing environment. These devices include televisions, set-top boxes, game consoles, etc.

[0207] The techniques described herein can be supported by these various configurations of computing device 1010, and are not limited to specific examples of the techniques described herein. Functionality can also be implemented, wholly or partially, on the “cloud” 1020 using distributed systems, such as through platform 1022 as described below.

[0208] Cloud 1020 includes and / or represents platform 1022 for resource 1024. Platform 1022 abstracts the underlying functionality of the hardware (e.g., server) and software resources of cloud 1020. Resource 1024 may include applications and / or data that can be used when performing computer processing on a server located remotely from computing device 1010. Resource 1024 may also include services provided via the Internet and / or via subscriber networks such as cellular or Wi-Fi networks.

[0209] Platform 1022 can abstract resources and functions to connect computing device 1010 to other computing devices. Platform 1022 can also be used to abstract resource hierarchy to provide a corresponding level of hierarchy for any encountered needs for resource 1024 implemented via platform 1022. Therefore, in interconnect device embodiments, the implementation of the functions described herein can be distributed throughout system 1000. For example, functions can be implemented partly on computing device 1010 and partly through platform 1022, which abstracts the functions of cloud 1020.

[0210] This disclosure provides a computer-readable storage medium having computer-readable instructions stored thereon, which, when executed, implement any of the methods described above.

[0211] This disclosure provides a computer program product or computer program including computer instructions stored in a computer-readable storage medium. A processor of a computing device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computing device to perform any of the methods provided in the various alternative implementations described above.

[0212] It should be understood that, for clarity, embodiments of this disclosure have been described with reference to different functional units. However, it will be apparent that, without departing from this disclosure, the functionality of each functional unit may be implemented in a single unit, in multiple units, or as part of other functional units. For example, functionality described as being performed by a single unit may be performed by multiple different units. Therefore, references to a particular functional unit are considered merely as references to the appropriate unit used to provide the described functionality, and not as indicating a strict logical or physical structure or organization. Thus, this disclosure may be implemented in a single unit, or may be physically and functionally distributed among different units and circuits.

[0213] It will be understood that although the terms first, second, third, etc., may be used herein to describe various devices, elements, components, or parts, these devices, elements, components, or parts should not be limited by these terms. These terms are used only to distinguish one device, element, component, or part from another device, element, component, or part.

[0214] Although this disclosure has been described in conjunction with some embodiments, it is not intended to be limited to the specific forms set forth herein. Rather, the scope of this disclosure is limited only by the appended claims. Additionally, although individual features may be included in different claims, these may be advantageously combined, and inclusion in different claims does not imply that such a combination of features is not feasible and / or advantageous. The order of features in the claims does not imply that the features must be in any particular order of their operation. Furthermore, in the claims, the word "comprising" does not exclude other elements, and the terms "a" or "an" do not exclude a plurality. Reference numerals in the claims are provided only by way of explicit example and should not be construed as limiting the scope of the claims in any way.

Claims

1. A graphics processing system, characterized in that, The graphics processing system includes at least two enabled graphics processing cores, and each of the at least two enabled graphics processing cores includes a vertex splitting module, a vertex processing pipeline module, a primitive assembly pipeline module, a primitive processing pipeline module, and a pixel processing pipeline module; wherein, the at least two enabled graphics processing cores include a target graphics processing core, and wherein, The vertex splitting module of the target graphics processing core is configured to obtain the primitive package to be processed by the target graphics processing core from the vertex index data; The vertex processing pipeline module of the target graphics processing core is configured to perform color processing on the vertices corresponding to the indices in the primitive package to obtain the color processing result; The primitive assembly pipeline module of the target graphics processing core is configured to acquire a primitive splitting initial state and split the primitive package into primitives based on the primitive splitting initial state. The primitive splitting initial state represents the information of primitives formed by the vertices corresponding to the indices included in the primitive package. The primitive processing pipeline module of the target graphics processing core is configured to perform primitive processing on the coloring processing result and the split primitives to obtain the primitive processing result. The pixel processing pipeline module of the target graphics processing core is configured to process the primitive processing results to obtain a visual graphic.

2. The graphics processing system according to claim 1, characterized in that, The vertex splitting module of the target graphics processing core is configured to: obtain target vertex index data from vertex index data, and determine the primitive package based on the target vertex index data. The primitive package includes vertex index fragments and suffix vertex indices, wherein the vertex index data includes indices of vertices of a graph with a specified topology to be drawn, and the suffix vertex indices are indices that are consecutively located after the vertex index fragments according to the index order in the vertex index data.

3. The graphics processing system according to claim 2, characterized in that, The vertex index fragments included in the primitive package to be processed by the at least two enabled graphics processing cores all include the same predetermined number of vertex indices, and the number of suffix vertex indices depends on the specified topology type.

4. The graphics processing system according to claim 1, characterized in that, The shading process performed by the vertex processing pipeline module of the target graphics processing core and the primitive assembly pipeline module of the target graphics processing core are separated into parallel operations.

5. The graphics processing system according to claim 1, characterized in that, The primitive assembly pipeline modules of at least two enabled graphics processing cores are unidirectionally connected in the order of their serial numbers 0 to N-1. The primitive assembly pipeline module of the graphics processing core with serial number N-1 is unidirectionally connected to the primitive assembly pipeline module of the graphics processing core with serial number 0, so that the communication connection is in a ring shape, where N is a positive integer greater than 1.

6. The graphics processing system according to claim 5, characterized in that, The target graphics processing core has a serial number of n, where n is an integer greater than or equal to 0 and less than or equal to N-1, and the primitive assembly pipeline module of the target graphics processing core is further configured as follows: In response to the sequence number n being 0 and the target graphics processing core being the first to acquire primitive splitting initial state, the pre-configured initial state is acquired as the primitive splitting initial state of the target graphics processing core; In response to the sequence number n being non-zero or the target graphics processing core being a non-first-time acquisition of primitive splitting initial state, the primitive splitting initial state sent by the primitive assembly pipeline module of the prior graphics processing core in the ring communication connection of the target graphics processing core is acquired as the primitive splitting initial state of the target graphics processing core.

7. The graphics processing system according to claim 6, characterized in that, The primitive assembly pipeline module of the target graphics processing core is also configured to: Generate the initial state of primitive splitting for the target graphics processing core in the ring communication connection and send it to the primitive assembly pipeline module of the target graphics processing core.

8. The graphics processing system according to claim 5, characterized in that, The vertex splitting module of the target graphics processing core is configured as follows: Obtain a graphics drawing command, which indicates that a graph with a specified topology type should be drawn; Determine the number sequence corresponding to the index of the predetermined number of vertices to be processed by the target graphics processing core; Based on the numbering sequence, obtain the vertex index fragments and suffix vertex indices that are to be processed by the target graphics processing core from the vertex index data, so as to determine the primitive package to be processed by the target graphics processing core.

9. The graphics processing system according to claim 7, characterized in that, The initial state of primitive decomposition in the subsequent graphics processing core includes the starting vertex number, the valid state of the starting vertex, the starting primitive number, the offset of the starting vertex, and the winding order of the starting primitive. The winding order of the starting primitive indicates the connection order of the vertices of the starting primitive when forming the starting primitive. The connection order includes either clockwise or counterclockwise. Furthermore, the primitive assembly pipeline module of the target graphics processing core is configured to: In response to the specified topology type being a point list, a line strip, or a line strip with adjacent points, the initial state of primitive splitting is determined to include: the effective state of the starting vertex is invalid, the number of the starting primitive is the sum of the last primitive number processed by the target graphics processing core and one, and the offset of the starting vertex is zero. In response to the specified topology type being a control packet list with K points, a line list, a line list with adjacency information, a triangle list, or a triangle list with adjacency information, the initial state of primitive splitting is determined as follows: the valid state of the starting vertex is invalid, the number of the starting primitive is the sum of the last primitive number processed by the target graphics processing core and one, and the offset of the starting vertex depends on the position of the virtual clipping point in the vertex index fragment processed by the target graphics processing core, wherein the position of the virtual clipping point includes the position of the reset point and the position of the primitive end, and the reset point indicates that there are no common vertices between the primitive containing the vertex before the reset point and the primitive containing the vertex after the reset point; In response to the specified topology type being a triangle strip, the initial state of primitive splitting is determined as follows: the valid state of the starting vertex is invalid, the number of the starting primitive is the sum of the last primitive number processed by the target graphics processing core and one, the offset of the starting vertex is zero, the winding order of the starting primitive is the opposite of the winding order of the last primitive processed by the target processing core, and the winding order of the starting primitive indicates the connection order of the vertices of the starting primitive when forming the starting primitive, the connection order including one of clockwise and counterclockwise. In response to the specified topology type being a triangle strip with adjacent points, the initial state of primitive splitting is determined as follows: the valid state of the starting vertex is invalid; the number of the starting primitive is the sum of the number of the last primitive processed by the target graphics processing core and one; the offset of the starting vertex is one when the last primitive processed by the target graphics processing core uses an odd number of suffix vertex indices and zero when the last primitive processed by the target graphics processing core uses an even number of suffix vertex indices; the winding order of the starting primitive is the opposite of the winding order of the last primitive processed by the target processing core; the winding order of the starting primitive indicates the connection order of the vertices of the starting primitive when forming the starting primitive, and the connection order includes one of clockwise and counterclockwise. In response to the specified topology type being a loop line or a triangle fan, the initial state of primitive splitting is determined as follows: the starting vertex is valid when the last vertex index of the vertex index segment to be processed by the target graphics processing core is not a reset point, and the starting vertex number is the starting vertex number of the last primitive of the vertex index segment processed by the target graphics processing core, the starting primitive number is the sum of the last primitive number processed by the target graphics processing core and one, and the offset of the starting vertex is zero.

10. The graphics processing system according to claim 1, characterized in that, The at least two enabled graphics processing cores include a central graphics processing core and at least one non-central graphics processing core. When the target graphics processing core is a central graphics processing core, the primitive assembly pipeline module of the target graphics processing core is configured to generate a primitive splitting initial state for each of the at least two enabled graphics processing cores. When the target graphics processing core is a non-central graphics processing core, the primitive assembly pipeline module of the target graphics processing core is configured to obtain the primitive splitting initial state from the primitive assembly pipeline module of the central graphics processing core.

11. The graphics processing system according to claim 10, characterized in that, When the target graphics processing core is the central graphics processing core, the primitive assembly pipeline module of the target graphics processing core is configured to generate a primitive splitting initial state for each of the at least two enabled graphics processing cores based on all vertex index data.

12. The graphics processing system according to claim 10, characterized in that, The vertex splitting module of the target graphics processing core is also configured to: If the target graphics processing core is a non-centralized graphics processing core, then the following steps are executed: Obtain a graphics drawing command, which indicates that a graph with a specified topology type should be drawn; Determine the number sequence corresponding to the index of the predetermined number of vertices to be processed by the target graphics processing core; Based on the numbering sequence, obtain the vertex index fragments and suffix vertex indices that are to be processed by the target graphics processing core from the vertex index data, so as to determine the primitive package to be processed by the target graphics processing core.

13. The graphics processing system according to claim 10, characterized in that, The vertex splitting module of the target graphics processing core is also configured to: If the target graphics processing core is a central graphics processing core, then the following steps are executed: Obtain a graphics drawing command, which indicates that a graph with a specified topology type should be drawn; Determine the number sequence corresponding to the index of the predetermined number of vertices to be processed by the target graphics processing core; Obtain all vertex index data required for drawing the graph, which serves as the target vertex index data; Based on the numbering sequence, determine the vertex index fragments and suffix vertex indices to be processed by the target graphics processing core from the target vertex index data, so as to determine the primitive package to be processed by the target graphics processing core.

14. The graphics processing system according to claim 12 or 13, characterized in that, The vertex index data is either pre-generated by the application that issues the graphics drawing command or generated by the vertex splitting module itself.

15. The graphics processing system according to claim 1, characterized in that, The vertex splitting module of the target graphics processing core is also configured to determine the number of suffix vertex indices in the following manner: In response to the specified topology type being a point list, the number of suffix vertex indices is zero; In response to the specified topology type being a line list, a circular line, or a line strip, the number of suffix vertex indices is one; In response to the specified topology type being a triangle list, triangle strip, or triangle fan, the number of suffix vertex indices is two; In response to the specified topology type being a line list with adjacency information or a line strip with adjacency information, the number of suffix vertex indices is three; In response to the specified topology being a triangle list with adjacency information, the number of suffix vertex indices is five; In response to the specified topology type being a triangle strip with adjacency information, the number of suffix vertex indices is seven; In response to the specified topology being a control packet list with K points, the number of suffix vertex indices is K-1, where K is a positive integer.

16. The graphics processing system according to claim 5, 12, or 13, characterized in that, The vertex splitting module of the target graphics processing core is also configured to: The consecutive numbers are divided into number sequences based on the number of vertex index segments, and the resulting number sequences are numbered sequentially. Determine the sequence number of the target graphics processing core among the at least two enabled graphics processing cores during this graphics processing process; If the remainder obtained by dividing the number of the target number sequence obtained by partitioning by the number of the at least two enabled graphics processing cores is the same as the sequence number of the target graphics processing core, then the target number sequence is determined as the number sequence corresponding to the index of the predetermined number of vertices to be processed by the target graphics processing core.

17. The graphics processing system according to claim 1, characterized in that, The graphics processing core also includes a vertex cache module with vertex index caching and vertex storage. The vertex cache module of the target graphics processing core is configured to: perform a hit test on multiple indexes included in the primitive package based on the vertex index cache, add the missing indexes to the vertex index cache, and send the indexes in the vertex index cache to the vertex processing pipeline module of the target graphics processing core. The vertex processing pipeline module of the target graphics processing core is configured to: perform color processing on the vertex corresponding to the received index, and store the color processing result in the vertex storage.

18. The graphics processing system according to claim 17, characterized in that, The primitive assembly pipeline module of the target graphics processing core is configured to: obtain the mapping relationship between the index in the primitive package and the shading result index, wherein the shading result index is used to identify the shading result of the vertex corresponding to the index in the primitive package.

19. The graphics processing system according to claim 18, characterized in that, The vertex cache module of the target graphics processing core is further configured to: generate vertex shader tasks and shading result indexes based on the missing indexes in the vertex index cache; send the vertex shader tasks and shading result indexes to the vertex processing pipeline module of the target graphics processing core; and send the mapping relationship between the indexes in the primitive package and the shading result indexes to the primitive assembly pipeline module of the target graphics processing core.

20. The graphics processing system according to claim 18, characterized in that, The primitive assembly pipeline module of the target graphics processing core is configured to: perform a hit test on multiple indexes included in the primitive package based on the shadow cache, and add the missing indexes to the shadow cache; Based on the order in which each index is added to the shadow cache, the coloring result index corresponding to each index is determined to determine the mapping relationship.

21. The graphics processing system according to claim 18, characterized in that, The primitive assembly pipeline module of the target graphics processing core is further configured to: determine the color processing result index corresponding to each index included in the split primitive based on the mapping relationship, and send the color processing result index corresponding to the split primitive to the primitive processing pipeline module of the target graphics processing core. The primitive processing pipeline module of the target graphics processing core is configured to: obtain the shading result corresponding to the primitive from the vertex storage based on the shading result index corresponding to the split primitive, and perform primitive processing.

22. The graphics processing system according to claim 18, characterized in that, The primitive assembly pipeline module of the target graphics processing core is further configured to send the mapping relationship and the index of the split primitives to the primitive processing pipeline module of the target graphics processing core. The primitive processing pipeline module of the target graphics processing core is configured to: determine the shading result index corresponding to the split primitive based on the mapping relationship and the index included in the split primitive, and obtain the shading result corresponding to the primitive from the vertex storage based on the shading result index corresponding to the split primitive, and perform primitive processing.

23. The graphics processing system according to claim 17, characterized in that, The vertex cache module of the target graphics processing core is configured to send the index in the vertex index cache to the vertex processing pipeline module of the target graphics processing core under any of the following conditions: The number of unsent vertices in the vertex index cache reaches the trigger threshold; The vertex index cache is full; The primitive packet includes multiple vertices, none of which are remaining vertices that have not been hit-tested.

24. A graphics processing method, characterized in that, The method is executed by a target graphics processing core, which is one of at least two enabled graphics processing cores in the graphics processing system. Each of the at least two enabled graphics processing cores includes a vertex splitting module, a vertex processing pipeline module, a primitive assembly pipeline module, a primitive processing pipeline module, and a pixel processing pipeline module. Furthermore, the method includes: The vertex splitting module of the target graphics processing core is used to obtain the primitive packet to be processed by the target graphics processing core from the vertex index data; Using the vertex processing pipeline module of the target graphics processing core, the vertices corresponding to the indices in the primitive package to be processed by the target graphics processing core are colored to obtain the coloring result. Using the primitive assembly pipeline module of the target graphics processing core, the primitive splitting initial state of the target graphics processing core is obtained, and the primitive package determined from the target vertex index data is split into primitives based on the primitive splitting initial state. The primitive splitting initial state represents the information of primitives composed of vertices corresponding to the indices included in the primitive package to be processed by the target graphics processing core. Using the primitive processing pipeline module of the target graphics processing core, primitive processing is performed on the coloring processing result and the split primitives to obtain the primitive processing result. The pixel processing pipeline module of the target graphics processing core is used to process the primitive processing results to obtain a visual graphic.

25. A computing device, characterized in that, The computing device includes: Memory, which is configured to store computer-executable instructions; A processor configured to perform the method of claim 24 when the computer-executable instructions are executed by the processor.

26. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions that, when executed, perform the method as described in claim 24.

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