A package ring for a chip heat dissipation package structure and a chip heat dissipation package structure

Abstract

This invention discloses a packaging ring for a chip heat dissipation packaging structure and a chip heat dissipation packaging structure configured thereon. The packaging ring includes a frame, a sealing strip, and a leakage detection coil. The frame has a through-hole to provide heat dissipation space. The frame has opposing first and second surfaces, each with a first and second groove respectively, which are arranged around the periphery of the through-hole. The sealing strip is disposed within the first and second grooves. The first and / or second surfaces also have a third groove, within which the leakage detection coil is disposed. When disposed on the first surface, the third groove is arranged around the periphery of the outermost first groove; when disposed on the second surface, the third groove is arranged around the periphery of the outermost second groove. The packaging ring decouples the sealing structure from the chip, does not occupy the effective area of ​​the chip, and integrates leakage detection functionality, improving the safety and reliability of the heat dissipation system.

Description

Technical Field

[0001] This invention relates to the field of chip heat dissipation packaging technology, and in particular to a chip heat dissipation packaging structure. Background Technology

[0002] With the development of artificial intelligence and high-performance computing, computing density and power consumption are constantly increasing, making heat dissipation a key challenge in chip design. Traditional air cooling is insufficient to meet the needs of new applications. Chip-level microchannel liquid cooling technology, which uses a liquid cooling medium to directly act on the back of the chip, effectively reduces the operating temperature and has become a competitive solution. Currently, there are three main types of publicly available chip-level microchannel liquid cooling technologies: The first type involves creating an open, turbulence-prone microchannel structure on the back of the chip substrate. The cooling medium is then transported to the microchannel through a guide channel within the packaging cover, or a jet array is directly installed on the packaging cover to spray the cooling medium microjet onto the back of the chip. The second type integrates a closed silicon-based microchannel heat sink on the back of the packaged chip. The glass cover is sealed to the microchannel substrate via anodic bonding to form the heat sink. The main microchannel is sealed by the glass cover, leaving only inlet and outlet channels. A diversion channel is provided within the packaging cover, allowing the cooling medium to enter from the microchannel inlet through the packaging diversion cover and finally flow back to the outlet. The third type is a side-entry microchannel heat sink for 3D-ICs. The microchannel is located between the chips, with the inlet and outlet located at the two ends of the chip's side. The cooling medium enters from the side inlet through the packaging diversion cover, is cooled, and then exits from the side outlet, finally flowing back to the packaging diversion cover outlet.

[0003] Representative chip-level microchannel liquid cooling technologies are as follows:

[0004] In 2021, TSMC proposed a direct silicon water cooling solution using a fusion-bonded silicon cap. Utilizing silicon oxide as the interface material, an open silicon cap with an etched square pillar array is bonded to the SoC chip via silicon-silicon fusion bonding, achieving extremely low thermal resistance. The edge of the silicon cap forms a water seal with a package cap featuring inlet and outlet ports via an O-ring, creating a closed cooling system. However, this O-ring occupies part of the effective area of ​​the silicon cap, reducing the heat dissipation area and affecting cooling efficiency; furthermore, leaks cannot be monitored in real time, making it difficult to handle malfunctions promptly, potentially leading to unstable cooling performance or even leaks.

[0005] In 2025, TSMC proposed a system based on CoWoS. ® The platform employs an open microchannel cooling solution on the back substrate of the chip. A micropillar array is etched on the back of each SoC chip, and a flexible sealant is applied in a "1D line" pattern around the chip periphery, rather than covering the entire chip surface. A cover plate with multiple inlets and outlets is then installed to form a leak-proof chamber. The cooling medium directly contacts the back of the silicon chip, achieving higher power dissipation. However, the sealant coating occupies chip area, limiting the effective heat dissipation area and making real-time leakage monitoring impossible, posing a safety hazard.

[0006] In 2025, Xiamen University proposed a closed silicon-based microchannel heat sink integrated on the back of a CMOS chip, consisting of a silicon-based microchannel substrate and a glass cover plate bonded together by anodic bonding. The cover plate, containing the cooling medium channels, is mechanically fixed to the PCB, and O-rings are installed around the inlet and outlet ports of the glass cover plate to achieve assembly sealing and prevent leakage. This solution can achieve high-power heat dissipation, but it cannot achieve leakage monitoring, affecting system stability and safety.

[0007] In 2025, Microsoft proposed a closed-loop microfluidic cooling technology for chips. This technology uses AI algorithms to analyze chip heat distribution and etches honeycomb-shaped microchannels (200-500 micrometers wide and 100-300 micrometers deep) on the back of the chip, employing a leaf vein-inspired branching structure to cover hot spots. To ensure sealing, a silicon-glass-metal three-layer anodic bonding technology is used, with a sealing ring at the glass inlet end, which is assembled with a cover plate with inlet and outlet ports. O-rings are also added to the reinforcing rings around the chip to prevent leakage. However, this solution also cannot monitor leaks in real time.

[0008] In summary, chip-level microchannel liquid cooling technology offers significant advantages in improving heat dissipation efficiency, but existing solutions still face challenges in sealing and leak detection. Whether using open-type baffles or closed-type microchannels, sealing typically employs O-rings or sealant applied to the chip, occupying valuable chip area, reducing heat dissipation space, and impacting efficiency. Furthermore, the risk of coolant leakage remains, and real-time monitoring and remedial measures are key bottlenecks in engineering applications. Therefore, it is necessary to propose a new technological solution that can create an effective sealing structure for the heat dissipation cavity in a location independent of the chip, and possess leak detection capabilities, thereby improving the efficiency, safety, and stability of the heat dissipation system. Summary of the Invention

[0009] The main technical problem to be solved by the present invention is to provide a chip heat dissipation packaging structure with higher heat dissipation efficiency and operational safety and stability.

[0010] To address the aforementioned technical problems, the present invention provides a packaging ring for a chip heat dissipation packaging structure, comprising a frame, several sealing strips, and a leakage detection coil.

[0011] The frame has a through-hole at its center that is no smaller than the size of the chip; the frame has a first surface and a second surface; the first surface has a first groove and the second surface has a second groove, and the first groove and the second groove are arranged around the periphery of the through-hole; the plurality of sealing strips include a first sealing strip coiled in the first groove and a second sealing strip coiled in the second groove;

[0012] The first surface and / or the second surface are further provided with a third groove, and the leakage detection coil is disposed in the third groove; when disposed on the first surface, the third groove is disposed around the outermost first groove on the side away from the opening; when disposed on the second surface, the third groove is disposed around the outermost second groove on the side away from the opening.

[0013] In a preferred embodiment, the side of the port near the second surface is configured with a profile that matches the chip so that the frame fits snugly against the periphery of the chip.

[0014] In a preferred embodiment, the frame is further configured with a recess for accommodating passive components and a fourth groove surrounding the outer periphery of the recess; the plurality of sealing strips further include a third sealing strip coiled within the fourth groove.

[0015] In a preferred embodiment, the frame is further configured with a wire outlet channel communicating with the third groove for leading out the leakage detection coil.

[0016] In a preferred embodiment, the leakage detection coil employs a humidity sensing element, which undergoes a change in electrical characteristics upon contact with the cooling medium.

[0017] In a preferred embodiment, the humidity sensing element includes two layers of wiring and a dielectric layer; wherein, one layer of wiring consists of two annular electrodes arranged side by side in the third groove, and the other layer of wiring consists of electrode leads arranged in the outgoing channel.

[0018] In a preferred embodiment, the third groove is disposed on one of the first surface and the second surface, which is opposite to the liquid inlet direction of the cooling medium.

[0019] In a preferred embodiment, the frame is made of metal and has an anti-corrosion layer wrapped around its surface.

[0020] The present invention also provides a chip heat dissipation packaging structure, including the packaging ring described above.

[0021] In a preferred embodiment, the chip heat dissipation packaging structure further includes a heat dissipation element, a cover plate, a substrate, a circuit board, and several fasteners; the cover plate is disposed on a first surface of the packaging ring, and the substrate is disposed on a second surface of the packaging ring, so as to form a heat dissipation cavity with the packaging ring at the opening; the heat dissipation element is disposed in the heat dissipation cavity for dissipating heat from the chip fixed on the substrate and also located in the heat dissipation cavity; the circuit board is disposed on the side of the substrate facing away from the packaging ring, and is connected to the cover plate on the periphery by the fasteners.

[0022] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0023] The encapsulation ring provided by the present invention encloses a heat dissipation space between the cover plate and the substrate. The sealing strips arranged on its two surfaces achieve reliable sealing of the heat dissipation space under the action of compression. The design has the following technical effects: (1) The sealing interface is set independently outside the chip and heat dissipation element, the sealing function is decoupled from the chip itself, and the entire back surface of the chip can be used for heat dissipation or contact with heat dissipation element, thereby maximizing the heat dissipation area and improving the overall heat dissipation efficiency. (2) Each sealing structure is highly integrated into the independent component of the packaging ring, which brings the following technological advancements: Compared with the discrete arrangement method where sealing performance may be “one thing at a time”, each sealing component has higher synergy and stability; the milling and grooving operation is completed uniformly in the separate packaging ring, reducing the processing difficulty of the entire chip heat dissipation packaging structure; it reserves a large degree of structural freedom for the differentiated adaptation of subsequent sealing schemes and the updating and deepening of sealing design; the sealing interface is concentrated on both sides of the packaging ring, reducing the difficulty of troubleshooting and maintaining sealing performance during use; (3) The sealing ring has the functions of mechanical support, heat dissipation space shaping and structural sealing, making it a promising standardized and modular component that can be widely adapted to chip packaging structures with different heat dissipation methods.

[0024] Meanwhile, the encapsulation ring also features leakage detection. The ring-shaped leakage detection coils provide sensitive, all-angle detection of any potential leaks of cooling fluid, alerting the user to perform timely maintenance in case of leakage. This ensures the safe and stable operation of the heat dissipation system and the chip itself. The layered layout with the encapsulation ring as the carrier allows for tight spatial coupling and logical collaboration between sealing and detection functions: the sealing strip intercepts the cooling fluid, while the detection coils monitor any trace amounts of fluid that might penetrate the first line of defense in real time. Compared to solutions that distribute multiple sensors around the chip, the integrated design of this invention significantly reduces assembly complexity and packaging burden, while improving the synergy of various functional components. Attached Figure Description

[0025] Figure 1 This is a three-dimensional structural diagram of the encapsulation ring described in Embodiment 1 of the present invention;

[0026] Figure 2 This is a plan view of the encapsulation ring on the second surface in Embodiment 1 of the present invention;

[0027] Figure 3 This is a three-dimensional structural diagram of the chip heat dissipation packaging structure described in Embodiment 1 of the present invention;

[0028] Figure 4 This is an exploded view of the chip heat dissipation packaging structure described in Embodiment 1 of the present invention;

[0029] Figure 5This is a cross-sectional view of the chip heat dissipation packaging structure described in Embodiment 1 of the present invention (i.e., Figure 4 (Cross-sectional view of AA)

[0030] Figure 6 This is a three-dimensional structural diagram of the chip heat dissipation packaging structure described in Embodiment 2 of the present invention;

[0031] Figure 7 This is an exploded view of the chip heat dissipation packaging structure described in Embodiment 2 of the present invention;

[0032] Figure 8 This is a cross-sectional view of the chip heat dissipation packaging structure described in Embodiment 2 of the present invention (i.e., Figure 7 (Cross-section view of BB)

[0033] Figure 9 This is a three-dimensional structural diagram of the chip heat dissipation packaging structure described in Embodiment 3 of the present invention;

[0034] Figure 10 This is an exploded view of the chip heat dissipation packaging structure described in Embodiment 3 of the present invention;

[0035] Figure 11 This is a cross-sectional view of the chip heat dissipation packaging structure described in Embodiment 3 of the present invention (i.e., Figure 10 (Central CC section view)

[0036] The diagram is labeled as follows: 1-Encapsulation ring, 11-Frame, 111-Port, 112-First surface, 113-Second surface, 121-First sealing strip, 122-Second sealing strip, 123-Third sealing strip, 131-First groove, 132-Second groove, 133-Third groove, 134-Fourth groove, 14-Leakage detection coil, 15-Submersible tank, 16-Wire outlet channel, 2-Heat dissipation element, 21-Liquid storage chamber, 22-Micropore array, 2 31-Inlet channel, 232-Outlet channel, 24-Interface board, 241-Inlet, 242-Outlet, 25-Microchannel substrate, 26-Glass cover, 271-Inlet, 272-Outlet, 281-First sealing ring, 282-Second sealing ring, 29-Microchannel heat sink, 3-Chip, 31-First chip, 32-Second chip, 4-Cover plate, 5-Substrate, 6-Circuit board, 7-Fastener, 8-Passive component, 9-Reinforcing plate. Detailed Implementation

[0037] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0038] In the description of this invention, it should be noted that the terms "upper," "lower," "inner," "outer," "top / bottom," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0039] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installed", "equipped", "sleeved / connected", "connected", etc., should be interpreted broadly. For example, "connection" can be a wall-mounted connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be a connection within two components. For those skilled in the art, the specific meaning of the above terms in this invention can be understood according to the specific circumstances.

[0040] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a packaging ring and a chip heat dissipation packaging structure according to the present invention. Those skilled in the art will understand that the drawings are simplified and not to scale, and are only used to illustrate the embodiments of the present invention.

[0041] Example 1

[0042] like Figures 1 to 5 As shown, this embodiment of the invention provides a chip heat dissipation packaging structure, including a heat dissipation element 2, a cover plate 4, a packaging ring 1, a substrate 5, a circuit board 6, and several fasteners 7. Overall, the cover plate 4 and the substrate 5 are supported by the packaging ring 1 to jointly enclose a heat dissipation cavity. The packaging ring 1 has multiple sets of sealing strips on its mating surface with the cover plate 4 and the substrate 5 to seal the heat dissipation cavity. The heat dissipation element 2 is integrated into the cover plate 4 and dissipates heat from the chip 3, which is fixed to the substrate 5 and also located within the heat dissipation cavity. The circuit board 6 is located on the side of the substrate 5 facing away from the packaging ring 1 and is connected to the cover plate 4 externally via the fasteners 7, achieving a solid seal for the chip 3 by inwardly pressing the substrate 5 and the packaging ring 1. The structure and connection method of the main components are further described below with reference to specific figures.

[0043] The encapsulation ring 1 includes a frame 11 and several sealing strips. The frame 11 has a through-hole 111, no smaller than the chip size, through its center to form the main body of the heat dissipation cavity and to allow passage for the chip 3 disposed on the substrate 5. It should be noted that the "center" mentioned above does not refer to the absolute geometric center of the frame 11; it should be understood as the position of the through-hole 111 allowing the frame 11 to close circumferentially around its outer periphery. The encapsulation ring 1 is preferably made of metal and has a corrosion-resistant layer on its surface; in other applications, it uses a material such as resin that is chemically inert to the cooling medium. For ease of description, the two opposing surfaces of the frame 11 are defined as the first surface 112 and the second surface 113, respectively, and: when the encapsulation ring 1 is assembled in the chip heat dissipation encapsulation structure, the first surface 112 faces the cover plate 4, and the second surface 113 faces the substrate 5. Preferably, the side of the port 111 near the second surface 113 is constructed with a profile that matches the chip 3, so that the frame 11 fits tightly against the periphery of the chip 3. This not only provides lateral restraint for the chip 3, but also prevents the cooling medium from entering the lateral gap between the packaging ring 1 and the chip 3 and causing turbulence.

[0044] The frame 11 has a first groove 131 formed on its first surface 112 and a second groove 132 formed on its second surface 113. The first groove 131 and the second groove 132 are arranged around the periphery of the opening 111. A plurality of the sealing elements include a first sealing strip 121 coiled within the first groove 131 and a second sealing strip 122 coiled within the second groove 132. Unless otherwise specified, "coiled" as used herein refers to the circumferential closure of the element. The first sealing strip 121 and the second sealing strip 122, under the compression of the fastener 7, respectively abut against the surfaces of the cover plate 4 and the substrate 5, preventing leakage of the cooling medium in the heat dissipation cavity. It is understood that, in another similar embodiment, the combination of the first groove 131 and the first sealing strip 121, or the combination of the second groove 132 and the second sealing strip 122, is provided in two or more forms to achieve multi-level sealing. Preferably, the frame 11 also has a recess 15 for accommodating passive components 8 such as I / O chips. Correspondingly, the frame 11 also has a circumferentially closed fourth groove 134 constructed on the outer periphery of the recess 15; the plurality of the sealing elements further include a third sealing strip 123, which is accommodated within the fourth groove 134 to seal the recess 15. Preferably, in this embodiment, the recess 15 is located on the second surface 113 of the frame 11. In terms of relative position in the planar direction, the recess 15 and the fourth groove 134 are located outside the second groove 132, that is, on the side away from the opening 111.

[0045] The encapsulation ring 1 has a leakage detection function. Specifically, the frame 11 has a third groove 133 constructed on at least one of the first surface 112 or the second surface 113. If necessary, when located on the first surface 112, the third groove 133 is disposed around the outer periphery of the outermost first groove 131, i.e., around the side of the outermost first groove 131 away from the opening 111; similarly, when located on the second surface 113, the third groove 133 is disposed around the outer periphery of the outermost second groove 132. The encapsulation ring 1 also includes a leakage detection coil 14 for detecting possible leakage of cooling fluid and issuing an alarm. Figure 5 In the specific application example shown, considering that the fluid force during liquid inflow makes liquid leakage more likely, the third groove 133 and the leakage detection coil 14 are located on the side surface of the frame 11 opposite to the liquid inflow direction of the cooling medium, i.e., the second surface 113. In this embodiment, the leakage detection coil 14 transmits signals via a wired method, so the frame 11 is also constructed with an outlet channel 16 communicating with the third groove 133 to lead out the leakage detection coil 14. Preferably, the outlet channel 16 connects the third groove 133 and the outer wall of the frame 11. Preferably, the leakage detection coil 14 is a humidity sensing element, which undergoes an electrical characteristic change upon contact with the cooling medium, and the monitoring system generates an alarm signal accordingly. In a specific application example, the humidity sensing element is fabricated using a redistribution layer process, which includes two layers of wiring and several dielectric layers. Preferably, the wiring is copper wiring, and the dielectric layers are polyimide dielectric layers. The first layer of copper wiring consists of two annular electrodes arranged side by side in the third groove 133. The second layer of copper wiring serves as the electrode lead-out end and is located in the outgoing channel 16. These two layers of copper wiring are isolated by the polyimide dielectric layer.

[0046] The encapsulation ring 1 provided in this embodiment intercepts the cooling medium by constructing a ring-shaped sealing structure on the surface of the frame 11. This structural basis facilitates the arrangement of the leakage detection element 14: simply by surrounding the outermost sealing strip with a leakage detection coil 14, full-angle interception and leakage detection of the cooling medium can be achieved simultaneously. The leakage detection function can remind users to troubleshoot and maintain in a timely manner, thereby effectively improving the safety and stability of the entire chip heat dissipation packaging structure. The above-mentioned sealing structure and leakage detection element 14, arranged in a ring shape, are compact, easy to assemble, and have high working coordination, avoiding the structural complexity and packaging burden of arranging sensors at multiple points around the chip 3.

[0047] The preferred features of the encapsulation ring 1 are now described from the perspectives of materials, molding, and assembly. The materials of the first sealing strip 121, the second sealing strip 122, and the third sealing strip 123 are compatible with the selected cooling medium to avoid changes in material properties due to chemical reactions, thereby improving sealing stability. In terms of manufacturing process, the encapsulation ring 1 preferably uses a metal plate such as copper or aluminum as the base material. Its surface is first nickel-plated to improve corrosion resistance. Then, the through-hole 111 is formed by hollowing out the center, and the first ring groove 131, the second ring groove 132, the third ring groove 133, the recess 15, and the cable outlet 16 are sequentially formed by precision milling. The flatness of the first surface 112 and the second surface 113 of the encapsulation ring 1 is controlled within 50 micrometers to ensure a tight fit with adjacent components during assembly. During assembly, to ensure reliable connection, adhesive is applied to the first surface 112 and the second surface 113 of the encapsulation ring 1, especially around the aforementioned grooves and recesses 15, and at the edges of the inner and outer rings of the encapsulation ring 1, so that it forms a firm bond with the cover plate 4 and the substrate 5, preventing loosening due to vibration or temperature stress.

[0048] The other parts of the chip heat dissipation packaging structure are described below.

[0049] In this embodiment, the heat dissipation method of the heat dissipation element 2 is direct injection of cooling working fluid into the chip. The heat dissipation element 2 is disposed on the cover plate 4, which includes a liquid storage cavity 21, a micropore array 22, a liquid outlet channel 232, and an interface plate 24. The cover plate 4 is recessed in the middle towards the chip 3 to form the liquid storage cavity 21. The micropore array 22 is provided through the recessed cover plate 4 along the thickness direction, which connects the liquid storage cavity 21 and the heat dissipation cavity. On the side of the liquid storage cavity 21, the cover plate 4 is provided with a liquid outlet hole that penetrates its own thickness; the liquid outlet channel 232 connects to the heat dissipation cavity and is independent of the liquid storage cavity 21. The interface plate 24 completely covers the liquid storage cavity 21 and the liquid outlet channel 232, realizing the isolation of the liquid storage cavity 21 and the liquid outlet channel 232 on this side. The interface plate 24 is provided with an inlet 241 communicating with the liquid storage cavity 21 and an outlet 242 aligned with the liquid outlet channel 232. In this way, the cooling medium enters the storage chamber 21 through the inlet 241, then passes through the micropore array 22 and is directly injected into the heat dissipation chamber onto the heating surface of the chip 3. The cooling medium then carries the heat to both sides and flows through the outlet channel 232 to the outlet 242, forming a complete heat dissipation path. To achieve efficient heat dissipation, deionized water is selected as the cooling medium in this embodiment.

[0050] The surface of the chip 3 is treated with DLC and coated with a waterproof film. The side of the substrate 5 facing away from the chip 3 is fixed to the circuit board 6 by solder balls. Preferably, the fastener 7 is a bolt assembly. Preferably, the chip heat dissipation packaging structure also includes a reinforcing plate 9. The reinforcing plate 9 is located on the side of the circuit board 6 away from the substrate 5 and is connected to the circuit board 6 and the cover plate 4 together by the fastener 7. The reinforcing plate 9 can not only reduce the concentrated stress on the circuit board 6 when the bolt assembly is locked, but also improve the integrity and synergy of each set of fasteners 7.

[0051] Example 2

[0052] like Figures 6 to 8 As shown, this embodiment of the invention provides a chip heat dissipation packaging structure, which differs from embodiment 1 in that the heat dissipation element 2 adopts a closed silicon-based microchannel heat sink.

[0053] Specifically, the heat dissipation element 2 includes a microchannel substrate 25, a glass cover plate 26, a first sealing ring 281, and a liquid inlet channel 231 and a liquid outlet channel 232. The microchannel substrate 25 is constructed with a plurality of microchannels, which are disposed on the heat-generating surface of the chip 3 and are anoly bonded to the glass cover plate 26 on the side facing away from the chip 3. In addition to having an inlet 271 and an outlet 272 for the cooling working fluid to enter and exit the microchannels, the glass cover plate 26 completely seals the microchannel substrate 25. The cover plate 4 covers the glass cover plate 26, and the liquid inlet channel 231 and the liquid outlet channel 232 are respectively constructed at the positions corresponding to the inlet 271 and the outlet 272. Two first sealing rings 281 are respectively disposed on the outer periphery of the inlet 271 and outlet 272 of the glass cover plate 26. Under the compression of the fastener 7, they simultaneously abut against the cover plate 4 and the glass cover plate 26 to prevent the cooling medium from overflowing when it flows from the inlet channel 231 to the inlet 271 or from the outlet 272 to the outlet channel 232. The cooling medium enters the inlet 271 of the glass cover plate 26 from the inlet channel 231 at the cover plate 4, flows through the microchannel to complete heat exchange, and then flows back from the outlet 272 to the outlet channel 232 at the cover plate 4, forming a complete heat dissipation path.

[0054] In this embodiment, most components or structures of the heat dissipation element 2 are independent of the cover plate 4, with only the liquid inlet channel 231 and the liquid outlet channel 232 located on the cover plate 4. Apart from the above differences, the other parts of the chip heat dissipation packaging structure provided in this embodiment are the same as in Embodiment 1, and will not be described in detail here. In particular, the structure of the packaging ring 1 and its connection relationship with adjacent components such as the cover plate 4 and the substrate 5 are the same as in Embodiment 1, demonstrating its high structural adaptability.

[0055] Example 3

[0056] like Figures 9 to 11As shown, this embodiment of the invention provides a chip heat dissipation packaging structure, which differs from embodiment 1 in that: the heat dissipation element 2 adopts a 3D-IC side-entry microchannel heat sink, which can dissipate heat from two chips 3 simultaneously.

[0057] Specifically, the chip 3 includes a first chip 31 disposed on one side of the cover plate 4 and a second chip 32 disposed on the substrate 5. The surfaces of these two chips 31 and 32 are treated with DLC and coated with a waterproof film. The heat dissipation element 2 includes a microchannel heat sink 29 and a liquid inlet channel 231 and a liquid outlet channel 232 constructed in the thickness direction of the cover plate 4. The liquid inlet channel 231 and the liquid outlet channel 232 are respectively connected to the heat dissipation cavity. The microchannel heat sink 29 is sandwiched between the first chip 31 and the second chip 32, and has an inlet on the side near the liquid inlet channel 231 and an outlet on the side near the liquid outlet channel 232. The cooling medium enters the heat dissipation cavity from the liquid inlet channel 231 and enters the microchannel heat sink 29 from the inlet; the cooling medium exchanges heat with the chips 31 and 32 on both sides when flowing through the microchannel heat sink 29, then flows into the heat dissipation cavity through the outlet, and finally flows out through the liquid outlet channel 232, forming a complete heat dissipation path. The second sealing ring 282 is disposed between the first chip 31 and the cover plate 4 to prevent the cooling medium from taking a shortcut from the gap between the first chip 31 and the cover plate 4 to flow directly from the liquid inlet channel 231 to the liquid outlet channel 232 without exchanging heat with the heating surfaces of the chips 31 and 32.

[0058] Apart from the differences mentioned above, the other parts of the chip heat dissipation packaging structure provided in this embodiment are the same as those in Embodiment 1, and will not be described in detail here. In particular, the structure of the packaging ring 1 and its connection relationship with adjacent components (cover plate 4, substrate 5, etc.) are the same as those in Embodiment 1, demonstrating its high structural adaptability.

[0059] As can be seen from the above three embodiments, the encapsulation ring 1 encloses a heat dissipation space between the cover plate 4 and the substrate 5. The sealing strips 121, 122, etc., which are compactly arranged on its two surfaces 112, 113, achieve a reliable seal for the heat dissipation space under compression. This design has the following technical effects:

[0060] (1) The sealing interface is set independently outside the chip 3 and the heat dissipation element 2. The sealing function is decoupled from the chip 3 itself. The entire back surface of the chip 3 can be used for heat dissipation or contact with the heat dissipation element 2, thereby maximizing the heat dissipation area and improving the overall heat dissipation efficiency.

[0061] (2) Each sealing structure is highly integrated into the independent component of the packaging ring 1, which brings the following technological advancements: Compared with the discrete arrangement method where sealing performance may be compromised, each sealing component 121, 122, etc. have higher synergy and stability; the milling and grooving operation is completed uniformly in the separate packaging ring 1, reducing the processing difficulty of the entire chip heat dissipation packaging structure; a large degree of structural freedom is reserved for the differentiated adaptation of subsequent sealing schemes and the updating and deepening of sealing design; the sealing interface is concentrated on both sides of the packaging ring 1, reducing the difficulty of troubleshooting and maintaining sealing performance during use;

[0062] (3) The sealing ring 1 has the functions of mechanical support, heat dissipation space shaping and structural sealing, making it a promising standardized and modular component that can be widely adapted to chip packaging structures with different heat dissipation methods.

[0063] Meanwhile, the encapsulation ring 1 also features leakage detection. The ring-shaped leakage detection coils 14 perform all-angle, sensitive detection of potentially leaking cooling fluid, alerting the user to perform timely maintenance when leakage occurs. This ensures the safe and stable operation of the heat dissipation system and the chip 3 itself. The layered layout with the encapsulation ring 1 as the carrier allows the sealing and detection functions to be tightly coupled spatially and work collaboratively logically: the sealing strips 121 and 122 intercept the cooling fluid, while the detection coils 14 monitor in real time any trace amounts of cooling fluid that may penetrate the first line of defense. Compared to the solution of distributing multiple sensors around the chip 3, the integrated design of this invention significantly reduces assembly complexity and packaging burden, while improving the collaborative operation of various functional components.

[0064] The above description is merely a preferred embodiment of the present invention and is not intended to limit the patent scope of the present invention. Any technically equivalent modifications made based on the content of this specification shall fall within the protection scope of the present invention.

Claims

1. A packaging ring for a chip heat dissipation packaging structure, characterized in that: The frame, the plurality of sealing strips and the liquid leakage detection coil are included. The frame is provided with a through opening with a size not less than that of the chip at the middle part; the frame has opposite first and second surfaces; the first surface is provided with a first groove, the second surface is provided with a second groove, and the first and second grooves are arranged around the periphery of the through opening; the plurality of sealing strips include a first sealing strip arranged in the first groove and a second sealing strip arranged in the second groove. The first or / and second surface is further provided with a third groove, and the liquid leakage detection coil is arranged in the third groove; when arranged on the first surface, the third groove is arranged on the side of the outermost first groove away from the through opening; when arranged on the second surface, the third groove is arranged on the side of the outermost second groove away from the through opening.

2. The encapsulation ring for a chip heat dissipation package structure of claim 1, wherein: The side of the through opening close to the second surface is provided with a contour matching the chip, so that the frame closely adheres to the peripheral side of the chip.

3. The encapsulation ring for a chip heat dissipation package structure of claim 1, wherein: The frame is further provided with a sink for accommodating a passive element, and a fourth groove arranged around the periphery of the sink; the plurality of sealing strips further include a third sealing strip arranged in the fourth groove.

4. The encapsulation ring for a chip heat dissipation package structure of claim 1, wherein: The frame is further provided with a wire outlet channel in communication with the third groove, for leading out the liquid leakage detection coil.

5. The encapsulation ring for a chip heat dissipation package structure of claim 4, wherein: The liquid leakage detection coil adopts a humidity sensing element which changes its electrical properties after contacting the cooling medium.

6. The encapsulation ring for a chip heat dissipation package structure of claim 5, wherein: The humidity sensing element includes two layers of wiring and a dielectric layer; one layer of wiring is two annular electrodes arranged side by side in the third groove, and the other layer of wiring is an electrode lead-out end arranged in the wire outlet channel.

7. The encapsulation ring for a chip heat dissipation package structure of claim 1, wherein: The third groove is arranged on one of the first and second surfaces which is arranged opposite to the direction of the cooling medium.

8. The encapsulation ring for a chip heat dissipation package structure of claim 1, wherein: The frame adopts a metal material, and a corrosion-resistant layer is arranged on the surface of the frame.

9. A chip heat dissipation package structure, characterized in that: The package ring as claimed in any one of claims 1-8 is included.

10. The chip heat dissipation package structure of claim 9, wherein: Further including a heat dissipation element, a cover plate, a substrate, a circuit board and a plurality of fasteners; the cover plate is arranged on the first surface of the package ring, the substrate is arranged on the second surface of the package ring, so as to form a heat dissipation cavity with the package ring at the through opening; the heat dissipation element is arranged in the heat dissipation cavity, for dissipating heat of the chip fixed on the substrate and also located in the heat dissipation cavity; the circuit board is arranged on the side of the substrate away from the package ring, and is connected with the cover plate at the periphery through the fasteners.

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