Chip package structure and packaging method thereof

By using staggered chip stacking and metallization of through-holes in plastic encapsulation, the problems of signal interconnection and size limitations in traditional multi-chip stacking packaging are solved, achieving efficient and low-cost multi-layer chip packaging, improving power and signal integrity, and making it suitable for large-scale integration.

CN122318906APending Publication Date: 2026-06-30JIANGSU PANGU SEMICONDUCTOR TECHNOLOGY CO LTD
View PDF 0 Cites 0 Cited by

Patent Information

Application Number
CN202610414859.X
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2026-03-31
Publication Date
2026-06-30

AI Technical Summary

Technical Problem

In traditional multi-chip stacking packaging, signal interconnection and product size are mutually restrictive, resulting in high process difficulty and high cost, making it difficult to meet the high efficiency and low cost requirements of integrated circuits.

Method used

By employing chip staggered stacking combined with TMV technology, vertical interconnection is achieved through multi-layer chip staggered stacking within the plastic package and metallization of the plastic package vias. Balls are then placed on the redistribution lines, and combined with metallization processes such as PVD and electroplated copper, a solid or overlay metallized structure is formed.

Benefits of technology

It effectively utilizes space, reduces package size, improves power and signal integrity, enhances I/O density and bandwidth, reduces power consumption, and is suitable for large-scale integration.

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure CN122318906A_ABST
    Figure CN122318906A_ABST
Patent Text Reader

Abstract

This invention discloses a chip packaging structure and packaging method, including a molding compound containing at least two identical or different chips. A molding layer is disposed on the molding compound, containing at least two identical or different chips. A second molding via is formed on the molding layer and metallized therein. Redistribution lines are disposed on the molding layer, and balls are placed on the redistribution lines. This invention achieves vertical interconnection of multi-layer chips through staggered chip stacking combined with TMV technology, effectively utilizing space and reducing package size. The second molding via uses a solid metallization scheme, which can effectively improve the power integrity and signal integrity of the product, improve the read / write performance of the storage product, increase I / O density and bandwidth, and reduce power consumption. The packaging structure can include multiple stacked structure arrays, suitable for large-scale integration, and increasing packaging density.
Need to check novelty before this filing date? Find Prior Art