Successive approximation analog-to-digital converter and method of calibrating the same

Abstract

This invention provides a successive approximation analog-to-digital converter (SAR ADC) and its calibration method. It utilizes the low-order and high-order capacitor arrays within the SAR ADC to mutually calibrate the weight of each capacitor, eliminating the need for an additional calibration DAC and simplifying the circuitry. Furthermore, the calibration method is performed before the SAR ADC operates normally, making the original design of SAR ADCs more flexible.

Description

Technical Field

[0001] This invention relates to the field of analog-to-digital conversion technology, and in particular to a successive approximation analog-to-digital converter and its calibration method. Background Technology

[0002] Successive approximation register analog-to-digital converters (SAR ADCs) have advantages such as low power consumption, small size, good speed and accuracy, and are a common structure for medium to high resolution analog-to-digital converter (ADC) applications with sampling rates below 5 MSPS.

[0003] Please refer to Figure 1 The basic structure of a SAR ADC mainly includes a comparator COMP, a SAR logic module, and a digital-to-analog converter (DAC). The comparator COMP compares the output signal VOUT of the DAC with the common-mode level VCM and sends the comparison result to the SAR logic module 10. The SAR logic module 10 processes the comparison result of the comparator COMP, obtains the switching direction of the DAC in the next round, and provides the quantization value of the corresponding bit for the next round of conversion.

[0004] In SAR ADCs, segmented capacitor arrays are typically used to implement digital-to-analog converters (DACs) to reduce the number of capacitors and save area. For example... Figure 1 As shown, the segmented capacitor array of the digital-to-analog converter (DAC) consists of a k-bit (k bits, k>1 and an integer) high-order segment capacitor array (MDAC) and an m-bit (m bits, m>1 and an integer) low-order segment capacitor array (LDAC). The two are connected by a bridge capacitor (Cb), with the MDAC located at the DAC output. Furthermore, when designing a DAC with a segmented capacitor array structure, the value of the bridge capacitor Cb must be carefully designed to ensure the correct weighting of each capacitor and the overall linearity of the DAC. The value of the bridge capacitor Cb may be a non-integer number of unit capacitances Cu. The parasitic capacitance and bias of the bridge capacitor Cb, as well as the capacitor mismatch between the MDAC and LDAC, can cause severe nonlinearity, degrading the performance of the SAR ADC and requiring calibration.

[0005] Please refer to Figure 1One existing calibration method is to add a calibration DAC11 composed of a corresponding capacitor array, and calibrate the MDAC through the calibration DAC11. The principle is as follows: The calibration DAC11 is connected to the output terminal of the digital-to-analog converter DAC through the coupling capacitor Cc, converts the error value of each bit capacitor of the MDAC into a digital value CAL_DAC_i, and stores it in the corresponding register (not shown). When the ADC is working normally, it outputs the corresponding calibration value CAL_DAC_i to the calibration DAC11 to compensate for the error of each bit capacitor of the MDAC.

[0006] The above calibration method has the following problems:

[0007] 1. The inability to calibrate the LDAC makes the design of the bridge capacitor Cb very demanding, affecting the flexibility of ADC design.

[0008] 2. As the number of bits in the MDAC increases, the capacitor array in the calibration DAC 11 may occupy an area comparable to that of the capacitor array in the MDAC itself, which directly leads to an increase in chip cost. Summary of the Invention

[0009] The purpose of this invention is to provide a successive approximation analog-to-digital converter and its calibration method, which can calibrate each capacitor in the internal digital-to-analog converter, avoid performance degradation caused by capacitor mismatch, and improve the flexibility of ADC design.

[0010] To achieve the above objectives, the present invention provides a calibration method for a successive approximation analog-to-digital converter (ADC). The successive approximation ADC includes a digital-to-analog converter (DAC), which comprises a bridging capacitor, a low-order segment capacitor array, and a high-order segment capacitor array. The first plate of each capacitor in the high-order segment capacitor array is coupled to one plate of the bridging capacitor, forming the output terminal of the high-order segment capacitor array. The first plate of each capacitor in the low-order segment capacitor array is coupled to the other plate of the bridging capacitor, forming the output terminal of the low-order segment capacitor array. The calibration method includes the following steps:

[0011] S1, use the low-level segment capacitor array to measure the weight of each capacitor in the high-level segment capacitor array;

[0012] S2, use the high-order segment capacitor array to measure the weight of each capacitor in the low-order segment capacitor array;

[0013] S3, repeat S1 and S2 several times to obtain the weight matrix of the entire digital-to-analog converter;

[0014] S4, normalize the weight matrix of the entire digital-to-analog converter to a weight matrix of the target resolution bit depth.

[0015] Therefore, the successive approximation analog-to-digital converter of this invention can mutually calibrate the weight of each capacitor using the low-order and high-order capacitor arrays in the digital-to-analog converter (DAC), eliminating the need for an additional calibration DAC and simplifying the circuit. Furthermore, performing the calibration method of this invention before the SAR ADC operates normally makes the original SAR ADC design more flexible, allowing for greater flexibility in the selection of the bridge capacitor value and the segmented capacitor array design of the DAC. Specifically, the value of the bridge capacitor (C) can be determined based on the DAC mismatch range, the accuracy of the weight calibration, and the target resolution bit depth. b The ADC uses two parameters: the bit depth (k) of the high-order capacitor array (MDAC) and the bit depth (m) of the low-order capacitor array (LDAC). The total weight of the low-order LDAC does not need to be scaled in binary. During ADC conversion, a portion of the high-order MDAC and low-order LDAC can be selected for sampling and conversion, as long as the total weight of the selected low-order LDAC is not less than the weight of the least significant bit of the selected high-order MDAC, and the overall ADC resolution meets the design target resolution.

[0016] Optionally, in step S1, the process of measuring the weight of the least significant capacitor in the high-order segment capacitor array using the low-order segment capacitor array includes:

[0017] S11, connect the output terminal of the high-order segment capacitor array to the common-mode level, connect the second plate of the lowest-order capacitor of the high-order segment capacitor array to the first reference voltage, and connect the second plates of the remaining capacitors of the high-order segment capacitor array and the second plates of each capacitor in the low-order segment capacitor array to the second reference voltage.

[0018] S12, disconnect the common-mode level from the output terminal of the high-level capacitor array, and reconnect the second plate of the lowest capacitor of the high-level capacitor array to the second reference voltage;

[0019] S13, the successive approximation analog-to-digital converter performs a successive approximation conversion to obtain a first conversion result;

[0020] S14. Based on the weights of each capacitor in the low-order segment capacitor array and the first conversion result, the weight of the least significant capacitor in the high-order segment capacitor array is obtained.

[0021] Therefore, through simple circuit operation, the least significant bit capacitor weight of the high-order segment capacitor array in the digital-to-analog converter (DAC) can be measured using the low-order segment capacitor array in the DAC.

[0022] Optionally, in step S1, before executing step S14, steps S11 to S13 are executed multiple times to obtain the corresponding average value as the first conversion result. This improves the accuracy of the least significant capacitor weight of the high-segment capacitor array.

[0023] Optionally, in step S1, the remaining capacitors in the high-order segment capacitor array are used as the first capacitor to be measured, and the process of measuring the weight of the first capacitor to be measured using the low-order segment capacitor array includes:

[0024] S15, connect the output terminal of the high-level capacitor array to the common-mode level, connect the second plate of the first capacitor under test and the second plate of the highest capacitor in the low-level capacitor array to the first reference voltage, and connect the second plates of the remaining capacitors in the high-level capacitor array and the second plates of the remaining capacitors in the low-level capacitor array to the second reference voltage.

[0025] S16, disconnect the common-mode level from the output terminal of the high-order segment capacitor array, and reconnect the second plate of the first capacitor under test to the second reference voltage. At the same time, reconnect the second plates of all capacitors in the high-order segment capacitor array that are lower than the first capacitor under test to the first reference voltage.

[0026] S17, the successive approximation analog-to-digital converter performs a successive approximation conversion to obtain a second conversion result;

[0027] S18, based on the weights of each capacitor in the low-order segment capacitor array and the second conversion result, the weight of the first capacitor to be tested is obtained.

[0028] Therefore, through simple circuit operation, the capacitance of each bit in the high-bit segment of the digital-to-analog converter (DAC) can be measured using the low-bit segment capacitor array. This measurement is possible for all bits except the least significant bit in the high-bit segment capacitor array of the DAC.

[0029] Optionally, in step S1, before executing step S18, steps S15 to S17 are executed multiple times to obtain the corresponding average value as the second conversion result. This improves the measurement accuracy of the capacitor weights of all other capacitors besides the lowest-order capacitor in the high-segment capacitor array.

[0030] Optionally, the low-level segment capacitor array has m-position capacitors CL0 to CL0. m-1 The weight of each capacitor in the low-order segment capacitor array is Weight_L = [Weight_L(m-1),…,Weight_L(0)], and the high-order segment capacitor array has k capacitors CM0~CM0. k-1 ;and,

[0031] The weight of the lowest - order capacitor CM0 in the high - order capacitor array is:

[0032] Weight_M(0) = RES0_1 * Weight_L;

[0033] The first capacitor under test CM i has a weight of:

[0034] , RES1 = RES0_2 * Weight_L - Weight_L(m - 1);

[0035] Furthermore, the weights of the capacitors in each position of the high - order capacitor array Weight_M = [Weight_M(k - 1), …, Weight_M(0)];

[0036] where RES0_1 is the first conversion result, RES0_2 is the second conversion result, both i and j are integers, 0 < i ≤ k - 1, 0 ≤ j ≤ i - 1, and / or

[0037] where the initial value of the weights Weight_L of the capacitors in each position of the low - order capacitor array is [2 m-1 , 2 m-2 , …, 2, 1].

[0038] Optionally, in step S2, the process of measuring the weight of the lowest - order capacitor in the low - order capacitor array using the high - order capacitor array includes:

[0039] S21, connect the output terminal of the low - order capacitor array to the common - mode level, connect the second plate of the lowest - order capacitor of the low - order capacitor array to the first reference voltage, and at the same time connect the second plates of the remaining capacitors of the low - order capacitor array and the second plates of the capacitors in each position of the high - order capacitor array to the second reference voltage;

[0040] S22, disconnect the connection between the common - mode level and the output terminal of the low - order capacitor array, and change the connection of the second plate of the lowest - order capacitor of the low - order capacitor array to the second reference voltage;

[0041] S23, the successive - approximation analog - to - digital converter performs successive - approximation conversion to obtain a third conversion result;

[0042] S24, obtain the weight of the lowest - order capacitor of the low - order capacitor array according to the weights of the capacitors in each position of the high - order capacitor array and the third conversion result.

[0043] Therefore, through simple circuit operation, the weight of the least significant capacitor in ...

[0044] Optionally, in step S2, before executing step S24, steps S21 to S23 are executed multiple times to obtain the corresponding average value as the third conversion result. This improves the measurement accuracy of the weight of the least significant capacitor in the low-order segment capacitor array.

[0045] Optionally, in step S2, the remaining capacitors in the lower segment capacitor array are used as the second capacitor to be measured, and the process of measuring the weight of the second capacitor to be measured using the higher segment capacitor array includes:

[0046] S25, connect the output terminal of the low-level capacitor array to the common-mode level, connect the second plate of the second capacitor under test and the second plate of the highest capacitor in the high-level capacitor array to the first reference voltage, and connect the second plates of the remaining capacitors in the high-level capacitor array and the second plates of the remaining capacitors in the low-level capacitor array to the second reference voltage.

[0047] S26, disconnect the common-mode level from the output terminal of the low-order segment capacitor array, and reconnect the second plate of the second capacitor under test to the second reference voltage. At the same time, reconnect the second plates of all capacitors in the low-order segment capacitor array that are lower than the second capacitor under test to the first reference voltage.

[0048] S27, the successive approximation analog-to-digital converter performs a successive approximation conversion to obtain a fourth conversion result;

[0049] S28. Based on the weights of each capacitor in the high-order segment capacitor array and the fourth conversion result, the weight of the second capacitor to be tested is obtained.

[0050] Therefore, through simple circuit operation, the weights of all capacitors except the least significant capacitor in ...

[0051] Optionally, in step S2, before executing step S28, steps S25 to S27 are executed multiple times to obtain the corresponding average value as the fourth conversion result. This improves the measurement accuracy of the weights of all capacitors except the least significant capacitor in the low-order segment capacitor array.

[0052] Optionally, the low-level segment capacitor array has m-position capacitors CL0 to CL0. m-1 The high-level capacitor array has k capacitors CM0 to CM0.k-1 And the weight of each capacitor in the high-order segment capacitor array is Weight_M=[Weight_M(k-1),…,Weight_M(0)];

[0053] The weight of the lowest-order capacitor CL0 in the low-order segment capacitor array is:

[0054] Weight_L(0)=RES0_3*Weight_M;

[0055] The second capacitor under test, CL i The weights are:

[0056] , RES2=RES0_4*Weight_M-Weight_M(k-1);

[0057] Furthermore, the weight of each capacitor in the low-order segment capacitor array is Weight_L=[Weight_L(m-1),…,Weight_L(0)]. / Weight_L(0);

[0058] Wherein, RES0_3 is the third transformation result, RES0_4 is the fourth transformation result, i and j are both integers, 0 <i≤m-1,0≤j≤i-1。

[0059] Optionally, the m-position capacitors CL0 to CL m-1 and k-position capacitor CM0~CM k-1 All are binary-weighted capacitor arrays, and the segmented capacitor array also includes terminal capacitors; in step S3, the weight matrix DAC_Weight_raw = [MDAC_Weight, LDAC_Weight] of the entire digital-to-analog converter is obtained, and the weight matrix for the target resolution bit depth N obtained in step S4 is:

[0060]

[0061] Wherein, ∑MDAC_Weight is the sum of the weights of each capacitor in the high-order segment capacitor array, and / or, Weight_M_(T) is the weight of the terminal capacitor, and the weight of the terminal capacitor is measured using the low-order segment capacitor array.

[0062] Based on the same inventive concept, the present invention also provides a successive approximation analog-to-digital converter (SAR ADC), comprising:

[0063] A digital-to-analog converter includes a bridging capacitor, a low-order segment capacitor array, and a high-order segment capacitor array. The first plate of each capacitor in the high-order segment capacitor array is coupled to one plate of the bridging capacitor to form the output terminal of the high-order segment capacitor array. The first plate of each capacitor in the low-order segment capacitor array is coupled to the other plate of the bridging capacitor to form the output terminal of the low-order segment capacitor array.

[0064] The comparison module has a first input terminal coupled to the output terminal of the low-order segment capacitor array and the output terminal of the high-order segment capacitor array, and a second input terminal coupled to the common-mode level, used to compare the output of the high-order segment capacitor array or the output of the low-order segment capacitor array with the corresponding common-mode level;

[0065] The SAR logic and digital calibration module has its input terminal coupled to the output terminal of the comparison module, and is used to perform successive approximation conversion based on the output of the comparison module, so as to realize the calibration method of the successive approximation analog-to-digital converter as described in this invention.

[0066] Optionally, the second plate of each capacitor in the digital-to-analog converter is coupled to a corresponding switch. The SAR logic and digital calibration module is also used to control the toggle direction of the switch connected to the second plate of each capacitor in the digital-to-analog converter, so as to connect the second plate of the corresponding capacitor to at least one of the first reference voltage, the second reference voltage and the input voltage.

[0067] Optionally, the comparison module includes:

[0068] A first switch and a first comparator, one end of the first switch is coupled to a common-mode level, the other end of the first switch is coupled to a first input terminal of the first comparator and the output terminal of the high-order segment capacitor array, and a second input terminal of the first comparator is coupled to the common-mode level;

[0069] A second switch and a second comparator, one end of the second switch is coupled to the common-mode level, and the other end of the second switch is coupled to the first input terminal of the second comparator and the output terminal of the low-order segment capacitor array, and the second input terminal of the second comparator is coupled to the common-mode level;

[0070] A gating device, wherein the first input terminal of the gating device is coupled to the output terminal of the first comparator, the second input terminal of the gating device is coupled to the output terminal of the second comparator, and the output terminal of the gating device is coupled to the input terminal of the SAR logic and digital calibration module;

[0071] Specifically, when measuring the weight of each capacitor in the high-order segment capacitor array using the low-order segment capacitor array, the selector provides the comparison result of the first comparator to the SAR logic and digital calibration module; when measuring the weight of each capacitor in the low-order segment capacitor array using the high-order segment capacitor array, the selector provides the comparison result of the second comparator to the SAR logic and digital calibration module.

[0072] Optionally, the comparison module includes:

[0073] A third comparator, the second input of which is coupled to the common-mode level, and the output of which is coupled to the input of the SAR logic and digital calibration module;

[0074] The third switch has one end coupled to the common-mode level and the other end selectively connected to either the output terminal of the high-order segment capacitor array or the output terminal of the low-order segment capacitor array.

[0075] A fourth switch, one end of which is coupled to the first input terminal of the third comparator, and the other end of which is selectively coupled to the output terminal of the low-order segment capacitor array or the output terminal of the high-order segment capacitor array. Attached Figure Description

[0076] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:

[0077] Figure 1 This is a schematic diagram of the circuit structure of an existing successive approximation analog-to-digital converter.

[0078] Figure 2 This is a schematic diagram of an example circuit structure of a successive approximation analog-to-digital converter according to an embodiment of the present invention.

[0079] Figure 3 This is a schematic flowchart of a calibration method for a successive approximation analog-to-digital converter according to an embodiment of the present invention.

[0080] Figure 4 This is a schematic diagram of the process for calibrating the CMO weights in the CMT and MDAC in a calibration method for a successive approximation analog-to-digital converter according to an embodiment of the present invention.

[0081] Figure 5 This is a schematic diagram of the process for calibrating the remaining bit capacitor weights in the MDAC in a calibration method for a successive approximation analog-to-digital converter according to an embodiment of the present invention.

[0082] Figure 6This is a schematic diagram of the process for calibrating the CL0 weight in the LDAC in a calibration method for a successive approximation analog-to-digital converter according to an embodiment of the present invention.

[0083] Figure 7 This is a schematic diagram of the process for calibrating the weights of the remaining bits of the LDAC in the calibration method of a successive approximation analog-to-digital converter according to an embodiment of the present invention.

[0084] Figure 8 This is a schematic diagram of another example circuit structure of a successive approximation analog-to-digital converter according to an embodiment of the present invention. Detailed Implementation

[0085] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid confusion with the invention. It should be understood that the invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, the provision of these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The same reference numerals denote the same elements throughout. It should be understood that when an element is referred to as "connected to" or "coupled to" other elements, it may be directly connected to other elements, or there may be intervening elements. Conversely, when an element is referred to as "directly connected to" other elements, there are no intervening elements. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. When used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0086] Please refer to Figure 2 An embodiment of the present invention provides a successive approximation analog-to-digital converter (SAR ADC), which includes a digital-to-analog converter (DAC), a comparison module 21, and a SAR & Calibration Logic module 20.

[0087] The digital-to-analog converter (DAC) employs a segmented design, which includes a bridging capacitor C. b The system consists of a low-bit capacitor array (LDAC) (which can be called a "low-bit sub-DAC") and a high-bit capacitor array (MDAC) (which can be called a "high-bit sub-DAC"). The high-bit capacitor array (MDAC) has k-bit binary weighted capacitors CM0 to CM0.k-1 The low-order segment capacitor array (LDAC) has m-bit binary-weighted capacitors CL0 to CL1. m-1 CM0 is the lowest-order capacitor of the high-order segment capacitor array MDAC, and its capacitance is 1CM. u CM u CM is the unit capacitance of the high-order segment capacitor array MDAC. k-1 The highest-order capacitor in the high-order segment capacitor array MDAC has a capacitance of 2. k- 1 CM u CL0 is the lowest-order capacitor of the low-order segment capacitor array (LDAC), and its capacitance is 1CL. u CL m-1 The highest-order capacitor in the low-order segment capacitor array (LDAC) has a capacitance of 2. m-1 CL u CL u This is the unit capacitance of the low-order segment capacitor array (LDAC). In one example, CM u =CL u =C u In the following text, C b The other end (or the other electrode), CM0~CM k-1 and CL0~CL m-1 The first electrode plate is taken as the upper electrode plate, C b The other end (or one of the plates), CM0~CM k-1 and CL0~CL m-1 The second electrode plate is described using the lower electrode plate as an example. In other embodiments of the present invention, C b CM0~CM k-1 and CL0~CL m-1 The first electrode can also be the lower electrode, C b CM0~CM k-1 and CL0~CL m-1 The second electrode is the upper electrode.

[0088] Furthermore, the bridging capacitor C can be determined based on the capacitor mismatch range of the digital-to-analog converter (DAC), the weight calibration accuracy, and the target resolution bit depth N of the SAR ADC design (where N is at most m+k). b The capacitance value, the number of bits k of the high-order segment capacitor array MDAC, and the number of bits m of the low-order segment capacitor array LDAC. In this invention, the bridging capacitor C bThe parasitic capacitance of the upper and lower plates is added to the total capacitance of the low-side capacitor array (LDAC) and the high-side capacitor array (MDAC), affecting their weights. After calibration using this invention, the true weight conversion of the LDAC and MDAC can be obtained, thereby eliminating the bridging capacitance C. b Parasitic effects, avoid bridging capacitor C b It affects the performance of the SAR ADC, causing the bridging capacitor C to... b It only affects the resolution of the SAR ADC, therefore the bridging capacitor C can be included when designing the resolution of the SAR ADC. b Parasitism on the upper and lower plates should be taken into account.

[0089] In the high-order segment capacitor array MDAC, each capacitor CM0~CM k-1 The upper plates are all coupled with bridging capacitors C b One end (or "one plate", such as the lower plate of Cb) forms the output terminal of the high-order segment capacitor array MDAC (which is also the output terminal of the digital-to-analog converter), with each capacitor CM0 to CM0 being a specific value. k-1 The lower electrode plate and the switch QM0~QM k-1 One end is coupled in a one-to-one correspondence, switches QM0~QM k-1 The other end changes its toggle direction under the control of the digital value (or "digital code") output by the SAR logic and digital calibration module 20. As an example, switches QM0 to QM... k-1 All are three-state switches. Under the control of the SAR logic and digital calibration module 20, switches QM0 to QM... k-1 The other end is coupled to one of a first reference voltage VREFH, a second reference voltage VREFL, and an analog input voltage VIN. The first reference voltage VREFH and the second reference voltage VREFL can be the positive and negative terminals of a single reference voltage VREF.

[0090] In the low-order segment capacitor array LDAC, each capacitor CL0~CL m-1 The upper plate is coupled to the bridge capacitor C. b The other end (or "the other plate," which is, for example, the upper plate of Cb) forms the output terminal of the low-order segment capacitor array LDAC. The capacitors CL0 to CL... m-1 The lower electrode plate and the switch QL0~QL m-1 One end is coupled in a one-to-one correspondence, switches QL0~QL m-1 The other end changes its toggle direction under the control of the digital value (or "digital code") output by the SAR logic and digital calibration module 20. As an example, switches QL0 to QL... m-1All are two-state switches. Under the control of the SAR logic and digital calibration module 20, switches QL0 to QL... m-1 The other end is coupled to one of the first reference voltage VREFH and the second reference voltage VREFL.

[0091] Optionally, the digital-to-analog converter (DAC) in this embodiment further includes a terminal capacitor (CM). T Its first electrode plate (e.g., the upper electrode plate) is coupled to the output terminal of the digital-to-analog converter (DAC) (i.e., CM0 to CM0). k-1 The upper plate and one end of the bridging capacitor), and its second plate (e.g., the lower plate) are coupled to the corresponding switch QM. T One end, switch QM T The other end changes its toggle direction under the control of the digital value (or "digital code") output by the SAR logic and digital calibration module 20. As an example, the switch QM... T As a three-state switch, under the control of the SAR logic and digital calibration module 20, switch QM T The other end is coupled to one of the first reference voltage VREFH, the second reference voltage VREFL, and the analog input voltage VIN. In one example, CM T =CM0=CMu.

[0092] The first input terminal of the comparator module 21 (e.g., the positive input terminal "+") is coupled to the output terminal of the low-order capacitor array LDAC and the output terminal of the high-order capacitor array MDAC, and the second input terminal of the comparator module 21 (e.g., the negative input terminal "-") is coupled to the common-mode level VCM. The comparator module 21 is used to compare the output of the high-order capacitor array MDAC or the output of the low-order capacitor array LDAC with the common-mode level VCM.

[0093] The SAR logic and digital calibration module 20 performs successive approximation conversion based on the output of the comparison module 21, and then outputs the corresponding digital value (or "digital code") to control the capacitors CL0 to CL1 in the digital-to-analog converter (DAC). m-1 CM T CM0~CM k-1 The switches QL0 to QL connected to the lower electrode plate m-1 QM T and QM0~QM k-1 The direction of the toggle is adjusted to connect the lower plate of the corresponding capacitor to at least one of the first reference voltage VREFH, the second reference voltage VREFL, and the analog input voltage VIN.

[0094] It should be understood that the comparison module 21 and the SAR logic and digital calibration module 20 can be designed in any suitable manner.

[0095] As an example, please refer to Figure 2 The comparison module 21 includes a first switch S1, a second switch S2, a first comparator COMP1, a second comparator COMP2, and a selector MUX. One end of the first switch S1 is coupled to the common-mode level VCM, and the other end of the first switch S1 is coupled to the first input terminal (e.g., the positive input terminal "+") of the first comparator COMP1 and the output terminal (i.e., CM0~CM1) of the high-order segment capacitor array MDAC. k-1 The upper plate of the first comparator COMP1 is coupled to the common-mode level VCM at its second input (e.g., the negative input "-"). One end of the second switch S2 is coupled to the common-mode level VCM, and the other end of the second switch S2 is coupled to the first input (e.g., the positive input "+") of the second comparator COMP2 and the output of the low-order capacitor array LDAC (i.e., capacitors CL0 to CL1). m-1 The upper plate of the second comparator COMP2, and the second input terminal (e.g., the negative input terminal "-") is coupled to the common-mode level VCM.

[0096] The first input terminal of the selector MUX (e.g., the "1" terminal) is coupled to the output terminal of the first comparator COMP1, and the second input terminal of the selector MUX (e.g., the "0" terminal) is coupled to the output terminal of the second comparator COMP2. The output terminal of the selector MUX (i.e., the output terminal of the comparison module 21) is coupled to the input terminal of the SAR logic and digital calibration module 20. The selector MUX selects whether to send the comparison result of the first comparator COMP1 or the second comparator COMP2 to the SAR logic and digital calibration module 20. The SAR logic and digital calibration module 20 performs successive approximation conversion based on the output result of the selector MUX.

[0097] In this embodiment of the successive approximation analog-to-digital converter (SAR ADC), the capacitance values ​​of each capacitor in the low-order segment capacitor array (LDAC) and the capacitance values ​​of each capacitor in the high-order segment capacitor array (MDAC) are ideally binary weighted. However, due to the bridging capacitor C... b Due to factors such as parasitic capacitance and bias, as well as capacitance mismatch between MDAC and LDAC, the weights of each capacitor will shift. This invention calibrates the weights of each capacitor in the low-order segment capacitor array LDAC and the weights of each capacitor in the high-order segment capacitor array MDAC, and then stores the calibrated weight matrix in the corresponding register. Thus, when the SAR ADC is working normally, the SAR logic and digital calibration module 20 uses the weight values ​​stored in the register.

[0098] Based on this, please combine Figure 2 and Figure 3This embodiment also provides a calibration method for a successive approximation analog-to-digital converter (SAR ADC), which is used to calibrate the weights of each capacitor in the successive approximation analog-to-digital converter before the SAR ADC is working normally. The calibration method includes the following steps:

[0099] S1, use the low-order segment capacitor array LDAC to measure the weight of each capacitor in the high-order segment capacitor array MDAC;

[0100] S2, use the high-order segment capacitor array MDAC to measure the weight of each capacitor in the low-order segment capacitor array LDAC;

[0101] S3, repeat S1 and S2 several times to obtain the weight matrix of the entire digital-to-analog converter (DAC);

[0102] S4 normalizes the weight matrix of the entire digital-to-analog converter (DAC) to a weight matrix with the target resolution bit depth.

[0103] In this embodiment, the initial value of the LDAC weight Weight_L = [Weight_L(m-1),…,Weight_L(0)] (i.e., the ideal value of the initial LDAC weight during design) is set to [2]. m-1 ,2 m-2 […,2,1] Therefore, in the calibration method of the successive approximation analog-to-digital converter (SAR ADC) in this embodiment, when the weight of each capacitor in the MDAC is measured (or calibrated) using the LDAC in step S1 for the first time (i.e., the first calibration), this initial value is used. When step S1 is executed for the second time, the Weight_L used is the weight value obtained after the first calibration in step S4. This process is iterated, meaning that the Weight_L used in step S1 in the next iteration is the weight value obtained in step S4 of the previous iteration. Similarly, when the weight of each capacitor in the LDAC in the lower segment capacitor array is measured using the higher segment capacitor array MDAC, the process is also iterated, meaning that the weight_M of the higher segment capacitor array MDAC used in step S2 in the next iteration is the weight value obtained in step S4 of the previous iteration.

[0104] In this embodiment, in step S1, the selector MUX selects its first input terminal "1" to receive the signal, so that the low-order segment capacitor array LDAC, the first comparator COMP1 and the loop of SAR logic and digital calibration module 20 form analog-to-digital converter ADC1.

[0105] As an example, in step S1, the terminal capacitance CM can be measured first using a low-order segment capacitor array (LDAC). TThe weight of the lowest-value capacitor CM0 in the high-level capacitor array MDAC is determined, and then the remaining capacitors CM1 to CM in the high-level capacitor array MDAC are measured. k-1 The weight.

[0106] Please refer to the following: Figure 4 In step S1, the low-order segment capacitor array LDAC is used to measure the terminal capacitance CM. T The steps for determining the weight of the least significant capacitor CM0 in the high-order capacitor array MDAC include:

[0107] S11, the first switch S1 is closed, thereby connecting the output terminal of the high-order segment capacitor array MDAC and the first input terminal "+" of the first comparator COMP1 to the common-mode level VCM, connecting the lower plate of the lowest-order capacitor CM0 in the high-order segment capacitor array MDAC to the first reference voltage VREFH, and simultaneously connecting the terminal capacitor CM... T The lower plate, the high-order segment capacitor array MDAC, and the remaining capacitors CM 1～ CM k-1 In the lower plate and low-side capacitor array LDAC, each capacitor CL0~CL m-1 The lower plates are all connected to the second reference voltage VREFL;

[0108] S12, the first switch S1 is opened, thereby disconnecting the common mode level VCM from the output terminal of the high-level capacitor array MDAC and the first input terminal "+" of the first comparator COMP1, and reconnecting the lower plate of the lowest capacitor CM0 in the high-level capacitor array MDAC to the second reference voltage VREFL.

[0109] S13, the analog-to-digital converter ADC1 performs successive approximation conversion to obtain the first conversion result RES0_1;

[0110] S14, the digital circuit in the SAR logic and digital calibration module 20 determines the capacitance CL0~CL0 of each bit in the low-order segment capacitor array LDAC based on the following: m-1 The weights Weight_L = [Weight_L(m-1),…,Weight_L(0)] and the first conversion result RES0_1 are used to obtain the weights Weight_M(0) = RES0_1*Weight_L of the lowest bit capacitor CM0 in the MDAC. Here, RES0_1*Weight_L is a matrix product, that is, the weight value of each bit is determined by whether each bit of RES0_1 is 1 or 0.

[0111] Optionally, in step S1, before executing step S14, steps S11 to S13 are executed multiple times to obtain the corresponding average value as the first conversion result RES0_1, thereby improving the measurement accuracy of the weight of CM0.

[0112] In this example, in step S1, the same method as the weight measurement principle of CM0 (i.e., steps S11 to S14 above) can be used to measure the terminal capacitance CM using the low-order segment capacitor array LDAC. T The weighting is as follows: first close the first switch S1, and then open the terminal capacitor CM. T The lower plate is connected to the first reference voltage VREFH, and simultaneously the capacitors CM in the high-order segment capacitor array MDAC are connected. 0～ CM k-1 In the lower plate and low-side capacitor array LDAC, each capacitor CL0~CL m-1 The lower plates are all connected to the second reference voltage VREFL (similar to step S11); then the first switch S1 is opened, and the terminal capacitor CM is connected. T The lower plate is reconnected to the second reference voltage VREFL (corresponding to step S12); the analog-to-digital converter ADC1 performs successive approximation conversion to obtain the corresponding first conversion result RES0_1' (corresponding to step S13); then, the digital circuit in the SAR logic and digital calibration module 20 calculates the voltage based on the capacitances CL0 to CL0 in the LDAC. m-1 The weights Weight_L = [Weight_L(m-1),…,Weight_L(0)] and the transformation result RES0_1' are used to obtain the terminal capacitance CM. T The weight is Weight_M(T) = RES0_1'*Weight_L, where RES0_1'*Weight_L is a matrix product, that is, the weight value of each bit is determined by whether each bit of RES0_1' is 1 or 0.

[0113] Please refer to Figure 5 In step S1, CM1 to CM2 are measured. k-1 When assigning weights, the corresponding bit capacitance currently being measured is taken as the first capacitance to be measured, CM. i Since 1≤i≤k-1, the capacitances CM1~CM in the remaining bits of the high-order segment capacitor array MDAC are measured using the low-order segment capacitor array LDAC. k-1 The weighting process includes:

[0114] S15, the first switch S1 is closed, thereby connecting the output terminal of the high-order segment capacitor array MDAC and the first input terminal "+" of the first comparator COMP1 to the common-mode level VCM, and connecting the first capacitor under test CM... i The lower plate and the highest-order capacitor CL in the low-order segment capacitor array LDAC m-1 The lower plates are all connected to the first reference voltage VREFH, and the terminal capacitor CM is also connected. T The lower electrode plate, the remaining capacitors of the high-position capacitor array CM0~CM i-1 and CM i+1~CM k-1 The lower plate and the remaining capacitors CL0 to CL in the low-position capacitor array m-2 The lower plates are all connected to the second reference voltage VREFL;

[0115] S16, the first switch S1 is opened, thereby disconnecting the common-mode level VCM from the output terminal of the high-order segment capacitor array MDAC and the first input terminal "+" of the first comparator COMP1, and disconnecting the first capacitor under test CM. i The lower plate is reconnected to the second reference voltage VREFL, and the capacitor array MDAC in the high-order segment is compared with the first capacitor under test CM. i Low-order capacitors CM0~CM i-1 The lower plates are all reconnected to the first reference voltage VREFH;

[0116] S17, analog-to-digital converter ADC1 performs successive approximation conversion to obtain the second conversion result RES0_2;

[0117] S18, the digital circuit in the SAR logic and digital calibration module 20 determines the capacitance CL0~CL0 in the low-order segment capacitor array LDAC based on the capacitance CL0~CL0 of each bit. m-1 The weights Weight_L = [Weight_L(m-1),…,Weight_L(0)] and the second transformation result RES0_2 are used to obtain the first capacitor under test CM. i The weights. And the first capacitor to be tested, CM. i The weights are:

[0118]

[0119] RES1=RES0_2*Weight_L-Weight_L(m-1);

[0120] Where i and j are both integers, 0 <i≤k-1,0≤j≤i-1。

[0121] Optionally, in the above-described measurement of the first capacitor under test CM i During the weighting process, before executing step S18, steps S15 to S17 are executed multiple times to obtain the corresponding average value as the second transformation result RES0_2, in order to improve CM1 to CM k-1 The accuracy of the measurement of the weights of each capacitor.

[0122] Therefore, in step S1, the terminal capacitance CM is measured through the above steps S11 to S18. T The weights and the capacitances CM0 to CM in the high-order segment capacitor array MDAC k-1The weights of each capacitor in the high-order segment capacitor array MDAC are MDAC_Weight=Weight_M=[Weight_M(k-1),…,Weight_M(0)];

[0123] In this embodiment, in step S2, the selector MUX selects its second input terminal "0" to receive the signal, so that the loop of the high-bit segment capacitor array MDAC, the second comparator COMP2 and the SAR logic and digital calibration module 20 forms the analog-to-digital converter ADC2.

[0124] As an example, in step S2, the weight of the least significant capacitor CL0 in the least significant capacitor array LDAC can be measured first using the high-order capacitor array MDAC, and then the remaining capacitors CL1 to CL2 in the least significant capacitor array LDAC can be measured using the high-order capacitor array MDAC. m-1 The weight.

[0125] Please refer to the following: Figure 6 In step S2, the step of measuring the weight of the least significant capacitor CL0 in the least significant capacitor array LDAC using the high-order segment capacitor array MDAC includes:

[0126] S21, the second switch S2 is closed, thereby connecting the output terminal of the low-order segment capacitor array LDAC to the common-mode level VCM, connecting the lower plate of the least significant capacitor CL0 of the low-order segment capacitor array LDAC to the first reference voltage VREFH, and simultaneously connecting the terminal capacitor CM... T In the lower plate and high-level capacitor array of the MDAC, each capacitor CM0~CM k-1 The lower plate and the remaining capacitors CL1 to CL in the low-order segment capacitor array LDAC m-1 The lower plates are all connected to the second reference voltage VREFL;

[0127] S22, the second switch S2 is opened, thereby disconnecting the common mode level VCM from the output terminal of the low-order segment capacitor array LDAC, and reconnecting the lower plate of the lowest capacitor CL0 of the low-order segment capacitor array LDAC to the second reference voltage VREFL.

[0128] S23, the analog-to-digital converter ADC2 performs successive approximation conversion to obtain the third conversion result RES0_3;

[0129] S24, based on the capacitors CM0~CM of each bit in the high-order segment capacitor array MDAC. k-1The weights Weight_M = [Weight_M(k-1),…,Weight_M(0)] (the weights are the weights after calibration by step S1 above) and the third transformation result RES0_3 are used to obtain the weights Weight_L(0) = RES0_3*Weight_M of the lowest bit capacitor CL0 of the low-bit segment capacitor array LDAC. Here, RES0_3*Weight_M is a matrix product, that is, the weight value of each bit is determined by whether each bit of RES0_3 is 1 or 0.

[0130] Optionally, in step S2, before executing step S24, steps S21 to S23 are executed multiple times to obtain the corresponding average value as the third transformation result RES0_3, thereby improving the measurement accuracy of the weight of CL0.

[0131] Please refer to Figure 7 In step S2, during the measurement of CL1 to CL m-1 When assigning weights, the corresponding bit capacitance currently being measured is used as the second capacitance to be measured, CL. i Since 1 ≤ i ≤ m-1, the capacitances of the remaining bits CL1 to CL2 are measured using the high-order segment capacitor array MDAC. m-1 The steps for weighting include:

[0132] S25, the second switch S2 is closed, thereby connecting the output terminal of the low-order segment capacitor array LDAC and the first input terminal "+" of the second comparator COMP2 to the common-mode level VCM, and connecting the second capacitor under test CL... i The lower plate and the highest-order capacitor CM in the high-order segment capacitor array of the MDAC k-1 The lower plates are all connected to the first reference voltage VREFH, and the terminal capacitor CM is also connected. T The lower plate, the high-order segment capacitor array, and the remaining capacitors CM0 to CM of the MDAC k-2 The lower plate and the remaining capacitors CL0 to CL in the low-order segment capacitor array LDAC i-1 and CL i+1 ~CL m-1 The lower plates are all connected to the second reference voltage VREFL;

[0133] S26, the second switch S2 is opened, thereby disconnecting the common-mode level VCM from the output terminal of the low-order segment capacitor array LDAC and the first input terminal "+" of the second comparator COMP2, and connecting the second capacitor under test CL. i The lower plate is reconnected to the second reference voltage VREFL, and the capacitor CL in the low-order segment capacitor array LDAC is compared with the second capacitor under test. i Low-order capacitors CL0~CL i-1 The lower plates are all reconnected to the first reference voltage VREFH;

[0134] S27, the analog-to-digital converter ADC2 performs successive approximation conversion to obtain the fourth conversion result RES0_4;

[0135] S28, the digital circuit in the SAR logic and digital calibration module 20 obtains the second capacitor under test CL based on the weights of each capacitor in the high-order segment capacitor array MDAC and the fourth conversion result RES0_4. i The weight of the second capacitor to be tested, CL. i The weights are:

[0136]

[0137] RES2=RES0_4*Weight_M-Weight_M(k-1);

[0138] Where i and j are both integers, 0 <i≤k-1,0≤j≤i-1。

[0139] Optionally, in step S2, before executing step S28, steps S25 to S27 are executed multiple times to obtain the corresponding average value as the fourth conversion result, so as to improve CL1 to CL. m-1 The accuracy of weight measurement.

[0140] Therefore, in step S2, the capacitances CL0 to CL0 in the low-order segment capacitor array LDAC are measured through the above steps S21 to S28. m-1 The weights are then used to obtain the weight matrix of the low-order segment capacitor array LDAC: Weight_L = [Weight_L(m-1),…,Weight_L(0)]. Then, the weights of each capacitor in the LDAC are divided by the weight of CL0, Weight_L(0), to obtain the normalized weight matrix LDAC_Weight = Weight_L. / Weight_L(0) = [Weight_L(m-1),…,Weight_L(0)]. / Weight_L(0). Here, ". / " is the dot division operator for matrices.

[0141] In step S3, steps S1 and S2 are iterated and executed several times to obtain more accurate weights MDAC_Weight and LDAC_Weight, and then the weight matrix DAC_Weight_raw = [MDAC_Weight, LDAC_Weight] of the entire DAC is obtained, where MDAC_Weight is the weight matrix of the high-order segment capacitor array MDAC, and LDAC_Weight is the weight matrix of the low-order segment capacitor array LDAC.

[0142] In step S4, the weight matrix DAC_Weight_raw of the entire digital-to-analog converter (DAC) is normalized to a weight matrix of the target resolution bit depth N:

[0143]

[0144] Where N is at most m+k, and ∑MDAC_Weight is the sum of the weights of each capacitor in the high-order segment capacitor array. ".*" is the matrix multiplication operator. Weight_M_(T) is the terminal capacitance CM. T The weights are measured using the low-level segment capacitor array through the methods described in steps S11 to S14.

[0145] Optionally, the weight matrix DAC_Weight_normal obtained in step S4 for the target resolution bit depth N can be used as the digital value CAL DAC and stored in the corresponding register of the SAR logic and digital calibration module 20. When the SAR ADC is working normally, the digital-to-analog converter DAC can be weighted by the digital value CAL DAC stored in the register: that is, the weight value of the bit is determined according to the comparator result corresponding to each bit capacitor. If the weight value of the bit is 1, the weight value corresponding to the bit is accumulated to obtain the final digital value result converted by the SAR ADC.

[0146] It is worth noting that during normal operation of the SAR ADC, a portion of the high-order capacitor array MDAC and a portion of the low-order capacitor array LDAC can be selected for sampling and conversion, as long as the total weight of the selected low-order capacitor array LDAC portion is not less than the weight of the least significant capacitor in the selected high-order capacitor array MDAC portion, and the overall resolution of the SAR ADC meets the design target resolution. Furthermore, the number of capacitor bits used during calibration of the SAR ADC can be more than the number of capacitor bits used during normal operation.

[0147] It should also be understood that, Figure 2 In the circuit structure shown, only the first comparator COMP1 needs to be used when the SAR ADC is working normally. Therefore, the accuracy of the second comparator COMP2 does not need to be too high, as long as it meets the calibration requirements.

[0148] Furthermore, as mentioned above, the comparison module 21 can also employ any other suitable circuit design. For example, please refer to... Figure 8In another example of this embodiment, the comparison module 21 may further include a third switch S3, a fourth switch S4, and a third comparator COMP3. The second input terminal "-" of the third comparator COMP3 is coupled to the common-mode level VCM, and the output terminal of the third comparator COMP3 is coupled to the input terminal of the SAR logic and digital calibration module 20. One end of the third switch S3 is coupled to the common-mode level VCM, and the other end is selectively connected to the output terminal of the high-order capacitor array MDAC or the output terminal of the low-order capacitor array LDAC, depending on the calibration requirements. One end of the fourth switch S4 is coupled to the first input terminal "+" of the third comparator COMP3, and the other end of the fourth switch S4 is selectively coupled to the output terminal of the low-order capacitor array LDAC or the output terminal of the high-order capacitor array MDAC, depending on the calibration requirements or normal operation requirements.

[0149] In this example, the circuit connections and weight calibrations in steps S1 and S2 can be achieved through the cooperation of the third switch S3 and the fourth switch S4. This allows the third comparator COMP3 to be reused in steps S1 and S2, eliminating the need for the selector MUX and simplifying the circuit. For example, in step S1, the other end of the fourth switch S4 is controlled to be coupled to the output of the high-order capacitor array MDAC, and the third switch S3 is equivalent to the first switch S1, implementing the operations in steps S11 to S18 above. In step S2, the other end of the fourth switch S4 is controlled to be coupled to the output of the low-order capacitor array LDAC, and the third switch S3 is equivalent to the first switch S2, implementing the operations in steps S11 to S28 above. The specific process will not be elaborated here.

[0150] In summary, the SAR ADC and its calibration method of this invention can mutually calibrate the weight of each capacitor using the low-order segment capacitor array (LDAC) and the high-order segment capacitor array (MDAC) in the digital-to-analog converter (DAC), eliminating the need for an additional calibration DAC and simplifying the circuit. Furthermore, performing the calibration method of this invention before the SAR ADC operates normally makes the original SAR ADC design more flexible, allowing the bridging capacitor C to... b The value of the capacitor and the segmented capacitor array design of the digital-to-analog converter (DAC) are relatively flexible.

[0151] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.

Claims

1. A calibration method for a successive approximation analog-to-digital converter (ADC), wherein the successive approximation ADC includes a digital-to-analog converter (DAC), and the DAC comprises a bridging capacitor, a low-order segment capacitor array, and a high-order segment capacitor array, wherein the first plate of each capacitor in the high-order segment capacitor array is coupled to one plate of the bridging capacitor to form the output terminal of the high-order segment capacitor array, and the first plate of each capacitor in the low-order segment capacitor array is coupled to the other plate of the bridging capacitor to form the output terminal of the low-order segment capacitor array; characterized in that... The calibration method includes the following steps: S1, use the low-level segment capacitor array to measure the weight of each capacitor in the high-level segment capacitor array; S2, use the high-order segment capacitor array to measure the weight of each capacitor in the low-order segment capacitor array; S3, repeat S1 and S2 several times to obtain the weight matrix of the entire digital-to-analog converter; S4, normalize the weight matrix of the entire digital-to-analog converter to a weight matrix of the target resolution bit depth.

2. The calibration method as described in claim 1, characterized in that, In step S1, the process of measuring the weight of the least significant capacitor in the high-order segment capacitor array using the low-order segment capacitor array includes: S11, connect the output terminal of the high-order segment capacitor array to the common-mode level, connect the second plate of the lowest-order capacitor of the high-order segment capacitor array to the first reference voltage, and connect the second plates of the remaining capacitors of the high-order segment capacitor array and the second plates of each capacitor in the low-order segment capacitor array to the second reference voltage. S12, disconnect the common-mode level from the output terminal of the high-level capacitor array, and reconnect the second plate of the lowest capacitor of the high-level capacitor array to the second reference voltage; S13, the successive approximation analog-to-digital converter performs a successive approximation conversion to obtain a first conversion result; S14. Based on the weights of each capacitor in the low-order segment capacitor array and the first conversion result, the weight of the least significant capacitor in the high-order segment capacitor array is obtained.

3. The calibration method as described in claim 2, characterized in that, In step S1, before executing step S14, steps S11 to S13 are executed multiple times to obtain the corresponding average value as the first conversion result.

4. The calibration method as described in claim 2, characterized in that, In step S1, the remaining capacitors in the high-order segment capacitor array are used as the first capacitor to be measured. The process of measuring the weight of the first capacitor to be measured using the low-order segment capacitor array includes: S15, connect the output terminal of the high-level capacitor array to the common-mode level, connect the second plate of the first capacitor under test and the second plate of the highest capacitor in the low-level capacitor array to the first reference voltage, and connect the second plates of the remaining capacitors in the high-level capacitor array and the second plates of the remaining capacitors in the low-level capacitor array to the second reference voltage. S16, disconnect the common-mode level from the output terminal of the high-order segment capacitor array, and reconnect the second plate of the first capacitor under test to the second reference voltage. At the same time, reconnect the second plates of all capacitors in the high-order segment capacitor array that are lower than the first capacitor under test to the first reference voltage. S17, the successive approximation analog-to-digital converter performs a successive approximation conversion to obtain a second conversion result; S18, based on the weights of each capacitor in the low-order segment capacitor array and the second conversion result, the weight of the first capacitor to be tested is obtained.

5. The calibration method as described in claim 4, characterized in that, In step S1, before executing step S18, steps S15 to S17 are executed multiple times to obtain the corresponding average value as the second conversion result.

6. The calibration method as described in claim 4, characterized in that, The low-level capacitor array has m-position capacitors CL0 to CL0. m-1 The weight of each capacitor in the low-order segment capacitor array is Weight_L = [Weight_L(m-1),…,Weight_L(0)], and the high-order segment capacitor array has k capacitors CM0~CM0. k-1 ;and, The weight of the lowest-order capacitor CM0 in the high-order segment capacitor array is: Weight_M(0)=RES0_1*Weight_L; The first capacitor under test CM i The weights are: ,RES1=RES0_2*Weight_L-Weight_L(m-1); Furthermore, the weights of the capacitors in each position of the high-order segment capacitor array, Weight_M = [Weight_M(k - 1), …, Weight_M(0)]; where RES0_1 is the first conversion result, RES0_2 is the second conversion result, both i and j are integers, 0 < i ≤ k - 1, 0 ≤ j ≤ i - 1, and / or The initial value of the weight_L of each capacitor in the low-order segment capacitor array is [2]. m-1 ,2 m-2 ,…,2,1).

7. The calibration method as described in claim 1, characterized in that, In the step S2, the process of measuring the weight of the lowest-position capacitor in the low-order segment capacitor array by using the high-order segment capacitor array includes: S21: Connect the output terminal of the low-order segment capacitor array to the common-mode level, connect the second plate of the lowest-position capacitor in the low-order segment capacitor array to the first reference voltage, and at the same time connect the second plates of the remaining capacitors in the low-order segment capacitor array and the second plates of the capacitors in each position of the high-order segment capacitor array to the second reference voltage; S22: Disconnect the connection between the common-mode level and the output terminal of the low-order segment capacitor array, and change the connection of the second plate of the lowest-position capacitor in the low-order segment capacitor array to the second reference voltage; S23: The successive approximation analog-to-digital converter performs successive approximation conversion to obtain a third conversion result; S24: According to the weights of the capacitors in each position of the high-order segment capacitor array and the third conversion result, obtain the weight of the lowest-position capacitor in the low-order segment capacitor array.

8. The calibration method as described in claim 7, characterized in that, In the step S2, before executing the step S24, the steps S21 to S23 are also executed multiple times to obtain the corresponding average value as the third conversion result.

9. The calibration method as described in claim 7, characterized in that, In the step S2, when the remaining capacitors in the low-order segment capacitor array are being measured as the second capacitor to be measured, the process of measuring the weight of the second capacitor to be measured by using the high-order segment capacitor array includes: S25: Connect the output terminal of the low-order segment capacitor array to the common-mode level, connect the second plate of the second capacitor to be measured and the second plate of the highest-position capacitor in the high-order segment capacitor array to the first reference voltage, and at the same time connect the second plates of the remaining capacitors in the high-order segment capacitor array and the second plates of the remaining capacitors in the low-order segment capacitor array to the second reference voltage; S26: Disconnect the connection between the common-mode level and the output terminal of the low-order segment capacitor array, change the connection of the second plate of the second capacitor to be measured to the second reference voltage, and at the same time change the connection of the second plates of the capacitors in the low-order segment capacitor array that are lower in position than the second capacitor to be measured to the first reference voltage; S27: The successive approximation analog-to-digital converter performs successive approximation conversion to obtain a fourth conversion result; S28: According to the weights of the capacitors in each position of the high-order segment capacitor array and the fourth conversion result, obtain the weight of the second capacitor to be measured.

10. The calibration method as described in claim 9, characterized in that, In the step S2, before executing the step S28, the steps S25 to S28 are also executed multiple times to obtain the corresponding average value as the fourth conversion result.

11. The calibration method as described in claim 9, characterized in that, The low-level capacitor array has m-position capacitors CL0 to CL0. m-1 The high-level capacitor array has k capacitors CM0 to CM0. k-1 And the weight of each capacitor in the high-order segment capacitor array is Weight_M=[Weight_M(k-1),…,Weight_M(0)]; The weight of the lowest-position capacitor CL0 in the low-order segment capacitor array is: Weight_L(0) = RES0_3 * Weight_M; The second capacitor under test, CL i The weights are: ,RES2=RES0_4*Weight_M-Weight_M(k-1); Furthermore, the weight of each capacitor in the low-order segment capacitor array is Weight_L=[Weight_L(m-1),…,Weight_L(0)]. / Weight_L(0); Wherein, RES0_3 is the third transformation result, RES0_4 is the fourth transformation result, i and j are both integers, 0 <i≤m-1,0≤j≤i-1。 12. The calibration method as described in claim 6 or 11, characterized in that, The m-position capacitor CL0~CL m-1 and k-position capacitor CM0~CM k-1 All are binary-weighted capacitor arrays, and the segmented capacitor array also includes terminal capacitors; in step S3, the weight matrix DAC_Weight_raw = [MDAC_Weight, LDAC_Weight] of the entire digital-to-analog converter is obtained, and the weight matrix for the target resolution bit depth N obtained in step S4 is: DAC_Weight_normal=DAC_Weight_raw.*[2 N / (∑MDAC_Weight+Weight_M_(T))]; Wherein, ∑MDAC_Weight is the sum of the weights of each capacitor in the high-order segment capacitor array, and / or Weight_M_(T) is the weight of the terminal capacitor, and the weight of the terminal capacitor is measured using the low-order segment capacitor array.

13. A successive approximation analog-to-digital converter, characterized in that, include: A digital-to-analog converter includes a bridging capacitor, a low-order segment capacitor array, and a high-order segment capacitor array. The first plate of each capacitor in the high-order segment capacitor array is coupled to one plate of the bridging capacitor to form the output terminal of the high-order segment capacitor array. The first plate of each capacitor in the low-order segment capacitor array is coupled to the other plate of the bridging capacitor to form the output terminal of the low-order segment capacitor array. The comparison module has a first input terminal coupled to the output terminal of the low-order segment capacitor array and the output terminal of the high-order segment capacitor array, and a second input terminal coupled to the common-mode level, used to compare the output of the high-order segment capacitor array or the output of the low-order segment capacitor array with the corresponding common-mode level; The SAR logic and digital calibration module has its input terminal coupled to the output terminal of the comparison module and is used to perform successive approximation conversion based on the output of the comparison module to implement the calibration method of the successive approximation analog-to-digital converter as described in any one of claims 1-12.

14. The successive approximation analog-to-digital converter as described in claim 13, characterized in that, The second plate of each capacitor in the digital-to-analog converter is coupled to a corresponding switch. The SAR logic and digital calibration module is also used to control the toggle direction of the switch connected to the second plate of each capacitor in the digital-to-analog converter, so as to connect the second plate of the corresponding capacitor to at least one of the first reference voltage, the second reference voltage and the input voltage.

15. The successive approximation analog-to-digital converter as described in claim 13, characterized in that, The comparison module includes: A first switch and a first comparator, one end of the first switch is coupled to a common-mode level, the other end of the first switch is coupled to a first input terminal of the first comparator and the output terminal of the high-order segment capacitor array, and a second input terminal of the first comparator is coupled to the common-mode level; A second switch and a second comparator, one end of the second switch is coupled to the common-mode level, and the other end of the second switch is coupled to the first input terminal of the second comparator and the output terminal of the low-order segment capacitor array, and the second input terminal of the second comparator is coupled to the common-mode level; A gating device, wherein the first input terminal of the gating device is coupled to the output terminal of the first comparator, the second input terminal of the gating device is coupled to the output terminal of the second comparator, and the output terminal of the gating device is coupled to the input terminal of the SAR logic and digital calibration module; Specifically, when measuring the weight of each capacitor in the high-order segment capacitor array using the low-order segment capacitor array, the selector provides the comparison result of the first comparator to the SAR logic and digital calibration module; when measuring the weight of each capacitor in the low-order segment capacitor array using the high-order segment capacitor array, the selector provides the comparison result of the second comparator to the SAR logic and digital calibration module.

16. The successive approximation analog-to-digital converter as described in claim 13, characterized in that, The comparison module includes: A third comparator, the second input of which is coupled to the common-mode level, and the output of which is coupled to the input of the SAR logic and digital calibration module; The third switch has one end coupled to the common-mode level and the other end selectively connected to either the output terminal of the high-order segment capacitor array or the output terminal of the low-order segment capacitor array. A fourth switch, one end of which is coupled to the first input terminal of the third comparator, and the other end of which is selectively coupled to the output terminal of the low-order segment capacitor array or the output terminal of the high-order segment capacitor array.

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