Clock tree synthesis method of high-bandwidth interface module, electronic device and medium

Abstract

This invention relates to the field of chip technology, and more particularly to a clock tree synthesis method for a high-bandwidth interface module, an electronic device, and a medium. The method includes S1, dividing the high-bandwidth interface module into a first region and a second region; S2, dividing the first region into M A m Divide the second region into M B regions. m S3, in A m Selecting the clock root node C m And taking the clock generation node as the starting point of the clock source, and taking all C... m Build a first-level distribution structure for the endpoint; S4, in each A m In the middle, with C m Starting from this point, construct each A m The corresponding sub-clock tree D m S5, in each B m In the middle, with adjacent A m C in m Starting from this point, construct B m The corresponding multi-tap clock tree E m And in C m and E m Delay compensation buffers are inserted between the points; S6, the clock tree of the high-bandwidth interface module is synthesized. This invention meets the timing convergence requirements of the high-bandwidth interface module and improves the performance and reliability of the chip.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a clock tree synthesis method for a high-bandwidth interface module, an electronic device, and a medium. Background Technology

[0002] In some high-bandwidth interface modules, there are some integrated sub-modules. These integrated sub-modules form a long and narrow channel structure. A large number of standard units are distributed in the long and narrow channel structure and in areas other than the sub-modules, resulting in an extremely irregular distribution of registers within the standard unit area.

[0003] Traditional clock tree synthesis methods have at least the following technical defects when dealing with the uneven distribution of registers in high-bandwidth interface modules: (1) They cannot simultaneously achieve the dual goals of low clock delay and low clock skew. When the clock signal is transmitted in a narrow channel, the path difference can easily lead to excessive local clock skew, which directly affects the timing performance of the chip; (2) When timing checks are performed between the sub-module and the top-level register of the high-bandwidth interface module, the length of the common path is seriously insufficient, which greatly amplifies the impact of on-chip variation (OCV), causing a large number of difficult-to-repair timing violations, which seriously restricts the yield and stability of the chip; (3) The clock distribution efficiency is low in the large area of ​​the high-bandwidth interface module that is not where the sub-module is located, which makes it difficult to meet the clock synchronization requirements of a large number of registers, further exacerbating the timing convergence difficulty and reducing the chip performance and reliability. Therefore, it can be seen that how to provide a clock tree synthesis method suitable for high-bandwidth interface modules, meet the timing convergence requirements of high-bandwidth interface modules, and improve the performance and reliability of the chip has become an urgent technical problem to be solved. Summary of the Invention

[0004] The purpose of this invention is to provide a clock tree synthesis method, electronic device, and medium for a high-bandwidth interface module, which meets the timing convergence requirements of the high-bandwidth interface module and improves the performance and reliability of the chip.

[0005] According to a first aspect of the present invention, a clock tree synthesis method for a high-bandwidth interface module is provided, comprising: Step S1: Divide the high-bandwidth interface module into a first region and a second region. The first region is used to set up sub-modules, and the second region is used to set up standard units. The first region includes multiple channels formed between multiple sub-modules. Step S2: Divide the first region into M identical sub-module regions {A1, A2, ..., A...} m ,...,A M The second region is divided into M identical standard unit regions {B1, B2, ..., B}.m ,...,B M}, A m For the m-th submodule region, B m For the m-th standard unit region, m ranges from 1 to M, where M is an even number, A m With B m Correspondingly, and A m With B m Adjacent in physical location; Step S3, in each A m Select a position as the corresponding clock root node C. m And taking the clock generation node as the starting point of the clock source, and taking all C... m A first-level distribution structure is constructed for the endpoint, wherein the clock start point to all C... m The clock delay is within the preset error range; Step S4, in each A m In the middle, with C m Starting from this point, construct each A m The corresponding sub-clock tree D m D m Used to transfer clock signals from C m Distribute to A m The registers within each submodule enable C m To A m The clock delay of the registers within each submodule is within the preset error range; Step S5, in each B m In the middle, with adjacent A m C in m Starting from this point, construct each B m The corresponding multi-tap clock tree E m And in C m and E m Insert delay compensation buffer F between m F m Used to compensate A m and B m The clock delay difference, E m Used to transfer clock signals from C m Distributed to B m The registers of each standard unit in C enable C m To B m The clock delay of the registers in each standard unit is within the preset error range; Step S6: Based on the first-level distribution structure, all D m All F m and all E m Synthesize the clock tree of the high-bandwidth interface module.

[0006] Furthermore, step S1 includes: Step S11: Divide the area where the sub-modules are located in the high-bandwidth interface module into a first area. The first area includes multiple channels formed between multiple sub-modules. Divide the area where no sub-modules are set into a second area. The first area and the second area are physically adjacent. Step S12: Move the standard unit originally set in the channel to the second area and adjust the timing. The timing between the registers in the moved standard unit and the corresponding sub-module and its interconnected registers meets the preset timing requirements.

[0007] Furthermore, step S3 includes: Step S31, in each A m Select a position located in the channel as the corresponding clock root node C. m And taking the clock generation node as the starting point of the clock source, and taking all C... m Construct a symmetric H-tree network for the endpoint; Step S32: Insert a transition buffer into the branch nodes of the H-tree network, and configure the parameters of the transition buffer so that the clock start point to all C... m If the clock delay is within a preset error range, the first-level distribution structure is generated.

[0008] Furthermore, each A m Includes N submodules {G1 m G2 m ,...,G n m ,...,G N M}, G n m For A m The nth submodule, G n m The sub-modules in the same way are arranged, and the value of n ranges from 1 to N. Step S4 includes: Step S41, in C m N first intermediate buffers are set in the channel, and C is established. m The connection with N first intermediate buffers, each G n m Corresponding to an intermediate buffer H n m C m To the corresponding A m In each H n m The clock delay is within the preset error range; Step S42, in A mEach submodule is configured with a port buffer, and each H is established. n m To the corresponding G n m The connection of the port buffers of each submodule in the process generates A. m The corresponding sub-clock tree D m Each H n m To the corresponding G n m The clock delay of the port buffer of each submodule is within a preset error range.

[0009] Furthermore, step S5 includes: Step S51, in C m A second intermediate buffer is set in the channel, and C is established. m Connection with the second intermediate buffer; Step S52, in B m Build B m The corresponding multi-tap clock tree E m Establish the output of the second intermediate buffer and E m The connection; Step S53, in the second intermediate buffer and E m Insert delay compensation buffer F between m This makes C m To B m The clock delay of the registers in each standard unit is within the preset error range.

[0010] Furthermore, step S53 includes: Step S531, obtain from C m The path from the first intermediate buffer and the port buffer of the submodule to the register in the submodule is the same as that from C. m After passing through the second intermediate buffer, E m Arrive at B m The maximum delay difference between register paths in a standard unit; Step S532, based on the maximum delay difference in the second intermediate buffer and E m Insert delay compensation buffer F between m .

[0011] Furthermore, the high-bandwidth interface module is an interface module that follows a preset protocol, which includes the HBM3e protocol, the lpddr6 protocol, and the gddr6 protocol.

[0012] According to a second aspect of the present invention, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the method described in the first aspect of the present invention.

[0013] According to a third aspect of the present invention, a computer-readable storage medium is provided, storing computer-executable instructions for performing the method described in the first aspect of the present invention.

[0014] Compared with existing technologies, this invention has significant advantages and beneficial effects. Through the above technical solution, the clock tree synthesis method, electronic device, and medium for a high-bandwidth interface module provided by this invention achieve considerable technological advancement and practicality, and have broad industrial application value. It has at least the following beneficial effects: The first-level distribution structure constructed in this invention significantly extends the common path length of the clock signal from the clock source to each sub-module, effectively weakening the impact of on-chip changes on clock latency, significantly improving the stability and consistency of clock signal transmission, reducing the workload of timing violation repair caused by on-chip changes, and lowering the iteration cost of chip design. The first-level distribution structure, combined with sub-clock trees, delay compensation buffers, and multi-tap clock trees, effectively solves the problem of excessive clock skew caused by uneven register distribution in narrow layouts, significantly improving the timing convergence efficiency of setup / hold time and greatly reducing the number of timing violations. Furthermore, the multi-tap clock tree structure adopts a short-path, uniform clock distribution method, reducing clock signal transmission loss in narrow layouts. Simultaneously, the precise layout of multi-level sub-clock trees in the sub-module area, combined with delay equalization buffer compensation, achieves clock latency synchronization between sub-modules and top-level registers, providing a stable clock synchronization foundation for high-speed data transmission, meeting the timing convergence requirements of high-bandwidth interface modules, and improving chip performance and reliability. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a flowchart of a clock tree synthesis method for a high-bandwidth interface module provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the HBM3e PHY region division provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the first-level distribution structure built in the HBM3e PHY module provided in an embodiment of the present invention; Figure 4 A schematic diagram of a sub-clock tree created in a sub-module region of the HBM3e PHY module provided in this embodiment of the invention, and a multi-tap clock tree structure created in the corresponding standard cell region.

[0017] Explanation of reference numerals in the attached figures: 100 - First Region 200 - Second Region 101 - Aword Submodule 102-Dword submodule; 103-Clock generation node; 104-Transition buffer 105 - Clock root node; 106 - Submodule area; 107 - First intermediate buffer 108 - Port Buffer; 109 - Second Intermediate Buffer; 110 - Delay Compensation Buffer 201-Multi-tap clock tree structure Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] This invention provides a method for synthesizing a clock tree for a high-bandwidth interface module, such as... Figure 1 As shown, it includes: Step S1: Divide the high-bandwidth interface module into a first region and a second region. The first region is used to set up sub-modules, and the second region is used to set up standard units. The first region includes multiple channels formed between multiple sub-modules.

[0020] It should be noted that a standard cell refers to a pre-designed basic circuit unit in a digital integrated circuit, possessing fixed logic functions and physical dimensions; it is the core component constituting the chip's logic function. A submodule refers to an integrated module composed of interconnected standard cells. The first area only contains submodules and does not directly contain standard cells. The second area does not contain submodules and only directly contains standard cells.

[0021] Step S2: Divide the first region into M identical sub-module regions {A1, A2, ..., A...} m ,...,A M The second region is divided into M identical standard unit regions {B1, B2, ..., B}.m ,...,B M}, A m For the m-th submodule region, B m For the m-th standard unit region, where m ranges from 1 to M, M is the number of sub-module regions, and the number of standard unit regions is also M, where M is an even number. m With B m Correspondingly, and A m With B m They are physically adjacent.

[0022] It should be noted that if it is not possible to directly divide the first region into an even number of identical sub-module regions, a virtual sub-module region can be added to achieve the same result.

[0023] Step S3, in each A m Select a position as the corresponding clock root node C. m And taking the clock generation node as the starting point of the clock source, and taking all C... m A first-level distribution structure is constructed for the endpoint, wherein the clock start point to all C... m The clock delay is within the preset error range.

[0024] Specifically, it can be seen from A m The corresponding clock root node C is selected when the geometric center is within a preset distance range and located in the channel. m It should be noted that submodules are pre-packaged and integrated modules, therefore C... m It is set in the channel, not in the submodule. The clock generation node can specifically be a phase-locked loop (PLL) clock generator. The clock generation node is the signal input source of the entire clock tree, outputting the initial clock signal to the first-level distribution structure, providing a stable clock source for the entire clock tree.

[0025] The primary distribution structure constructed in this invention significantly extends the common path length of the clock signal from the clock generation node to each submodule, effectively mitigating the impact of on-chip variations on clock latency. This significantly improves the stability and consistency of clock signal transmission, reduces the workload of timing violation repair caused by on-chip variations, and lowers the iteration cost of chip design. On-chip variations refer to the differences in electrical parameters (such as delay and voltage) at different locations and times on the same wafer during chip manufacturing and operation, which exacerbate the uncertainty of clock signal transmission.

[0026] Step S4, in each A m In the middle, with C m Starting from this point, construct each A m The corresponding sub-clock tree Dm D m Used to transfer clock signals from C m Distribute to A m The registers within each submodule enable C m To A m The clock delay of the registers in each submodule is within the preset error range.

[0027] Step S5, in each B m In the middle, with adjacent A m C in m Starting from this point, construct each B m The corresponding multi-tap clock tree E m And in C m and E m Insert delay compensation buffer F between m F m Used to compensate A m and B m The clock delay difference, E m Used to transfer clock signals from C m Distributed to B m The registers of each standard unit in C enable C m To B m The clock delay of the registers in each standard unit is within the preset error range.

[0028] Among them, the multi-tap clock tree is a clock tree structure that distributes the clock signal evenly to each load unit by setting multiple tap nodes on the clock tree trunk, and has the advantages of low clock skew and high flexibility.

[0029] It should be noted that, considering the large number and wide distribution of registers in the second region, this invention employs a multi-tap clock tree structure: iteratively optimizing the position and spacing of each tap node, and combining this with the actual distribution of standard cells, the clock signal is distributed to all registers in the region in a short-path, uniform manner. Furthermore, due to the high internal logic complexity of the submodules, their internal clock tree transmission paths are relatively long, resulting in a significant difference in clock delay compared to the clock tree in the second region. To achieve delay equalization of the overall clock tree, a delay compensation buffer F is inserted before the main path of the multi-tap clock tree. m By configuring the buffer's drive strength and delay, the clock delay difference between the submodule side and the right-side standard cell side is precisely compensated, ultimately achieving delay consistency across the entire clock tree and further reducing global clock skew. Clock skew refers to the time difference between the arrival of the same clock signal at different register clock ends, and it is a core parameter affecting chip timing performance; excessive skew can lead to timing violations.

[0030] Step S6: Based on the first-level distribution structure, all Dm All F m and all E m Synthesize the clock tree of the high-bandwidth interface module.

[0031] The connection relationships of the clock tree of the high-bandwidth interface module are as follows: the output of the clock generation node is connected to the backbone of the primary distribution structure, the end of the backbone is connected to M clock root nodes, each root node is connected to the input of a set of multi-level sub-clock trees, and the output of the multi-level sub-clock trees is connected to the sub-modules in the corresponding area; the end of the multi-level sub-clock trees is connected to the input of the delay compensation buffer, and the output of the delay compensation buffer is connected to the backbone entry of the multi-tap clock tree structure; each tap node of the multi-tap clock tree structure is connected to the registers and logic units in the standard cell area on the right.

[0032] It should be noted that the preset error range is ideally 0, but in reality, due to various factors, there may be a small amount of error. The preset error range should be set according to the specific application scenario.

[0033] This invention employs a hierarchical distribution architecture based on region partitioning, multi-level clock trees, and multi-tap clock tree structures. Combined with precise configuration of transition buffers and delay compensation buffers, it controls the global clock skew to an extremely low level of <50ps and the local clock skew to <30ps. Simultaneously, by optimizing the tap positions of the multi-tap clock tree structure for the register distribution characteristics of the second region, it effectively solves the problem of excessive clock skew caused by uneven register distribution in a narrow layout. This significantly improves the timing convergence efficiency of setup / hold time, drastically reduces the number of timing violations, and shortens the timing convergence cycle by more than 60% compared to traditional solutions.

[0034] As one embodiment, step S1 includes: Step S11: Divide the area where the sub-modules are located in the high-bandwidth interface module into a first area. The first area includes multiple channels formed between multiple sub-modules. Divide the area where no sub-modules are set into a second area. The first area and the second area are physically adjacent.

[0035] The channels formed between multiple sub-modules are usually long and narrow.

[0036] Step S12: Move the standard unit originally set in the channel to the second area and adjust the timing. The timing between the registers in the moved standard unit and the corresponding sub-module and its interconnected registers meets the preset timing requirements.

[0037] It should be noted that in existing designs, standard cells are typically placed even in narrow channels, resulting in a highly irregular distribution of registers within these standard cells. In this embodiment of the invention, before synthesizing the clock tree, the standard cells originally located in the channel are moved to the second region. This ensures that the registers of the standard cells are evenly distributed in the second region, resulting in a more regular distribution and reducing the difficulty of timing convergence. Furthermore, timing adjustments are performed to ensure that the timing between the registers in the moved standard cells and the corresponding submodules and their interconnected registers meets preset timing requirements.

[0038] As one embodiment, step S3 includes: Step S31, in each A m Select a position located in the channel as the corresponding clock root node C. m And taking the clock generation node as the starting point of the clock source, and taking all C... m Construct a symmetric H-tree network for the endpoint.

[0039] H-tree network refers to a symmetric recursive fractal clock distribution topology, which branches into H-shaped equal branches from the root node. The physical length of the traces from the root to all leaf nodes is completely consistent, and theoretically there is zero clock offset.

[0040] Step S32: Insert a transition buffer into the branch nodes of the H-tree network, and configure the parameters of the transition buffer so that the clock start point to all C... m If the clock delay is within a preset error range, the first-level distribution structure is generated.

[0041] It should be noted that the transition buffer is connected between the branch nodes and the root node of the H-tree trunk. By optimizing the parameter configuration and placement of the transition buffer, the delay balance of the first-level clock distribution is achieved, laying the foundation for the subsequent clock tree construction.

[0042] As one example, each A m Includes N submodules {G1 m G2 m ,...,G n m ,...,G N M}, G n m For A m The nth submodule, G n m The sub-modules in the same way are arranged, and the value of n ranges from 1 to N. Step S4 includes: Step S41, in C m N first intermediate buffers are set in the channel, and C is established. m The connection with N first intermediate buffers, each Gn m Corresponding to an intermediate buffer H n m C m To the corresponding A m In each H n m The clock delay is within the preset error range.

[0043] Step S42, in A m Each submodule is configured with a port buffer, and each H is established. n m To the corresponding G n m The connection of the port buffers of each submodule in the process generates A. m The corresponding sub-clock tree D m Each H n m To the corresponding G n m The clock delay of the port buffer of each submodule is within a preset error range.

[0044] It should be noted that, based on the register distribution, logic unit layout, and signal transmission paths within the submodules, the first intermediate buffer and port buffers are rationally arranged to accurately distribute the clock signal from the root node to the registers within each submodule. During the selection and placement of the first intermediate buffer and port buffers, the timing constraints and load characteristics within the submodules must be fully considered to ensure consistent clock signal transmission delay within the submodules and reduce local clock skew.

[0045] As one embodiment, step S5 includes: Step S51, in C m A second intermediate buffer is set in the channel, and C is established. m Connection to the second intermediate buffer.

[0046] It should be noted that the second intermediate buffer and the first intermediate buffer are at the same level in the clock tree. Preferably, the second intermediate buffer and the first intermediate buffer have the same configuration.

[0047] Step S52, in B m Build B m The corresponding multi-tap clock tree E m Establish the output of the second intermediate buffer and E m The connection.

[0048] Step S53, in the second intermediate buffer and E m Insert delay compensation buffer F between m This makes Cm To B m The clock delay of the registers in each standard unit is within the preset error range.

[0049] It should be noted that the multi-tap clock tree employs a short-path, uniform clock distribution method, reducing transmission loss of clock signals in narrow layouts. Simultaneously, the precise layout of the multi-level sub-clock trees on the sub-module side, combined with delay compensation buffers, achieves clock delay synchronization between the sub-modules and the top-level registers. This provides a stable clock synchronization foundation for high-speed data transmission of the high-bandwidth interface module, effectively improving the overall operating performance of the chip. Furthermore, the clock tree structure of this invention does not rely on a strictly geometrically symmetrical layout. The tap nodes and buffer positions can be flexibly adjusted according to the actual distribution of the narrow channels and standard cell areas of the high-bandwidth interface module, perfectly adapting to the narrow physical layout of the high-bandwidth interface module.

[0050] As one embodiment, step S53 includes: Step S531, obtain from C m The path from the first intermediate buffer and the port buffer of the submodule to the register in the submodule is the same as that from C. m After passing through the second intermediate buffer, E m Arrive at B m The maximum delay difference between register paths in a standard unit; Step S532, based on the maximum delay difference in the second intermediate buffer and E m Insert delay compensation buffer F between m .

[0051] Specifically, the delay compensation corresponding to the delay compensation buffer can be set to the maximum delay difference.

[0052] In summary, the embodiments of the present invention solve the core technical pain points of large clock tree clock offset, short common path and difficult timing convergence under the narrow layout of high bandwidth interface modules. It also has the advantages of low latency, low power consumption, high stability and high adaptability, and can be widely used in the design of high bandwidth interface module chips in fields such as high-performance computing, artificial intelligence and data centers.

[0053] The high-bandwidth interface module is an interface module that follows a preset protocol, including HBM3e protocol, lpddr6 protocol, gddr6 protocol, etc.

[0054] Taking the HBM3e protocol as an example, the high-bandwidth interface module is a high-bandwidth memory third-generation enhanced physical layer (HBM3e PHY) module, such as... Figure 2As shown, it contains 32 Dword submodules 102 and 16 Aword submodules 101. According to the design specifications of the HBM3e protocol, its physical layout forms multiple narrow channel structures in the HBM3e PHY module. The 32 Dword submodules, 16 Aword submodules, and the narrow channels belong to the first region 100. There is also a vertically elongated standard unit distribution area on the right side of the HBM3e PHY module, which is the second region.

[0055] The first-level distribution structure built in the HBM3e PHY module is as follows: Figure 3 As shown, the HBM3e PHY includes four sub-module regions 106, and the primary distribution structure includes one clock generation node 103, two transition buffers 104, and four clock root nodes 105.

[0056] The sub-clock tree created in a sub-module area of ​​the HBM3e PHY module and the multi-tap clock tree structure created in the corresponding standard cell area are shown in Figure 201. Figure 4 As shown, the sub-clock tree includes four first intermediate buffers 107 disposed in the channel (the four first intermediate buffers are on the same horizontal line in the figure) and twelve port buffers 108 disposed on the sub-module. A second intermediate buffer 109 and a delay compensation buffer 110 are disposed between the sub-clock tree and the multi-tap clock tree structure.

[0057] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0058] It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the steps as sequential processes, many of these steps can be performed in parallel, concurrently, or simultaneously. Furthermore, the order of the steps can be rearranged. A process can be terminated when its operation is complete, but it may also have additional steps not included in the figures. A process can correspond to a method, function, procedure, subroutine, subroutine, etc.

[0059] This invention also provides an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the method described in this invention.

[0060] This invention also provides a computer-readable storage medium storing computer-executable instructions for performing the methods described in this invention.

[0061] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A method for synthesizing a clock tree for a high-bandwidth interface module, characterized in that, include: Step S1: Divide the high-bandwidth interface module into a first region and a second region. The first region is used to set up sub-modules, and the second region is used to set up standard units. The first region includes multiple channels formed between multiple sub-modules. Step S2: Divide the first region into M identical sub-module regions {A1, A2, ..., A...} m ,...,A M The second region is divided into M identical standard unit regions {B1, B2, ..., B}. m ,...,B M }, A m For the m-th submodule region, B m For the m-th standard unit region, m ranges from 1 to M, where M is an even number, A m With B m Correspondingly, and A m With B m Adjacent in physical location; Step S3, in each A m Select a position as the corresponding clock root node C. m And taking the clock generation node as the starting point of the clock source, and taking all C... m A first-level distribution structure is constructed for the endpoint, wherein the clock start point to all C... m The clock delay is within the preset error range; Step S4, in each A m In the middle, with C m Starting from this point, construct each A m The corresponding sub-clock tree D m D m Used to transfer clock signals from C m Distribute to A m The registers within each submodule enable C m To A m The clock delay of the registers within each submodule is within the preset error range; Step S5, in each B m In the middle, with adjacent A m C in m Starting from this point, construct each B m The corresponding multi-tap clock tree E m And in C m and E m Insert delay compensation buffer F between m F m Used to compensate A m and B m The clock delay difference, E m Used to transfer clock signals from C m Distributed to B m The registers of each standard unit in C enable C m To B m The clock delay of the registers in each standard unit is within the preset error range; Step S6: Based on the first-level distribution structure, all D m All F m and all E m Synthesize the clock tree of the high-bandwidth interface module.

2. The clock tree synthesis method according to claim 1, characterized in that, Step S1 includes: Step S11: Divide the area where the sub-modules are located in the high-bandwidth interface module into a first area. The first area includes multiple channels formed between multiple sub-modules. Divide the area where no sub-modules are set into a second area. The first area and the second area are physically adjacent. Step S12: Move the standard unit originally set in the channel to the second area and adjust the timing. The timing between the registers in the moved standard unit and the corresponding sub-module and its interconnected registers meets the preset timing requirements.

3. The clock tree synthesis method according to claim 1, characterized in that, Step S3 includes: Step S31, in each A m Select a position located in the channel as the corresponding clock root node C. m And taking the clock generation node as the starting point of the clock source, and taking all C... m Construct a symmetric H-tree network for the endpoint; Step S32: Insert a transition buffer into the branch nodes of the H-tree network, and configure the parameters of the transition buffer so that the clock start point to all C... m If the clock delay is within a preset error range, the first-level distribution structure is generated.

4. The clock tree synthesis method according to claim 1, characterized in that, Each A m Includes N submodules {G1 m G2 m ,...,G n m ,...,G N M }, G n m For A m The nth submodule, G n m The sub-modules in the same way are arranged, and the value of n ranges from 1 to N. Step S4 includes: Step S41, in C m N first intermediate buffers are set in the channel, and C is established. m The connection with N first intermediate buffers, each G n m Corresponding to an intermediate buffer H n m C m To the corresponding A m In each H n m The clock delay is within the preset error range; Step S42, in A m Each submodule is configured with a port buffer, and each H is established. n m To the corresponding G n m The connection of the port buffers of each submodule in the process generates A. m The corresponding sub-clock tree D m Each H n m To the corresponding G n m The clock delay of the port buffer of each submodule is within a preset error range.

5. The clock tree synthesis method according to claim 1, characterized in that, Step S5 includes: Step S51, in C m A second intermediate buffer is set in the channel, and C is established. m Connection with the second intermediate buffer; Step S52, in B m Build B m The corresponding multi-tap clock tree E m Establish the output of the second intermediate buffer and E m The connection; Step S53, in the second intermediate buffer and E m Insert delay compensation buffer F between m This makes C m To B m The clock delay of the registers in each standard unit is within the preset error range.

6. The clock tree synthesis method according to claim 5, characterized in that, Step S53 includes: Step S531, obtain from C m The path from the first intermediate buffer and the port buffer of the submodule to the register in the submodule is the same as the path from C. m After passing through the second intermediate buffer, E m Arrive at B m The maximum delay difference between register paths in a standard unit; Step S532, based on the maximum delay difference in the second intermediate buffer and E m Insert delay compensation buffer F between m .

7. The clock tree synthesis method according to claim 1, characterized in that, The high-bandwidth interface module is an interface module that follows a preset protocol, which includes the HBM3e protocol, the lpddr6 protocol, and the gddr6 protocol.

8. An electronic device, characterized in that, include: At least one processor; And, a memory communicatively connected to the at least one processor; The memory stores instructions that are executed by the at least one processor, the instructions being configured to perform the method as described in any one of claims 1-7.

9. A computer-readable storage medium, characterized in that, The device stores computer-executable instructions for performing the method as described in any one of claims 1-7.

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