A data latch circuit and an integrated circuit including the same

Abstract

The application discloses a data latch circuit and an integrated circuit comprising the same, which comprises a sampling module and a level conversion module, the sampling module comprising a data end, an enable end and a capacitor C2, the data end being used for receiving backup data, the enable end being used for receiving an enable signal, the sampling module being configured to selectively charge or discharge the capacitor C2 according to the backup data when the enable signal is at a high level, and cut off the charging and discharging path of the capacitor C2 when the enable signal is at a low level, and the level conversion module being used for converting the level state stored by the capacitor C2 into a standard digital level for reading by a digital processing module in a power supply module power-on stage. The data latch circuit utilizes the charge storage characteristics of the capacitor C2 itself, locks and keeps the data before power failure, and can directly read the backup data after the power supply is re-powered, so that the whole system can quickly recover to the stable working state before power failure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit technology, and more particularly to a data latch circuit and an integrated circuit comprising the same. Background Technology

[0002] During the operation of digital circuits or mixed-signal circuits, intermediate data or final results generated by logical operations are usually temporarily stored in registers for the system to call and read at any time.

[0003] Registers are the most fundamental sequential logic circuits in digital systems. Their core structure consists of flip-flops or latches, and they are volatile memories that require a continuous power supply to maintain their internal storage state. Once the chip experiences an abnormal power outage, the data stored in the register will be lost and the register will enter an indeterminate state. After the circuit is powered on again, the register cannot restore the valid data before the power outage and only outputs meaningless random noise levels. The system can only recover by re-initializing and repeating logical operations, which brings startup delays and additional system operating overhead. Summary of the Invention

[0004] This application provides a data latch circuit and an integrated circuit including the same.

[0005] In a first aspect, this application provides a data latching circuit for quickly restoring data before power failure when the power module is powered on again after a power failure, including: a sampling module and a level conversion module;

[0006] The sampling module includes a data terminal, an enable terminal, and a capacitor C2; The data terminal is configured to receive backup data; The enabling terminal is configured to receive an enabling signal; The sampling module is configured as follows: When the enable signal is high, the capacitor C2 is selectively charged or discharged according to the backup data, so that the level state stored in the capacitor C2 is consistent with the backup data; When the enable signal is low, the charging and discharging path of capacitor C2 is cut off, and capacitor C2 latches and maintains the level state before the enable signal is pulled low. The level conversion module is configured to convert the level state stored in the capacitor C2 into a standard digital level, which is then read by the digital processing module during the power-on phase of the power module to quickly restore the backup data received by the data terminal before the power failure.

[0007] In conjunction with the first aspect, in one possible implementation, the sampling module further includes a clock detection terminal configured to receive a clock detection signal; The sampling module is configured as follows: When the clock detection signal is high, the clock detection signal and the enable signal work together to selectively charge or discharge the capacitor C2, so that the level state stored in the capacitor C2 is consistent with the backup data; When the clock detection signal is low, the charging and discharging path of capacitor C2 is cut off.

[0008] In conjunction with the first aspect, in one possible implementation, the sampling module further includes a sampling logic unit, a first NMOS transistor, and a second NMOS transistor; The sampling logic unit generates two drive signals based on the backup data and the enable signal, which are respectively connected to the gates of the first NMOS transistor and the second NMOS transistor to control the turn-on and turn-off of the first NMOS transistor and the second NMOS transistor. The drain of the first NMOS transistor is connected to the power supply terminal, and the source is connected to the common node A, which is used to control the conduction and cutoff of the charging path of the capacitor C2 by the power supply terminal. The drain of the second NMOS transistor is connected to the common node A, and the source is connected to ground, which is used to control the conduction and cutoff of the discharge path of the capacitor C2 to ground.

[0009] In conjunction with the first aspect, in one possible implementation, the sampling module further includes a third NMOS transistor; the gate of the third NMOS transistor is used to receive the clock detection signal, the drain is connected to the common node A, and the source is connected to the first terminal of the capacitor C2.

[0010] In conjunction with the first aspect, in one possible implementation, the sampling logic unit includes an AND gate, a NOR gate, and a NOT gate; The first input terminal of the AND gate is connected to the data terminal, the second input terminal is connected to the enable terminal, and the output terminal is connected to the gate of the first NMOS transistor. The first input terminal of the NOR gate is connected to the data terminal, the second input terminal is connected to the enable terminal via the NOT gate, and the output terminal is connected to the gate of the second NMOS transistor.

[0011] In conjunction with the first aspect, in one possible implementation, the data latch circuit of this application further includes an inverting module; the inverting module is configured to invert the level state stored in the capacitor C2 and output an inverted level state.

[0012] In conjunction with the first aspect, in one possible implementation, the level conversion module has a non-inverting output terminal and an inverting output terminal; The level conversion module outputs complementary in-phase and in-phase standard digital levels based on the level state and the inverted level state, which are then read by the digital processing module upon power-up to restore the working state before power failure.

[0013] In conjunction with the first aspect, in one possible implementation, the inverting module includes a first PMOS transistor, a second PMOS transistor, a constant current source, and a fifth NMOS transistor; The gates of the first PMOS transistor and the second PMOS transistor are connected, and the drains of both are connected to the power supply. The source of the first PMOS transistor is grounded through the constant current source on one hand, and shorted to its own gate on the other hand. The source of the second PMOS transistor is connected to the drain of the fifth NMOS transistor; The gate of the fifth NMOS transistor is connected to the first terminal of the capacitor C2, the source is grounded, and its drain node serves as the output terminal of the inverting module, connected to the level conversion module.

[0014] In conjunction with the first aspect, in one possible implementation, the level conversion module includes a third PMOS transistor, a fourth PMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor; The gate of the sixth NMOS transistor is connected to the drain node of the fifth NMOS transistor, the source is grounded, and the drain is connected to the gate of the fourth PMOS transistor and the source of the third PMOS transistor, respectively. The gate of the seventh NMOS transistor is connected to the first terminal of the capacitor C2, the source is grounded, and the drain is connected to the gate of the third PMOS transistor and the source of the fourth PMOS transistor, respectively. The drains of the third PMOS transistor and the fourth PMOS transistor are connected to the power supply terminal.

[0015] In a second aspect, this application provides an integrated circuit chip, including a power module, a clock module, a digital processing module, a register module, and a data latch module, wherein the data latch module includes at least one of the above-mentioned data latch circuits; The power module provides operating power to each module and outputs a power-on reset (POR) signal to the digital processing module. The clock module provides a synchronous operating clock for all modules; The digital processing module establishes a bidirectional data interaction channel with the register module to realize data writing and reading from the register module; The digital processing module establishes bidirectional data interaction channels with the register module and the data latch module respectively, for synchronously writing backup data consistent with the register module to the data latch circuit, and reading the standard digital signal output by the data latch circuit during the power-on recovery phase to complete the rapid recovery of the register data written before power failure.

[0016] In conjunction with the second aspect, in one possible implementation, the enable terminal of each of the data latch circuits is connected to the global enable signal line, the clock detection terminal is connected to the global clock detection signal line, and the data terminals are respectively connected to the corresponding bit channels of the multi-bit data bus.

[0017] Compared with existing technologies, the advantages of this application are as follows: First, the data latch circuit of this application can charge or discharge capacitor C2 according to the backup data written at the data terminal, and utilize the charge storage characteristics of capacitor C2 itself to lock and maintain the level state before power failure, thus completing the power failure latching of backup data; after the system is powered on again, the signal output by the data latch circuit can be quickly read, eliminating the system initialization and repetitive calculation process, enabling the entire circuit system to quickly return to the stable working state before power failure. It can also cope with various operating conditions where the power supply is abnormally depleted due to external interference, significantly improving the overall circuit operation stability and anti-interference capability, and enhancing the overall robustness of the circuit. Second, the circuit structure of this invention is simple and highly adaptable, and can be widely applied to various types and different fabrication processes of mixed-signal integrated circuits. Third, a single data latch circuit can independently complete the power failure latching and power-on recovery of one bit of logic data. During circuit design, the number of data storage bits can be flexibly cascaded to expand the data storage bits according to the actual bit width requirements, meeting the needs of synchronous backup latching of multiple bits of data. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of a data latch circuit provided in an embodiment of this application; Figure 2 An overall structural block diagram of an integrated circuit provided in an embodiment of this application; Figure 3 This is a timing diagram of a data latch circuit provided in an embodiment of this application. Detailed Implementation

[0019] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] The technical problem to be solved by this application is explained below.

[0021] In sensor applications, it is typically necessary to detect changes in external signals in real time and output analog or digital signals with low latency. When the circuit operates in complex and harsh environments, it is susceptible to strong external interference. If the circuit is subjected to pulse interference or abnormal power failure during operation, it may trigger a digital or analog reset. When the interference disappears and the power is restored, the data stored in the registers is lost, and the circuit needs to complete initialization and recalculation to restore its pre-power-loss operating state.

[0022] During the power-on initialization phase, some circuits need to read preset configuration parameters stored in erasable and programmable random access memory (EEPROM) through serial communication interfaces such as I2C and SPI, which may require millisecond-level delays. In addition, some operating condition characteristic data need to be obtained by complex calculations through main control devices such as MCU and DSP. These calculation processes will further lengthen the signal output delay, making it difficult to meet the circuit's requirements for low latency and fast response.

[0023] To address this issue, this application proposes a data latch circuit that can quickly restore the register data before the power failure upon power-on after an abnormal power outage. This circuit provides real-time backup and rapid power-on recovery of register data, effectively resolving the time delay caused by system re-initialization and repetitive logic operations in traditional power-on processes, and significantly improving the system's power-on recovery response speed. When the power supply is continuously and stably supplied, the data latch circuit can synchronously complete the backup of the register data and update the backup data in real time following the system clock. When the power supply fails and is restored, the digital processing module can prioritize reading the backup data from the data latch circuit and write it back to the register, quickly restoring the operating state before the power failure and significantly reducing the power-on startup time.

[0024] Combination Figure 1 As shown, the data latch circuit of this application includes a sampling module and a level conversion module. The sampling module has a data terminal, an enable terminal, and a capacitor C2. The data terminal receives parallel backup data D written by the digital processing module, and the enable terminal receives the enable signal EN output by the digital processing module. The sampling module is configured to: when the enable signal EN is high, selectively charge or discharge capacitor C2 according to the backup data received at the data terminal, ensuring that the level state of capacitor C2 is consistent with the backup data; when the enable signal EN is low, cut off the charging and discharging path of capacitor C2, and capacitor C2, based on its own charge storage characteristics, latches and maintains the level state before the enable signal EN was pulled low. The level conversion module converts the level state of capacitor C2 into a standard digital level for the digital processing module to read during the power-on phase after a power outage, so as to quickly restore the backup data written at the data terminal before the power outage.

[0025] When the power supply is normal, the data latch circuit of this application is in real-time data backup state. The enable signal EN is driven by the clock signal output by the external clock module and flips periodically with the clock signal. When the power supply fails, the circuit enters latching mode, and the enable signal EN is pulled down to a low level. After the power supply is restored, the circuit enters power-on recovery mode, and the enable signal EN is pulled up to a high level. In this embodiment, the power-on reset signal POR is preferably used as the power state determination indicator signal: when the power supply is normally and stably supplied, the power-on reset signal POR remains at a high level, and the enable signal EN flips periodically with the system clock signal; when the power supply fails, the power-on reset signal POR flips to a low level, synchronously triggering the enable signal EN to be pulled down to a low level; when the power supply is restored to normal, the power-on reset signal POR resets and flips to a high level, synchronously triggering the enable signal EN to be pulled up to a high level.

[0026] Optionally, the sampling module includes a sampling logic unit, a first NMOS transistor, and a second NMOS transistor. The sampling logic unit is composed of an AND gate, a NOR gate, and a NOT gate. Based on the received backup data D and the enable signal EN, the sampling logic unit generates two drive signals, which are respectively connected to the gates of the first and second NMOS transistors to control their on / off states. The specific circuit connections are as follows: the first input of the AND gate is connected to the data terminal, the second input is connected to the enable terminal, and the output is connected to the gate of the first NMOS transistor; the first input of the NOR gate is connected to the data terminal, the second input is connected to the enable terminal via the NOT gate INV, and the output is connected to the gate of the second NMOS transistor. The drain of the first NMOS transistor is connected to the power supply terminal, and the source is connected to the common node A; the source of the second NMOS transistor is connected to the common node A, and the drain is grounded. When the first NMOS transistor is turned on, the power supply charges capacitor C2 through the conducting NMOS transistor, charging capacitor C2 to a high level. When the second NMOS transistor is turned on, the charge stored in capacitor C2 is discharged to ground through the conducting second NMOS transistor, and its stored voltage level is pulled down to a low level. It is important to emphasize that because the first NMOS transistor is an N-channel metal-oxide-semiconductor field-effect transistor, with its drain connected to the power supply and its source connected to capacitor C2, and its body diode pointing from the P-type substrate to the N-type drain, when the power supply is abnormally de-energized to zero potential and the voltage level stored in capacitor C2 is high, the body diode between the drain and the substrate of the first NMOS transistor is in a reverse bias state, thus physically blocking the leakage of the charge stored in capacitor C2 to the power supply. If a conventional PMOS transistor is used, if the power supply is de-energized, its body diode will conduct in the forward direction, and the charge on capacitor C2 will leak to the power supply.

[0027] Furthermore, during the initial power-on phase, due to the unstable clock and the potential for missampling leading to erroneous overwriting of backup data, this application adds a clock detection terminal and a third NMOS transistor to the sampling module to ensure data read reliability and prevent backup data from being tampered with or corrupted. The clock detection terminal receives the clock detection signal NG, which remains high when the power supply is normal; it is pulled down to a low level during an abnormal power outage, assisting in cutting off the charging and discharging path of capacitor C2; after power-on, the clock detection signal NG is pulled up to a high level after a delay of several clock cycles. The digital processing module reads the standard digital level output by the level conversion module within this delay window, completing the restoration of the operating state before the power outage. The gate of the third NMOS transistor is connected to the clock detection signal NG, its drain is connected to node A, and its source is connected to the first terminal of capacitor C2. The working mode of the data latch circuit is controlled by the cooperation of the enable signal EN and the clock detection signal NG. It should be noted that the length of the delay window of the clock detection signal NG is greater than the interval time from the start of oscillation to the stabilization of the clock module. After the delay window ends, the clock detection signal NG is pulled high.

[0028] The working logic of the data latch circuit in this application is described in detail below: Under normal operating conditions, the power supply provides a continuous and stable power supply, the power-on reset (POR) signal remains at a high level, the clock module oscillates stably, the enable signal (EN) output by the digital processing module flips periodically following the clock signal, and the clock detection signal (NG) remains at a high level.

[0029] When the enable signal EN is high: If the backup data written to the data terminal is high, the output of the AND gate is high, and the output of the NOR gate is low. At this time, the first NMOS transistor is turned on, the second NMOS transistor is turned off, and the third NMOS transistor is turned on. The power supply charges capacitor C2 through the first and third NMOS transistors, charging capacitor C2 to a high level. If the backup data written to the data terminal is low, the output of the AND gate is low, and the output of the NOR gate is high. At this time, the first NMOS transistor is turned off, the second NMOS transistor is turned on, and the third NMOS transistor is turned on. Capacitor C2 discharges to ground through the second and third NMOS transistors, and the level of capacitor C2 is pulled low.

[0030] When the enable signal EN is low, regardless of whether the backup data written to the data terminal is high or low, the outputs of the AND gate and the NOR gate are both low, the first NMOS transistor and the second NMOS transistor are both turned off, and capacitor C2 will maintain the level state before the enable signal EN went low.

[0031] When a power failure occurs, the power-on reset (POR) signal output from the power supply terminal flips to a low level. The digital processing module detects this POR signal level change and determines that the power supply is abnormal. It then pulls the enable signal EN down to a low level. Simultaneously, the clock module stops oscillating as the power supply voltage drops, and the clock detection signal NG is pulled down to a low level. At this time, the first, second, and third NMOS transistors are all turned off, cutting off the charging and discharging path of capacitor C2. The circuit enters a latching state, and the voltage level stored in capacitor C2 remains unchanged from the state before the power failure, thus achieving power-off data backup.

[0032] When the system is powered on and reset, the power supply returns to a stable level, the power-on reset POR signal flips to a high level, and the enable signal EN is pulled high. The clock detection signal NG is delayed for several clock cycles before being pulled high. During this delay window, although the first and second NMOS transistors can periodically turn on and off with the enable signal, the third NMOS transistor remains off, and the charging and discharging path of capacitor C2 remains closed, so the latched data will not be overwritten. Once the clock detection signal NG is pulled high, the data latch circuit re-enters the real-time synchronous backup mode, and the system returns to normal operation closed loop.

[0033] Furthermore, the data latch circuit of this application is also configured with an inverting module for logically inverting the level state of the capacitor C2 and outputting an inverted level state. Specifically, the inverting module includes a first PMOS transistor, a second PMOS transistor, a constant current source, and a fifth NMOS transistor. The first PMOS transistor and the second PMOS transistor form a mirror active load structure, with their gates interconnected and their drains connected to the power supply. The first PMOS transistor serves as a reference branch, with its source shorted to its own gate and grounded through the constant current source. The second PMOS transistor serves as a mirror output branch, equivalent to a constant pull-up current source, with its source connected to the drain node of the fifth NMOS transistor to provide a constant pull-up current to the node. The source of the fifth NMOS transistor is grounded, and its gate is connected to the first terminal of the capacitor C2. The drain node of the fifth NMOS transistor constitutes the inverting output terminal of the inverting module.

[0034] Therefore, the voltage level stored in capacitor C2 serves as the gate control voltage for the fifth NMOS transistor, controlling its on / off state. When capacitor C2 is high, the fifth NMOS transistor is on, and its drain node is pulled down to a low level, achieving logic inversion (input high, output low). When capacitor C2 is low, the fifth NMOS transistor is off, and the active load composed of the first and second PMOS transistors pulls the drain node up to a high level, achieving logic inversion (input low, output high).

[0035] Furthermore, the level conversion module receives the level state of capacitor C2 and the inverted level state output by the inverting module, converts the two levels into standard digital levels, and outputs complementary in-phase output signal Q and out-of-phase output signal QN, which are reliably read by the digital processing module during the power-on phase to restore the system's operating state before power failure. Specifically, the level conversion module of this application includes a third PMOS transistor, a fourth PMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor. The gate of the sixth NMOS transistor is connected to the drain node of the fifth NMOS transistor, and the gate of the seventh NMOS transistor is connected to the first terminal of capacitor C2. The sources of the sixth and seventh NMOS transistors are grounded. The drain of the sixth NMOS transistor is connected to the gate of the fourth PMOS transistor and the source of the third PMOS transistor. The source node of the third PMOS transistor serves as the non-inverting output terminal of the level conversion module, used to output the non-inverting output signal Q. The drain of the seventh NMOS transistor is connected to the gate of the third PMOS transistor and the source of the fourth PMOS transistor. The source node of the fourth PMOS transistor serves as the inverting output terminal of the level conversion module, used to output the out-of-phase output signal QN. The drains of the third and fourth PMOS transistors are connected to the power supply terminal.

[0036] The level conversion module of this application uses a cross-coupling structure composed of the third and fourth PMOS transistors, together with the sixth and seventh NMOS transistors, to convert the level state stored in capacitor C2 into a stable full-amplitude standard digital level, and differentially outputs complementary in-phase output signal Q and out-of-phase output signal QN for reliable reading by the digital processing module during the power-on phase. The specific working principle is as follows: When capacitor C2 stores a high level, the inverting module outputs a low level, causing the sixth NMOS transistor to turn off and the seventh NMOS transistor to turn on. With the sixth NMOS transistor off, its drain node cannot conduct to ground and remains at a high potential; with the seventh NMOS transistor on, its drain node is pulled down to a low level. Since the drain node of the sixth NMOS transistor is connected to the source of the third PMOS transistor and the gate of the fourth PMOS transistor, and the drain node of the seventh NMOS transistor is connected to the gate of the third PMOS transistor and the source of the fourth PMOS transistor, the PMOS transistors conduct when the gate voltage is lower than the source voltage, causing the third PMOS transistor to turn on and the fourth PMOS transistor to turn off. After the third PMOS transistor turns on, its source node is pulled up to VDD, and the non-inverting output terminal Q outputs a high level; with the fourth PMOS transistor off, its source node remains at a low level, and the non-inverting output terminal QN outputs a low level.

[0037] When capacitor C2 stores a low level, the inverting module outputs a high level, causing the sixth NMOS transistor to turn on and the seventh NMOS transistor to turn off. With the sixth NMOS transistor on, its drain node is pulled down to a low level; with the seventh NMOS transistor off, its drain node cannot conduct to ground and remains high. Similarly, the fourth PMOS transistor is turned on, and the third PMOS transistor is turned off. When the fourth PMOS transistor turns on, its source node is pulled up to VDD, and the out-of-phase output Q outputs a low level; when the fourth PMOS transistor turns off, its source node remains low, and the out-of-phase output QN outputs a low level.

[0038] Combination Figure 2 As shown, the data latch circuit of this application is integrated within an application-specific integrated circuit (ASIC). This ASIC mainly integrates five core modules: a power supply module, a clock module, a digital processing module, a register module, and a data latch module. Each module has a clear division of labor and works in concert to jointly realize core functions such as data storage, timing control, power-on reset, real-time data backup, and power-on rapid recovery, effectively improving the operational stability of the ASIC under complex power interference conditions. It should be emphasized that the data latch module is composed of multiple independent data latch circuits in parallel, and each data latch circuit can independently complete the power-off latching and power-on recovery of one bit of logic data. During the circuit design process, the number of circuits can be flexibly expanded according to the actual storage bit width requirements to adapt to application scenarios of multi-bit data synchronous backup storage. Specifically, multiple data latch circuits are arranged in parallel to form a multi-bit array structure. The enable terminal of each data latch circuit is uniformly connected to the global enable signal line, the clock detection terminal is uniformly connected to the global clock detection signal line, and each data terminal is connected to the corresponding bit channel of the multi-bit data bus.

[0039] The power supply module provides a stable power supply to all functional modules within the integrated circuit and outputs a power-on reset (POR) signal to the digital processing module, enabling real-time feedback of the power supply status. The clock module, serving as the system's timing reference unit, provides a unified synchronous clock for the digital processing module, register module, and data latch module, ensuring timing consistency across modules. The digital processing module, as the core control unit, possesses core functions such as data processing, logic control, signal monitoring, and instruction output. The data processing module establishes a bidirectional data interaction channel with the register module, enabling it to read and write configuration and runtime data according to the integrated circuit's operational requirements. Simultaneously, the digital processing module synchronously writes parallel backup data identical to that of the register module to the data latch circuit, achieving real-time backup of the register module's data. During the system's power-on recovery phase after a power outage, the digital processing module can directly read the backup data latched by the data latch module to quickly restore the register state before the power failure, effectively avoiding the time delay caused by system re-initialization and repeated logic operations in traditional power-on processes, significantly improving the integrated circuit's power-on recovery response speed.

[0040] At the circuit logic control level, the digital processing module determines the power-down / power-on condition based on the level of the received power-on reset (POR) signal, and precisely controls the working mode of the data latch module through the coordinated operation of the enable signal (EN) and the clock detection signal (NG).

[0041] The following is combined Figure 3 The timing diagram shown illustrates the operation of the data latch circuit in this application. As can be seen from the timing diagram, the data terminal completes one write update of backup data D within one clock cycle; the enable signal EN completes one level toggle within one clock cycle; the clock detection signal NG remains high when the power module is continuously and stably powered, is pulled down to low when the power module experiences an abnormal power failure, and is pulled up to high within several clock cycles after the power module is powered on again. The specific process is as follows: Under normal operating conditions, the power supply module provides a continuous and stable power supply, the power-on reset (POR) signal remains high, the clock module oscillates stably, and the digital processing module performs logic operations and parameter configurations normally. It writes the generated operating status data in parallel to the register module and the data latch module, allowing the data latch module to mirror and back up the data stored in the register module in real time. Under these conditions, the enable signal EN output by the digital processing module periodically toggles with the clock signal, the clock detection signal NG remains high, and the data latch circuit is always in a real-time synchronous backup state. The circuit dynamically updates the level state stored in capacitor C2 based on the input backup data D and the periodically toggling enable signal EN. Simultaneously, the in-phase output signal Q and the out-of-phase output signal QN output by the level conversion module change synchronously with the backup data D, maintaining a complementary logic relationship. During the first clock cycle, the backup data D input at the data terminal is at a high level. When the enable signal EN is high, the output of the AND gate is high and the output of the NOR gate is low, driving the first NMOS transistor to turn on and the second NMOS transistor to turn off. Simultaneously, the clock detection signal NG is high, turning on the third NMOS transistor. The power module forms a complete charging path through the first and second NMOS transistors, charging capacitor C2 to a high level. Correspondingly, the non-inverting output signal Q is high, and the out-of-inverting output signal QN is low.

[0042] When the enable signal EN transitions to low level during this cycle, the outputs of both the AND gate and the NOR gate are low. The first and second NMOS transistors are simultaneously turned off, cutting off the charging and discharging path of capacitor C2. Capacitor C2, relying on its own charge storage characteristics, stably latches the high-level state of the first half of the cycle. Correspondingly, the in-phase output signal Q remains high, and the out-of-phase output signal QN remains low, completing the backup of the high-level data for the current cycle.

[0043] During the second clock cycle, the backup data D input at the data terminal switches to a low level. When the enable signal EN is high, the output of the AND gate is low and the output of the NOR gate is high, driving the first NMOS transistor to turn off and the second NMOS transistor to turn on. Simultaneously, the clock detection signal NG is high, turning on the third NMOS transistor. Capacitor C2 forms a discharge path to ground through the third and second NMOS transistors, pulling capacitor C2 down to a low level. Correspondingly, the in-phase output signal Q flips to a low level, and the out-of-phase output signal QN flips to a high level.

[0044] When the enable signal EN transitions to low level during the current clock cycle, the outputs of both the AND gate and the NOR gate are low. The first and second NMOS transistors are simultaneously turned off, cutting off the charging and discharging path of capacitor C2 and latching the low-level state of capacitor C2. Correspondingly, the non-inverting output signal Q remains low, and the out-of-inverting output signal QN remains high, latching the low-level data for that cycle.

[0045] During subsequent normal operating clock cycles, the circuit repeats the closed-loop logic of sampling update and level latching, so that the in-phase output signal Q and the out-of-phase output signal QN always follow the state of the backup data D input from the data terminal in real time and are updated synchronously. When the enable signal EN is low, the current data state is latched to realize real-time mirror backup of the register data.

[0046] During the third clock cycle, the backup data D input to the data terminal switches back to a high level. When the enable signal EN is high, the circuit repeats the high-level sampling logic. The in-phase output signal Q flips to a high level, and the out-of-phase output signal QN flips to a low level. If a power failure occurs at this time, the power-on reset POR signal output by the power module flips to a low level. After the digital processing module detects the power-on reset POR signal level change, it determines that the power supply is abnormal and immediately pulls the enable signal EN down to a low level. At the same time, the power supply voltage drops, causing the clock module to stop oscillating, and the clock detection signal NG is synchronously pulled down to a low level. At this time, the data in the register module is lost due to the power interruption. However, under the control of the enable signal EN and the clock detection signal NG, the data latch circuit completely cuts off the charging and discharging path of capacitor C2. Capacitor C2 stably latches the high-level state before the power failure, realizing the power failure preservation of the backup data. The in-phase output signal Q remains high, and the out-of-phase output signal QN remains low.

[0047] When the power supply is powered on and reset, the power module resumes stable power supply, and the power-on reset POR signal flips to a high level. The clock module gradually starts oscillating and stabilizes. To avoid the problem of backup data being accidentally flushed due to clock jitter in the initial power-on period, the clock detection signal NG is delayed for several clock cycles before being pulled high. During this delay window, the data latch circuit maintains a data-locked state, allowing the digital processing module to accurately and reliably read the backup data and quickly write it back to the register module, completing a rapid recovery of the working state before the power failure. After the clock module stabilizes, the clock detection signal NG is pulled high, and the data latch circuit re-enters the real-time synchronous backup mode, returning to the normal operating closed loop.

[0048] In summary, the data latch circuit of this application can charge or discharge capacitor C2 according to the backup data written at the data terminal, and utilize the charge storage characteristics of capacitor C2 itself to lock and maintain the level state before power failure, thus completing the power failure latching of backup data. After the system is powered on again, the signal output by the data latch circuit can be quickly read, eliminating the system initialization and repetitive calculation process, allowing the entire circuit system to quickly return to the stable working state before power failure. It can also cope with various operating conditions where the power supply is abnormally interrupted by external interference, significantly improving the overall circuit operation stability and anti-interference capability, and enhancing the overall robustness of the circuit. Secondly, the circuit structure of this invention is simple and highly adaptable, and can be widely applied to various types of mixed-signal integrated circuits with different fabrication processes. Thirdly, a single data latch circuit can independently complete the power failure latching and power-on recovery of one bit of logic data. During the circuit design process, the number of data storage bits can be flexibly cascaded to expand the data storage bits according to the actual bit width requirements, meeting the needs of synchronous backup latching of multiple bits of data.

[0049] It should be emphasized that the above are merely preferred embodiments of the present invention and are not intended to limit the present invention in any way. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention shall still fall within the scope of the technical solution of the present invention.

Claims

1. A data latch circuit for quickly restoring the data in a register before the power failure upon power restoration after an abnormal power outage, characterized in that, include: Sampling module and level conversion module; The sampling module includes a data terminal, an enable terminal, and a capacitor C2; The data terminal is configured to receive backup data; The enabling terminal is configured to receive an enabling signal; The sampling module is configured as follows: When the enable signal is high, the capacitor C2 is selectively charged or discharged according to the backup data, so that the level state stored in the capacitor C2 is consistent with the backup data; When the enable signal is low, the charging and discharging path of capacitor C2 is cut off, and capacitor C2 latches and maintains the level state before the enable signal is pulled low. The level conversion module is configured to convert the level state stored in the capacitor C2 into a standard digital level, which is then read by the digital processing module during the power-on phase to quickly restore the backup data received by the data terminal before the power failure.

2. The data latch circuit according to claim 1, characterized in that, The sampling module also includes a clock detection terminal, which is configured to receive a clock detection signal; The sampling module is configured as follows: When the clock detection signal is high, the clock detection signal and the enable signal work together to selectively charge or discharge the capacitor C2, so that the level state stored in the capacitor C2 is consistent with the backup data; When the clock detection signal is low, the charging and discharging path of capacitor C2 is cut off.

3. The data latch circuit according to claim 2, characterized in that, The sampling module further includes a sampling logic unit, a first NMOS transistor, and a second NMOS transistor; The sampling logic unit generates two drive signals based on the backup data and the enable signal, which are respectively connected to the gates of the first NMOS transistor and the second NMOS transistor to control the turn-on and turn-off of the first NMOS transistor and the second NMOS transistor. The drain of the first NMOS transistor is connected to the power supply terminal, and the source is connected to the common node A, which is used to control the conduction and cutoff of the charging path of the capacitor C2 by the power supply terminal. The drain of the second NMOS transistor is connected to the common node A, and the source is connected to ground, which is used to control the conduction and cutoff of the discharge path of the capacitor C2 to ground.

4. The data latch circuit according to claim 3, characterized in that, The sampling module also includes a third NMOS transistor; the gate of the third NMOS transistor is used to receive the clock detection signal, the drain is connected to the common node A, and the source is connected to the first end of the capacitor C2.

5. The data latch circuit according to claim 3, characterized in that, The sampling logic unit includes AND gates, NOR gates, and NOT gates; The first input terminal of the AND gate is connected to the data terminal, the second input terminal is connected to the enable terminal, and the output terminal is connected to the gate of the first NMOS transistor. The first input terminal of the NOR gate is connected to the data terminal, the second input terminal is connected to the enable terminal via the NOT gate, and the output terminal is connected to the gate of the second NMOS transistor.

6. The data latch circuit according to claim 5, characterized in that, It also includes an inverting module; the inverting module is configured to invert the level state stored in the capacitor C2 and output an inverted level state.

7. The data latch circuit according to claim 6, characterized in that, The level conversion module has a non-inverting output terminal and an inverting output terminal; The level conversion module outputs complementary in-phase and in-phase standard digital levels based on the level state and the inverted level state, which are then read by the digital processing module upon power-up to restore the working state before power failure.

8. The data latch circuit according to claim 6, characterized in that, The inverting module includes a first PMOS transistor, a second PMOS transistor, a constant current source, and a fifth NMOS transistor; The gates of the first PMOS transistor and the second PMOS transistor are connected, and the drains of both are connected to the power supply. The source of the first PMOS transistor is grounded through the constant current source on one hand, and shorted to its own gate on the other hand. The source of the second PMOS transistor is connected to the drain of the fifth NMOS transistor; The gate of the fifth NMOS transistor is connected to the first terminal of the capacitor C2, the source is grounded, and its drain node serves as the output terminal of the inverting module, connected to the level conversion module.

9. The data latch circuit according to claim 6, characterized in that, The level conversion module includes a third PMOS transistor, a fourth PMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor; The gate of the sixth NMOS transistor is connected to the drain node of the fifth NMOS transistor, the source is grounded, and the drain is connected to the gate of the fourth PMOS transistor and the source of the third PMOS transistor, respectively. The gate of the seventh NMOS transistor is connected to the first terminal of the capacitor C2, the source is grounded, and the drain is connected to the gate of the third PMOS transistor and the source of the fourth PMOS transistor, respectively. The drains of the third PMOS transistor and the fourth PMOS transistor are connected to the power supply terminal.

10. An integrated circuit, characterized in that, It includes a power supply module, a clock module, a digital processing module, a register module, and a data latch module, wherein the data latch module includes at least one data latch circuit as described in any one of claims 1-9; The power module provides operating power to each module and outputs a power-on reset signal to the digital processing module; The clock module provides a synchronous operating clock for all modules; The digital processing module establishes a bidirectional data interaction channel with the register module to realize data writing and reading from the register module; The digital processing module establishes bidirectional data interaction channels with the register module and the data latch module respectively, for synchronously writing backup data consistent with the register module to the data latch circuit, and reading the standard digital signal output by the data latch circuit during the power-on recovery phase to complete the rapid recovery of the register data written before power failure.

11. The integrated circuit according to claim 10, characterized in that, The enable terminals of each of the data latch circuits are connected to the global enable signal line, the clock detection terminals are connected to the global clock detection signal line, and the data terminals are respectively connected to the corresponding bit channels of the multi-bit data bus.

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