Package substrate with capacitor and method of manufacturing the same
By setting alternating openings in the inner insulating layer and filling them with electrode plates, the problem of insufficient energy storage of the embedded capacitor in the integrated circuit substrate is solved, resulting in a significant increase in capacitance and high electrical performance of the packaging substrate.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- LEADING INTERCONNECT SEMICONDUCTOR TECHNOLOGY QINHUANGDAO CO LTD
- Filing Date
- 2025-01-21
- Publication Date
- 2026-07-21
AI Technical Summary
The energy storage capacity of the embedded capacitors in existing integrated circuit substrates is insufficient to meet the demands of increasingly complex electronic devices and high-performance computing.
Alternating first and second openings are provided inside the inner insulating layer, and first and second electrode plates are filled in them respectively. The electrode plates are constructed by local filling to increase the facing area between the electrode plates.
It significantly improves capacitance while maintaining a compact package substrate structure, and enhances electrical performance and reliability to meet the needs of high-frequency and high-voltage applications.
Smart Images
Figure CN122438342A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of packaging substrate manufacturing technology, and in particular to a packaging substrate with capacitors and a method for manufacturing the same. Background Technology
[0002] Embedded capacitors on integrated circuit substrates can reduce parasitic inductance in circuits, thereby improving signal transmission speed and stability. However, with the increasing complexity of electronic devices, the growing demand for longer battery life in portable devices, and the increasing power storage requirements in high-performance computing and communications, the existing power storage capacity of embedded capacitors on integrated circuit substrates is insufficient to meet practical application needs. Summary of the Invention
[0003] In view of this, it is necessary to provide a method for manufacturing a high-capacity, capacitor-equipped packaging substrate.
[0004] Additionally, it is necessary to provide a packaging substrate with capacitors.
[0005] A method for manufacturing a capacitor-equipped packaging substrate includes the steps of: providing an inner insulating layer, the inner insulating layer including opposing first and second surfaces; forming a first opening on the first surface, the depth of the first opening being less than the thickness of the inner insulating layer; forming a second opening on the second surface, the depth of the second opening being less than the thickness of the inner insulating layer; forming a first electrode plate on the first surface, a portion of the first electrode plate filling the first opening; forming a second electrode plate on the second surface, a portion of the second electrode plate filling the second opening, thereby obtaining a capacitor, wherein the capacitor includes the first electrode plate and the second electrode plate spaced apart.
[0006] A capacitor-equipped packaging substrate includes: an inner insulating layer comprising a first surface and a second surface facing each other; the first surface having a plurality of first openings spaced apart; and the second surface having a plurality of second openings spaced apart; the depth of both the first and second openings being less than the thickness of the inner insulating layer; a first electrode plate disposed on the first surface, a portion of which fills the plurality of first openings; and a second electrode plate disposed on the second surface, a portion of which fills the plurality of second openings.
[0007] The method for manufacturing a capacitor-equipped substrate provided in this application effectively increases the facing area between the electrode plates by setting alternating first and second openings inside the inner insulating layer and filling the first and second electrode plates therein, thereby achieving a significant increase in capacitance value. Attached Figure Description
[0008] Figure 1This is a schematic cross-sectional view of the inner insulating layer provided in an embodiment of this application.
[0009] Figure 2 for Figure 1 The diagram shows a cross-sectional view of the inner insulating layer with a first opening and a second opening.
[0010] Figure 3 for Figure 2 The diagram shows a cross-sectional view of the inner insulating layer with a first pre-plating layer and a second pre-plating layer.
[0011] Figure 4 for Figure 3 The diagram shows a cross-sectional view of the inner insulating layer after the first and second conductive electrode plates are installed.
[0012] Figure 5 for Figure 4 The diagram shows a cross-sectional view of the first conductive electrode plate after the first outer insulating layer has been applied.
[0013] Figure 6 for Figure 5 The diagram shows a cross-sectional view of the first outer insulating layer after the first outer circuit layer has been installed.
[0014] Figure 7 for Figure 6 The diagram shows a cross-sectional view of the first outer circuit layer after the first solder mask layer has been applied.
[0015] Explanation of main component symbols
[0016] Packaging substrate 800
[0017] 700 capacitors
[0018] Inner insulation layer 100
[0019] First surface 110
[0020] Second surface 120
[0021] First opening 111
[0022] Second opening 121
[0023] First electrode plate 200
[0024] Second electrode plate 210
[0025] First pre-plating layer 201
[0026] Second pre-plating layer 211
[0027] First outer insulating layer 300
[0028] Second outer insulating layer 310
[0029] First line layer 400
[0030] Second line layer 410
[0031] 500 Conductor
[0032] First weld resist layer 600
[0033] Second weld shielding layer 610
[0034] Thickness direction A
[0035] Length direction B
[0036] Distance from W1, W2, W3, W4
[0037] Thickness D3
[0038] Depths D1 and D2
[0039] The following detailed description, in conjunction with the accompanying drawings, will further illustrate this application. Detailed Implementation
[0040] To better understand the above-mentioned objectives, features, and advantages of this application, the application will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Many specific details are set forth in the following description to provide a thorough understanding of this application; the described embodiments are merely some, not all, of the embodiments described in this application.
[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The term "and / or" as used herein includes all and any combination of one or more of the associated listed items.
[0042] In the various embodiments of this application, for ease of description and not limitation, the term "connection" used in the patent application specification and claims is not limited to physical or mechanical connections, whether direct or indirect. Terms such as "upper," "lower," "above," "below," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship also changes accordingly.
[0043] Please see Figures 1 to 7 One embodiment of this application provides a method for manufacturing a packaging substrate 800 having a capacitor 700, including the following steps:
[0044] S1: Please see Figure 1 An inner insulating layer 100 is provided, comprising a first surface 110 and a second surface 120 opposite to each other. The inner insulating layer 100 has a thickness direction A and a length direction B. Along the thickness direction A, the first surface 110 and the second surface 120 are arranged parallel to each other.
[0045] In this embodiment, the inner insulating layer 100 is made of ceramic. In other embodiments, the inner insulating layer 100 can also be made of dielectric materials with different dielectric constants and breakdown strengths, such as resins with high glass transition temperatures, ceramic-polymer composite materials, etc., to meet the requirements of the packaging substrate 800 in high-frequency, high-density, and high-reliability scenarios.
[0046] S2: Please see Figure 2 A first opening 111 is provided on the first surface 110, the depth of the first opening 111 being less than the thickness of the inner insulating layer 100; and a second opening 121 is provided on the second surface 120, the depth of the second opening 121 being less than the thickness of the inner insulating layer 100.
[0047] In this embodiment, the positions and shapes of the first opening 111 and the second opening 121 are planned according to a pre-designed layout, and the first opening 111 and the second opening 121 are alternately arranged. Along the length direction B, the cross-sectional shape of each first opening 111 is approximately rectangular. Multiple first openings 111 are spaced apart, with approximately the same distance between any two adjacent first openings 111. The distance between the centers of any two adjacent first openings 111 is defined as W1. Similarly, along the length direction B, the cross-sectional shape of each second opening 121 is approximately rectangular. Multiple second openings 121 are spaced apart, with approximately the same distance between any two adjacent second openings 121. The distance between the centers of any two adjacent second openings 121 is defined as W2. Wherein, W1 = W2. Along the thickness direction A, the distance between the bottom of each first opening 111 and the second surface 120 is W3, and the distance between the bottom of each second opening 121 and the first surface 110 is W4, where W3 = W4.
[0048] In this embodiment, along the thickness direction A, the depth D1 of the first opening 111 and the depth D2 of the second opening 121 are both greater than half the thickness D3 of the inner insulating layer 100, thereby forming a larger effective overlapping area inside the inner insulating layer 100 to increase the capacitance value per unit area.
[0049] In other embodiments of this application, the distance between the plurality of first openings 111 and / or the distance between the plurality of second openings 121 may be different, and their cross-sectional shape may also be other polygonal, circular or with rounded corners, in order to adapt to different processing accuracy and electric field distribution requirements, or to reduce the problem of field strength concentration generated at the edges of the plurality of first openings 111 and / or the plurality of second openings 121.
[0050] S3: Please see Figures 3 to 4 A first electrode plate 200 is disposed on the first surface 110, and a portion of the first electrode plate 200 is filled into the first opening 111. A second electrode plate 210 is disposed on the second surface 120, and a portion of the second electrode plate 210 is filled into the second opening 121, thereby obtaining a capacitor 700.
[0051] In this embodiment, the capacitor 700 includes a first electrode plate 200 and a second electrode plate 210 spaced apart. The presence of the first opening 111 and the second opening 121 provides a crucial structural basis for the subsequent forming of the first electrode plate 200 and the second electrode plate 210. By partially filling the first opening 111 and the second opening 121, the first electrode plate 200 and the second electrode plate 210 are constructed in a curved and extended manner. Along the thickness direction A, the first electrode plate 200 and the second electrode plate 210 are arranged parallel to each other, and along the length direction B, the first electrode plate 200 and the second electrode plate 210 are also arranged parallel to each other.
[0052] Specifically, using electrode material deposition processes, such as electroplating and chemical vapor deposition, a first electrode plate 200 and a second electrode plate 210 are constructed on both sides of the inner insulating layer 100. The electrode material grows and fills along the edges of the first opening 111 and the second opening 121 and the surface of the inner insulating layer 100, thereby enabling the first electrode plate 200 and the second electrode plate 210 to bend and extend according to the shape of the first opening 111 and the second opening 121, respectively, changing the relatively regular and simple structural form of traditional flat electrode.
[0053] By adopting the above construction method, the relative area between the first electrode plate 200 and the second electrode plate 210 can be effectively increased. From the principle of capacitance, according to the formula for determining capacitance:
[0054]
[0055] Where C represents the capacitance, ε is the relative permittivity of the dielectric, S is the area of the two plates facing each other, and d is the distance between the two plates. With other conditions such as the relative permittivity of the dielectric and the distance between the plates remaining relatively stable, increasing the area of the plates facing each other can significantly increase the capacitance, thus achieving a high-capacitance effect. At the same time, this structural design does not additionally increase the space occupied by the entire capacitor 700 in the planar dimension.
[0056] In this embodiment, step S3 specifically includes:
[0057] S31: Please see Figure 3 A first pre-plating layer 201 is provided on the first surface 110, and a portion of the first pre-plating layer 201 fills the first opening 111. The first pre-plating layer 201 is made of copper and is formed by sputtering copper.
[0058] Specifically, the inner insulating layer 100 with the first surface 110 is first placed and fixed in the vacuum chamber of the sputtering equipment, and the chamber is evacuated to a high vacuum (e.g., below 10⁻³ Pa). Next, a copper target with a purity of 99.9% or higher is loaded, and the ion source is activated to generate a high-energy argon ion beam. This beam, accelerated, bombards the copper target, causing copper atoms to be sputtered out and diffuse towards the inner insulating layer 100, depositing within the first surface 110 and the first opening 111. This copper sputtering method has the advantage of achieving uniform and dense coating deposition.
[0059] S32: A first electroplating layer 202 is formed on the first pre-plating layer 201. Step S32 includes:
[0060] S321: A first photoresist pattern is formed on the first pre-plating layer 201. The first photoresist pattern has multiple first windows, and a portion of the first pre-plating layer 201 is exposed through the first windows to obtain an intermediate. The first photoresist pattern is formed by photolithography. For example, a suitable photoresist is first selected and uniformly coated on the surface of the first pre-plating layer 201. Then, it is exposed using a photolithography machine with a photomask. After that, it is developed with a developer to form a pattern containing the first windows according to the design, allowing a portion of the first pre-plating layer 201 to be exposed through the windows, preparing for subsequent electroplating.
[0061] S322: The first electroplating layer is formed within the first window using a vertical continuous electroplating method. Specifically, the intermediate body with the first photoresist pattern is first fixed on the fixture of the vertical continuous electroplating equipment, allowing the intermediate body to contact the electroplating solution. Next, an electroplating solution containing copper ions and other components is prepared, and the parameters are adjusted. Then, the vertical continuous electroplating equipment is started, with the intermediate body acting as the cathode and the copper anode immersed in the electroplating solution. Under the action of direct current, copper ions are deposited at the exposed first pre-plating layer 201 to form the first electroplating layer. Vertical continuous electroplating can achieve continuous, efficient, and uniform electroplating, ensuring a uniform and reliable electroplating layer quality, which is beneficial for subsequent electrode plate structure fabrication and the performance realization of capacitor 700.
[0062] S323: Remove the first photoresist pattern. Specifically, select a suitable remover according to the type of photoresist, then immerse the intermediate with the first photoresist pattern in a solution containing the remover, or use a spray method to allow the remover to fully contact the photoresist, thereby removing the first photoresist pattern without damaging the formed first electroplated layer.
[0063] S33: Etch the first electroplated layer and the first pre-plated layer 201 to form the first electrode plate 200. Specifically, first prepare an etching solution suitable for copper material (such as an acidic etching solution), then put the intermediate with the first electroplated layer and the first pre-plated layer 201 into the etching equipment, and start the etching by controlling the etching solution temperature, concentration, etching time and other parameters to dissolve and remove the excess part, leaving the corresponding part to form the first electrode plate 200 according to the design requirements.
[0064] In this embodiment, step S3 further includes:
[0065] S34: A second pre-plating layer 211 is formed on the second surface 120, and a portion of the second pre-plating layer 211 fills the second opening 121. Step S34 is performed simultaneously with step S32, and will not be described in detail here.
[0066] S35: A second electroplating layer is formed on the second pre-plating layer 211. In this embodiment, step S35 includes:
[0067] S351: A second photoresist pattern is formed on the second pre-plating layer 211. The second photoresist pattern has multiple second windows, and a portion of the second pre-plating layer 211 is exposed through the second windows. Specifically, step S351 is performed simultaneously with step S321, and will not be described in detail here.
[0068] S352: A second electroplating layer is formed in the second window by vertical continuous electroplating; step S352 is performed simultaneously with step S322, and will not be described again here.
[0069] S353: Remove the second photoresist pattern. Step S353 is performed simultaneously with step S323, and will not be described again here.
[0070] S36: Etch the second electroplating layer and the second pre-plating layer 211 to form the second electrode plate 210. Step S36 is performed simultaneously with step S33, and will not be described in detail here.
[0071] S4: Please see Figure 5 A first outer insulating layer 300 is provided on the first surface 110, the first outer insulating layer 300 covers the first electrode plate 200, and a portion of the first outer insulating layer 300 fills the first opening 111. A second outer insulating layer 310 is provided on the second surface 120, the second outer insulating layer 310 covers the second electrode plate 210, and a portion of the second outer insulating layer 310 fills the second opening 121.
[0072] In this embodiment, the first outer insulating layer 300 and the second outer insulating layer 310 can be made of one of polyimide (PI), polyethylene terephthalate (PET), polypropylene (PP), or polyethylene naphthalate (PEN).
[0073] S5: Please see Figure 6 A first circuit layer 400 is disposed on a first outer insulating layer 300, and a second circuit layer 410 is disposed on a second outer insulating layer 310. The first circuit layer 400 and the second circuit layer 410 are formed by a combination of photolithography and electroplating. Specifically, photoresist is first coated onto the surfaces of the first outer insulating layer 300 and the second outer insulating layer 310, and a circuit pattern window is formed by photolithography. Then, metal ions are deposited by electroplating, and finally, the photoresist is removed to obtain the first circuit layer 400 and the second circuit layer 410.
[0074] In other embodiments of this application, the first circuit layer 400 and the second circuit layer 410 can also be formed by chemical plating or sputtering. For example, in chemical plating, the insulating layer can be pretreated to give it catalytically active sites, then placed in a plating solution containing metal salts and reducing agents, and under suitable conditions, metal atoms are deposited to form the first circuit layer 400 and the second circuit layer 410 through a chemical reaction. In sputtering, the insulating layer is placed in a vacuum chamber, a corresponding metal is used as a target, and target atoms are deposited on the surface of the insulating layer under high-energy ion bombardment, with parameters controlled to form the first circuit layer 400 and the second circuit layer 410 according to a preset pattern.
[0075] S6: Please see Figure 6 A conductor 500 is installed between the first circuit layer 400 and the second circuit layer 410. Specifically, holes are drilled at the corresponding positions according to the design requirements, and debris and impurities are cleaned from the holes. Then, an electroplating solution containing suitable metal ions is prepared and the parameters are adjusted. Under the action of direct current, the metal ions are deposited on the hole wall, and the hole is filled with metal through electroplating to form the conductor 500.
[0076] S7: Please see Figure 7 A first solder resist layer 600 is provided on the first circuit layer 400, and a second solder resist layer 610 is provided on the second circuit layer 410. Specifically, the first solder resist layer 600 and the second solder resist layer 610 are typically made of photosensitive ink. This material has good insulation, chemical corrosion resistance, and a certain degree of hardness, and can effectively protect the first circuit layer 400 and the second circuit layer 410.
[0077] Compared with the prior art, the manufacturing method of the packaging substrate 800 provided in this application has the following advantages:
[0078] (i) Significantly improved capacitance: By setting alternating first openings 111 and second openings 121 inside the inner insulating layer 100, and filling the first electrode plate 200 and the second electrode plate 210 therein respectively, the facing area S between the electrode plates is effectively increased, thereby achieving a significant improvement in capacitance according to the above capacitance formula.
[0079] (ii) Compact structure: The manufacturing method, through the design of embedded capacitors, does not increase the space occupied by the packaging substrate in the planar dimension, so that the packaging substrate 800 can meet the high-density packaging requirements of electronic devices while maintaining a high capacitance value.
[0080] (III) Reliable manufacturing process: High-precision deposition processes such as sputtering and vertical continuous electroplating are adopted to ensure the uniformity and density of the first electrode plate 200 and the second electrode plate 210, thereby improving the electrical performance and reliability of the packaging substrate 800.
[0081] (iv) High adaptability: The shape and spacing of the openings can be adjusted according to different needs to adapt to different processing precision and electric field distribution requirements. At the same time, by reducing the concentration of field strength through design, the performance of the packaging substrate 800 in high frequency and high voltage applications is improved.
[0082] Please see Figure 7 An embodiment of this application also provides a packaging substrate 800 with a capacitor 700, including an inner insulating layer 100, a first electrode plate 200, and a second electrode plate 210. The inner insulating layer 100 includes a first surface 110 and a second surface 120 opposite to each other. The first surface 110 is provided with a plurality of first openings 111 spaced apart, and the second surface 120 is provided with a plurality of second openings 121 spaced apart. The depth of both the first openings 111 and the second openings 121 is less than the thickness of the inner insulating layer 100. The first electrode plate 200 is disposed on the first surface 110, and a portion of the first electrode plate 200 fills the plurality of first openings 111. The second electrode plate 210 is disposed on the second surface 120, and a portion of the second electrode plate 210 fills the plurality of second openings 121. Based on the above improved design, a larger capacitor 700 and better electrical characteristics can be obtained inside the packaging substrate 800, while ensuring mechanical strength and the feasibility of processing technology.
[0083] The above embodiments are only used to illustrate the technical solutions of this application and are not intended to limit it. Although this application has been described in detail with reference to the above preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions to the technical solutions of this application should not depart from the scope of the technical solutions of this application.
Claims
1. A method for manufacturing a packaged substrate with capacitors, characterized in that, Including steps: An inner insulating layer is provided, the inner insulating layer comprising opposing first and second surfaces; A first opening is provided on the first surface, and the depth of the first opening is less than the thickness of the inner insulating layer; A second opening is provided on the second surface, the depth of the second opening being less than the thickness of the inner insulating layer; A first electrode plate is disposed on the first surface, and a portion of the first electrode plate is filled into the first opening; A second electrode plate is disposed on the second surface, and a portion of the second motor plate is filled into the second opening to obtain a capacitor, wherein the capacitor includes the first electrode plate and the second electrode plate disposed at intervals.
2. The manufacturing method as described in claim 1, characterized in that, The depth of the first opening and the depth of the second opening are both greater than half the thickness of the inner insulating layer, and the first opening and the second opening are staggered along the length of the inner insulating layer.
3. The manufacturing method as described in claim 1, characterized in that, The step of "depositing a first electrode plate on the first surface" includes: A first pre-plating layer is provided on the first surface, and a portion of the first pre-plating layer fills the first opening; A first electroplating layer is formed on the first pre-plating layer; The first electroplated layer and the first pre-plated layer are etched to form the first electrode plate.
4. The manufacturing method as described in claim 3, characterized in that, The step "to form a first electroplating layer on the first pre-plating layer" includes: A first photoresist pattern is provided on the first pre-coating layer, and the first photoresist pattern is provided with a plurality of first windows, with a portion of the first pre-coating layer exposed in the first windows; The first electroplating layer is formed within the first window by a vertical continuous electroplating method; Remove the first photoresist pattern.
5. The manufacturing method as described in claim 1, characterized in that, The step of "depositing a second electrode plate on the second surface" includes: A second pre-plating layer is provided on the second surface, and a portion of the second pre-plating layer fills the second opening; A second electroplating layer is formed on the second pre-plating layer; The second electroplated layer and the second pre-plated layer are etched to form the second electrode plate.
6. The manufacturing method as described in claim 5, characterized in that, The step "to form a second electroplating layer on the second preplating layer" includes: A second photoresist pattern is provided on the second pre-coating layer, and the second photoresist pattern is provided with a plurality of second windows, with a portion of the second pre-coating layer exposed in the second windows; The second electroplating layer is formed within the second window by a vertical continuous electroplating method; Remove the second photoresist pattern.
7. The manufacturing method as described in claim 1, characterized in that, It also includes the following steps: A first outer insulating layer is provided on the first surface, and the first outer insulating layer covers the first electrode plate; A second outer insulating layer is provided on the second surface, and the second outer insulating layer covers the second electrode plate.
8. The manufacturing method as described in claim 7, characterized in that, It also includes the following steps: A first circuit layer is provided on the first outer insulating layer; A second line layer is provided on the second outer line layer; A conductor is provided between the first line layer and the second line layer.
9. The manufacturing method as described in claim 8, characterized in that, It also includes the following steps: A first solder resist layer is provided on the first circuit layer; A second solder mask layer is provided on the second circuit layer.
10. A packaging substrate with a capacitor, characterized in that, include: The inner insulating layer includes a first surface and a second surface opposite to each other. The first surface is provided with a plurality of first openings at intervals, and the second surface is provided with a plurality of second openings at intervals. The depth of the first openings and the second openings is less than the thickness of the inner insulating layer. A first electrode plate is disposed on the first surface, and a portion of the first electrode plate is filled with a plurality of the first openings; The second electrode plate is disposed on the second surface, and a portion of the second electrode plate is filled with a plurality of the second openings.