A method and system for automatically identifying a semiconductor dicing lane

Abstract

The application provides a kind of semiconductor cutting path automatic identification method, comprising the following steps: step 1: identify the straight line segment set in the semiconductor wafer image as candidate line segment set;Step 2: identify potential cutting path edge from candidate line segment;Step 3: identify multiple parallel cutting paths and locate the coordinates of each cutting path;Step 4: use the size of wafer design as calibration constraint to calibrate the cutting path identification result periodically;Step 5: extract sub-pixel center coordinates from calibrated cutting path area, and finally score according to line segment coverage and periodicity matching degree.The application realizes fast and accurate identification of semiconductor cutting path, improves the work efficiency and accuracy of semiconductor quantity detection machine.

Description

Technical Field

[0001] This invention relates to the field of semiconductor inspection technology, and in particular to an automatic identification method and system for semiconductor dicing based on periodic features and multi-channel parallel logic. Background Technology

[0002] In semiconductor metrology and inspection equipment, the dicing track is a critical reference for wafer alignment and chip positioning. With the continuous development of chip technology, existing semiconductor metrology and inspection equipment also faces some challenges. (See also...) Figure 1 , Figure 1 This is an optical microscopic image of a semiconductor wafer, showing multiple chip units.

[0003] The following challenges remain to be addressed: 1. Susceptibility to interference: As process nodes shrink, the internal texture of chips becomes increasingly complex. Traditional edge detection algorithms are highly susceptible to interference from repetitive metal structures within the chip, leading to errors in cut track identification. 2. Difficulty in multi-track extraction: During measurement, when multiple parallel cut tracks frequently appear within the field of view, existing technologies struggle to quickly and accurately extract the center lines of all cut tracks, failing to effectively eliminate interference and impacting detection efficiency and accuracy. Summary of the Invention

[0004] The present invention aims to solve the problems mentioned in the background art, and aims to provide an automatic identification method and system for semiconductor dicing tracks based on periodic features and multi-channel parallel logic, so as to achieve rapid and accurate identification of semiconductor dicing tracks and improve the working efficiency and accuracy of semiconductor quantity inspection equipment.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] This invention provides an automatic identification method for semiconductor dicing lines, comprising the following steps:

[0007] Step 1: Identify the set of straight line segments in the semiconductor wafer image as a candidate line segment set;

[0008] Step 2: Identify potential cutting edges from candidate line segments;

[0009] Step 3: Identify multiple parallel cutting tracks and locate the coordinates of each cutting track;

[0010] Step 4: Use the dimensions of the wafer design as a calibration constraint to perform periodic prior calibration on the dicing identification results;

[0011] Step 5: Extract sub-pixel center coordinates from the calibrated cutting area and give a final score based on line segment coverage and periodicity matching.

[0012] Furthermore, in the automatic semiconductor dicing identification method provided by this invention, step 1 specifically includes the following steps: 1) extracting the original line segment features in the semiconductor wafer image using a straight line segment detection algorithm; 2) extracting the horizontal line segment features using a directional filter. and vertical direction are Candidate line segments in two directions are selected, and stray angle interference is eliminated.

[0013] Furthermore, in the semiconductor dicing automatic identification method provided by the present invention, step 2 specifically includes the following steps: 1) Projecting candidate line segments onto the X-axis and Y-axis with weights respectively, the projection weights being based on the line segment length and gradient intensity; 2) Within the projection domain, using a dynamic threshold to find energy peak regions, each peak region found corresponds to a potential dicing edge.

[0014] Furthermore, in the automatic semiconductor dicing identification method provided by the present invention, step 3 specifically includes the following steps: 1) For the case where there are multiple dicing tracks in the same direction, the system sets a minimum physical spacing threshold; 2) Search for local maxima in the projection domain, identify and separate parallel peaks with a distance greater than the minimum physical spacing threshold; 3) Perform independent center positioning for each peak region, and the system simultaneously outputs the coordinates of multiple dicing tracks.

[0015] Furthermore, in the automatic semiconductor dicing identification method provided by this invention, in step 4, the spacing between all candidate dicing lines is first calculated to establish a spacing matrix, and then the following calibrations are performed: Validity verification: If the spacing between two lines conforms to a periodic pattern, that is, the spacing between two lines is equal to n times the pitch, where n is an integer, then the confidence score of the group of lines is increased; False feature removal: Isolated lines that do not conform to a periodic pattern are masked; Compensation mechanism: When a dicing line is missing features due to occlusion, prediction compensation is performed based on the position of the adjacent channel and the pitch parameter.

[0016] Furthermore, in the semiconductor dicing automatic identification method provided by the present invention, step 5 involves performing Gaussian fitting or grayscale centroid calculation on the calibrated dicing region to extract the sub-pixel center coordinates.

[0017] Furthermore, in the automatic semiconductor dicing identification method provided by the present invention, the Gaussian fitting operation is used to model the grayscale distribution of the dicing and extract the center coordinates.

[0018] Furthermore, in the semiconductor dicing automatic identification method provided by the present invention, the gray-scale centroid is calculated by weighted average of the pixel gray-scale values ​​within the region to obtain the center position.

[0019] Furthermore, in the automatic semiconductor dicing identification method provided by this invention, the scoring model in step 5 is as follows:

[0020]

[0021] In the formula, Indicates the final score; Indicates the basic contrast ratio score; Indicates projection coverage; Indicates the minimum periodic residual; Periodic matching degree.

[0022] The formula for calculating periodic residuals is as follows:

[0023]

[0024] In the formula, Indicates periodic residuals, The closer the two lines are to 0, the more they conform to a periodic pattern.

[0025] For the remainder function; Indicates the positions of the two candidate cutting paths; This indicates the theoretical design size of the wafer.

[0026] This invention also provides an automatic semiconductor kerf identification system for implementing the aforementioned automatic semiconductor kerf identification method, comprising: a straight line segment detection module, which extracts original straight line segment features from an image using the LSD algorithm; a filtering and screening module, which extracts candidate line segment sets in both horizontal and vertical directions using a directional filter to eliminate stray angle interference; an axial projection module, which projects candidate line segments onto the X-axis and Y-axis with weights; a kerf identification module, which uses a dynamic threshold to find energy peak regions and identify potential kerf edges; a multi-kerf parallel identification module, which identifies multiple kerfs based on a set minimum physical distance threshold; a periodic prior calibration module, which performs periodic prior calibration on all candidate kerfs; a sub-pixel localization module, which performs Gaussian fitting or gray-scale centroid calculation on the calibrated kerf regions to extract sub-pixel center coordinates; and a scoring module, which scores the detection results.

[0027] Compared with the prior art, the present invention has the following beneficial effects:

[0028] 1. Strong anti-interference capability: This invention introduces the wafer design size as a calibration constraint, establishes a spacing matrix, calculates the spacing between candidate dicing channels, and improves the confidence score and eliminates false features based on whether it conforms to a periodic pattern. This effectively solves the interference problem of chip internal structures resembling dicing channels and improves the recognition accuracy.

[0029] 2. High efficiency: This invention uses multi-channel parallel recognition logic to set a minimum physical distance threshold and local peak detection in the projection domain. Multiple lines are positioned in one projection, which can quickly process multiple parallel cutting channels in a single field of view, thus improving the machine's WPH (output per hour).

[0030] 3. Support for non-perfect imaging: In the method of this invention, when the cutting path is missing features due to occlusion or other reasons, prediction compensation is performed based on the position and size parameters of the adjacent channels, which solves the problem of "flow interruption" in the cutting path caused by process defects and greatly improves the stability of the machine. Attached Figure Description

[0031] Figure 1 It is an optical microscopic image of a semiconductor wafer;

[0032] Figure 2 This is a simplified flowchart of the semiconductor dicing track automatic identification method in an embodiment of the present invention;

[0033] Figure 3 This is a schematic diagram of extracting straight line segments from an image in an embodiment of the present invention;

[0034] Figure 4 This is a schematic diagram of the energy peak value in an embodiment of the present invention;

[0035] Figure 5 This is a schematic diagram of the parallel peak values ​​in an embodiment of the present invention for identifying and separating distances greater than the minimum physical distance threshold;

[0036] Figure 6 This is a schematic diagram of the compensation mechanism in an embodiment of the present invention;

[0037] Figure 7 This is a schematic diagram of the Gaussian fitting process in an embodiment of the present invention. Detailed Implementation

[0038] To make the technical means, creative features, objectives and effects of the present invention easy to understand, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings.

[0039] Please see Figure 2 This embodiment provides an automatic semiconductor dicing trace identification method based on periodic features and multi-channel parallel logic, including the following steps:

[0040] Step 1: Line Feature Extraction and Initial Screening (Please refer to...) Figure 3 )

[0041] 1) Extract raw line segment features from semiconductor wafer images using the Line Segment Detection (LSD) algorithm;

[0042] 2) Extract the horizontal direction using a directional filter. and vertical direction are Candidate line segments in two directions are selected, and stray angle interference is eliminated.

[0043] Step 2: Axial Projection Clustering

[0044] 1) Project the candidate line segments onto the X-axis and Y-axis respectively with weights, where the projection weights are based on the line segment length and gradient strength;

[0045] 2) Within the projection domain, use a dynamic threshold to find the energy peak region (see [link to relevant documentation]). Figure 4 Each peak region found corresponds to a potential cutting edge.

[0046] Step 3: Multichannel parallel recognition (see [link]) Figure 5 )

[0047] 1) For situations where there are multiple cutting paths in the same direction, the system sets a minimum physical spacing threshold;

[0048] 2) Search for local maxima within the projection domain, identify and separate parallel peaks whose distance is greater than the minimum physical spacing threshold;

[0049] 3) Perform independent center positioning for each peak region to ensure that the system can output the coordinates of multiple cutting channels simultaneously.

[0050] Step 4: Periodic Prior Calibration

[0051] By using the wafer design size (Pitch) as a calibration constraint, spatial constraint verification is performed on the detection results. Interference textures inside the chip are filtered out by the pitch matching degree, and the prediction and recovery of missing features are supported.

[0052] First, the system calculates the spacing between all candidate cutting paths and establishes a spacing matrix. Then, the following calibration is performed:

[0053] Validation: If the spacing between the two lines follows a periodic pattern, that is, the spacing between the two lines is equal to n times the pitch, where n is an integer, then the confidence score of the set of lines is increased.

[0054] False feature removal: Masking out isolated lines that do not conform to periodic patterns.

[0055] Compensation mechanism: Please refer to Figure 6 When a cutting channel is missing features due to occlusion, prediction compensation is performed based on the location of neighboring channels and the pitch parameter.

[0056] Step 5: Subpixel localization and scoring

[0057] Gaussian fitting or gray-scale centroid calculation is performed on the calibrated cutting area to extract the sub-pixel center coordinates. The detection and recognition results are then scored based on the line segment coverage and periodic matching degree. The line segment coverage is used to evaluate the completeness of the recognition, while the periodic matching degree is used to verify the consistency of the results.

[0058] Gaussian fitting: Please refer to Figure 7 The grayscale distribution of the cutting path is modeled, and the center coordinates are accurately extracted to achieve sub-pixel level positioning.

[0059] Gray-scale centroid calculation: Based on the weighted average of pixel gray-scale values ​​within the region, quickly obtain the center position with high precision.

[0060] The confidence scoring model is as follows:

[0061]

[0062] In the formula, Indicates the final score; Indicates the basic contrast ratio score; Indicates projection coverage; Indicates the minimum periodic residual; Periodic matching degree.

[0063] The above model comprehensively considers multiple key factors such as the basic contrast of the cutting path, the coverage of the projection threshold, and the periodic matching degree, and finally gives a confidence score between 0 and 1 to quantitatively evaluate the reliability of the detection and recognition results.

[0064] The periodic residuals are calculated as follows:

[0065]

[0066] In the formula, Indicates periodic residuals, The closer the two lines are to 0, the more they conform to a periodic pattern.

[0067] For the remainder function; Indicates the positions of the two candidate cutting paths; This indicates the theoretical design size of the wafer.

[0068] This invention also provides an automatic semiconductor kerf identification system. This system executes the steps of the aforementioned automatic semiconductor kerf identification method. The system includes a straight line segment detection module, a filtering module, an axial projection module, a kerf identification module, a multi-channel parallel identification module, a periodic prior calibration module, a sub-pixel localization module, and a scoring module. The straight line segment detection module uses the LSD algorithm to extract the original straight line segment features from the image. The filtering module extracts candidate line segment sets in both horizontal and vertical directions using a directional filter, eliminating stray angle interference. The axial projection module projects the candidate line segments onto the X and Y axes with weights. The kerf identification module uses a dynamic threshold to find energy peak regions and identify potential kerf edges. The multi-channel parallel identification module identifies multiple kerfs based on a set minimum physical distance threshold. The periodic prior calibration module performs periodic prior calibration on all candidate kerfs. The sub-pixel localization module performs Gaussian fitting or gray-level centroid calculation on the calibrated kerf regions to extract sub-pixel center coordinates. The scoring module uses a confidence scoring model to give a final score to the detection results.

[0069] The above embodiments are merely preferred embodiments of the present invention and are not intended to limit the scope of protection of the present invention. For those skilled in the art, the present invention can have various modifications and variations. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A method for automatic identification of a semiconductor dicing lane, characterized by, Includes the following steps: Step 1: Identify the set of straight line segments in the semiconductor wafer image as a candidate line segment set; Step 2: Identify potential cutting edges from candidate line segments; Step 3: Identify multiple parallel cutting tracks and locate the coordinates of each cutting track; Step 4: Use the dimensions of the wafer design as a calibration constraint to perform periodic prior calibration on the dicing identification results; Step 5: Extract the sub-pixel center coordinates of the calibrated cutting area, and give a final score to the cutting area recognition result based on the line segment coverage and periodic matching degree.

2. The method of claim 1, wherein the step of automatically identifying the semiconductor dicing lane comprises the steps of: automatically identifying the semiconductor dicing lane by using a neural network. Its features are: Step 1 specifically includes the following steps: 1) Extract the original line segment features from the semiconductor wafer image using a line segment detection algorithm; 2) Extract the candidate line segment set in horizontal direction by directional filter and in vertical direction by directional filter and remove the spurious angle interference.

3. The method for automatic identification of semiconductor dicing tracks as described in claim 1, characterized in that: wherein Step 2 specifically includes the following steps: 1) Project the candidate line segments onto the X-axis and Y-axis respectively with weights, where the projection weights are based on the line segment length and gradient strength; 2) Within the projection domain, use dynamic thresholds to find energy peak regions. Each peak region found corresponds to a potential cutting edge.

4. The method for automatic identification of semiconductor dicing tracks as described in claim 1, characterized in that: wherein Step 3 specifically includes the following steps: 1) For situations where there are multiple cutting paths in the same direction, the system sets a minimum physical spacing threshold; 2) Search for local maxima within the projection domain, identify and separate parallel peaks whose distance is greater than the minimum physical spacing threshold; 3) Each peak region is independently centered, and the system outputs the coordinates of multiple cutting channels simultaneously.

5. The method of claim 1, wherein the semiconductor street is automatically recognized. Its features are: In step 4, the spacing between all candidate cutting paths is first calculated to establish a spacing matrix, and then the following calibration is performed: Validity verification: If the spacing between the two lines conforms to a periodic pattern, that is, the spacing between the two lines is equal to n times the pitch, where n is an integer, then the confidence score of the set of lines is increased. False feature removal: Masking isolated lines that do not conform to periodic patterns; Compensation mechanism: When a cutting channel is missing features due to occlusion, prediction compensation is performed based on the location of neighboring channels and the pitch parameter.

6. The method for automatic identification of semiconductor dicing tracks as described in claim 1, characterized in that: wherein, In step 5, Gaussian fitting is performed on the calibrated cutting area: the gray-scale distribution of the cutting area is modeled and the center coordinates are extracted.

7. The method for automatic identification of semiconductor dicing tracks as described in claim 1, characterized in that: in, In step 5, grayscale centroid calculation is performed on the calibrated cutting area: the center position coordinates are obtained based on the weighted average of the pixel grayscale values ​​within the area.

8. The method for automatic identification of semiconductor dicing tracks as described in claim 1, characterized in that: wherein, The scoring model in step 5 is as follows: In the formula, Indicates the final score; Indicates the basic contrast ratio score; Show projection coverage; Indicates the minimum periodic residual; Periodic matching degree.

9. An automatic semiconductor dicing identification system, used to implement the automatic semiconductor dicing identification method as described in any one of claims 1-8, comprising: The line segment detection module uses the LSD algorithm to extract the original line segment features from the image. The filtering module extracts candidate line segment sets in both horizontal and vertical directions using a directional filter, eliminating stray angle interference. The axial projection module is used to project candidate line segments onto the X-axis and Y-axis with weights, respectively. The cutting path identification module uses dynamic thresholds to find energy peak areas and identify potential cutting path edges; The multi-channel parallel recognition module identifies multiple cutting channels based on a set minimum physical distance threshold. The periodic prior calibration module is used to perform periodic prior calibration on all candidate cutting paths; The subpixel positioning module is used to perform Gaussian fitting or grayscale centroid calculation on the calibrated cutting area to extract the subpixel center coordinates; The scoring module is used to give a final score to the detection results.

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