A multi-channel cable continuity and wire sequence automatic detection method and system

Abstract

The application relates to the technical field of cable detection, and discloses a multi-channel cable on-off and line sequence automatic detection method and system, which comprises the following steps: loading a corresponding standard connection mapping relationship according to a received detection mode instruction, and configuring a single-chip microcomputer to generate a serial mask signal and a synchronous timing control signal; the single-chip microcomputer sends the serial mask signal to a cascaded shift register group, and the shift register group converts the serial mask signal into multi-channel parallel excitation levels under the driving of the timing control signal and sequentially injects the multi-channel parallel excitation levels into the input end of a measured cable. By adopting the technical means that the single-chip microcomputer configures the serial mask signal and the cascaded shift register group converts the serial mask signal into the multi-channel parallel excitation levels, the detection speed of the multi-channel cable is improved, and through bit-by-bit logical comparison and voltage amplitude double-threshold determination between a measured connection matrix and a standard mapping matrix, the accuracy and efficiency of fault identification are improved.

Description

Technical Field

[0001] This invention relates to the field of cable testing technology, specifically to a method and system for automatic detection of multi-channel cable continuity and wiring sequence. Background Technology

[0002] In the fields of industrial production and rail transit equipment operation and maintenance, the continuity and correct wiring sequence of multi-core cables are core elements for ensuring stable equipment operation. This is especially true for customized multi-core cables in rail transit lines (such as the LVDS customized cabling for the West Coast Express), whose wiring sequence is special and whose application scenarios are demanding. The reliability of cable connections directly affects the normal operation of rail transit on-board equipment and station equipment. Currently, the industry mainly relies on manual operation for the inspection of multi-core cables. For cables with a large number of cores, such as 28-core cables, manual inspection has become an important procedure in equipment operation and maintenance and cabling modification. The aim is to confirm the continuity and wiring sequence of the cable by inspecting each core, so as to avoid equipment damage and operational failures caused by cable faults.

[0003] In existing cable testing methods, traditional manual testing uses simple tools such as multimeters to measure continuity and check wire sequence core by core. In some scenarios, simple continuity indicator devices are used to assist in testing. However, as the customization level of rail transit equipment increases and the requirements for operation and maintenance efficiency rise, traditional testing methods are gradually becoming unable to meet the high-precision and high-efficiency testing needs of the rail transit industry. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides a method and system for automatic detection of multi-channel cable continuity and wiring sequence, solving the problem of failing to meet the high-precision and high-efficiency detection requirements of the rail transit industry.

[0005] To achieve the above objectives, the present invention provides the following technical solution: a method for automatic detection of continuity and wiring sequence of multi-channel cables, comprising the following steps: The corresponding standard connection mapping relationship is loaded according to the received detection mode instruction, and the microcontroller is configured to generate serial mask signal and synchronous timing control signal; The microcontroller sends the serial mask signal to the cascaded shift register group. Driven by the timing control signal, the shift register group converts the serial mask signal into multiple parallel excitation levels and injects them sequentially into the input end of the cable under test. While injecting the excitation level, the microcontroller drives a multi-channel analog switch to synchronously select the corresponding channel at the output end of the cable under test, and obtains the induced level data at the output end in real time. The induced voltage level data is compared with the standard connection mapping relationship to identify abnormal induced voltage and channel mapping deviation, and to generate fault identification results including open circuit, out-of-order and loose connection states. The fault identification results are packaged and uploaded to the host computer. The topology diagram of cable connectivity is dynamically updated through a graphical interface, and the hardware indicator lights are driven to provide status feedback. The system stores data records including test time, cable identification, and fault identification results into a database and generates exportable test reports based on user instructions.

[0006] Preferably, loading the corresponding standard connection mapping relationship includes the following steps: Obtain the cabling mode selected by the user, which includes a custom cabling mode and a general cable mode; Retrieve the above wiring pattern from the preset database, and index the logical correspondence table of input and output channels based on the instructions issued under the wiring pattern; A judgment benchmark matrix is ​​constructed based on the logical correspondence table and then sent to the microcontroller.

[0007] Preferably, the step of converting the serial mask signal into multiple parallel excitation levels includes the following steps: A continuous displacement clock signal is generated according to a preset scanning frequency as the timing control signal, and it is synchronously transmitted to each cascaded shift register. At the start of the shift clock cycle, a high-level start pulse is injected into the input of the first-stage shift register as the serial mask signal; During subsequent shift clock cycles, the serial mask signal is passed bit by bit through the cascaded shift register group by the shift control logic, and a shift level synchronized with the clock is generated at the parallel output of each shift register. The shifted level state is latched to the output buffer using a latch control signal, thereby forming a single high-level scan excitation that is continuous in time and isolated in space at multiple parallel output ports as the excitation level.

[0008] Preferably, the real-time acquisition of the sensing level data at the output terminal includes the following steps: According to the timing logic synchronized with the excitation level, a multi-bit binary address control signal is generated and sent to the acquisition array composed of multiple analog switch chips; The address control signal sequentially switches the conduction channels of the analog switch, thereby connecting each physical channel of the output end of the cable under test to the signal acquisition pin of the microcontroller one by one. During the conduction of each channel, the returned voltage signal is sampled by the high-speed analog-to-digital converter integrated by the microcontroller to obtain the original quantized value representing the physical connection status of each channel; The quantized values ​​are filtered to obtain an inductive level data stream that reflects the true level state of the output terminal, and then transmitted to the subsequent judgment stage.

[0009] Preferably, comparing the sensed level data with the standard connection mapping relationship includes the following steps: The acquired channel sensing level data are arranged according to the sampling time sequence to construct a measured connection matrix that reflects the current cable connection status. The measured connection matrix is ​​compared bit by bit with the preset standard connection mapping relationship, and the comparison results are used to detect whether there is a discrepancy between the excitation channel and the response channel. The amplitude variation characteristics of the induced level data stream are analyzed to identify the physical link connectivity performance, and the differential information generated by the comparison is extracted as the basis for fault determination.

[0010] Preferably, generating fault identification results including open circuit, out-of-order, and loose connection states includes the following steps: Extract the voltage amplitude characteristics and location topology characteristics of each channel from the original fault determination criteria; Based on the comparison results between the voltage amplitude characteristics and the preset threshold, open circuit faults and loose connection faults are identified; Based on the comparison results between the location topology features and the standard connection mapping relationship, line sequence misorder and short circuit faults are identified, and the identification results of each channel are integrated to form a unified fault identification result set.

[0011] Preferably, the step of dynamically updating the cable connectivity topology diagram through a graphical interface and synchronously driving hardware indicator lights for status feedback includes the following steps: The parsed fault identification results are mapped to the virtual connector model on the host computer interface. By changing the display status of the corresponding channel node, the visual rendering of the physical status of the cable is achieved. Based on the fault type defined in the fault identification results, the detailed text description is updated synchronously in the sidebar of the interface to locate the starting and ending channel indices of the fault. The microcontroller sends specific drive level pulses to the indicator light array on the hardware board through the general purpose input / output port; Different combinations of pulse frequencies or levels are used to control indicator lights to generate different visual feedback, thereby presenting the detection results synchronously on the software interface and the hardware terminal.

[0012] Preferably, storing the data records containing detection time, cable identification, and fault identification results into the database includes the following steps: The system clock is invoked to obtain the current real-time date and time, and combined with the cable type identifier generated by the current detection mode, a unique retrieval header for the data record is constructed. The identified channel on / off status, fault type, and specific out-of-order mapping relationship are formatted and transformed into structured data entries that can be recognized by the database. The database connection engine associates the generated search header with the corresponding structured data entries and automatically updates the database index for retrieval.

[0013] Preferably, generating an exportable test report based on user instructions includes the following steps: Obtain the report export command triggered by the user on the host computer interface, and retrieve the preset time period parameters or cable batch filtering conditions. Based on the filtering criteria, perform a correlation query in the database to extract matching detection time, cable mode, on / off status of each channel, and detailed fault location data; The extracted raw data is serialized according to the preset report template, and the detection results containing logical judgments are converted into text descriptions and statistical summaries. Call the file processing interface to write the serialized content to a CSV file and save it to the storage path specified by the user.

[0014] Preferably, a multi-channel cable continuity and wiring sequence automatic detection system includes the following modules: The mode configuration module is used to load the corresponding standard connection mapping relationship according to the received detection mode instruction, and configure the generation of serial mask signal and synchronous timing control signal; The excitation injection module is used to convert the serial mask signal into multiple parallel excitation levels and inject them sequentially into the input end of the cable under test under the drive of the timing control signal. The selection acquisition module is used to synchronously select the corresponding channel at the output end of the cable under test and acquire the induction level data stream at the output end in real time. The comparison and identification module is used to compare the induced level data stream with the standard connection mapping relationship, identify induced voltage abnormalities and channel mapping deviations, and generate fault identification results. The status feedback module is used to encapsulate and upload the fault identification results, dynamically update the cable connectivity status topology diagram through a graphical interface, and synchronously drive hardware indicator lights to provide status feedback. The report storage module is used to store data records containing detection time, cable identification, and fault identification results into the database, and generate detection reports according to user instructions.

[0015] This invention provides a method and system for automatic detection of continuity and wiring sequence in multi-channel cables. It has the following beneficial effects: 1. This invention improves the detection speed of multi-channel cables by using a microcontroller to configure serial mask signals and converting them into multi-channel parallel excitation levels with a cascaded shift register group. Combined with synchronous gating of multiple analog switches and high-speed analog-to-digital conversion sampling, it also improves the accuracy of identifying faults such as open circuits, out-of-order connections, short circuits, and loose connections by comparing the measured connection matrix with the standard mapping matrix bit by bit and determining the voltage amplitude with dual thresholds.

[0016] 2. This invention dynamically loads customized cabling or general cable routing modes on the host computer and issues a judgment benchmark matrix, enabling the detection system to automatically adjust the judgment criteria according to different cable specifications. Combined with visualization rendering and real-time feedback from the hardware indicator array, it lowers the technical threshold for operators and can flexibly meet the cable detection needs of various complex scenarios such as laboratory research and development and industrial production line quality inspection.

[0017] 3. This invention converts the test results into structured data entries and stores them in a non-volatile database by calling a unique search header. It also retrieves filtering operators for correlation queries according to user instructions and finally automatically serializes and generates a digital test report. This achieves closed-loop management of the entire lifecycle of test data from acquisition and judgment to traceability and export, ensuring the objectivity, authenticity and immutability of the test results. Attached Figure Description

[0018] Figure 1 This is a flowchart of the method of the present invention; Figure 2 This is a system architecture diagram of the present invention. Detailed Implementation

[0019] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Example 1:

[0020] Please see the appendix Figure 1 This invention provides a method for automatic detection of continuity and wiring sequence of multi-channel cables, comprising the following steps: The corresponding standard connection mapping relationship is loaded according to the received detection mode instruction, and the microcontroller is configured to generate serial mask signal and synchronous timing control signal; Furthermore, loading the corresponding standard connection mapping relationship includes the following steps: Obtain the cabling mode selected by the user, which includes custom cabling mode and general cable mode; Retrieve the above wiring pattern from the preset database, and index the logical correspondence table of input and output channels based on the instructions issued under the wiring pattern; A judgment benchmark matrix is ​​constructed based on the logical correspondence table and then sent to the microcontroller. Specifically, the system first responds to the user's detection request via the interactive interface and captures the cabling mode selection command. If the general cable mode is selected, the host computer retrieves a logical mapping table conforming to industry standards from a preset database. If the custom cabling mode is selected, the system extracts the user-defined specific topology logic and retrieves the matching input and output channel index information through the database connection engine. To transform the abstract physical wiring sequence into a digital judgment benchmark, a judgment benchmark matrix is ​​dynamically constructed in memory based on the retrieved logical mapping table. The criterion matrix is ​​represented as follows: ; in, This represents the total number of physical channels at the input end of the cable being tested. Represents the total number of physical channels at the output end of the cable being tested, and the row index in the matrix. Corresponding to the channel number of the input terminal, column index The corresponding output channel number, when the standard matching relationship is defined as the input channel number... Channel and output terminal When the path is in the preset connection state, this matrix element The quantization value is assigned a high logic level characteristic value of 1. If not connected in the standard state, the element will be... The quantized value is assigned a logic low level characteristic value of zero. This allows for precise mapping of the desired topological features of each physical link within the cable through the rows and columns of the matrix. Subsequently, the host computer encapsulates this judgment benchmark matrix into a standard communication data frame and sends it to the microcontroller's memory buffer. After parsing the matrix, the microcontroller configures the overflow interrupt period of its internal timer and the output state of its general-purpose input / output ports according to the total number of channels. It generates a continuous displacement clock signal as a timing control signal according to a preset scanning frequency. At the beginning of this displacement clock cycle, a high-level start pulse signal is injected into the input of the cascaded shift register group as a row scan instruction. This enables the preset wiring topology to be directly converted into hardware control logic for the subsequent cascaded shift register group to pass the scan excitation bit by bit. This allows the system to automatically adjust the judgment criteria for cables of different specifications and wiring patterns. It not only achieves dynamic adaptive adjustment of the detection logic according to the cable connection characteristics but also provides a fundamental logical reference for the subsequent bit-by-bit logical comparison of the measured connection matrix and the standard mapping relationship, improving the automation level of multi-channel cable detection and the real-time response of the system.

[0021] The microcontroller sends the serial mask signal to the cascaded shift register group. Driven by the timing control signal, the shift register group converts the serial mask signal into multiple parallel excitation levels and injects them into the input end of the cable under test in sequence. Furthermore, converting the serial mask signal into multiple parallel excitation levels includes the following steps: A continuous displacement clock signal is generated according to a preset scanning frequency as a timing control signal, and it is synchronously transmitted to each cascaded shift register. At the start of the shift clock cycle, a high-level start pulse is injected into the input of the first-stage shift register as a serial mask signal; During subsequent shift clock cycles, the serial mask signal is passed bit by bit through the cascaded shift register group by the shift control logic, and a shift level synchronized with the clock is generated at the parallel output of each shift register. The shifted level state is latched to the output buffer using a latch control signal, thereby forming a single high-level scanning excitation that is continuous in time and isolated in space at multiple parallel output ports as the excitation level. Specifically, the microcontroller configures its internal timer according to a preset scanning frequency, periodically toggling the states of the input and output pins to generate a continuous square wave signal. This square wave signal is synchronously transmitted to the shift clock input of the cascaded shift register group as a shift clock signal. During the first pulse period of the shift clock, the microcontroller injects a high-level start pulse with a pulse width equal to the clock period into the data input of the first-stage shift register. This start pulse serves as the initial serial mask signal. Subsequently, triggered by the rising edge of each subsequent shift clock, this high-level start pulse passes through the shift clock input of the cascaded shift register. Bit-wise logic is passed from the data output pin of the current stage to the data input pin of the next stage, thus forming a bit-by-bit shift process on the time axis. This ensures that the parallel output of each shift register generates a shift level synchronized with the clock. After the start pulse completes the shift of the predetermined number of channels, the microcontroller sends a latch control signal to the latch control terminal, latching the level state stored in each shift register at this time into the output buffer. This buffer is then output to the input of the cable under test through the output port in a spatially isolated manner, forming a single-channel high-level scan excitation that is continuously progressive in time. The excitation output matrix is ​​defined as follows: ; in, Representative at the The input terminal at the nth scan time The level status of each channel, This represents the total number of scan steps. The total number of cable input channels satisfies: ; That is, if and only if at the scan time With channel index When the values ​​are equal, the output is high; otherwise, it is low. Through the conversion of the shift register hardware logic, the serial data is interpreted and reconstructed in the time and spatial domains, ensuring that only one physical channel is applied with a single high-level scanning excitation at any given time. This eliminates the intermodulation interference that may be caused by the simultaneous injection of multiple signals, and improves the steepness and stability of the scanning waveform.

[0022] While injecting the excitation level, the microcontroller drives a multi-channel analog switch to synchronously select the corresponding channel at the output end of the cable under test, and obtains the induced level data at the output end in real time. Furthermore, acquiring the real-time sensing level data at the output terminal includes the following steps: According to the timing logic synchronized with the excitation level, a multi-bit binary address control signal is generated and sent to the acquisition array composed of multiple analog switch chips; By sequentially switching the conduction channels of the analog switch using the address control signal, each physical channel of the output end of the cable under test is connected to the signal acquisition pin of the microcontroller one by one. During the conduction of each channel, the returned voltage signal is sampled by the high-speed analog-to-digital converter integrated by the microcontroller to obtain the original quantized value representing the physical connection status of each channel; The quantized values ​​are filtered to obtain the induced level data stream that reflects the true level state of the output terminal, and then the data stream is passed to the subsequent judgment stage. Specifically, while the microcontroller injects an excitation level into the input terminal, its internal timing controller synchronously generates a set of multi-bit binary address control signals according to the current scan step. These address signals are then sent in real-time and in parallel through the address bus to a data acquisition array composed of multiple cascaded analog switch chips. Driven by the address logic, the data acquisition array sequentially switches its internal analog switch channels, connecting each physical channel of the cable under test output terminal to the microcontroller's signal acquisition pins according to a preset timing relationship. During the stable period of each physical channel selection, the microcontroller activates its integrated high-speed analog-to-digital converter to perform multiple high-speed samplings of the returned voltage signal, obtaining raw quantized values ​​that represent the true performance of each channel's physical connection. To eliminate thermal noise and cable-induced pulse interference in the acquisition circuit, a digital moving average filtering algorithm is used to smooth the raw quantized values. The induced level data stream sequence is defined as follows: ; Among them, the Filtered level of the output channel satisfy: ; in, This represents the preset sampling window width. Representing the The output channel is in the first The raw quantized voltage values ​​obtained during each successive sampling convert the continuously transmitted analog voltage signal into an induced level data stream with a high signal-to-noise ratio. Each element It not only includes the connectivity information of the corresponding channel, but also directly reflects the impedance state of the physical link through the strength characteristics of the voltage amplitude, thereby realizing the decoupling and quantization of the output end sensing signal on the time scale, ensuring the real-time and accuracy of the acquisition of the physical state of each acquisition channel.

[0023] The induced voltage level data is compared with the standard connection mapping relationship to identify abnormal induced voltage and channel mapping deviation, and to generate fault identification results including open circuit, out-of-sequence and loose connection states. Furthermore, comparing the sensed level data with the standard connection mapping includes the following steps: The acquired channel sensing level data are arranged according to the sampling time sequence to construct a measured connection matrix that reflects the current cable connection status. The measured connection matrix is ​​compared bit by bit with the preset standard connection mapping relationship, and the comparison results are used to detect whether there is a discrepancy between the excitation channel and the response channel. The amplitude variation characteristics of the induced level data stream are analyzed to identify the physical link connectivity performance, and the differential information generated by the comparison is extracted as the basis for fault judgment. Generating fault identification results that include open circuit, out-of-order, and loose connection states includes the following steps: Extract the voltage amplitude characteristics and location topology characteristics of each channel from the original fault determination criteria; Based on the comparison results between voltage amplitude characteristics and preset thresholds, open circuit faults and loose connection faults are identified. Based on the comparison results between the location topology features and the standard connection mapping relationship, line sequence misordering and short circuit faults are identified, and the identification results of each channel are integrated to form a unified fault identification result set. Specifically, the system first arranges the real-time acquired sensing level data of each channel according to the sampling clock sequence on the time axis, and constructs a measured connection matrix that reflects the actual physical connectivity status of the current cable. Defined as: ; in, Representative at the The first incentive cycle The quantized value of the induced voltage amplitude acquired by each output channel, here This represents the total number of input channels. To output the total number of channels, the standard connection mapping relationship loaded and stored in memory during the aforementioned initialization phase is then retrieved and transformed into a decision benchmark matrix of the same dimension. This baseline matrix, composed of logical eigenvalues ​​of zero and one, is used to characterize the topological correspondence between input and output channels under ideal conditions. This is achieved through the measured connection matrix. With the judgment benchmark matrix The system performs bit-by-bit logical comparison and feature extraction, calculates the judgment deviation for each channel, and analyzes the stability and integrity characteristics of voltage amplitude from the induced level data stream to extract information for fault diagnosis. When generating fault identification results, the system introduces a logical judgment threshold. With noise margin threshold Perform multi-level classification and determination. If the voltage amplitude characteristics of all output response points corresponding to a certain excitation channel satisfy... If the measured location topology features show that a non-zero element appears at an unexpected column index position, then the line sequence misalignment fault is identified by the coordinate offset of the matrix elements. If the location topology features are correct but the voltage amplitude features meet the requirements... The voltage drop ratio is used to identify the loose connection fault caused by poor physical link contact. Finally, the identification status of each channel is encapsulated into a unified fault identification result set. This not only accurately identifies the correctness of the wire connection, but also evaluates the quality of the electrical connection through quantitative analysis of amplitude characteristics.

[0024] After the fault identification results are packaged, they are uploaded to the host computer. The topology diagram of cable connectivity status is dynamically updated through the graphical interface, and the hardware indicator lights are driven to provide status feedback in a synchronous manner. Furthermore, dynamically updating the cable connectivity topology through a graphical interface and synchronously driving hardware indicator lights for status feedback includes the following steps: The parsed fault identification results are mapped to the virtual connector model on the host computer interface. By changing the display status of the corresponding channel node, the visual rendering of the physical status of the cable is achieved. Based on the fault type defined in the fault identification results, the detailed text description is updated synchronously in the sidebar of the interface to locate the starting and ending channel indices of the fault. The microcontroller sends specific drive level pulses to the indicator light array on the hardware board through the general purpose input / output port; Different combinations of pulse frequencies or levels are used to control indicator lights to generate different visual feedback, thereby presenting the detection results synchronously on the software interface and the hardware terminal; Specifically, the microcontroller encapsulates the generated fault identification result set into a binary stream according to the host computer communication protocol and uploads it in real time. After receiving the data packet, the host computer software calls the graphical rendering engine to map the parsed channel status data to the virtual connector topology model preset on the interface. By changing the color saturation of the corresponding physical nodes or the virtual / real state of the cable connection, dynamic visualization rendering of the cable physical connection status is achieved. At the same time, based on the error type label carried in the fault identification result, the text description information in the interface sidebar is automatically updated to locate the starting and ending channel indices of the fault. While the software interface is updating, the microcontroller sends drive level pulses with specific duty cycles and periods to the indicator light array on the hardware board through its general-purpose input / output port according to the overall health status of the cable. Different pulse frequency characteristics are used to control the red and green dual-color indicator lights to produce flashing or constant visual feedback, defining feedback synchronization. : ; in, The timestamp representing the completion of the graphical interface node status update. This represents the timestamp when the hardware indicator light level change takes effect. Represents the total cycle of a single detection scan, controlling the synchronization coefficient. The convergence ensures a high degree of spatiotemporal consistency between the software virtual view and the hardware physical terminal when presenting test results. This not only allows operators to intuitively obtain complex wiring layouts and fault details, but also enables rapid identification through intuitive prompts from on-site hardware lights, improving the efficiency of human-machine interaction and the intuitiveness of fault location at cable maintenance sites.

[0025] The system stores data records containing test time, cable identification, and fault identification results into a database and generates exportable test reports based on user instructions. Furthermore, storing data records containing detection time, cable identification, and fault identification results into the database includes the following steps: The system clock is invoked to obtain the current real-time date and time, and combined with the cable type identifier generated by the current detection mode, a unique retrieval header for the data record is constructed. The identified channel on / off status, fault type, and specific out-of-order mapping relationship are formatted and transformed into structured data entries that can be recognized by the database. The database connection engine associates the generated search header with the corresponding structured data entries and automatically updates the database index for retrieval. Generating an exportable test report based on user instructions includes the following steps: Obtain the report export command triggered by the user on the host computer interface, and retrieve the preset time period parameters or cable batch filtering conditions. Based on the filtering criteria, perform a correlation query in the database to extract matching detection time, cable mode, on / off status of each channel, and detailed fault location data; The extracted raw data is serialized according to the preset report template, and the detection results containing logical judgments are converted into text descriptions and statistical summaries. Call the file processing interface to write the serialized content to a CSV file and save it to the storage path specified by the user; Specifically, after completing a single test, the host computer software accesses the kernel clock in real time to obtain the current date and precise time. It then concatenates this information with the unique cable type code generated under the current testing mode to construct a unique retrieval header for data storage. Subsequently, the identified channel on / off status quantization values, fault type markers, and specific out-of-order mapping coordinates are serialized according to a preset data structure, transforming them into structured data entries recognizable by the database. Through the database connection engine, the retrieval header and data entries are associated and written to a data table in non-volatile memory. A synchronized index update mechanism is triggered to optimize subsequent query efficiency. When a report export command is received from the user via the interactive interface, the system uses the user-input start and end time periods or cable batch codes as filtering operators to execute a relational query in the database to extract matching historical test records. The extracted raw data stream, containing detailed fault location information, is then filled into a preset report template, defining the retrieval success rate. : ; in, This represents the number of cable inspection records that were successfully extracted and verified under the specified filtering conditions. This represents the total number of actual stored records in the database that meet the filtering criteria. It enables closed-loop management of the entire lifecycle of detection data, from collection and storage to traceability and export. The automatically generated detection reports replace manual recording, reducing the error rate of data archiving. Implementation 2:

[0026] Please see the appendix Figure 2 This invention provides a multi-channel cable continuity and wiring sequence automatic detection system, comprising the following modules: The mode configuration module is used to load the corresponding standard connection mapping relationship according to the received detection mode instruction, and configure the generation of serial mask signal and synchronous timing control signal; The excitation injection module is used to convert the serial mask signal into multiple parallel excitation levels and inject them sequentially into the input terminal of the cable under test under the drive of the timing control signal. The selection acquisition module is used to synchronously select the corresponding channel at the output end of the cable under test and acquire the induction level data stream at the output end in real time. The comparison and identification module is used to compare the induced voltage data stream with the standard connection mapping relationship, identify abnormal induced voltage and channel mapping deviation, and generate fault identification results. The status feedback module is used to encapsulate and upload the fault identification results, dynamically update the cable connectivity status topology diagram through a graphical interface, and synchronously drive hardware indicator lights to provide status feedback. The report storage module is used to store data records containing detection time, cable identification, and fault identification results into the database, and generate detection reports according to user instructions.

[0027] Specifically, the mode configuration module reads the wiring mode instruction issued by the host computer, retrieves the matching physical channel mapping table from the local database and converts it into a judgment benchmark, and at the same time coordinates the microcontroller's internal timer to generate clock signals and initial pulses to drive the scanning logic; The excitation injection module realizes signal transformation through hardware logic circuits. It uses cascaded shift registers to perform shift-by-shift operation driven by the clock signal, expanding the single-channel serial mask signal into multiple parallel scanning levels that are spatially isolated on the time axis. It also uses a latching mechanism to ensure that the excitation signal is injected stably and orderly into the input end of the cable under test. The selection acquisition module drives the analog switch array to switch the acquisition channels in real time by sending binary address codes, and selects the return voltage from the cable output end to the high-precision analog-to-digital converter one by one. After digital filtering, environmental noise interference is eliminated, thereby obtaining a quantized level data stream that can reflect the physical link connection quality. The comparison and identification module performs bit-by-bit logical operations on the measured level matrix and the preset standard mapping matrix. By extracting the strength characteristics of the voltage amplitude and the offset characteristics of the position topology, it identifies open circuits, wire sequence crossings, physical short circuits, and loose connection faults caused by poor contact in the link. The status feedback module maps complex fault data to a virtual connector model for graphical rendering and controls the flashing frequency or color combination of hardware indicator lights through a microcontroller to provide intuitive on-site detection status prompts. The storage report module constructs structured data entries by associating system clocks with cable identifiers and stores them in the database. It also supports retrieving historical records based on user-defined filtering conditions and automatically calling report templates to serialize and generate digital inspection documents.

[0028] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A method for automatic detection of continuity and wiring sequence of multi-channel cables, characterized in that, Includes the following steps: The corresponding standard connection mapping relationship is loaded according to the received detection mode instruction, and the microcontroller is configured to generate serial mask signal and synchronous timing control signal; The microcontroller sends the serial mask signal to the cascaded shift register group. Driven by the timing control signal, the shift register group converts the serial mask signal into multiple parallel excitation levels and injects them sequentially into the input end of the cable under test. While injecting the excitation level, the microcontroller drives a multi-channel analog switch to synchronously select the corresponding channel at the output end of the cable under test, and obtains the induced level data at the output end in real time. The induced voltage level data is compared with the standard connection mapping relationship to identify abnormal induced voltage and channel mapping deviation, and to generate fault identification results including open circuit, out-of-order and loose connection states. The fault identification results are packaged and uploaded to the host computer. The topology diagram of cable connectivity is dynamically updated through a graphical interface, and the hardware indicator lights are driven to provide status feedback. The system stores data records including test time, cable identification, and fault identification results into a database and generates exportable test reports based on user instructions.

2. The method for automatic detection of continuity and wiring sequence of multi-channel cables according to claim 1, characterized in that, The loading of the corresponding standard connection mapping relationship includes the following steps: Obtain the cabling mode selected by the user, which includes a custom cabling mode and a general cable mode; Retrieve the above wiring pattern from the preset database, and index the logical correspondence table of input and output channels based on the instructions issued under the wiring pattern; A judgment benchmark matrix is ​​constructed based on the logical correspondence table and then sent to the microcontroller.

3. The method for automatic detection of continuity and wiring sequence of multi-channel cables according to claim 1, characterized in that, The process of converting the serial mask signal into multiple parallel excitation levels includes the following steps: A continuous displacement clock signal is generated according to a preset scanning frequency as the timing control signal, and it is synchronously transmitted to each cascaded shift register. At the start of the shift clock cycle, a high-level start pulse is injected into the input of the first-stage shift register as the serial mask signal; During subsequent shift clock cycles, the serial mask signal is passed bit by bit through the cascaded shift register group by the shift control logic, and a shift level synchronized with the clock is generated at the parallel output of each shift register. The shifted level state is latched to the output buffer using a latch control signal, thereby forming a single high-level scan excitation that is continuous in time and isolated in space at multiple parallel output ports as the excitation level.

4. The method for automatic detection of continuity and wiring sequence of multi-channel cables according to claim 1, characterized in that, The real-time acquisition of the sensing level data at the output terminal includes the following steps: According to the timing logic synchronized with the excitation level, a multi-bit binary address control signal is generated and sent to the acquisition array composed of multiple analog switch chips; The address control signal sequentially switches the conduction channels of the analog switch, thereby connecting each physical channel of the output end of the cable under test to the signal acquisition pin of the microcontroller one by one. During the conduction of each channel, the returned voltage signal is sampled by the high-speed analog-to-digital converter integrated by the microcontroller to obtain the original quantized value representing the physical connection status of each channel; The quantized values ​​are filtered to obtain an inductive level data stream that reflects the true level state of the output terminal, and then transmitted to the subsequent judgment stage.

5. The method for automatic detection of continuity and wiring sequence of multi-channel cables according to claim 1, characterized in that, The step of comparing the sensed level data with the standard connection mapping relationship includes the following steps: The acquired channel sensing level data are arranged according to the sampling time sequence to construct a measured connection matrix that reflects the current cable connection status. The measured connection matrix is ​​compared bit by bit with the preset standard connection mapping relationship, and the comparison results are used to detect whether there is a discrepancy between the excitation channel and the response channel. The amplitude variation characteristics of the induced level data stream are analyzed to identify the physical link connectivity performance, and the differential information generated by the comparison is extracted as the basis for fault determination.

6. The method for automatic detection of continuity and wiring sequence of multi-channel cables according to claim 1, characterized in that, The process of generating fault identification results, including open circuit, out-of-order, and loose connection states, includes the following steps: Extract the voltage amplitude characteristics and location topology characteristics of each channel from the original fault determination criteria; Based on the comparison results between the voltage amplitude characteristics and the preset threshold, open circuit faults and loose connection faults are identified; Based on the comparison results between the location topology features and the standard connection mapping relationship, line sequence misorder and short circuit faults are identified, and the identification results of each channel are integrated to form a unified fault identification result set.

7. The method for automatic detection of continuity and wiring sequence of multi-channel cables according to claim 1, characterized in that, The process of dynamically updating the cable connectivity topology through a graphical interface and simultaneously driving hardware indicator lights for status feedback includes the following steps: The parsed fault identification results are mapped to the virtual connector model on the host computer interface. By changing the display status of the corresponding channel node, the visual rendering of the physical status of the cable is achieved. Based on the fault type defined in the fault identification results, the detailed text description is updated synchronously in the sidebar of the interface to locate the starting and ending channel indices of the fault. The microcontroller sends specific drive level pulses to the indicator light array on the hardware board through the general purpose input / output port; Different combinations of pulse frequencies or levels are used to control indicator lights to generate different visual feedback, thereby presenting the detection results synchronously on the software interface and the hardware terminal.

8. The method for automatic detection of continuity and wiring sequence of multi-channel cables according to claim 1, characterized in that, The process of storing data records containing detection time, cable identification, and fault identification results into the database includes the following steps: The system clock is invoked to obtain the current real-time date and time, and combined with the cable type identifier generated by the current detection mode, a unique retrieval header for the data record is constructed. The identified channel on / off status, fault type, and specific out-of-order mapping relationship are formatted and transformed into structured data entries that can be recognized by the database. The database connection engine associates the generated search header with the corresponding structured data entries and automatically updates the database index for retrieval.

9. The method for automatic detection of continuity and wiring sequence of multi-channel cables according to claim 1, characterized in that, The process of generating an exportable test report based on user instructions includes the following steps: Obtain the report export command triggered by the user on the host computer interface, and retrieve the preset time period parameters or cable batch filtering conditions. Based on the filtering criteria, perform a correlation query in the database to extract matching detection time, cable mode, on / off status of each channel, and detailed fault location data; The extracted raw data is serialized according to the preset report template, and the detection results containing logical judgments are converted into text descriptions and statistical summaries. Call the file processing interface to write the serialized content to a CSV file and save it to the storage path specified by the user.

10. A multi-channel cable continuity and wiring sequence automatic detection system, characterized in that, The method for automatic detection of continuity and wiring sequence of multi-channel cables as described in any one of claims 1-9 includes the following modules: The mode configuration module is used to load the corresponding standard connection mapping relationship according to the received detection mode instruction, and configure the generation of serial mask signal and synchronous timing control signal; The excitation injection module is used to convert the serial mask signal into multiple parallel excitation levels and inject them sequentially into the input end of the cable under test under the drive of the timing control signal. The selection acquisition module is used to synchronously select the corresponding channel at the output end of the cable under test and acquire the induction level data stream at the output end in real time. The comparison and identification module is used to compare the induced level data stream with the standard connection mapping relationship, identify induced voltage abnormalities and channel mapping deviations, and generate fault identification results. The status feedback module is used to encapsulate and upload the fault identification results, dynamically update the cable connectivity status topology diagram through a graphical interface, and synchronously drive hardware indicator lights to provide status feedback. The report storage module is used to store data records containing detection time, cable identification, and fault identification results into the database, and generate detection reports according to user instructions.

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