A bandgap reference circuit, PCB board and controller

Abstract

The application discloses a band gap reference circuit, a PCB and a controller, comprising a self-starting unit, an input end of the self-starting unit is connected with an external power supply end, an output end of the self-starting unit is connected with an enable end of a low-dropout current mirror unit, and is used for providing a starting driving signal to complete initial biasing; an input end of the low-dropout current mirror unit is connected with the external power supply end, an output end of the low-dropout current mirror unit is connected with an input end of a PTAT current generation unit and a reference voltage synthesis unit, and is used for providing a clamping bias voltage to the PTAT current generation unit and providing a current source to the reference voltage synthesis unit; the input end of the PTAT current generation unit is also connected with the external power supply end, an output end of the PTAT current generation unit is connected with the reference voltage synthesis unit, and is used for providing a PTAT current with a positive temperature coefficient; the reference voltage synthesis unit is used for synthesizing a reference voltage according to the PTAT current and the current of the current source; and the low-dropout current mirror unit is used for realizing voltage clamping, so that the generated current does not change with the power supply voltage.

Description

Technical Field

[0001] This invention relates to the field of reference power supply technology, and in particular to a reference circuit with a gap, a PCB board, and a controller. Background Technology

[0002] Traditional bandgap reference circuits generally use operational amplifiers (OPAMPs) to construct feedback control loops, achieving a stable output of the reference voltage through the clamping effect of the opamps. However, this type of bandgap reference circuit has the following problems: 1. Operational amplifiers have complex circuit architectures, including multiple amplification, biasing, and compensation sub-modules. They occupy a large silicon area in the chip, which is not conducive to the miniaturization of integrated circuits and goes against the miniaturization trend of portable devices, IoT nodes and other products. 2. Operational amplifiers require continuous bias current and power consumption to operate. In addition, the dynamic power consumption of the feedback loop results in high overall power consumption of traditional bandgap reference circuits, making it difficult to meet the design requirements of low-power integrated circuits. 3. Operational amplifiers have inherent limitations in bandwidth, and their power supply rejection ratio (PSR) shows a significant attenuation trend at high frequencies. This makes the bandgap reference circuit based on op-amps poor at suppressing power supply noise at high frequencies, and susceptible to high-frequency interference signals at the power supply end, resulting in fluctuations in the reference voltage output and reducing the circuit's anti-interference capability and output accuracy.

[0003] It is evident that existing technologies still need improvement and enhancement. Summary of the Invention

[0004] In view of the shortcomings of the prior art, the purpose of the present invention is to provide a gapped reference circuit that uses a low-dropout current mirror unit with self-biasing to achieve voltage clamping and ensures that the generated current does not change with the power supply voltage, thus ensuring the stability of the reference voltage output.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: A gapped reference circuit includes a self-starting unit, a low-dropout current mirror unit, a PTAT current generation unit, and a reference voltage synthesis unit. The input terminal of the self-starting unit is connected to an external power supply. The output terminal of the self-starting unit is connected to the enable terminal of the low-dropout current mirror unit. The input terminal of the low-dropout current mirror unit is also connected to an external power supply. The output terminal of the low-dropout current mirror unit is connected to the input terminals of the PTAT current generation unit and the reference voltage synthesis unit. The input terminal of the PTAT current generation unit is also connected to an external power supply. The output terminal of the PTAT current generation unit is connected to the reference voltage synthesis unit. The system is connected in units. The output of the reference voltage synthesis unit is used to output a reference voltage. The self-starting unit is used to provide a start-up drive signal to the low-dropout current mirror unit to complete the initial bias of the low-dropout current mirror unit. The low-dropout current mirror unit is used to provide a clamping bias voltage to the PTAT current generation unit and a current source to the reference voltage synthesis unit according to the voltage of the external power supply. The PTAT current generation unit is used to provide a positive temperature coefficient PTAT current to the reference voltage synthesis unit. The reference voltage synthesis unit is used to synthesize a reference voltage based on the PTAT current and the current source current.

[0006] The gapped reference circuit further includes a low-pass filter unit, which is connected to the output terminal of the reference voltage synthesis unit; the low-pass filter unit is used to filter high-frequency noise in the reference voltage output by the reference voltage synthesis unit.

[0007] In the aforementioned gap-band reference circuit, the self-starting unit includes a first field-effect transistor M1, a second field-effect transistor M2, a third field-effect transistor M3, an eleventh field-effect transistor M11, and a first resistor R1. The sources of the first field-effect transistor M1, the second field-effect transistor M2, and the third field-effect transistor M3 are respectively connected to an external power supply terminal. The gate of the first field-effect transistor M1 and the gate of the second field-effect transistor M2 are connected. The drain of the first field-effect transistor M1 is connected to the drain of the eleventh field-effect transistor M11. The drain of the second field-effect transistor M2 is connected to one end of the first resistor R1 and the gate of the third field-effect transistor M3. The other end of the first resistor R1 and the source of the eleventh field-effect transistor M11 are grounded. The gate of the eleventh field-effect transistor M11 and the drain of the third field-effect transistor M3 are connected to the enable terminal of the low-dropout current mirror unit.

[0008] In the aforementioned gap-based reference circuit, the low-dropout current mirror unit includes a bias voltage providing section, a fourteenth field-effect transistor M14, a fifteenth field-effect transistor M15, a sixteenth field-effect transistor M16, and a seventeenth field-effect transistor M17. The input terminal of the bias voltage providing section is connected to an external power supply terminal, and the output terminal of the bias voltage providing section is connected to the gate of the fourteenth field-effect transistor M14, the gate of the sixteenth field-effect transistor M16, and the enable terminal of the PTAT current generation unit. The drain of the third field-effect transistor M3 is connected to the gate of the fifteenth field-effect transistor M15 and the drain of the sixteenth field-effect transistor M16. The gate of the seventeenth field-effect transistor M17 is connected to the enable terminal of the PTAT current generation unit. The source of the fourteenth field-effect transistor M14 is connected to the source of the fifteenth field-effect transistor M15. The drain of the fourteenth field-effect transistor M14 is connected to the input terminal of the PTAT current generation unit. The source of the fifteenth field-effect transistor M15 is grounded. The drain of the sixteenth field-effect transistor M16 is also connected to the input terminal of the PTAT current generation unit. The source of the sixteenth field-effect transistor M16 is connected to the drain of the seventeenth field-effect transistor M17. The source of the seventeenth field-effect transistor M17 is grounded.

[0009] In the aforementioned gap-band reference circuit, the bias voltage providing section includes a twelfth field-effect transistor M12, a thirteenth field-effect transistor M13, and a second resistor R2. One end of the second resistor R2 is connected to an external power supply terminal, and the other end of the second resistor R2 is connected to the drain and gate of the twelfth field-effect transistor M12, the gate of the thirteenth field-effect transistor M13, and the gate of the fourteenth field-effect transistor M14. The source of the twelfth field-effect transistor M12 is connected to the drain of the thirteenth field-effect transistor M13, and the source of the thirteenth field-effect transistor M13 is grounded.

[0010] In the aforementioned gap-band reference circuit, the PTAT current generation unit includes a fourth field-effect transistor M4, a fifth field-effect transistor M5, an eighteenth field-effect transistor M18, a nineteenth field-effect transistor M19, a first transistor Q1, a second transistor Q2, and a third resistor R3. The base and collector of the first transistor Q1 are connected to an external power supply terminal, as are the base and collector of the second transistor Q2. The emitter of the first transistor Q1 is connected to the source of the fourth field-effect transistor M4, and the emitter of the second transistor Q2 is connected to one end of the third resistor R3. The other end of the third resistor R3 is connected to the source of the fifth field-effect transistor M5. The gate of the fifth field-effect transistor M5, the gate and drain of the fourth field-effect transistor M4 are connected to the drain of the fourteenth field-effect transistor M14. The drain of the fifth field-effect transistor M5 is connected to the drain of the sixteenth field-effect transistor M16. The gate of the eighteenth field-effect transistor M18 is connected to the drain of the twelfth field-effect transistor M12. The gate of the nineteenth field-effect transistor M19 is connected to the drain of the third field-effect transistor M3. The source of the eighteenth field-effect transistor M18 is connected to the drain of the nineteenth field-effect transistor M19. The drain of the eighteenth field-effect transistor M18 is connected to the input terminal of the reference voltage synthesis unit. The source of the nineteenth field-effect transistor M19 is grounded.

[0011] In the aforementioned gap-band reference circuit, the reference voltage synthesis unit includes a sixth field-effect transistor M6, a seventh field-effect transistor M7, an eighth field-effect transistor M8, a ninth field-effect transistor M9, a third transistor Q3, and a fourth resistor R4. The sources of the sixth field-effect transistor M6 and the seventh field-effect transistor M7 are connected to an external power supply. The gate and drain of the sixth field-effect transistor M6 and the gate of the seventh field-effect transistor M7 are connected to the source of the eighth field-effect transistor M8. The drain of the seventh field-effect transistor M7 is connected to the source of the ninth field-effect transistor M9. The gate and drain of the eighth field-effect transistor M8 are connected to the drain of the eighteenth field-effect transistor M18. The drain of the ninth field-effect transistor M9 is connected to the collector and base of the third transistor Q3. The emitter of the third transistor Q3 is connected to one end of the fourth resistor R4, and the other end of the fourth resistor R4 is grounded.

[0012] In the aforementioned gap-based reference circuit, the low-pass filter unit includes a tenth field-effect transistor M10 and a fifth resistor R5. One end of the fifth resistor R5 is connected to the output terminal of the reference voltage synthesis unit, and the other end of the fifth resistor R5 is connected to the gate of the tenth field-effect transistor M10. The source and drain of the tenth field-effect transistor M10 are grounded.

[0013] This application also provides a PCB board printed with the gapped reference circuit described above.

[0014] This application also provides a controller that uses a gapped reference circuit as described above for operational control.

[0015] Beneficial effects: This invention provides a gapped reference circuit. First, in terms of circuit area and integration density, a low-dropout current mirror unit replaces the operational amplifier, which typically includes a differential input stage, gain stage, output stage, and complex frequency compensation network. This simplifies the overall circuit structure and reduces the number of transistors and internal nodes. This helps reduce the circuit's footprint on the silicon wafer, thus better meeting the design requirements of integrated circuit miniaturization and high integration.

[0016] Secondly, in terms of power consumption, omitting the operational amplifier itself eliminates the main power consumption caused by the static bias current of each stage. At the same time, the simplified feedback loop composed of low-dropout current mirror units effectively controls the dynamic operating current and switching activity, thereby reducing the total static power consumption of the entire reference circuit and better meeting the needs of low-power application scenarios.

[0017] Finally, regarding power supply noise suppression, the limited gain-bandwidth product and deteriorating power supply rejection ratio at high frequencies of traditional operational amplifiers are intrinsic limitations. In contrast, the low-dropout current mirror unit possesses a wider bandwidth, and its output current sensitivity to power supply voltage variations can be effectively constrained through a self-biasing structure. Therefore, the feedback mechanism dominated by this unit can maintain power supply disturbance suppression over a wider frequency range (including high frequencies), helping to improve the stability and accuracy of the output reference voltage and reduce output fluctuations caused by high-frequency interference at the power supply end. Attached Figure Description

[0018] Figure 1 A circuit block diagram of the gapped reference circuit provided by the present invention; Figure 2 The circuit structure diagram of the gapped reference circuit provided by the present invention is shown.

[0019] Explanation of key component symbols: 1-Self-starting unit, 2-Low differential current mirror unit, 3-PTAT current generation unit, 4-Reference voltage synthesis unit, 5-Low-pass filter unit. Detailed Implementation

[0020] This invention provides a gapped reference circuit, a PCB board, and a controller. To make the objectives, technical solutions, and effects of this invention clearer and more explicit, the invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only for explaining the invention and are not intended to limit the invention.

[0021] In the description of this invention, it should be understood that the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.

[0022] Please see Figures 1 to 2 This invention provides a gapped reference circuit, including a self-starting unit 1, a low-dropout current mirror unit 2, a PTAT current generation unit 3, and a reference voltage synthesis unit 4. The input terminal of the self-starting unit 1 is connected to an external power supply, and its output terminal is connected to the enable terminal of the low-dropout current mirror unit 2, providing a start-up drive signal to the low-dropout current mirror unit 2 to complete its initial bias. The input terminal of the low-dropout current mirror unit 2 is connected to an external power supply, and its output terminal is connected to the input terminals of the PTAT current generation unit 3 and the reference voltage synthesis unit 4. The low-dropout current mirror unit 2 provides a clamping bias voltage to the PTAT current generation unit 3 and a current source to the reference voltage synthesis unit 4 based on the voltage of the external power supply, and the current source is designed to remain unchanged with the power supply voltage. The input terminal of the PTAT current generation unit 3 is also connected to an external power supply, and its output terminal is connected to the reference voltage synthesis unit 4. The PTAT current generation unit 3 operates after being biased, providing a positive temperature coefficient PTAT current to the reference voltage synthesis unit 4. The input of the reference voltage synthesis unit 4 receives current from the low-dropout current mirror unit 2 and PTAT current information from the PTAT current generation unit 3, and synthesizes and outputs a reference voltage at its output. By using a low-dropout current mirror unit 2 with self-biasing capability instead of a traditional operational amplifier to achieve voltage clamping and current supply, this circuit architecture helps reduce circuit area, lower static power consumption, and may exhibit improved suppression characteristics against power supply voltage variations.

[0023] In this embodiment, firstly, regarding circuit area and integration, the overall circuit structure is simplified by replacing the operational amplifier, which typically includes a differential input stage, gain stage, output stage, and complex frequency compensation network, with a low-dropout current mirror unit 2. This reduces the number of transistors and internal nodes, thus minimizing the circuit's footprint on the silicon wafer and better meeting the design requirements of integrated circuit miniaturization and high integration. Secondly, regarding power consumption, omitting the operational amplifier itself eliminates the main power consumption caused by its stage static bias current. Simultaneously, the simplified feedback loop formed by the low-dropout current mirror unit 2 allows for control of its dynamic operating current and switching activity, reducing the total static power consumption of the entire reference circuit and better meeting the requirements of low-power applications. Finally, regarding power supply noise suppression, the finite gain-bandwidth product and deteriorating power supply rejection ratio at high frequencies are intrinsic limitations of traditional operational amplifiers. In this solution, the low-dropout current mirror unit 2 typically has a wider bandwidth, and its output current sensitivity to power supply voltage changes can be effectively constrained by a self-biasing structure. Therefore, the feedback mechanism led by this unit can maintain the ability to suppress power supply disturbances over a wider frequency range, including the high-frequency band, thereby helping to improve the stability and accuracy of the output reference voltage and reduce output fluctuations caused by high-frequency interference at the power supply end.

[0024] The working principle of this application is as follows: The self-starting unit 1 ensures that the circuit can escape the zero-current degeneracy point and enter normal operation after power-on. Subsequently, the low-dropout current mirror unit 2 begins operation, utilizing its self-biasing characteristics to generate a relatively stable internal bias condition. The output of the low-dropout current mirror unit 2 is divided into two paths: first, it provides a clamping bias voltage to the PTAT current generation unit 3, unaffected by large fluctuations in the power supply voltage, establishing the operating point for PTAT current generation; second, it itself acts as a stable current source, injecting current into the reference voltage synthesis unit 4. After obtaining a stable bias, the PTAT current generation unit 3 generates a current proportional to absolute temperature based on the junction voltage difference of the bipolar transistor. The reference voltage synthesis unit 4 is based on two signals: one is the stable current source from the low-dropout current mirror unit 2, and the other is the PTAT current information reflecting temperature changes. This unit synthesizes a reference voltage with minimal variation over a wide temperature range by weighted superposition of the negative temperature coefficient voltage of the bipolar transistor and the positive temperature coefficient voltage generated by the PTAT current across the resistor.

[0025] Furthermore, in this embodiment, to improve the purity of the output reference voltage, the bandgap reference circuit further includes a low-pass filter unit 5. The input terminal of the low-pass filter unit 5 is connected to the output terminal of the reference voltage synthesis unit 4, and the low-pass filter unit 5 is used to filter out high-frequency noise components that may be contained in the reference voltage output by the reference voltage synthesis unit 4.

[0026] Specifically, the self-starting unit 1 includes a first field-effect transistor (FET) M1, a second field-effect transistor (FET) M2, a third field-effect transistor (FET) M3, an eleventh field-effect transistor (FET) M11, and a first resistor R1. The sources of the first FET M1, the second FET M2, and the third FET M3 are connected to an external power supply. The gate of the first FET M1 is connected to the gate of the second FET M2. The drain of the first FET M1 is connected to the drain of the eleventh FET M11. The drain of the second FET M2 is connected to one end of the first resistor R1 and the gate of the third FET M3. The other end of the first resistor R1 and the source of the eleventh FET M11 are grounded. The gate of the eleventh FET M11 and the drain of the third FET M3 are connected together and serve as the output terminal of the self-starting unit 1, connected to the enable terminal of the low-dropout current mirror unit 2. During power-on, the self-starting unit 1 generates a transient control signal to guide the entire circuit out of the zero-current degeneracy state.

[0027] The specific working principle is as follows: At the initial power-on moment, the external power supply voltage VDD rises from zero. Since the initial gate potentials of the first field-effect transistor M1 and the second field-effect transistor M2 are low, they are initially in the conducting state. At this time, the current flowing through the first field-effect transistor M1 provides a path for the drain current of the eleventh field-effect transistor M11 (whose gate is also initially low, in the off or weakly conducting state). Simultaneously, the external power supply voltage VDD charges the node formed by the first resistor R1 and the gate capacitance of the third field-effect transistor M3 through the conducting second field-effect transistor M2. Due to the presence of the first resistor R1, there is a certain delay in the potential rise of this node. During this delay, the gate voltage of the third field-effect transistor M3 is low, keeping it in the off or slightly conducting state, thereby causing its drain (i.e., output terminal) potential to be pulled up to a high level (close to VDD). This high-level signal serves as an effective start-up drive signal, applied to the enable terminal of the low-dropout current mirror unit 2, forcing its internal node to leave the zero-current degenerate stable point and enter the normal operating current state. As the charging process progresses, when the gate voltage of the third field-effect transistor M3 rises above its threshold voltage, M3 begins to fully conduct. Its drain (output) potential is then rapidly pulled down to a low level. Simultaneously, this low-level signal is fed back to the gate of the eleventh field-effect transistor M11, causing it to completely turn off, thereby cutting off the static current path of the self-starting unit 1. At this point, the startup process is complete, and the output of the self-starting unit 1 stabilizes at a low level, no longer affecting the normal operation of the low-dropout current mirror unit 2, thus achieving self-shutdown after startup.

[0028] The low-dropout current mirror unit 2 includes a bias voltage providing unit, a fourteenth field-effect transistor (FET) M14, a fifteenth field-effect transistor (FET) M15, a sixteenth field-effect transistor (FET) M16, and a seventeenth field-effect transistor (FET) M17. The input terminal of the bias voltage providing unit is connected to an external power supply. The output terminal of the bias voltage providing unit is connected to the gates of the fourteenth FET M14 and the sixteenth FET M16, and provides this bias voltage to the enable terminal of the PTAT current generating unit 3. The start-up signal from the self-starting unit 1, i.e., the drain potential of the third FET M3, is connected to the gates of the fifteenth FET M15, the drain of the sixteenth FET M16, and the gate of the seventeenth FET M17, and is also provided to another enable terminal of the PTAT current generating unit 3. The source of the fourteenth FET M14 is connected to the source of the fifteenth FET M15. The drain of the fourteenth field-effect transistor M14 serves as one output and is connected to the input terminal of the PTAT current generation unit 3. The drain of the fifteenth field-effect transistor M15 is grounded. The drain of the sixteenth field-effect transistor M16 is also connected to another input terminal of the PTAT current generation unit 3. The source of the sixteenth field-effect transistor M16 is connected to the drain of the seventeenth field-effect transistor M17. The source of the seventeenth field-effect transistor M17 is grounded. This low-dropout current mirror unit 2 utilizes a self-biasing structure to generate a stable internal bias.

[0029] Furthermore, the bias voltage providing section includes a twelfth field-effect transistor (FET) M12, a thirteenth field-effect transistor (FET) M13, and a second resistor R2. One end of the second resistor R2 is connected to an external power supply. The other end of the second resistor R2 is connected to the drain and gate of the twelfth FET M12, the gate of the thirteenth FET M13, and the gate of the fourteenth FET M14. The source of the twelfth FET M12 is connected to the drain of the thirteenth FET M13. The source of the thirteenth FET M13 is grounded. Through the cooperation of the second resistor R2, the twelfth FET M12, and the thirteenth FET M13, a relatively stable bias voltage is generated.

[0030] The specific working principle consists of the following two processes: Firstly, the bias voltage providing section consists of the twelfth field-effect transistor M12, the thirteenth field-effect transistor M13, and the second resistor R2. Its core function is to generate a stable bias voltage to provide a reference bias for the low-dropout current mirror unit 2 and the PTAT current generation unit 3. The working process is as follows: One end of the second resistor R2 is connected to an external power supply to obtain power. The current flows through the second resistor R2 to the connection node between the twelfth field-effect transistor M12 and the thirteenth field-effect transistor M13, forming a bias voltage generation circuit. The twelfth field-effect transistor M12 is connected with its gate and drain shorted, forming a current mirror relationship with the thirteenth field-effect transistor M13. The source of the thirteenth field-effect transistor M13 is grounded to form a current discharge path. Through the current limiting effect of the second resistor R2 and the current mirror characteristics of the two transistors, a stable DC bias voltage is formed at the drain-gate node of the twelfth field-effect transistor M12. The bias voltage is directly output to the gate of the fourteenth field-effect transistor M14 and the gate of the sixteenth field-effect transistor M16, providing them with a fixed gate bias. At the same time, the bias voltage is also output as an enable signal to the corresponding enable terminal of the PTAT current generation unit 3, laying the bias foundation for the operation of the PTAT current generation unit 3.

[0031] Secondly, the low-dropout current mirror is composed of fourteenth field-effect transistor M14, fifteenth field-effect transistor M15, sixteenth field-effect transistor M16, and seventeenth field-effect transistor M17. Based on the bias voltage generated by the bias voltage supply unit, it receives the start-up signal (drain potential of the third field-effect transistor M3) from the self-starting unit 1 to complete the activation, realizing potential clamping and current mirroring under low dropout, and at the same time providing clamping bias and current path for the PTAT current generation unit 3. The working process is as follows: Start-up signal reception and operation activation: The start-up signal output by the self-starting unit 1 is connected to the gate of the fifteenth field-effect transistor M15, the drain of the sixteenth field-effect transistor M16, and the gate of the seventeenth field-effect transistor M17. This signal serves as the enable signal for the low-dropout current mirror unit 2 and the PTAT current generation unit 3, triggering the fifteenth field-effect transistor M15 and the seventeenth field-effect transistor M17 to enter the working state. At the same time, it provides a potential reference for the sixteenth field-effect transistor M16, completing the operation activation of the entire low-dropout current mirror unit 2 and causing it to leave the zero-current state after power-on. Low dropout bias and potential clamping: The gate of the fourteenth field-effect transistor M14 receives the fixed bias of the bias voltage supply section, and its source is connected to the source of the fifteenth field-effect transistor M15. The drain of the fifteenth field-effect transistor M15 is grounded to form a current path. Through the fixed gate bias of the fourteenth field-effect transistor M14 and the grounding discharge of the fifteenth field-effect transistor M15, a stable low dropout potential is formed at the source of the fourteenth field-effect transistor M14, thereby clamping the potential of the input terminal of the subsequent PTAT current generation unit 3 and ensuring that the potential is not affected by large fluctuations in the external power supply voltage. Current mirroring and path construction: The gate of the sixteenth field-effect transistor M16 receives the fixed bias of the bias voltage supply section, and its source is connected to the drain of the seventeenth field-effect transistor M17. The source of the seventeenth field-effect transistor M17 is grounded to form a discharge path. Under the cooperation of the gate bias and the seventeenth field-effect transistor M17, the sixteenth field-effect transistor M16 forms a stable current path. At the same time, the drains of the fourteenth field-effect transistor M14 and the sixteenth field-effect transistor M16 serve as two output terminals, which are connected to the two input terminals of the PTAT current generation unit 3 respectively, thus constructing two stable low-dropout current paths for the PTAT current generation unit 3 to achieve accurate current mirroring and transmission. Self-biased stabilization characteristic: The entire low-dropout current mirror unit 2, through the fixed bias of the bias voltage supply section and in conjunction with the low-dropout architecture of the fourteenth field-effect transistor M14 / fifteenth field-effect transistor M15, sixteenth field-effect transistor M16 / seventeenth field-effect transistor M17, forms a self-biased feedback mechanism, which keeps the potential and current inside the unit stable at all times. The output clamping bias voltage and mirror current will not fluctuate significantly with changes in the external power supply voltage. At the same time, this self-biased structure effectively reduces the minimum operating voltage of the circuit, making it suitable for low power supply voltage application scenarios.

[0032] The PTAT current generation unit 3 includes a fourth field-effect transistor M4, a fifth field-effect transistor M5, an eighteenth field-effect transistor M18, a nineteenth field-effect transistor M19, a first transistor Q1, a second transistor Q2, and a third resistor R3. The base and collector of the first transistor Q1 are connected to an external power supply. The base and collector of the second transistor Q2 are also connected to an external power supply. The emitter of the first transistor Q1 is connected to the source of the fourth field-effect transistor M4. The emitter of the second transistor Q2 is connected to one end of the third resistor R3. The other end of the third resistor R3 is connected to the source of the fifth field-effect transistor M5. The gate of the fifth field-effect transistor M5, the gate of the fourth field-effect transistor M4, and the drain are connected together and connected to the drain of the fourteenth field-effect transistor M14 in the low-dropout current mirror unit 2. The drain of the fifth field-effect transistor M5 is connected to the drain of the sixteenth field-effect transistor M16 in the low-dropout current mirror unit 2. The gate of the eighteenth field-effect transistor M18 is connected to the drain of the twelfth field-effect transistor M12 in the bias voltage providing section to receive the bias voltage. The gate of the nineteenth field-effect transistor M19 is connected to the drain of the third field-effect transistor M3 in the self-starting unit 1 to receive the enable signal. The source of the eighteenth field-effect transistor M18 is connected to the drain of the nineteenth field-effect transistor M19. The drain of the eighteenth field-effect transistor M18 is connected to the input terminal of the reference voltage synthesis unit 4 to provide the PTAT current. The source of the nineteenth field-effect transistor M19 is grounded. The first transistor Q1 and the second transistor Q2 typically have different emitter junction areas, and the difference in their emitter junction voltages (ΔVbe) is reflected across the third resistor R3, thereby generating the PTAT current.

[0033] The reference voltage synthesis unit 4 includes a sixth field-effect transistor (FET) M6, a seventh field-effect transistor (FET) M7, an eighth field-effect transistor (FET) M8, a ninth field-effect transistor (FET) M9, a third transistor Q3, and a fourth resistor R4. The sources of the sixth FET M6 and the seventh FET M7 are connected to an external power supply. The gate and drain of the sixth FET M6 and the gate of the seventh FET M7 are connected to the source of the eighth FET M8. The drain of the seventh FET M7 is connected to the source of the ninth FET M9. The gate and drain of the eighth FET M8 are connected to the drain of the eighteenth FET M18 in the PTAT current generation unit 3 to receive PTAT current. The drain of the ninth FET M9 is connected to the collector and base of the third transistor Q3. The emitter of the third transistor Q3 is connected to one end of the fourth resistor R4. The other end of the fourth resistor R4 is grounded. The PTAT current flowing through the third transistor Q3 and the fourth resistor R4 generates a voltage drop with a positive temperature coefficient across the fourth resistor R4. This voltage drop is superimposed on the base-emitter voltage of the third transistor Q3 (which has a negative temperature coefficient). After passing through the buffer or transmission path formed by the seventh field-effect transistor M7 and the ninth field-effect transistor M9, it is synthesized at the drain of the seventh field-effect transistor M7 or the drain of the ninth field-effect transistor M9 (i.e., the base of the third transistor Q3) to obtain a reference voltage with a low temperature coefficient.

[0034] To achieve a smoother reference voltage output, this invention also includes a low-pass filter unit 5. In this embodiment, the low-pass filter unit 5 includes a tenth field-effect transistor M10 and a fifth resistor R5. One end of the fifth resistor R5 is connected to the output terminal of the reference voltage synthesis unit 4 (i.e., the drain of the ninth field-effect transistor M9 or the base of the third transistor Q3). The other end of the fifth resistor R5 is connected to the gate of the tenth field-effect transistor M10. The source and drain of the tenth field-effect transistor M10 are grounded. The gate capacitance of the tenth field-effect transistor M10 and the fifth resistor R5 form an RC filter network to attenuate high-frequency noise in the output reference voltage.

[0035] This application also provides a PCB board printed with the gapped reference circuit described above.

[0036] This application also provides a controller that uses a gapped reference circuit as described above for operational control.

[0037] It is understood that those skilled in the art can make equivalent substitutions or modifications to the technical solution and inventive concept of the present invention, and all such substitutions or modifications should fall within the protection scope of the appended claims.

Claims

1. A reference circuit with a gap, characterized in that, The system includes a self-starting unit, a low-dropout current mirror unit, a PTAT current generation unit, and a reference voltage synthesis unit. The input of the self-starting unit is connected to an external power supply, and its output is connected to the enable terminal of the low-dropout current mirror unit. The input of the low-dropout current mirror unit is also connected to an external power supply, and its output is connected to the inputs of the PTAT current generation unit and the reference voltage synthesis unit. The input of the PTAT current generation unit is also connected to an external power supply, and its output is connected to the reference voltage synthesis unit, which outputs a reference voltage. The self-starting unit provides a start-up drive signal to the low-dropout current mirror unit, completing its initial bias. The low-dropout current mirror unit is used to provide a clamping bias voltage to the PTAT current generation unit and a current source to the reference voltage synthesis unit based on the voltage of the external power supply terminal. The PTAT current generation unit is used to provide a positive temperature coefficient PTAT current for the reference voltage synthesis unit; The reference voltage synthesis unit is used to synthesize a reference voltage based on the PTAT current and the current source current.

2. The reference circuit with gap according to claim 1, characterized in that, It also includes a low-pass filter unit, which is connected to the output terminal of the reference voltage synthesis unit; the low-pass filter unit is used to filter high-frequency noise in the reference voltage output by the reference voltage synthesis unit.

3. The reference circuit with gap according to claim 1, characterized in that, The self-starting unit includes a first field-effect transistor M1, a second field-effect transistor M2, a third field-effect transistor M3, an eleventh field-effect transistor M11, and a first resistor R1. The sources of the first field-effect transistor M1, the second field-effect transistor M2, and the third field-effect transistor M3 are respectively connected to an external power supply. The gate of the first field-effect transistor M1 is connected to the gate of the second field-effect transistor M2. The drain of the first field-effect transistor M1 is connected to the drain of the eleventh field-effect transistor M11. The drain of the second field-effect transistor M2 is connected to one end of the first resistor R1 and the gate of the third field-effect transistor M3. The other end of the first resistor R1 and the source of the eleventh field-effect transistor M11 are grounded. The gate of the eleventh field-effect transistor M11 and the drain of the third field-effect transistor M3 are connected to the enable terminal of the low-dropout current mirror unit.

4. The reference circuit with gap according to claim 3, characterized in that, The low-dropout current mirror unit includes a bias voltage providing section, a fourteenth field-effect transistor M14, a fifteenth field-effect transistor M15, a sixteenth field-effect transistor M16, and a seventeenth field-effect transistor M17. The input terminal of the bias voltage providing section is connected to an external power supply terminal, and the output terminal of the bias voltage providing section is connected to the gate of the fourteenth field-effect transistor M14, the gate of the sixteenth field-effect transistor M16, and the enable terminal of the PTAT current generating unit. The drain of the third field-effect transistor M3 is connected to the gate of the fifteenth field-effect transistor M15, the drain of the sixteenth field-effect transistor M16, and the enable terminal of the seventeenth field-effect transistor M17. The gate of the field-effect transistor M17 is connected to the enable terminal of the PTAT current generation unit. The source of the fourteenth field-effect transistor M14 is connected to the source of the fifteenth field-effect transistor M15. The drain of the fourteenth field-effect transistor M14 is connected to the input terminal of the PTAT current generation unit. The source of the fifteenth field-effect transistor M15 is grounded. The drain of the sixteenth field-effect transistor M16 is also connected to the input terminal of the PTAT current generation unit. The source of the sixteenth field-effect transistor M16 is connected to the drain of the seventeenth field-effect transistor M17. The source of the seventeenth field-effect transistor M17 is grounded.

5. The reference circuit with gap according to claim 4, characterized in that, The bias voltage providing section includes a twelfth field-effect transistor M12, a thirteenth field-effect transistor M13, and a second resistor R2. One end of the second resistor R2 is connected to an external power supply terminal, and the other end of the second resistor R2 is connected to the drain and gate of the twelfth field-effect transistor M12, the gate of the thirteenth field-effect transistor M13, and the gate of the fourteenth field-effect transistor M14. The source of the twelfth field-effect transistor M12 is connected to the drain of the thirteenth field-effect transistor M13, and the source of the thirteenth field-effect transistor M13 is grounded.

6. The gapped reference circuit according to claim 5, characterized in that, The PTAT current generation unit includes a fourth field-effect transistor M4, a fifth field-effect transistor M5, an eighteenth field-effect transistor M18, a nineteenth field-effect transistor M19, a first transistor Q1, a second transistor Q2, and a third resistor R3. The base and collector of the first transistor Q1 are connected to an external power supply terminal, and the base and collector of the second transistor Q2 are also connected to an external power supply terminal. The emitter of the first transistor Q1 is connected to the source of the fourth field-effect transistor M4. The emitter of the second transistor Q2 is connected to one end of the third resistor R3, and the other end of the third resistor R3 is connected to the source of the fifth field-effect transistor M5. The gate of M5, the gate and drain of the fourth field-effect transistor M4 are connected to the drain of the fourteenth field-effect transistor M14. The drain of the fifth field-effect transistor M5 is connected to the drain of the sixteenth field-effect transistor M16. The gate of the eighteenth field-effect transistor M18 is connected to the drain of the twelfth field-effect transistor M12. The gate of the nineteenth field-effect transistor M19 is connected to the drain of the third field-effect transistor M3. The source of the eighteenth field-effect transistor M18 is connected to the drain of the nineteenth field-effect transistor M19. The drain of the eighteenth field-effect transistor M18 is connected to the input terminal of the reference voltage synthesis unit. The source of the nineteenth field-effect transistor M19 is grounded.

7. The reference circuit with gap according to claim 6, characterized in that, The reference voltage synthesis unit includes a sixth field-effect transistor M6, a seventh field-effect transistor M7, an eighth field-effect transistor M8, a ninth field-effect transistor M9, a third transistor Q3, and a fourth resistor R4. The sources of the sixth field-effect transistor M6 and the seventh field-effect transistor M7 are connected to an external power supply. The gate and drain of the sixth field-effect transistor M6 and the gate of the seventh field-effect transistor M7 are connected to the source of the eighth field-effect transistor M8. The drain of the seventh field-effect transistor M7 is connected to the source of the ninth field-effect transistor M9. The gate and drain of the eighth field-effect transistor M8 are connected to the drain of the eighteenth field-effect transistor M18. The drain of the ninth field-effect transistor M9 is connected to the collector and base of the third transistor Q3. The emitter of the third transistor Q3 is connected to one end of the fourth resistor R4, and the other end of the fourth resistor R4 is grounded.

8. The reference circuit with gap according to claim 2, characterized in that, The low-pass filter unit includes a tenth field-effect transistor M10 and a fifth resistor R5. One end of the fifth resistor R5 is connected to the output terminal of the reference voltage synthesis unit, and the other end of the fifth resistor R5 is connected to the gate of the tenth field-effect transistor M10. The source and drain of the tenth field-effect transistor M10 are grounded.

9. A PCB board, characterized in that, The PCB board is printed with a gapped reference circuit as described in any one of claims 1-8.

10. A controller, characterized in that, The controller employs a gapped reference circuit as described in any one of claims 1-8.

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