A method and apparatus for optimizing proportion of DRAM and CXL extended memory for CXL hierarchical memory system

Abstract

The application discloses a DRAM and CXL extended memory proportion optimization method and device for a CXL layered memory system, and relates to the technical field of computing systems. The method is to first acquire an offline experience dataset containing a DRAM capacity proportion, a memory access mode feature and a bandwidth-concurrent core number mapping relationship, then determine an effective extended core number as a sample label according to the bandwidth-concurrent core number mapping relationship, and combine the DRAM capacity proportion and the memory access mode feature to form a sample feature vector, train an effective extended core number prediction model, and then, after receiving an effective extended core number target value and a memory access mode feature of a current workload, solve a minimum DRAM capacity proportion that meets a target constraint condition in combination with the prediction model, and finally generate a proportion scheme according to the minimum DRAM capacity proportion and output the proportion scheme for system configuration. In this way, under a given performance target and workload feature, an interpretable and reproducible DRAM and CXL extended memory recommended proportion can be automatically given, and experience-based head-on configuration can be avoided.

Description

Technical Field

[0001] This invention belongs to the field of computing system technology, specifically relating to a method and apparatus for optimizing the ratio of DRAM to CXL extended memory in a CXL layered memory system. Background Technology

[0002] CXL (Compute Express Link) is an open, high-speed interconnect protocol that provides scalable memory tiering capabilities for server systems. Based on CXL, systems can pool local DRAM (Dynamic Random Access Memory) and CXL extended memory, sharing the memory access load in different ratios (i.e., different proportions of DRAM and CXL extended memory), thereby overcoming the performance and capacity bottlenecks of a single memory wall.

[0003] Currently, research on CXL tiered memory mainly focuses on two directions: one is to conduct early exploratory research relying on full-system simulators or approximate methods based on the Non-Uniform Memory Access (NUMA) architecture; the other is to conduct baseline performance testing and device characterization on commercial CXL platforms to understand the basic behavioral characteristics of CXL memory. While the aforementioned research provides an important foundation for understanding the performance characteristics of the CXL memory subsystem, the following technical gaps remain regarding how to proactively plan the ratio of DRAM to CXL extended memory to meet predictable performance targets based on specific workload characteristics and concurrency pressures: (1) The optimal storage ratio is highly workload-dependent. That is, on the same hardware platform, different input / output (I / O) modes (such as pure read mode, mode with write operation and mode with non-sequential write operation, etc.) may result in significant differences in the ratio of DRAM to CXL extended memory that achieves optimal system performance. At the same time, there are complex coupling relationships and trade-offs among multiple performance indicators such as throughput, average latency and performance stability, making it difficult to take into account the overall performance target when simply selecting the storage ratio based on a single indicator. (2) The system saturation boundary is determined by the number of concurrent cores and the storage ratio, and exhibits nonlinear and counterintuitive characteristics. Experimental observations show that under high concurrency pressure, some seemingly “balanced” DRAM to CXL extended memory ratios may achieve lower average latency than configurations with a higher DRAM capacity ratio. This nonlinear behavior contradicts the traditional linear expansion expectation, making it difficult for storage ratio selection methods based on linear thinking or rules of thumb to accurately predict the actual performance of the system under actual load. (3) The fixed ratio strategy commonly used in existing engineering practices has limitations. For example, the common fixed 50:50 or fixed 90:10 ratio of DRAM to CXL extended memory is essentially a static empirical configuration. Such strategies lack the ability to quantitatively model the above-mentioned nonlinear characteristics and multi-dimensional performance trade-offs. Therefore, given specific performance targets (such as expected concurrent processing capacity and latency limits), it is difficult to provide an interpretable, reproducible and generalizable storage ratio optimization scheme.

[0004] In summary, how to proactively plan and optimize the ratio of DRAM to CXL extended memory while considering workload characteristics, concurrency pressure, and multi-dimensional performance goals has become an urgent technical problem to be solved in current research on CXL tiered memory systems. Summary of the Invention

[0005] The purpose of this invention is to provide a method, apparatus, computer device, computer-readable storage medium, and computer program product for optimizing the ratio of DRAM to CXL extended memory in a CXL tiered memory system, in order to solve the problem that existing CXL tiered memory systems lack an active planning mechanism for the ratio of DRAM to CXL extended memory oriented towards workload characteristics and quantifiable performance targets, which makes it difficult to achieve interpretable and reproducible ratio optimization recommendations.

[0006] To achieve the above objectives, the present invention adopts the following technical solution: Firstly, a method for optimizing the DRAM to CXL extended memory ratio in a CXL tiered memory system is provided, including: Obtain an offline experience dataset, wherein the offline experience dataset contains multiple sets of experience data obtained through offline experiments, and each set of experience data contains DRAM capacity percentage, memory access pattern characteristics, and memory bandwidth measured when the number of concurrent cores is N, where N represents a positive integer; For each set of experience data in the offline experience dataset, the corresponding effective number of extended cores is determined as the corresponding sample label based on the mapping relationship between memory bandwidth and concurrent cores in the corresponding data. The DRAM capacity ratio and memory access mode features in the corresponding data are combined to form the corresponding sample feature vector. The effective number of extended cores refers to the maximum number of concurrent cores that the CXL hierarchical memory system can support when the extension efficiency is not lower than a preset efficiency threshold. Based on each pair of sample feature vectors and sample labels that correspond one-to-one with the aforementioned groups of empirical data, an effective extended kernel number prediction model is trained. After receiving the target value for the effective number of extended cores and the memory access pattern characteristics of the current workload, the minimum DRAM capacity ratio that satisfies the target constraint is obtained by combining the effective number of extended cores prediction model. The target constraint means that the predicted value of the effective number of extended cores obtained after importing the solution of the DRAM capacity ratio and the memory access pattern characteristics of the current workload into the effective number of extended cores prediction model must be greater than or equal to the target value for the effective number of extended cores. Based on the minimum DRAM capacity ratio, a DRAM to CXL extended memory ratio scheme is generated; The aforementioned scaling scheme is output for configuration by the CXL tiered memory system.

[0007] Based on the above-mentioned invention, a novel scheme for proactive planning and optimization recommendation of the DRAM to CXL extended memory ratio is provided. First, an offline empirical dataset containing DRAM capacity ratio, memory access mode characteristics, and bandwidth-concurrent core count mapping is acquired. Then, the effective extended core count is determined based on the bandwidth-concurrent core count mapping and used as sample labels. The DRAM capacity ratio and memory access mode characteristics are combined to form a sample feature vector, and an effective extended core count prediction model is trained. Next, upon receiving the target value of the effective extended core count and the memory access mode characteristics of the current workload, the prediction model is used to solve for the minimum DRAM capacity ratio that satisfies the target constraints. Finally, a ratio scheme is generated based on the minimum DRAM capacity ratio and output for system configuration. This approach automatically provides an interpretable and reproducible recommended DRAM to CXL extended memory ratio under given performance targets and workload characteristics, avoiding arbitrary configuration based on experience and facilitating practical application and promotion.

[0008] In one possible design, the memory access pattern characteristics include the proportion of write operations and / or the proportion of non-sequential write operations in the total write operations.

[0009] In one possible design, for each set of experience data in the offline experience dataset, the corresponding effective number of extended cores is determined based on the mapping relationship between memory bandwidth and concurrent core count in the corresponding data, including: For a set of experience data in the offline experience dataset, obtain the mapping relationship between memory bandwidth and concurrent core count in the corresponding data; Based on the mapping relationship, the expansion efficiency is calculated using the following formula.

[0010]

[0011] In the formula, This represents the number of concurrent cores used as an argument to the function. This represents the functional form used as the dependent variable of the memory bandwidth in the mapping relationship. This represents the baseline concurrent core count used for normalization; According to the expansion efficiency The effective number of extended cores corresponding to a certain set of empirical data is determined according to the following formula. :

[0012] In the formula, This represents the function that takes the maximum value. This indicates the preset efficiency threshold.

[0013] In one possible design, the effective extended kernel number prediction model is obtained by regularization training based on a quadratic polynomial regression model containing interaction terms and nonlinear terms.

[0014] In one possible design, after receiving the target value for the effective number of extended cores and the memory access pattern characteristics of the current workload, the minimum DRAM capacity percentage that satisfies the target constraints is obtained by combining the effective number of extended cores prediction model, including: After receiving the target value for the effective number of extended cores and the memory access pattern characteristics of the current workload, and combining the effective number of extended cores prediction model, the following objective function is determined. :

[0015] In the formula, This represents the percentage of DRAM capacity used as the independent variable of the function. This indicates the memory access pattern characteristics of the current workload. This represents the functional form of the effective extended core number prediction model. This represents the target value for the effective extended core count; judge Is it less than zero? If yes, then output a warning message indicating that the minimum DRAM capacity percentage required to meet the target constraint is unattainable; otherwise, output a message within the specified range. Inside, solve for the condition that satisfies The root or equivalent solution is used to find the minimum DRAM capacity percentage that makes the target constraint condition first true, and the solution result is used as the minimum DRAM capacity percentage that satisfies the target constraint condition. The target constraint condition refers to the effective extended core number prediction value obtained after importing the solution result of the DRAM capacity percentage and the memory access mode characteristics of the current workload into the effective extended core number prediction model, which needs to be greater than or equal to the effective extended core number target value.

[0016] In a possible design, solve for the following: The root or equivalent solution for the minimum DRAM capacity percentage that makes the target constraint condition first true includes: When the effective extended kernel number prediction model is obtained through regularized training based on a quadratic polynomial regression model containing interaction and nonlinear terms, a one-dimensional solver based on the bisection method or Newton's method is used to solve for the condition... The root or equivalent solution is the minimum DRAM capacity percentage that makes the target constraint condition first true.

[0017] In a second aspect, a device for optimizing the ratio of DRAM to CXL extended memory in a CXL hierarchical memory system is provided, comprising a dataset acquisition unit, a sample data processing unit, a prediction model training unit, a minimum ratio solution unit, a ratio scheme generation unit, and a ratio scheme output unit that are connected in sequence. The dataset acquisition unit is used to acquire an offline experience dataset, wherein the offline experience dataset contains multiple sets of experience data obtained through offline experiments. Each set of experience data contains DRAM capacity percentage, memory access mode characteristics, and memory bandwidth measured when the number of concurrent cores is N, where N represents a positive integer. The sample data processing unit is used to determine the corresponding effective number of extended cores as the corresponding sample label for each group of experience data in the offline experience dataset, based on the mapping relationship between memory bandwidth and concurrent cores in the corresponding data, and to form the corresponding sample feature vector by combining the DRAM capacity ratio and memory access mode features in the corresponding data. The effective number of extended cores refers to the maximum number of concurrent cores that the CXL hierarchical memory system can support when the extension efficiency is not lower than a preset efficiency threshold. The prediction model training unit is used to train an effective extended kernel number prediction model based on each pair of sample feature vectors and sample labels that correspond one-to-one with each group of empirical data. The minimum percentage calculation unit is used to, after receiving the target value of the effective extended core count and the memory access mode characteristics of the current workload, combine the effective extended core count prediction model to calculate the minimum DRAM capacity percentage that satisfies the target constraint condition. The target constraint condition means that the predicted value of the effective extended core count obtained after importing the solution result of the DRAM capacity percentage and the memory access mode characteristics of the current workload into the effective extended core count prediction model needs to be greater than or equal to the target value of the effective extended core count. The ratio scheme generation unit is used to generate a ratio scheme of DRAM and CXL extended memory based on the minimum DRAM capacity ratio. The scaling scheme output unit is used to output the scaling scheme for the CXL hierarchical memory system to configure.

[0018] Thirdly, the present invention provides a computer device comprising a storage module, a processing module, and a transceiver module connected in sequence for communication, wherein the storage module is used to store a computer program, the transceiver module is used to send and receive messages, and the processing module is used to read the computer program and execute the DRAM to CXL extended memory ratio optimization method as described in the first aspect or any possible design in the first aspect.

[0019] Fourthly, the present invention provides a computer-readable storage medium storing instructions that, when executed on a computer, perform the DRAM to CXL extended memory ratio optimization method as described in the first aspect or any possible design in the first aspect.

[0020] Fifthly, the present invention provides a computer program product, including a computer program or instructions, wherein the computer program or instructions, when executed by a computer, implement the DRAM to CXL extended memory ratio optimization method as described in the first aspect or any possible design in the first aspect.

[0021] The beneficial effects of the above scheme are: (1) This invention creatively provides a new scheme for proactive planning and optimization recommendation of the ratio of DRAM to CXL extended memory. That is, firstly, an offline experience dataset containing DRAM capacity ratio, memory access mode features and bandwidth-concurrent core number mapping relationship is obtained. Then, the effective number of extended cores is determined according to the bandwidth-concurrent core number mapping relationship as a sample label. The DRAM capacity ratio and memory access mode features are combined to form a sample feature vector and a prediction model for the effective number of extended cores is trained. After receiving the target value of the effective number of extended cores and the memory access mode features of the current workload, the minimum DRAM capacity ratio that satisfies the target constraint is solved by combining the prediction model. Finally, the ratio scheme is generated according to the minimum DRAM capacity ratio and output for system configuration. In this way, under the given performance target and workload characteristics, an interpretable and reproducible recommended ratio of DRAM to CXL extended memory can be automatically given, avoiding arbitrary configuration based on experience. (2) Through the two-stage framework of “acquiring offline experience dataset → determining effective extended core number as sample label → training prediction model → solving minimum DRAM ratio online → output ratio scheme”, active planning of storage ratio for quantifiable performance goals is realized. Compared with the traditional fixed ratio strategy, it can automatically give an interpretable and reproducible recommended ratio based on the performance goals and workload characteristics given by the user, avoiding the blindness of relying on experience to make “gut feeling” configuration. (3) By limiting the memory access mode features to include the proportion of write operations and / or the proportion of non-sequential write operations in the write operations, the model can distinguish the impact of different I / O modes on the optimal ratio, thus solving the technical problem that "configuration optimality has a strong workload dependency" (for example, the optimal ratio of pure read mode and non-sequential write mode may be different, ensuring that the model can capture this difference). (4) By precisely defining the calculation formula for the effective number of extended cores, the complex “bandwidth-concurrent cores” curve can be transformed into a learnable scalar target. This transformation is the basis for subsequent quantitative modeling, turning the curve relationship that was originally difficult to optimize directly into a numerical label that can be used for regression analysis, which reflects the effect of the core technology. (5) By limiting the prediction model to a quadratic polynomial regression model containing interaction terms and nonlinear terms, the coupling relationship between DRAM capacity ratio, write ratio and non-sequential write ratio is explicitly characterized. This enables the model to cover counterintuitive phenomena such as "balanced ratio is better than high DRAM ratio" under high concurrency, and to make target-driven trade-offs among multi-dimensional indicators such as throughput, average latency and stability, which reflects the effect of core technology. (6) By limiting the online solution process to perform a feasibility judgment (determining whether g(1.0) is less than zero), the system avoids making invalid configuration attempts when the performance target cannot be achieved, thus improving the engineering practicality of the method. If the target is unattainable, the system can output a reminder message in advance to guide the user to adjust their expectations. If the target is attainable, the optimal ratio is obtained by solving the zero point of the objective function, which reflects the completeness and robustness of the algorithm design. (7) By limiting the prediction model to a quadratic polynomial regression model, a one-dimensional solver based on the bisection method or Newton's method is used to solve the problem. This fully utilizes the characteristic that low-order polynomials are easy to find roots and realizes the rapid online calculation of the ratio recommendation. This makes the solution have real-time deployment capability and can meet the requirements of response speed in the actual production environment, reflecting the technical effect of "rapid output". (8) In real hardware evaluation, the “non-fixed” ratio recommended by this solution is superior to the traditional fixed ratio strategy in a variety of scenarios: it achieves a latency reduction of up to about 10.2% in latency-sensitive scenarios and a bandwidth fluctuation (coefficient of variation) improvement of up to about 22.2% in high-stress stability scenarios, which is convenient for practical application and promotion. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a flowchart illustrating the method for optimizing the ratio of DRAM to CXL extended memory in a CXL layered memory system, as provided in an embodiment of this application.

[0024] Figure 2 This is a schematic diagram of the structure of the DRAM and CXL extended memory ratio optimization device for the CXL layered memory system provided in the embodiments of this application.

[0025] Figure 3 A schematic diagram of the structure of a computer device provided in an embodiment of this application. Detailed Implementation

[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the present invention will be briefly introduced below in conjunction with the accompanying drawings and descriptions of the embodiments or the prior art. Obviously, the following description of the structure of the accompanying drawings is only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these embodiments without creative effort. It should be noted that the description of these embodiments is for the purpose of helping to understand the present invention, but does not constitute a limitation of the present invention.

[0027] It should be understood that although the terms "first" and "second", etc., may be used herein to describe various objects, these objects should not be limited by these terms. These terms are only used to distinguish one object from another. For example, the first object may be referred to as the second object, and similarly, the second object may be referred to as the first object, without departing from the scope of the exemplary embodiments of the invention.

[0028] It should be understood that the term "and / or" that may appear in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, B exists alone, or A and B exist simultaneously. Another example is A, B and / or C, which can mean that any one of A, B, and C or any combination thereof exists. The term " / and" that may appear in this document describes another relationship between related objects, indicating that two relationships can exist. For example, A / and B can mean: A exists alone or A and B exist simultaneously. In addition, the character " / " that may appear in this document generally indicates that the related objects before and after it are in an "or" relationship.

[0029] Example like Figure 1As shown, the method for optimizing the ratio of DRAM to CXL extended memory in a CXL tiered memory system provided in the first aspect of this embodiment can be executed, but is not limited to, by a computer device with certain computing resources, such as a server containing local DRAM and CXL extended memory (e.g., a CXL 2.0 Gen5 Type-3 memory extender) and generating memory load due to multi-core concurrent access by the CPU (Central Processing Unit). Figure 1 As shown, the method for optimizing the ratio of DRAM to CXL extended memory includes, but is not limited to, the following steps S1 to S6.

[0030] S1. Obtain an offline experience dataset, wherein the offline experience dataset includes, but is not limited to, multiple sets of experience data obtained through offline experiments, and each set of experience data includes, but is not limited to, DRAM capacity ratio, memory access pattern characteristics, and memory bandwidth measured when the number of concurrent cores is N, where N represents a positive integer.

[0031] In step S1, the offline experience dataset can be denoted as... ,in, Indicates the experimental group number. Indicates the first Group experience data, Indicated in the first The proportion of DRAM capacity in the group of empirical data and has (The ratio of DRAM to CXL extended memory is...) ), Indicated in the first The percentage of write operations in the group's experience data. Indicated in the first The proportion of non-sequential write operations in the total write operations within the empirical data set. Indicated in the first The memory bandwidth measured in the empirical data set when the number of concurrent cores is N (i.e., the functional form of the dependent variable when the independent variable is the number of concurrent cores N). The aforementioned proportion of write operations and the proportion of non-sequential write operations in the write operations can be used as the memory access pattern features, that is, the memory access pattern features include, but are not limited to, the proportion of write operations and / or the proportion of non-sequential write operations in the write operations. In addition, the empirical data can be obtained through conventional offline experimental records and stored in a database, and then the offline empirical dataset can be obtained from the database through conventional access methods.

[0032] S2. For each set of experience data in the offline experience dataset, based on the mapping relationship between memory bandwidth and concurrent core count in the corresponding data, determine the corresponding effective extended core count as the corresponding sample label, and combine the DRAM capacity ratio and memory access mode features in the corresponding data to form the corresponding sample feature vector. The effective extended core count refers to the maximum number of concurrent cores that the CXL hierarchical memory system can support when the extension efficiency is not lower than a preset efficiency threshold.

[0033] In step S2, the mapping relationship between memory bandwidth and concurrent cores is the memory bandwidth measured when the number of concurrent cores is N; for example, for the first... Group of experience data, the mapping relationship can be obtained through This can be represented as a complex curve of memory bandwidth versus concurrent cores, which needs to be compressed into a learnable scalar target—the effective number of expanded cores. Specifically, for each set of empirical data in the offline empirical dataset, the corresponding effective number of expanded cores is determined based on the mapping relationship between memory bandwidth and concurrent cores in the corresponding data, including but not limited to the following steps S21 to S23.

[0034] S21. For a certain set of experience data in the offline experience dataset, obtain the mapping relationship between memory bandwidth and concurrent cores in the corresponding data.

[0035] S22. Based on the mapping relationship, the expansion efficiency is calculated according to the following formula.

[0036]

[0037] In the formula, This represents the number of concurrent cores used as an argument to the function. This represents the functional form used as the dependent variable of the memory bandwidth in the mapping relationship. This represents the baseline concurrent core count used for normalization.

[0038] In step S22, the baseline concurrent core count It is a fixed value.

[0039] S23. Based on the aforementioned expansion efficiency The effective number of extended cores corresponding to a certain set of empirical data is determined according to the following formula. :

[0040] In the formula, This represents the function that takes the maximum value. This indicates the preset efficiency threshold.

[0041] In step S23, the above formula reflects that the effective extended core count refers to the maximum number of concurrent cores that the CXL tiered memory system can support when the extended efficiency is not lower than a preset efficiency threshold. Furthermore, the efficiency threshold... Examples are possible, but not limited to the default settings. .

[0042] S3. Based on each pair of sample feature vectors and sample labels that correspond one-to-one with the empirical data of each group, an effective extended kernel number prediction model is trained.

[0043] In step S3, the sample feature vector is the model input during model training, and the sample label is the model output during model training. The effective extended kernel number prediction model can be trained using conventional calibration and validation modeling methods. Specifically, the effective extended kernel number prediction model can be obtained through regularized training based on a quadratic polynomial regression model containing interaction and nonlinear terms. An example of such a quadratic polynomial regression model is as follows:

[0044] In the formula, This represents the functional form of the effective extended core number prediction model. The model parameters can be obtained by fitting the model through training, for example... , , , , , , , and This enables the effective extended kernel number prediction model to be used for rapid inference and solution in the online phase. Furthermore, the regularization training refers to using regularization techniques to constrain the model training process, such as using Ridge Regression with L2 regularization, where the loss function is the sum of the squared loss term and the L2 regularization term, and the model coefficients are solved by minimizing this loss function.

[0045] S4. After receiving the target value of the effective extended core count and the memory access mode characteristics of the current workload, the minimum DRAM capacity ratio that satisfies the target constraint is obtained by combining the effective extended core count prediction model. The target constraint means that the predicted value of the effective extended core count obtained after importing the solution of the DRAM capacity ratio and the memory access mode characteristics of the current workload into the effective extended core count prediction model must be greater than or equal to the target value of the effective extended core count.

[0046] In step S4, the target value for the effective expanded core count is the scalable concurrency capability given by the user (which can be equivalently understood as the system's desire to maintain sufficient scalability at the target concurrency level); the memory access pattern characteristics of the current workload specifically include, but are not limited to, the proportion of write operations and / or the proportion of non-sequential write operations in the write operations; the aforementioned two pieces of information can be, but are not limited to, obtained from user input. This step expresses the storage ratio selection as a constrained optimization problem and solves it: given the workload (i.e., the memory access pattern characteristics of the current workload) and the target (i.e., the target value for the effective expanded core count), the minimum DRAM capacity ratio that satisfies the target is solved. For ease of numerical solution, preferably, after receiving the target value for the effective expanded core count and the memory access pattern characteristics of the current workload, the minimum DRAM capacity ratio that satisfies the target constraint is solved by combining the effective expanded core count prediction model, including but not limited to the following steps S41 to S43.

[0047] S41. After receiving the target value for the effective expanded core count and the memory access pattern characteristics of the current workload, and combining the effective expanded core count prediction model, determine the following objective function. :

[0048] In the formula, This represents the percentage of DRAM capacity used as the independent variable of the function. This indicates the memory access pattern characteristics of the current workload. This represents the functional form of the effective extended core number prediction model. This represents the target value for the effective number of extended cores.

[0049] S42. Judgment Is it less than zero?

[0050] In step S42, specifically, the numerical value is... Import the target function Then, the calculation results are obtained and a threshold judgment is performed.

[0051] S43. If yes, output a warning message indicating that the minimum DRAM capacity percentage required to meet the target constraint is unattainable; otherwise, output a message within the interval... Inside, solve for the condition that satisfies The root or equivalent solution is used to find the minimum DRAM capacity percentage that makes the target constraint condition first true, and the solution result is used as the minimum DRAM capacity percentage that satisfies the target constraint condition. The target constraint condition refers to the effective extended core number prediction value obtained after importing the solution result of the DRAM capacity percentage and the memory access mode characteristics of the current workload into the effective extended core number prediction model, which needs to be greater than or equal to the effective extended core number target value.

[0052] In step S43, because This indicates that even with 100% DRAM capacity (i.e., no CXL extended memory involved), the target cannot be achieved, therefore the aforementioned warning message needs to be output (at this time, the corresponding predicted value can also be output). Furthermore, since the effective extended kernel number prediction model is obtained through regularized training based on a quadratic polynomial regression model containing interaction terms and nonlinear terms, Since it is a low-order polynomial, a one-dimensional solver based on methods such as the bisection method or Newton's method can also be used to solve for the polynomial that satisfies the following conditions. The root or equivalent solution is the minimum DRAM capacity percentage that makes the target constraint condition first true.

[0053] S5. Based on the minimum DRAM capacity ratio, generate a ratio scheme for DRAM and CXL extended memory.

[0054] In step S5, for example, when the minimum DRAM capacity percentage is used When expressed, the ratio of DRAM to CXL extended memory can be configured as follows: .

[0055] S6. Output the ratio scheme for configuration by the CXL hierarchical memory system.

[0056] In step S6, the minimum DRAM capacity percentage can also be used as a basis. Output the corresponding predicted value For configuration reference.

[0057] Based on the above steps S1 to S6, this embodiment also provides a typical experimental configuration: using a commercial CXL 2.0 server platform, a workload is generated using a memory benchmark tool, covering: the ratio of DRAM to CXL extended memory (e.g., 90:10 to 25:75), the number of concurrent cores (e.g., 2 to 22), and the I / O mode (e.g., 100% read, 3 reads and 1 write, 2 reads and 1 non-sequential write); model training is completed based on this data, and the effectiveness of online recommendations and model accuracy are verified, showing good performance.

[0058] Therefore, based on the DRAM and CXL extended memory ratio optimization method described in steps S1 to S6 above, a new scheme is provided to achieve proactive planning and optimization recommendation of the DRAM and CXL extended memory ratio. First, an offline experience dataset containing DRAM capacity ratio, memory access mode characteristics, and bandwidth-concurrent core number mapping relationship is obtained. Then, the effective extended core number is determined based on the bandwidth-concurrent core number mapping relationship as a sample label. The DRAM capacity ratio and memory access mode characteristics are combined to form a sample feature vector, and an effective extended core number prediction model is trained. Next, after receiving the target value of the effective extended core number and the memory access mode characteristics of the current workload, the prediction model is used to solve for the minimum DRAM capacity ratio that satisfies the target constraints. Finally, a ratio scheme is generated based on the minimum DRAM capacity ratio and output for system configuration. In this way, given performance targets and workload characteristics, an interpretable and reproducible recommended DRAM and CXL extended memory ratio can be automatically provided, avoiding arbitrary configuration based on experience, and facilitating practical application and promotion.

[0059] like Figure 2 As shown, the second aspect of this embodiment provides a virtual device for implementing the DRAM and CXL extended memory ratio optimization method described in the first aspect, including a dataset acquisition unit, a sample data processing unit, a prediction model training unit, a minimum ratio solution unit, a ratio scheme generation unit, and a ratio scheme output unit that are sequentially connected in communication. The dataset acquisition unit is used to acquire an offline experience dataset, wherein the offline experience dataset contains multiple sets of experience data obtained through offline experiments. Each set of experience data contains DRAM capacity percentage, memory access mode characteristics, and memory bandwidth measured when the number of concurrent cores is N, where N represents a positive integer. The sample data processing unit is used to determine the corresponding effective number of extended cores as the corresponding sample label for each group of experience data in the offline experience dataset, based on the mapping relationship between memory bandwidth and concurrent cores in the corresponding data, and to form the corresponding sample feature vector by combining the DRAM capacity ratio and memory access mode features in the corresponding data. The effective number of extended cores refers to the maximum number of concurrent cores that the CXL hierarchical memory system can support when the extension efficiency is not lower than a preset efficiency threshold. The prediction model training unit is used to train an effective extended kernel number prediction model based on each pair of sample feature vectors and sample labels that correspond one-to-one with each group of empirical data. The minimum percentage calculation unit is used to, after receiving the target value of the effective extended core count and the memory access mode characteristics of the current workload, combine the effective extended core count prediction model to calculate the minimum DRAM capacity percentage that satisfies the target constraint condition. The target constraint condition means that the predicted value of the effective extended core count obtained after importing the solution result of the DRAM capacity percentage and the memory access mode characteristics of the current workload into the effective extended core count prediction model needs to be greater than or equal to the target value of the effective extended core count. The ratio scheme generation unit is used to generate a ratio scheme of DRAM and CXL extended memory based on the minimum DRAM capacity ratio. The scaling scheme output unit is used to output the scaling scheme for the CXL hierarchical memory system to configure.

[0060] The working process, working details and technical effects of the aforementioned device provided in the second aspect of this embodiment can be found in the DRAM and CXL extended memory ratio optimization method described in the first aspect, and will not be repeated here.

[0061] like Figure 3 As shown, the third aspect of this embodiment provides a computer device for executing the DRAM and CXL extended memory ratio optimization method as described in the first aspect. The device includes a storage module, a processing module, and a transceiver module connected in sequence. The storage module stores a computer program, the transceiver module sends and receives messages, and the processing module reads the computer program and executes the DRAM and CXL extended memory ratio optimization method as described in the first aspect. Specifically, the storage module may include, but is not limited to, random-access memory (RAM), read-only memory (ROM), flash memory, first-in-first-out (FIFO) memory, and / or first-in-last-out (FILO) memory, etc.; the processing module may, but is not limited to, use a microprocessor of the STM32F105 series. Furthermore, the computer device may also include, but is not limited to, a power supply module, a display screen, and other necessary components.

[0062] The working process, working details and technical effects of the aforementioned computer device provided in the third aspect of this embodiment can be found in the DRAM and CXL extended memory ratio optimization method described in the first aspect, and will not be repeated here.

[0063] This fourth aspect of the embodiment provides a computer-readable storage medium storing instructions comprising the DRAM and CXL extended memory ratio optimization method as described in the first aspect. Specifically, the computer-readable storage medium stores instructions that, when executed on a computer, perform the DRAM and CXL extended memory ratio optimization method as described in the first aspect. The computer-readable storage medium refers to a data storage medium, which may include, but is not limited to, floppy disks, optical disks, hard disks, flash memory, USB flash drives, and / or Memory Sticks. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices.

[0064] The working process, working details and technical effects of the aforementioned computer-readable storage medium provided in the fourth aspect of this embodiment can be found in the DRAM and CXL extended memory ratio optimization method described in the first aspect, and will not be repeated here.

[0065] This fifth aspect of the embodiment provides a computer program product, including a computer program or instructions, which, when executed by a computer, implements the DRAM to CXL extended memory ratio optimization method as described in the first aspect. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device.

[0066] Finally, it should be noted that the above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for optimizing the ratio of DRAM to CXL extended memory in a CXL tiered memory system, characterized in that, include: Obtain an offline experience dataset, wherein the offline experience dataset contains multiple sets of experience data obtained through offline experiments, and each set of experience data contains DRAM capacity percentage, memory access pattern characteristics, and memory bandwidth measured when the number of concurrent cores is N, where N represents a positive integer; For each set of experience data in the offline experience dataset, the corresponding effective number of extended cores is determined as the corresponding sample label based on the mapping relationship between memory bandwidth and concurrent cores in the corresponding data. The DRAM capacity ratio and memory access mode features in the corresponding data are combined to form the corresponding sample feature vector. The effective number of extended cores refers to the maximum number of concurrent cores that the CXL hierarchical memory system can support when the extension efficiency is not lower than a preset efficiency threshold. Based on each pair of sample feature vectors and sample labels that correspond one-to-one with the aforementioned groups of empirical data, an effective extended kernel number prediction model is trained. After receiving the target value for the effective number of extended cores and the memory access pattern characteristics of the current workload, the minimum DRAM capacity ratio that satisfies the target constraint is obtained by combining the effective number of extended cores prediction model. The target constraint means that the predicted value of the effective number of extended cores obtained after importing the solution of the DRAM capacity ratio and the memory access pattern characteristics of the current workload into the effective number of extended cores prediction model must be greater than or equal to the target value for the effective number of extended cores. Based on the minimum DRAM capacity ratio, a DRAM to CXL extended memory ratio scheme is generated; The aforementioned scaling scheme is output for configuration by the CXL tiered memory system.

2. The method for optimizing the ratio of DRAM to CXL extended memory according to claim 1, characterized in that, The memory access pattern features include the proportion of write operations and / or the proportion of non-sequential write operations in the total write operations.

3. The method for optimizing the ratio of DRAM to CXL extended memory according to claim 1, characterized in that, For each set of experience data in the offline experience dataset, the corresponding effective number of extended cores is determined based on the mapping relationship between memory bandwidth and concurrent core count in the corresponding data, including: For a set of experience data in the offline experience dataset, obtain the mapping relationship between memory bandwidth and concurrent core count in the corresponding data; Based on the mapping relationship, the expansion efficiency is calculated using the following formula. In the formula, This represents the number of concurrent cores used as an argument to the function. This represents the functional form used as the dependent variable of the memory bandwidth in the mapping relationship. This represents the baseline concurrent core count used for normalization; According to the expansion efficiency The effective number of extended cores corresponding to a certain set of empirical data is determined according to the following formula. : In the formula, This represents the function that takes the maximum value. This indicates the preset efficiency threshold.

4. The method for optimizing the ratio of DRAM to CXL extended memory according to claim 1, characterized in that, The effective extended kernel number prediction model is obtained by regularization training based on a quadratic polynomial regression model containing interaction terms and nonlinear terms.

5. The method for optimizing the ratio of DRAM to CXL extended memory according to claim 1, characterized in that, After receiving the target value for the effective number of extended cores and the memory access pattern characteristics of the current workload, and combining the effective number of extended cores prediction model, the minimum DRAM capacity percentage that satisfies the target constraints is calculated, including: After receiving the target value for the effective number of extended cores and the memory access pattern characteristics of the current workload, and combining the effective number of extended cores prediction model, the following objective function is determined. : In the formula, This represents the percentage of DRAM capacity used as the independent variable of the function. This indicates the memory access pattern characteristics of the current workload. This represents the functional form of the effective extended core number prediction model. This represents the target value for the effective extended core count; judge Is it less than zero? If yes, then output a warning message indicating that the minimum DRAM capacity percentage required to meet the target constraint is unattainable; otherwise, output a message within the specified range. Inside, solve for the condition that satisfies The root or equivalent solution is used to find the minimum DRAM capacity percentage that makes the target constraint condition first true, and the solution result is used as the minimum DRAM capacity percentage that satisfies the target constraint condition. The target constraint condition refers to the effective extended core number prediction value obtained after importing the solution result of the DRAM capacity percentage and the memory access mode characteristics of the current workload into the effective extended core number prediction model, which needs to be greater than or equal to the effective extended core number target value.

6. The method for optimizing the ratio of DRAM to CXL extended memory according to claim 5, characterized in that, Solve for the condition The root or equivalent solution for the minimum DRAM capacity percentage that makes the target constraint condition first true includes: When the effective extended kernel number prediction model is obtained through regularized training based on a quadratic polynomial regression model containing interaction and nonlinear terms, a one-dimensional solver based on the bisection method or Newton's method is used to solve for the condition... The root or equivalent solution is the minimum DRAM capacity percentage that makes the target constraint condition first true.

7. A device for optimizing the ratio of DRAM to CXL extended memory in a CXL tiered memory system, characterized in that, It includes a dataset acquisition unit, a sample data processing unit, a prediction model training unit, a minimum proportion solution unit, a proportion scheme generation unit, and a proportion scheme output unit, which are connected in sequence. The dataset acquisition unit is used to acquire an offline experience dataset, wherein the offline experience dataset contains multiple sets of experience data obtained through offline experiments. Each set of experience data contains DRAM capacity percentage, memory access mode characteristics, and memory bandwidth measured when the number of concurrent cores is N, where N represents a positive integer. The sample data processing unit is used to determine the corresponding effective number of extended cores as the corresponding sample label for each group of experience data in the offline experience dataset, based on the mapping relationship between memory bandwidth and concurrent cores in the corresponding data, and to form the corresponding sample feature vector by combining the DRAM capacity ratio and memory access mode features in the corresponding data. The effective number of extended cores refers to the maximum number of concurrent cores that the CXL hierarchical memory system can support when the extension efficiency is not lower than a preset efficiency threshold. The prediction model training unit is used to train an effective extended kernel number prediction model based on each pair of sample feature vectors and sample labels that correspond one-to-one with each group of empirical data. The minimum percentage calculation unit is used to, after receiving the target value of the effective extended core count and the memory access mode characteristics of the current workload, combine the effective extended core count prediction model to calculate the minimum DRAM capacity percentage that satisfies the target constraint condition. The target constraint condition means that the predicted value of the effective extended core count obtained after importing the solution result of the DRAM capacity percentage and the memory access mode characteristics of the current workload into the effective extended core count prediction model needs to be greater than or equal to the target value of the effective extended core count. The ratio scheme generation unit is used to generate a ratio scheme of DRAM and CXL extended memory based on the minimum DRAM capacity ratio. The scaling scheme output unit is used to output the scaling scheme for the CXL hierarchical memory system to configure.

8. A computer device, characterized in that, It includes a storage module, a processing module, and a transceiver module that are sequentially connected in communication. The storage module is used to store computer programs, the transceiver module is used to send and receive messages, and the processing module is used to read the computer programs and execute the DRAM to CXL extended memory ratio optimization method as described in any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that... The computer-readable storage medium stores instructions that, when executed on a computer, perform the DRAM to CXL extended memory ratio optimization method as described in any one of claims 1 to 6.

10. A computer program product, comprising a computer program or instructions, characterized in that, When the computer program or the instructions are executed by the computer, they implement the DRAM to CXL extended memory ratio optimization method as described in any one of claims 1 to 6.

Images