A hardware atomic jump execution interface for a computing center

Abstract

The application discloses a kind of hardware atomic jump execution interfaces of wisdom calculation center, belong to wisdom calculation center instruction execution technical field, solve the problem that existing atomic jump instruction is easily interrupted, execution integrity cannot be guaranteed, dependent on software analysis, easily be multi-instruction preemption channel.The interface is exclusive physical interface, with general data instruction interface whole hardware electrical isolation, only for the transmission and execution of hardware level atomic jump instruction;Core includes single instruction whole process physical exclusive hardware channel, atomic instruction hardware identification circuit, non-interruptible hardware execution module;Channel whole process physical exclusive in single instruction execution cycle, without any multiplexing mechanism;Atomic instruction feature code is identified by non-reconfigurable fixed hardware logic, without software pre-intervention port;Execution whole process without any interruption can be broken, can guarantee the uniqueness of instruction execution, non-interruptibility and integrity.The application realizes hardware level atomic jump execution without software dependence, can effectively reduce the probability that instruction is interrupted, tampered, preemption, execution reliability is high, applicable to the accurate and reliable execution scene of wisdom calculation center, supercomputing center bottom hardware instruction.

Description

Technical Field

[0001] This invention belongs to the field of intelligent computing center instruction execution technology, and specifically relates to an intelligent computing center hardware atomic jump execution interface that is suitable for the underlying management and control architecture and ensures the uniqueness of instructions. Background Technology

[0002] In the underlying hardware management architecture of intelligent computing centers, atomic jump instructions are the core to ensure the accurate and reliable execution of hardware scheduling, data addressing, and access control instructions. These instructions must be unique, uninterruptible, and complete in execution—that is, "either fully executed or not executed at all," with no possibility of interruption or partial execution. Currently, the execution of atomic jump instructions in intelligent computing centers relies on software implementations, including software atomic locks, kernel-mode instruction encapsulation, and driver-level execution scheduling. This presents the following unresolved technical shortcomings: 1. Instruction execution is easily interrupted and its integrity cannot be guaranteed: During the execution of atomic instructions, they can be interrupted by hardware interrupts, software interrupts, and firmware interrupts, which can easily lead to partial execution of instructions or execution exceptions. This makes it impossible to achieve true atomicity, resulting in errors in the underlying hardware scheduling and chaotic data addressing. 2. Channels are easily preempted, and instruction uniqueness cannot be guaranteed: Existing instruction interfaces mostly adopt time-division multiplexing and frequency-division multiplexing mechanisms. During the execution of a single instruction, the channel can be preempted by other instructions, which can easily lead to problems such as multiple instructions overlapping, instruction tampering, and disordered execution order, and cannot guarantee the uniqueness of instructions. 3. Relies on software parsing, making it vulnerable to tampering and bypass: Atomic instructions need to go through multiple stages such as software pre-parsing, pre-packaging, and kernel forwarding. Malicious code can execute illegal instructions by tampering with instruction characteristics, forging atomic instructions, and bypassing software verification, posing serious security risks. 4. No true hardware-level atomic execution solution: All existing publicly available solutions cannot be separated from the participation of software and firmware, and cannot achieve fully hardware-based atomic instruction recognition, channel exclusivity, and uninterrupted execution, thus failing to fundamentally guarantee the reliability of atomic jump instruction execution. Summary of the Invention

[0003] Technical problems to be solved The purpose of this invention is to overcome the shortcomings of the prior art and provide a hardware atomic jump execution interface for intelligent computing centers. This solves the technical problems of existing atomic jump instructions being easily interrupted, lacking integrity of execution, relying on software parsing that is easily tampered with, and channels being easily preempted. It achieves stable and uninterrupted hardware-level atomic jump execution without software dependencies. Technical solution

[0004] To achieve the above objectives, the present invention adopts the following technical solution: A hardware atomic jump execution interface for intelligent computing centers includes a single-instruction, fully physically exclusive hardware channel, an atomic instruction hardware identification circuit, and an uninterruptible hardware execution module. This interface is a dedicated physical interface for the global underlying hardware management architecture of computing infrastructure such as intelligent computing centers and supercomputing centers. It is fully electrically isolated from general data instruction interfaces and is used solely for the transmission and execution of hardware-level atomic jump instructions. The single-instruction, fully physically exclusive hardware channel allows only that single atomic jump instruction to be physically exclusive throughout its entire execution cycle, without any time-division multiplexing, frequency-division multiplexing, or virtual channel multiplexing mechanisms, thus preventing the superposition of multiple instructions. Instruction interruption and channel preemption; the atomic instruction hardware identification circuit uses non-reconfigurable, non-field programmable gate array (NFPGA) fixed hardware logic to solidify the unique feature code of the atomic jump instruction, identifying only the exclusive native hardware atomic jump instruction, shielding all non-compliant instructions, and without any software pre-parsing, pre-packaging, pre-intervention, or firmware processing ports; the uninterruptible hardware execution module is directly connected to the computing power node hardware execution unit, and the entire execution of the atomic jump instruction is without any software intervention ports, hardware interrupts, software interrupts, or firmware interrupts, ensuring the uniqueness, uninterruptibility, and execution integrity of the atomic jump operation.

[0005] Furthermore, the interface is equipped with a hardware feedback circuit for instruction execution completion. After the instruction is executed, a hardware level feedback signal is sent directly to the global control architecture, eliminating the need for software feedback and achieving pure hardware real-time feedback of the instruction execution status.

[0006] Furthermore, the single-instruction, fully physically exclusive hardware channel is equipped with an instruction timeout hardware monitoring unit. By pre-setting a timeout threshold through fixed hardware logic, the channel is automatically released after the instruction execution times out, without the need for software monitoring and triggering, thus avoiding resource waste caused by long-term channel occupation. Beneficial effects

[0007] Compared with the prior art, the present invention has the following outstanding substantive features and significant beneficial effects: 1. Stable and uninterruptible atomic execution is achieved. The entire instruction execution process is uninterrupted by any hardware, software, or firmware interrupts, which greatly reduces the probability of interruption or partial execution during instruction execution, ensuring the integrity of instruction execution and fundamentally solving the core defect of existing solutions that cannot guarantee atomicity. 2. Hardware-level guarantee of instruction uniqueness is achieved. During the complete execution cycle of a single instruction, the channel is physically exclusive throughout the entire process without any reuse mechanism. This effectively prevents problems such as multiple instructions overlapping, channel preemption, and disordered execution order, ensuring the uniqueness and accuracy of instruction execution. 3. The entire process is software-free, which greatly reduces the risk of instructions being tampered with, forged, or bypassed. The atomic instruction signature is identified through fixed hardware logic that cannot be reconfigured. There is no software pre-parsing or pre-intervention port. It only identifies exclusive native hardware atomic jump instructions and blocks all non-compliant instructions, which significantly improves security and reliability. 4. Completely free from the architectural defects of existing software atomic locks, it can run independently without relying on operating systems, kernel scheduling, and drivers. With an execution response time of less than 10 nanoseconds, it can guarantee a high success rate of instruction execution and effectively reduce the probability of software crashes and scheduling deadlocks. It provides accurate, reliable, and secure atomic instruction execution capabilities for the underlying hardware management architecture of intelligent computing centers and supercomputing centers. Detailed Implementation

[0008] The technical solution of the present invention will be further described in detail below.

[0009] The intelligent computing center hardware atomic jump execution interface described in this embodiment is applied to the global underlying hardware management architecture of the intelligent computing center. It provides dedicated atomic jump instruction execution capabilities for hardware-level parallel directory management, targeted power-off energy-saving management, and permission management of the intelligent computing center, ensuring the accurate, reliable, and uninterrupted execution of underlying hardware scheduling instructions.

[0010] The interface includes a single-instruction, fully physical, dedicated hardware channel, an atomic instruction hardware identification circuit, and an uninterruptible hardware execution module. The modules are directly connected to each other via onboard hardware circuitry, without any software intermediaries.

[0011] The interface is a dedicated physical interface, which is fully electrically isolated from the general data instruction interface in hardware. It is used only for the transmission and execution of hardware-level atomic jump instructions and does not carry any general data instruction transmission function, thus avoiding interference and preemption of atomic jump instructions by general instructions.

[0012] The single-instruction, fully physically exclusive hardware channel is a dedicated onboard hardware transmission path. Within the complete execution cycle of a single atomic jump instruction, only that instruction is allowed to physically occupy the channel exclusively. There are no time-division multiplexing, frequency-division multiplexing, or virtual channel multiplexing mechanisms, which can effectively prevent multiple instructions from overlapping, instruction interruptions, and channel preemption. The channel is equipped with an instruction timeout hardware monitoring unit. A timeout threshold of 100 milliseconds is preset through fixed hardware logic. After the instruction execution times out, the channel is automatically released through hardware logic without the need for software monitoring and triggering, thus avoiding resource waste caused by long-term channel occupation.

[0013] The atomic instruction hardware identification circuit implements fixed hardware logic that is non-reconfigurable and programmable by a non-field programmable gate array through an application-specific integrated circuit. The unique feature code of the atomic jump instruction is solidified through hardware tape-out, without any software pre-parsing, pre-packaging, pre-intervention, or firmware processing ports. The circuit only identifies exclusive native hardware atomic jump instructions that completely match the solidified feature code, shielding all non-compliant and forged instructions. This reduces the probability of illegal instruction execution from a physical level and solves the problem that software parsing is easily tampered with and bypassed.

[0014] The uninterruptible hardware execution module is directly connected to the hardware execution units of the computing power nodes and hardware control modules of the intelligent computing center. The atomic jump instruction is executed without any software intervention ports, hardware interruptions, software interruptions, or firmware interruptions. Once the instruction starts executing, it will definitely complete all operations, either all of them will be executed successfully or none of them will be executed. This greatly reduces the probability of interruption or partial execution, and ensures the uniqueness, uninterruptibility, and integrity of the atomic jump operation.

[0015] The interface is equipped with a hardware feedback circuit for instruction execution completion. After the instruction is executed, it directly sends a feedback signal indicating execution completion / failure to the global management architecture through a hardware level signal. No software feedback is required, which realizes pure hardware real-time feedback of the instruction execution status with a feedback delay of less than 5 nanoseconds.

[0016] The single-instruction, fully physical exclusive timing sequence of this embodiment is as follows: 1. Initial moment: When an atomic jump instruction enters the channel, the channel immediately enters an exclusive state, locking all transmission resources and rejecting any other instructions from entering; 2. Verification period: The atomic instruction hardware recognition circuit completes the instruction feature code verification. After successful verification, the instruction is transmitted to the uninterruptible hardware execution module. 3. Execution period: The uninterruptible hardware execution module has exclusive access to the channel throughout the entire process, fully executing all operations of the atomic jump instruction, completely disabling all interruptions, and no operation can interrupt the execution process; 4. Completion time: When the instruction is executed, the hardware feedback circuit sends an execution completion signal, the channel is released from exclusive status, and the transmission resources are released.

[0017] The interface described in this embodiment involves no software intervention throughout the entire process, and the atomic instruction execution response time is less than 10 nanoseconds. This ensures a high success rate for instruction execution and significantly reduces the risk of instruction interruption, tampering, preemption, or forgery. It provides stable hardware-level atomic execution capabilities for the underlying hardware management architecture of intelligent computing centers, and can meet the high reliability and high security requirements of the underlying scheduling of national-level computing infrastructure.

Claims

1. A hardware atomic jump execution interface for an intelligent computing center, characterized in that, It includes a single-instruction, fully physically exclusive hardware channel, an atomic instruction hardware identification circuit, and an uninterruptible hardware execution module. The interface is a dedicated physical interface for the global underlying hardware management architecture of computing infrastructure such as intelligent computing centers and supercomputing centers. It is fully electrically isolated from general data instruction interfaces and is used solely for the transmission and execution of hardware-level atomic jump instructions. During the complete execution cycle of a single atomic jump instruction, the single-instruction, fully physically exclusive hardware channel allows only that instruction to be physically exclusive, without any time-division multiplexing, frequency-division multiplexing, or virtual channel multiplexing mechanisms, thus preventing the superposition of multiple instructions, instruction interruptions, and channel contention. The atomic instruction hardware identification circuit uses fixed hardware logic that is non-reconfigurable and programmable by a field-programmable gate array to solidify the unique feature code of the atomic jump instruction. It only identifies exclusive native hardware atomic jump instructions, shields all non-compliant instructions, and has no software pre-parsing, pre-packaging, pre-intervention, or firmware processing ports. The uninterruptible hardware execution module is directly connected to the hardware execution unit of the computing power node. The entire execution of the atomic jump instruction is uninterrupted by any software intervention ports, hardware interrupts, software interrupts, or firmware interrupts, ensuring the uniqueness, uninterruptibility, and execution integrity of the atomic jump operation.

2. The intelligent computing center hardware atomic jump execution interface according to claim 1, characterized in that, The interface is equipped with a hardware feedback circuit for instruction execution completion. After the instruction is completed, it directly sends a hardware level feedback signal to the global management architecture without the need for software feedback.

3. The intelligent computing center hardware atomic jump execution interface according to claim 1, characterized in that, The single-instruction, fully physically exclusive hardware channel is equipped with an instruction timeout hardware monitoring unit. The channel is automatically released after the instruction execution times out, without the need for software monitoring or triggering.