Battery management system and vehicle

Abstract

The embodiment of the application provides a battery management system and a vehicle; the battery management system comprises a master control unit and a package body connected with the master control unit; a substrate is packaged in the package body, and the substrate is integrally provided with an analog front-end chip, a power supply circuit, a sampling circuit and a differential communication circuit; under the power supply of the power supply circuit, the analog front-end chip transmits state data of each cell of a vehicle battery pack collected by the sampling circuit to the master control unit through the differential communication circuit, so as to realize communication between the master control unit. The scheme of the application improves the reliability of the battery management system.

Description

Technical Field

[0001] This application relates to the field of vehicle technology, and more particularly to a battery management system and a vehicle. Background Technology

[0002] A Battery Management System (BMS) is a core control system used to monitor, protect, and optimize battery pack performance. It is widely used in electric vehicles, hybrid electric vehicles, energy storage systems, and other fields. Its core objectives are to monitor battery status in real time, ensure battery safety through battery balancing and thermal management, and enable communication and data interaction to ensure the battery continues to be used with high performance, high efficiency, and long lifespan.

[0003] Current BMS solutions suffer from problems such as large circuit area, high signal transmission delay, poor electromagnetic compatibility, and complex testing and maintenance, resulting in poor reliability of the battery management system. Therefore, there is an urgent need for a technical solution to improve the reliability of the battery management system. Summary of the Invention

[0004] The battery management system and vehicle provided in this application embodiment improve the reliability of the battery management system.

[0005] In a first aspect, embodiments of this application provide a battery management system, including:

[0006] The main control unit and the package connected to the main control unit; the package contains a substrate, and the substrate integrates an analog front-end chip, a power supply circuit, a sampling circuit and a differential communication circuit;

[0007] The analog front-end chip, powered by the power supply circuit, transmits the status data of each cell in the vehicle battery pack collected by the sampling circuit to the main control unit through the differential communication circuit, thereby realizing communication with the main control unit.

[0008] In one possible implementation, the substrate is further integrated with an equalization circuit;

[0009] The equalization circuit is used to equalize the voltage of the battery cells in the vehicle battery pack when the voltages are uneven.

[0010] In one possible implementation, the substrate includes multiple conductive layers and multiple insulating layers;

[0011] The multilayer conductive layer and the multilayer insulating layer are stacked alternately;

[0012] The analog front-end chip, as well as the power supply circuit, the sampling circuit, the differential communication circuit, and the equalization circuit, are all disposed on the surface of the substrate;

[0013] The electrical connection traces between the analog front-end chip and the power supply circuit, the sampling circuit, the differential communication circuit, and the equalization circuit are formed in the multilayer conductive layer;

[0014] The multiple conductive layers are connected by through holes that penetrate the insulating layer.

[0015] In one possible implementation, the thickness of the substrate is not less than a first preset value, the roughness of the substrate is not less than a second preset value, and the glass transition temperature of the substrate material is not less than a third preset value.

[0016] In one possible implementation, a solder ball array is disposed on the lower surface of the substrate, the solder ball array extending through the lower surface of the substrate to the outside of the package.

[0017] In one possible implementation, the power supply circuit includes: a first protection module, a first filtering module, a voltage divider module, a drive module, and a second filtering module;

[0018] The first end of the first protection module is connected to the battery pack, and the second end of the first protection module is connected to the first end of the first filter module, for overcurrent protection of the output voltage of the battery pack;

[0019] The second terminal of the first filtering module is connected to the input terminal of the voltage divider module, and is used to filter the output voltage of the battery pack;

[0020] The first output terminal of the voltage divider module is connected to the analog front-end chip, and the second output terminal of the voltage divider module is connected to the analog front-end chip through the driving module. The voltage divider module is used to divide the output voltage after filtering by the first filtering module, and generate the start-up voltage of the analog front-end chip according to the voltage signal after voltage division, so that the first output terminal of the voltage divider module outputs the start-up voltage to the analog front-end chip.

[0021] The driving module receives the driving voltage signal after the analog front-end chip is started, and in response to the driving voltage signal, generates the analog power supply voltage of the analog front-end chip according to the voltage signal after voltage division by the voltage divider module, so that the second output terminal of the voltage divider module outputs the analog power supply voltage to the analog front-end chip;

[0022] The first end of the second filtering module is connected to the driving module, and the second end of the second filtering module is connected to the analog front-end chip, for filtering the analog power supply voltage.

[0023] In one possible implementation, the driving module includes: a transistor and a first resistor;

[0024] The collector of the transistor is connected to the first output terminal of the voltage divider module, the emitter of the transistor is connected to the first terminal of the second filter module, and the base of the transistor is connected to the first terminal of the third resistor.

[0025] The second end of the first resistor is connected to the analog front-end chip.

[0026] In one possible implementation, the first filtering module includes: a first ferrite bead and a first capacitor;

[0027] The first end of the first magnetic bead is connected to the second end of the first protection module, and the second end of the first magnetic bead is connected to the first end of the first capacitor.

[0028] The second terminal of the first capacitor is grounded.

[0029] In one possible implementation, the second filtering module includes: a second ferrite bead, a second capacitor, and a third capacitor;

[0030] The first end of the second magnetic bead is connected to the emitter of the transistor, and the second end of the second magnetic bead is connected to the first end of the second capacitor;

[0031] The second terminal of the second capacitor is grounded;

[0032] The third capacitor is connected in parallel with the second capacitor.

[0033] In one possible implementation, the sampling circuit includes: a sensor sampling circuit and a voltage sampling circuit;

[0034] The sensor sampling circuit is used to collect the operating status data of the cells in the battery pack and transmit it to the analog front-end chip;

[0035] The voltage sampling circuit is used to collect the voltage signal of the battery cell in the battery pack and transmit it to the analog front-end chip.

[0036] In one possible implementation, the sensor sampling circuit includes: multiple sensor acquisition units; the multiple sensor acquisition units are used to acquire cell operating status data of the battery pack; the sensor acquisition unit includes: a sensor, a second protection module, and a third filtering module;

[0037] The sensor receives the measured input and outputs a corresponding analog voltage signal;

[0038] The first end of the second protection module is connected to the sensor, and the second end of the second protection module is grounded, which is used to clamp the analog voltage signal.

[0039] The first end of the third filtering module is connected to the sensor, and the second end of the third filtering module is grounded, for filtering the analog voltage signal.

[0040] In one possible implementation, the voltage sampling circuit includes: a fourth filtering module;

[0041] One end of the fourth filtering module is connected to the battery cell, and the fourth filtering module is connected to the analog front-end chip. It is used to filter the collected battery cell voltage signal so that the filtered battery cell voltage signal is transmitted to the analog front-end chip.

[0042] In one possible implementation, the differential communication circuit includes: at least one differential communication unit; the differential communication unit includes: a fifth filtering module, a current limiting module, and a sixth filtering module;

[0043] The first end of the fifth filtering module is connected to the differential communication interface of the main control unit, and the second end of the fifth filtering module is connected to the first end of the current limiting module, for filtering the differential voltage signal output by the main control unit;

[0044] The second terminal of the current limiting module is connected to the first terminal of the sixth filtering module, and is used to limit the current of the filtered differential voltage signal.

[0045] The second end of the sixth filtering module is connected to the analog front-end chip and is used to filter the differential voltage signal after current limiting.

[0046] In one possible implementation, the equalization circuit includes: a discharge module and a third protection module;

[0047] The first end of the discharge module is connected to the battery cell, and the second end of the discharge module is connected to the analog front-end chip. It is used to discharge the high-voltage battery cell to the low-voltage battery cell when the voltage of the battery cells is unbalanced.

[0048] The first end of the third protection module is connected in parallel with the battery cell to provide surge protection for the output current of the battery cell.

[0049] Secondly, embodiments of this application provide a vehicle, including: a battery management system as described above.

[0050] The battery management system and vehicle provided in this application include a main control unit and a package connected to the main control unit. The package contains a substrate, which integrates an analog front-end chip, a power supply circuit, a sampling circuit, and a differential communication circuit. Powered by the power supply circuit, the analog front-end chip transmits the state data of each cell in the vehicle battery pack collected by the sampling circuit to the main control unit via the differential communication circuit, thus achieving communication with the main control unit. This application's solution integrates and packages a front-end unit for collecting battery state data—comprising the analog front-end chip, its peripheral power supply circuit, the sampling circuit for sampling cell state data, and the differential communication circuit—into a package. This reduces the area of ​​the front-end acquisition hardware circuit, significantly miniaturizing and thinning the battery management system, achieving ultra-high functional density, and enabling signal transmission to achieve higher quality, faster speed, lower latency, and lower power consumption, thereby improving the reliability of the battery management system. Attached Figure Description

[0051] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0052] Figure 1 A schematic diagram of the architecture of a battery management system for example;

[0053] Figure 2 A schematic diagram of the assembly of a battery management system in the form of a printed circuit board, as an example;

[0054] Figure 3 A schematic diagram of the internal circuit structure of the battery management system package provided in an embodiment of this application;

[0055] Figure 4 This is a top view of the package of an example from this application;

[0056] Figure 5 This is a schematic diagram of the ball grid array at the bottom of a substrate, as an example.

[0057] Figure 6 This is a schematic diagram of the structure of the side of the substrate as an example;

[0058] Figure 7 Pin mapping diagram of SiP package as an example;

[0059] Figure 8 This is a schematic diagram of the power supply circuit provided in an embodiment of this application;

[0060] Figure 9 This is a schematic diagram of the sensor sampling circuit provided in an embodiment of this application;

[0061] Figure 10This is a schematic diagram of the voltage sampling circuit provided in an embodiment of this application;

[0062] Figure 11 This is a schematic diagram of the differential communication circuit provided in an embodiment of this application;

[0063] Figure 12 A schematic diagram of the equalization circuit provided in an embodiment of this application.

[0064] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0065] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0066] A Battery Management System (BMS) is a core control system used to monitor, protect, and optimize battery pack performance. It is widely used in electric vehicles, hybrid electric vehicles, energy storage systems, and other fields. Its core objectives are to monitor battery status in real time, ensure battery safety through battery balancing and thermal management, and enable communication and data interaction to ensure the battery continues to be used with high performance, high efficiency, and long lifespan.

[0067] Figure 1 This is a schematic diagram of the architecture of a battery management system as an example; such as Figure 1 As shown, the battery management system includes modules for cell voltage acquisition, cell power balancing, cell analog voltage signal acquisition, isolation communication, battery total voltage measurement, and functional safety. The battery management system is connected to the battery pack, which includes multiple cells, and is used to monitor the status of the battery pack and the multiple cells.

[0068] In the relevant technical solutions, the BMS system is assembled in the form of a printed circuit board assembly (PCBA). Figure 2 This is a schematic diagram of a printed circuit board assembly for an example battery management system; as shown. Figure 2As shown, due to the high-voltage operating limitations of the multi-cell battery pack, various high-power devices and chips are densely packed on the PCB board, making it difficult to reduce the board area. This results in excessively long electrical bridging distances between components, leading to large coupling inductance and poor electromagnetic compatibility. Furthermore, the limited space on the board results in longer traces for some circuits, increasing overall system energy loss and causing signal attenuation and cross-interference, thus affecting system performance and reliability. This contradicts the evolutionary direction of BMS. Figure 2 The circuit board shown measures 80mm x 25mm.

[0069] Printed circuit boards (PCBs) exposed to high temperatures for extended periods experience accelerated aging of solder joints, becoming potential failure points for the system. Occasional mechanical stress or corrosion from the battery cell's electrolyte further contributes to long-term failure due to uncontrollable factors. For fields with higher demands for precision and reliability, such as electric vehicles, energy storage systems, wearable devices, drones, and light power tools, there are clear and rigid requirements for performance and efficiency, but current PCB solutions cannot meet these needs.

[0070] Setting up analog front-end chips and peripheral circuits independently on a PCB board for testing requires not only designing and manufacturing highly customized test fixtures, but also designing dispersed test points for numerous components or networks on the board. This increases development costs, and connection reliability becomes an uncertain factor in subsequent test failures. Environmental testing of the PCB, such as temperature and vibration, is more likely to introduce noise or faults, making it more complex to distinguish between chip-level and board-level issues. PCB repair may involve replacing individual chips, repairing traces, and replacing small components; improper operation can affect surrounding components, complicating rework processes and impacting product yield. When tests fail, the PCB application circuit may exhibit complex interactive faults such as single chip failures, chip soldering problems, PCB trace / via failures, and peripheral component errors, making it difficult to pinpoint the specific fault location.

[0071] PCB board solutions increase material and production costs due to their larger size, and require a large number of discrete peripheral components (resistors, capacitors, inductors, etc.). These components are numerous, expensive, and have complex layouts, requiring multi-layer board designs, which further increases costs. At the same time, selection, procurement, surface mount technology, and supply chain delivery involve more control links and mass production risks. Therefore, there is great room for optimization of PCB system solutions in high-density, high-reliability, and low-cost application environments.

[0072] To address the issues of high cost, large size, low reliability, and high testing difficulty associated with AFE chips in PCB applications, there are currently three optimization levels in electronic integration. The first is integrated circuit (IC) level integration, which involves fabricating numerous transistors, resistors, capacitors, and other components on a tiny silicon wafer using semiconductor processes and connecting them to form electronic circuits with specific functions. This achieves the goals of minimal size, better performance, and lowest mass production cost. However, its complex processes and compatibility issues lead to longer design cycles and increased costs due to repeated error correction during the design process. The second is PCB level integration, mainly reflected in increased line density, increased layer count, and improved component assembly density. However, its limitations in 3D integration are significant, limiting further development potential. The third is system-in-package (SiP) level integration, which involves combining and mounting various components with different functions in three-dimensional space in various forms within a single package to form a complete system. This effectively reduces system size, improves product performance, offers high compatibility, lowers R&D costs, and shortens the R&D cycle.

[0073] The battery management system and vehicle provided in this application include a main control unit and a package connected to the main control unit. The package contains a substrate, which integrates an analog front-end chip, a power supply circuit, a sampling circuit, and a differential communication circuit. Powered by the power supply circuit, the analog front-end chip transmits the state data of each cell in the vehicle battery pack collected by the sampling circuit to the main control unit via the differential communication circuit, thus achieving communication with the main control unit. This application integrates and packages a front-end unit for collecting battery state data—comprising the analog front-end chip, its peripheral power supply circuit, the sampling circuit for sampling cell state data, and the differential communication circuit—into a package. This reduces the area of ​​the front-end acquisition hardware circuit, significantly miniaturizing and thinning the battery management system, achieving ultra-high functional density, and enabling signal transmission to achieve higher quality, faster speed, lower latency, and lower power consumption, thereby improving the reliability of the battery management system.

[0074] This application's solution integrates chip packaging and PCBA assembly processes, and integrates the production supply chain; it integrates chip packaging and PCBA testing, simplifying the testing process; it decouples PCBA circuits and structural functions, improving assembly efficiency; it is suitable for application scenarios such as high-string-count, high-reliability high-voltage battery packs, and the design can be flexibly adjusted according to the application solution, achieving integration and cost reduction.

[0075] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0076] Example 1

[0077] Figure 3 This is a schematic diagram of the internal circuit structure of the battery management system package provided in the embodiments of this application; as shown below. Figure 3 As shown, the battery management system includes: a main control unit and a package connected to the main control unit; the package contains a substrate, and the substrate integrates an analog front-end chip 1, a power supply circuit 2, a sampling circuit and a differential communication circuit 3.

[0078] Under the power supply of the power supply circuit 2, the analog front-end chip 1 transmits the status data of each cell of the vehicle battery pack collected by the sampling circuit to the main control unit through the differential communication circuit 3, thereby realizing communication with the main control unit.

[0079] In this embodiment, the battery management system includes a main control unit and Figure 3 The package shown; Figure 3 The main control unit is not shown. The package contains a substrate. Figure 3 (not shown in the image) Figure 3 The package includes an internal analog front-end chip 1 and external power supply circuit 2, sampling circuit, and differential communication circuit 3. The power supply circuit 2 supplies power to the analog front-end chip 1, enabling it to operate normally. The status data collected by the sampling circuit is transmitted to the analog front-end chip 1. The analog front-end chip 1 communicates with the main control unit of the battery management system through the differential communication circuit 3. The main control unit performs relevant control based on the received battery status data.

[0080] For example, the main control unit of the BMS, as the energy management hub, typically consists of a main control microcontroller (MCU), memory, isolated power supply, and communication interface. The slave control unit is directly connected to the battery cell and is responsible not only for sensing the cell's status, equalization management, and safety protection, but also for data transmission with the main control MCU through a specific protocol. It consists of a dedicated analog front-end chip (AFE) and its peripheral circuitry, and is the core subsystem of the entire battery energy storage system. In this embodiment, the slave control unit is packaged in a SiP (System-in-Package) form and integrated into a single chip unit. Furthermore, the BMS system may also include a sensor network, which assists the slave control unit in acquiring more battery pack parameters through external shunts and temperature sensors. Additionally, protection circuitry is included, primarily to prevent instantaneous current surges and localized overcurrent.

[0081] Reference Figure 3 The power supply circuit 2 is connected to the battery pack under test, receives the total output voltage VDD of the battery pack, and generates a power supply voltage to power the analog front-end chip 1 based on the total output voltage VDD of the battery pack.

[0082] The sampling circuit includes: sensor sampling circuit 4 and voltage sampling circuit 5.

[0083] Sensor sampling circuit 4 is used to collect the cell voltage signal in the battery pack and transmit it to analog front-end chip 1.

[0084] Voltage sampling circuit 5 is used to collect the voltage signal of the battery cells in the battery pack and transmit it to analog front-end chip 1.

[0085] In this embodiment, the sensor sampling circuit 4 can acquire analog voltage signals from each cell of the battery pack. For example, the sensor sampling circuit can be connected to various sensor inputs, such as temperature, current, pressure, and gas sensors, to acquire state data of each cell in the battery pack, which is then acquired in the form of analog voltage. In one example, Figure 3 The thermistor RTa, which is connected to ground, can collect the temperature signal of the battery cell.

[0086] The voltage sampling circuit 5 is used to collect the voltage across each cell in the battery pack, thus enabling the collection of voltage signals from each cell in the battery pack. Figure 3 Ports BN+, B(N+1)+, and B(N+2)+ in the configuration are all connected to the ports of the battery cells, and any two ports can be connected to one battery cell. By acquiring the voltage values ​​of each port, the voltage of the battery cells in the battery pack can be obtained. For example, the voltage signals received by the analog front-end chip 1 are VCN, VC(N+1), and VC(N+2).

[0087] In this embodiment, by setting up a sampling circuit, the operating status data of the battery pack cells and the accurate voltage signal of the battery pack cells are collected. This allows for accurate reception of the current operating status of the battery pack, improving the reliability of the battery management system in managing the battery pack.

[0088] In this embodiment, the battery management system includes a main control unit and a package connected to the main control unit. A substrate is encapsulated within the package, and the substrate integrates an analog front-end chip, a power supply circuit, a sampling circuit, and a differential communication circuit. Powered by the power supply circuit, the analog front-end chip transmits the state data of each cell in the vehicle battery pack collected by the sampling circuit to the main control unit via the differential communication circuit, thus achieving communication with the main control unit. This application's solution integrates and packages a front-end unit for collecting battery state data—comprising an analog front-end chip, its peripheral power supply circuit, a sampling circuit for sampling cell state data, and a differential communication circuit—into a package. This reduces the area of ​​the front-end acquisition hardware circuitry, significantly miniaturizing and thinning the battery management system, achieving ultra-high functional density, and enabling signal transmission to achieve higher quality, faster speed, lower latency, and lower power consumption, thereby improving the reliability of the battery management system.

[0089] Optionally, the substrate may also integrate an equalization circuit 6.

[0090] The equalization circuit is used to balance the voltage of the battery cells in a vehicle battery pack when the voltages are uneven.

[0091] In this embodiment, the package also includes an equalization circuit 6. When the voltage signal of the battery pack is collected and an unbalanced cell is detected, the analog front-end chip 1 activates the voltage equalization circuit 6 to equalize the voltage of the unbalanced cell. For example, when the analog front-end chip 1 determines that an unbalanced cell exists based on the received voltage values ​​of VCN, VC(N+1), and VC(N+2), it activates the equalization circuit, causing the high-voltage cell to discharge to the low-voltage cell, thereby achieving voltage equalization.

[0092] In this embodiment, by acquiring the voltage signals of the battery pack cells in real time, cells with unbalanced voltage can be detected in a timely manner, and voltage balancing can be performed on the cells, further improving the reliability of the battery management system's management and control of the battery pack cells.

[0093] Optionally, the substrate includes multiple conductive layers and multiple insulating layers.

[0094] Multiple conductive layers and multiple insulating layers are stacked alternately.

[0095] The analog front-end chip 1, as well as the power supply circuit 2, sampling circuit, differential communication circuit 3 and equalization circuit 6 are all disposed on the surface of the substrate.

[0096] The electrical connection traces between the analog front-end chip 1 and the power supply circuit 2, sampling circuit, differential communication circuit 3 and equalization circuit 6 are formed in a multilayer conductive layer.

[0097] The multiple conductive layers are connected through through-holes that penetrate the insulating layer.

[0098] In this embodiment, to reduce the electrical bridging distance between circuit components within the package, the package substrate is designed as a multi-layer structure, including multiple conductive layers and insulating layers stacked in an alternating manner. The components of the aforementioned power supply circuit 2, differential communication circuit 3, temperature sampling circuit 4, voltage sampling circuit 5, and equalization circuit 6 are disposed on the surface of the substrate. The connection traces of each circuit are formed on the conductive layers, and the multiple conductive layers are connected through vias penetrating the insulating layers; this forms a vertical connection path, reducing the electrical bridging distance between circuits, lowering signal delay, and reducing electromagnetic interference.

[0099] Figure 4 This is a top view of the package of an example from this application; as shown Figure 4 As shown, the package contains an analog front-end chip 1, a power supply circuit 2, a differential communication circuit 3, a temperature sampling circuit 4, a voltage sampling circuit 5, and an equalization circuit 6.

[0100] The SiP-packaged AFE chip in this embodiment significantly reduces the hardware circuit area for front-end battery status data acquisition in a BMS. The SiP-integrated AFE chip has an application size of only 22.5mm*25mm. Due to the high integration of functional circuits within the SiP-packaged driver chip of the high-voltage AFE, the electrical bridging distance between components is extremely short, greatly reducing the parasitic inductance of the drive circuit and effectively suppressing electromagnetic radiation generated by the drive circuit, thus significantly improving operational reliability. Simultaneously, chip-based design reduces the size and weight of the high-voltage AFE chip application circuit, improving the stability of cell sampling parameters in the BMS system.

[0101] SiP (System-in-Package) packaging of AFE (Automatic External Component) chips in BMS (Browser Management System) integrates chip packaging with PCBA (Printed Circuit Board Assembly) processes and the production supply chain. SiP integrates AFE chips, passive components (resistors and capacitors for various circuits), protection circuits, and communication circuits into a single package, significantly reducing the number of discrete components and soldering points on the PCB, simplifying PCB layout and assembly processes, and reducing process complexity. SiP integrates chips and passive components into a single material, reducing the number of suppliers and procurement management costs. Traditional PCBs require managing dozens of components, while SiP only requires purchasing the packaged module, significantly reducing the number of Bill of Materials (BOM) items and accelerating the overall manufacturing process.

[0102] SiP-packaged AFE chips integrate chip packaging and PCBA testing in BMS, significantly simplifying the testing process. SiP completes internal circuit testing during the packaging stage, requiring only system-level testing after PCB assembly. In contrast, traditional PCBs require calibration and troubleshooting for each sampling channel (such as cold solder joints or component parameter drift), greatly reducing the complexity of the testing process.

[0103] SiP-packaged AFE chips are used in BMS to decouple PCBA circuits and structural functions. SiP can flexibly integrate different functional modules (such as isolated communication, temperature sensors, and protection circuits) to form a complete subsystem of "AFE + peripherals", which can not only improve assembly efficiency, but also enhance automation compatibility.

[0104] Optionally, the thickness of the substrate is not less than a first preset value, the roughness of the substrate is not less than a second preset value, and the glass transition temperature of the substrate material is not less than a third preset value.

[0105] In this embodiment, SiP packaging is a complex system composed of multiple materials (wafer, passive components, molding compound, carrier, adhesive, metal leads, etc.). This multi-material and multi-structure characteristic may lead to various high failure risk phenomena such as delamination, warping, and thermal accumulation in the packaging.

[0106] Due to the significant differences in the coefficient of thermal expansion (CTE) among different materials, temperature changes (such as during soldering, aging, and extreme operating environments) can lead to localized stress concentrations, even exceeding the material's tolerance limits. This can cause delamination at the interface between the molding compound and the substrate, solder joint breakage between the chip and the substrate, and microcracks within the chip, resulting in deterioration of the chip's mechanical properties, functional interruption, or even complete failure. Therefore, material matching and design of experiments (DOE) molding parameters for SiP molding compounds can be optimized to increase the roughness of the substrate solder mask, for example, ensuring that the substrate roughness is not less than a second preset value, thus reducing stress caused by thermal expansion. Furthermore, the board thickness can be increased without significantly increasing the package size and weight, for example, ensuring that the substrate thickness is not less than a first preset value, thereby improving its rigidity and resistance to deformation, and reducing the stress on the solder joints. A substrate material with a high glass transition temperature (Tg) value can also be selected; for example, the substrate material with a glass transition temperature not less than a third preset value, such as 170°C, can be chosen. This provides a lower coefficient of thermal expansion, reducing stress concentration caused by temperature changes, while maintaining good rigidity at high temperatures, effectively resisting deformation caused by thermal stress.

[0107] Optionally, a solder ball array is provided on the lower surface of the substrate, and the solder ball array extends through the lower surface of the substrate to the outside of the package.

[0108] In this embodiment, SiP packaging manufacturing involves multiple processes (such as wafer mounting, molding, reflow soldering, and curing), each of which may introduce and accumulate residual stress: during injection molding, uneven material shrinkage or insufficient curing leads to localized stress concentration, exacerbating warpage; during soldering, large temperature gradients and differences in thermal expansion in different areas may cause deformation of the carrier board or chip. The SiP structure design can be optimized by rationally arranging passive components, increasing the rigidity of the substrate support structure, optimizing the flowability of the molding material, predicting warpage risk through finite element analysis (FEA), and assessing packaging reliability using X-ray inspection and thermal imaging.

[0109] Since the single-channel balancing current of multiple acquisition channels within the package can reach 50mA, heat dissipation is a critical challenge. Effective heat dissipation of the balancing path can be achieved by optimizing the circuit layout and solder ball array layout. To avoid heat concentration, a distributed layout strategy, away from sensitive components, is adopted. The balancing resistors can be distributed along the edge of the substrate, away from temperature-sensitive components such as the AFE chip, avoiding both the formation of hot spots due to close arrangement and the adverse effects of excessive temperature on the sampling accuracy of the AFE chip. In SiP packaging, the solder ball array can be considered the main heat conduction interface. By establishing a dedicated, low-thermal-resistance vertical heat path located directly below the heat source, the thermal conductivity of the solder balls is maximized, and heat is efficiently conducted to the system PCB, thereby achieving efficient three-dimensional vertical heat conduction. Figure 5 This is a schematic diagram of the ball grid array at the bottom of a substrate, as an example. Figure 6 This is a schematic diagram of the structure of the side of the substrate as an example; Figure 7 Here is an example of a SiP package pinout; as shown. Figure 5 As shown, a ball grid array is set on the lower surface of the substrate to achieve heat conduction. Figure 7 For the pins of each circuit on the basic lower surface, through Figure 7 The VDD, GND, and other pins shown enable connections to the main control unit and external PCB board.

[0110] Optional, Figure 8 This is a schematic diagram of the power supply circuit provided in the embodiments of this application; as shown below. Figure 8 As shown, the power supply circuit 2 includes: a first protection module 21, a first filter module 22, a voltage divider module 23, a drive module 24, and a second filter module 25.

[0111] The first end of the first protection module 21 is connected to the battery pack, and the second end of the first protection module 21 is connected to the first end of the first filter module 22, which is used to provide overcurrent protection for the output voltage VDD of the battery pack.

[0112] The second terminal of the first filter module 22 is connected to the input terminal of the voltage divider module 23, and is used to filter the output voltage VDD of the battery pack.

[0113] The first output terminal of the voltage divider module 23 is connected to the analog front-end chip 1, and the second output terminal of the voltage divider module 23 is connected to the analog front-end chip 1 through the driver module 24. The voltage divider module 23 is used to divide the output voltage after filtering by the first filter module 22, and generate the start-up voltage VH of the analog front-end chip 1 according to the voltage signal after voltage division, so that the first output terminal of the voltage divider module 23 outputs the start-up voltage VH to the analog front-end chip 1.

[0114] The drive module 24 receives the drive voltage signal DRIVE after the analog front-end chip 1 is started. In response to the drive voltage signal DRIVE, it generates the analog power supply voltage VD7 of the analog front-end chip 1 according to the voltage signal after voltage division by the voltage divider module 23, so that the second output terminal of the voltage divider module 23 outputs the analog power supply voltage VD7 to the analog front-end chip 1.

[0115] The first end of the second filtering module 25 is connected to the driving module 24, and the second end of the second filtering module 25 is connected to the analog front-end chip 1, which is used to filter the analog power supply voltage VD7.

[0116] In this embodiment, the power supply circuit 2 is connected to the battery pack at one end, receiving the total positive voltage VDD output by the battery pack. This voltage is then passed through the first protection module 21 for overcurrent protection of the battery pack voltage; exemplarily, the first protection module can be a fuse F1. The voltage VDD input to the power supply circuit is then filtered by the first filtering module 22. Optionally, the first filtering module 22 includes a first ferrite bead L1 and a first capacitor C1.

[0117] The first end of the first magnetic bead L1 is connected to the second end of the first protection module 21, and the second end of the first magnetic bead L1 is connected to the first end of the first capacitor C1.

[0118] The second terminal of the first capacitor C1 is grounded.

[0119] In this embodiment, the first ferrite bead L1 and the first capacitor C1 together form an LC filter network. The first ferrite bead L1 can suppress high-frequency noise. Ferrite beads are essentially high-frequency loss devices, presenting high impedance to high-frequency interference, effectively absorbing and attenuating high-frequency noise, glitches, and electromagnetic interference (EMI) in the circuit, while allowing DC and low-frequency signals to pass smoothly. At the same time, the first ferrite bead L1 can block interference, preventing high-frequency noise generated by the preceding circuit from entering the subsequent sensitive circuit, and also preventing noise from the subsequent circuit from reflecting back to the preceding stage. The first capacitor C1 can perform filtering and decoupling, providing a low-impedance path to ground for high-frequency noise, further bypassing residual high-frequency interference that the ferrite bead could not completely filter to ground, making the power supply or signal lines "cleaner"; as an energy storage element, the first capacitor C1 can buffer small current changes in local circuits, helping to stabilize the voltage of that node. The first ferrite bead L1 and the first capacitor C1 together form a highly efficient second-order low-pass filter; it can allow useful DC or low-frequency operating signals to pass through, while filtering out, absorbing and bypassing high-frequency electromagnetic interference (EMI) and power supply noise to the maximum extent, thereby protecting the subsequent circuits from interference and improving the electromagnetic compatibility (EMC) and stability of the system.

[0120] Subsequently, the voltage signal filtered by the first filtering module is then used by the voltage divider module 23 to generate the startup voltage VH and the analog power supply voltage VD7 for the analog front-end chip 1. Optionally, the voltage divider module 23 includes resistors R1 and R2.

[0121] The first end of resistor R1 is connected to the second end of the first filter module 22, and the second end of resistor R1 is connected to the first end of the drive module 24.

[0122] The first end of resistor R2 is connected to the first end of resistor R1, and the second end of resistor R2 is connected to the first end of the second filter module 25.

[0123] In this embodiment, the filtered voltage is divided into two paths by resistors R1 and R2 in the voltage divider module 23. One path generates the startup voltage VH to power the analog front-end chip 1, and the other path generates the analog power supply voltage VD7 to power the analog circuitry inside the analog front-end. After generating the VH voltage, to ensure its stability, it is filtered by a filter module composed of capacitors C4 and C5 before being transmitted to the analog front-end chip 1 through pin VH.

[0124] Optionally, the drive module 24 includes a transistor Q1 and a first resistor R3.

[0125] The collector of transistor Q1 is connected to voltage divider module 23, the emitter of transistor Q1 is connected to the first end of second filter module 25, and the base of transistor Q1 is connected to the first end of first resistor R3.

[0126] The second terminal of the first resistor R3 is connected to the analog front-end chip 1.

[0127] For the branch that generates VD7, the voltage after passing through resistor R1 is first filtered by capacitor C6. When the analog front-end chip 1 starts working, it sends a drive voltage signal DRIVE. When the power supply circuit 2 receives this signal, transistor Q1 responds to the drive signal DRIVE by turning on and off. When transistor Q1 is on, the analog power supply voltage VD7 is generated. The analog power supply voltage VD7 consumes most of the current, so a transistor Q1 is needed for buffering. For example, the drive voltage signal DRIVE sent by the analog front-end chip 1 is also filtered by a filter capacitor C7 before being transmitted to the drive module 24 composed of transistor Q1 and the first resistor R3, so that the drive module 24 drives the generation of the analog power supply voltage VD7; the first resistor R3 is used to limit the current of the drive voltage signal DRIVE.

[0128] The generated analog power supply voltage VD7 is filtered by the second filtering module 25 before being transmitted to the analog front-end chip 1, ensuring that the voltage signal transmitted to the analog front-end chip is a stable and clean signal, thereby improving the stability and reliability of the battery management system.

[0129] Optionally, the second filter module 25 includes: a second ferrite bead L2, a second capacitor C2, and a third capacitor C3;

[0130] The first end of the second ferrite bead L2 is connected to the emitter of the transistor Q1, and the second end of the second ferrite bead L2 is connected to the first end of the second capacitor C2.

[0131] The second terminal of the second capacitor C2 is grounded.

[0132] The third capacitor C3 is connected in parallel with the second capacitor C2.

[0133] In this embodiment, the second filtering module consists of a second magnetic bead L2 and two parallel-connected second capacitors C2 and third capacitors C3, thereby filtering the analog power supply voltage VD7. Its implementation principle is the same as that of the aforementioned first filtering module 22, and will not be described in detail here.

[0134] In this embodiment, the power supply circuit provides power to the analog front-end chip. After protecting and filtering the internal transmission voltage, a clean and stable voltage signal is transmitted to the analog front-end chip, which improves the stability of the power supply to the analog front-end chip and further enhances the reliability and stability of the battery management system.

[0135] Figure 9 This is a schematic diagram of the sensor sampling circuit provided in the embodiments of this application; as shown below. Figure 9As shown, the sensor sampling circuit 4 includes: multiple sensor acquisition units; the multiple sensor acquisition units are used to acquire the cell operating status data of the battery pack; the sensor acquisition unit includes: a sensor, a second protection module 41 and a third filtering module 42.

[0136] The sensor receives the measured input and outputs the corresponding analog voltage signal.

[0137] The first end of the second protection module 41 is connected to the sensor, and the second end of the second protection module 41 is grounded, which is used to clamp the analog voltage signal.

[0138] The first end of the third filtering module 42 is connected to the sensor, and the second end of the third filtering module 42 is grounded, which is used to filter the analog voltage signal.

[0139] In this embodiment, the VD33T port is connected to the analog front-end chip 1 and is the voltage output by the analog front-end chip 1. Figure 9 The sensor acquisition circuit for measuring battery pack cell temperature data, with the ground pin as an example, can be connected to a thermistor RTa, which is placed close to the battery pack cell. The temperature information is read using the negative temperature coefficient (NTC) characteristic of the thermistor. The high-precision ADC integrated inside the AFE chip acquires the voltage at the GPIO terminal and calculates the resistance value of the thermistor at this time. The current ambient temperature can be obtained by looking up a table.

[0140] GPIO6 / GPIO5 / GPIO4 can be connected to any sensor that collects data on the operating status of battery pack cells, such as current and pressure. Figure 9 The pull-up resistors in the diagram are resistors R4, R5, R6, and R7. For example, pull-up resistors are resistors connected between the signal pin and the power supply. Pull-up resistors prevent pins from floating and provide a definite default level. When a GPIO is configured as an input, if the pin is not connected to any external signal source, its voltage will be in a "floating" or "high-impedance" state. In this state, the pin's level is uncertain and highly susceptible to electromagnetic interference from the surrounding environment, causing the read logic level to randomly fluctuate between high and low, leading to system misjudgment or instability. Pull-up resistors provide a weak connection to the power supply, "pulling" the pin's default level to a stable high level. Even without an external device actively driving the pin, the MCU can still read a definite high-level signal. Pull-up resistors can also provide high-level drive capability for open-drain / open-collector outputs. Pull-up resistors also serve a current-limiting function. If a pin is directly connected to the power supply, a short circuit will occur when an external device attempts to pull the pin low to ground. One of the core functions of a pull-up resistor is current limiting. It allows current to flow safely when the pin is pulled low, pulling the voltage to a low level while limiting the current magnitude to prevent short circuits and protect the circuit.

[0141] The second protection module 41 includes diodes TVS1 and TVS2, used to protect against transient overvoltage events such as electrostatic discharge and surge voltage, protecting the downstream GPIO pins and related sensitive sampling circuits. The TVS diodes are connected in parallel between the GPIO signal line and ground, and are normally in a high-impedance state, not affecting signal transmission. When the circuit encounters a transient high voltage, the TVS diodes can turn on instantaneously (on the nanosecond level), clamping the overvoltage to a safe level, while simultaneously diverting the transient large current to ground, thereby protecting the downstream devices.

[0142] Figure 9 The analog voltage signal acquired by the sensor shown is filtered by an RC filter module before being transmitted to the backend. For example, the RC filter module may include an RC filter module composed of resistor R12 and capacitor C12; an RC filter module composed of resistor R13 and capacitor C13; an RC filter module composed of resistor R14 and capacitor C14; an RC filter module composed of resistor R15 and capacitor C15; each analog input signal port is equipped with an RC filter module.

[0143] After the analog voltage is filtered, it is filtered again by the third filtering module 42 before being output to the analog front-end chip.

[0144] In this embodiment, the third filtering module is also an RC filtering unit composed of resistors and capacitors; for example, resistor R8 and capacitor C8 form a filtering unit; resistor R9 and capacitor C9 form a filtering unit; resistor R10 and capacitor C10 form a filtering unit; and resistor R11 and capacitor C11 form a filtering unit. After filtering the analog voltage signal again, it is transmitted to the analog front-end chip 1, which improves the stability of the battery management system's acquired signal and further improves the reliability of the battery management system.

[0145] Figure 10 This is a schematic diagram of the voltage sampling circuit provided in the embodiments of this application; as shown below. Figure 10 As shown, the voltage sampling circuit 5 includes: a fourth filtering module 51;

[0146] One end of the fourth filtering module 51 is connected to the battery cell, and the fourth filtering module 51 is connected to the analog front-end chip 1. It is used to filter the collected battery cell voltage signal so that the filtered battery cell voltage signal is transmitted to the analog front-end chip 1.

[0147] In this embodiment, ports B(N+2)+, B(N+1)+, and BN+ are connected to the two ends of the battery cells in the battery pack. For example, B(N+2)+ is connected to the positive terminal of the first battery cell, B(N+1)+ is connected to the negative terminal of the first battery cell and the positive terminal of the second battery cell, and BN+ is connected to the negative terminal of the second battery cell. Therefore, once the voltage of each port is collected, the voltage value of the battery cell can be determined.

[0148] In this embodiment, the voltage sampling circuit first filters the voltage at the positive and negative terminals of the battery cell using the corresponding filter capacitors at each port, such as capacitors C19, C20, and C21. Then, the fourth filter module 51 filters the voltage value input to the analog front-end chip 1 again. The voltage is then transmitted to the analog front-end chip 1 via ports VS(N+2), VS(N+1), and VSN. Figure 10 The fourth filter module 51 may include resistor R16 and capacitor C16, resistor R17 and capacitor C17, and resistor R18 and capacitor C18.

[0149] In this embodiment, an RC filter circuit is integrated into each cell voltage sampling circuit to reduce voltage sampling fluctuations caused by changes in signal source impedance.

[0150] Figure 11 This is a schematic diagram of the differential communication circuit provided in the embodiments of this application; as shown Figure 11 As shown, the differential communication circuit 3 includes: at least one differential communication unit; the differential communication unit includes: a fifth filtering module 31, a current limiting module 32 and a sixth filtering module 33.

[0151] The first end of the fifth filtering module 31 is connected to the differential communication interface of the main control unit, and the second end of the fifth filtering module 31 is connected to the first end of the current limiting module 32, which is used to filter the differential voltage signal output by the main control unit.

[0152] The second terminal of the current limiting module 32 is connected to the first terminal of the sixth filtering module 33, and is used to limit the current of the filtered differential voltage signal.

[0153] The second terminal of the sixth filtering module 33 is connected to the analog front-end chip 1 and is used to filter the differential voltage signal after current limiting.

[0154] In this embodiment, ports COMH_N, COMH_P, COML_N, and COML_P are all ports for transmitting and receiving external differential signals, connecting to external units such as the main control unit of the battery management system. The differential communication circuit receives the differential voltage signal through COMH_N, COMH_P, COML_N, and COML_P.

[0155] Figure 10The diagram shows two sets of protection modules: one set consists of an ESD protection transistor (TVS5) composed of two diodes; the other set consists of a TVS6. The TVS5 provides protection at the input port, while the TVS6 provides protection before the input AFE wafer. For example, TVS4 and TVS6 are also protection modules; these are used to protect against transient overvoltage events such as electrostatic discharge and surge voltage.

[0156] The differential voltage signal needs to be filtered by the fifth filtering module 31. Optionally, the fifth filtering module 31 includes: resistor R19, resistor R20, and capacitor C22.

[0157] The first end of resistor R19 is connected to the positive terminal of the differential communication interface of the main control unit, and the second end of resistor R19 is connected to the first end of resistor R20.

[0158] The second end of resistor R20 is connected to the negative end of the differential communication interface of the main control unit.

[0159] The first terminal of capacitor C22 is connected to the second terminal of resistor R19, and the second terminal of capacitor C22 is grounded.

[0160] In this embodiment, a filtering module composed of resistors R19 and R20 and capacitor C22 is used to filter the received differential voltage signal, thereby improving the stability of the input differential voltage. For example, Figure 11 The resistors R23 and R24, and the capacitor C25 in the filter module also form the fifth filter module 31.

[0161] The filtered differential voltage signal is then output after being current-limited by the current-limiting module 32. Optionally, the current-limiting module 32 includes resistors R21 and R22.

[0162] The first end of resistor R21 is connected to the positive terminal of the differential communication interface of the main control unit, and the second end of resistor R21 is connected to the positive terminal of the differential communication interface of analog front-end chip 1.

[0163] The first end of resistor R22 is connected to the negative terminal of the differential communication interface of the main control unit, and the second end of resistor R22 is connected to the negative terminal of the differential communication interface of analog front-end chip 1.

[0164] In this embodiment, resistor R21 is connected to the positive terminal of the differential communication interface to limit the current of the positive phase voltage of the differential voltage signal. Resistor R21 is also connected to the negative terminal of the differential communication interface to limit the current of the negative phase voltage of the differential voltage signal. Resistors R25 and R26 also constitute the current limiting module 32.

[0165] The differential voltage signal, after current limiting, is filtered again by the sixth filtering module before being input to the analog front-end chip 1. Optionally, the sixth filtering module 33 includes capacitors C23 and C24.

[0166] The first terminal of capacitor C23 is connected to the second terminal of resistor R21, and the second terminal of capacitor C23 is connected to the first terminal of capacitor C24.

[0167] The second terminal of capacitor C24 is connected to the second terminal of resistor R22.

[0168] The sixth filtering module 33 consists of two capacitors, used to filter the differential voltage signal input to or output from the analog front-end chip, thereby improving the stability of the differential voltage signal. For example, Figure 11 Ports PA_N, PA_P, PB_N, and PB_P shown are the ports connected to analog front-end chip 1. Capacitors C26 and C27 also form the sixth filter module.

[0169] In this embodiment, communication between the analog front-end chip and external units is achieved through a differential communication circuit, which improves the reliability of communication and further enhances the reliability of the battery management system.

[0170] Figure 12 This is a schematic diagram of the equalization circuit provided in the embodiments of this application; as shown below. Figure 12 As shown, the equalization circuit 6 includes a discharge module 61 and a third protection module 62.

[0171] The first end of the discharge module 61 is connected to the battery cell, and the second end of the discharge module 61 is connected to the analog front-end chip 1. It is used to discharge the high-voltage battery cell to the low-voltage battery cell when the voltage of the battery cells is unbalanced.

[0172] The first end of the third protection module 62 is connected in parallel with the battery cell to provide surge protection for the output current of the battery cell.

[0173] Reference Figure 12 The discharge module 61 includes resistors R27 and R28 and capacitor C28. For example, when the cell voltage between ports B(N+2)+ and B(N+1)+ is higher, and the cell voltage between ports B(N+1)+ and BN+ is lower, discharge occurs from port B(N+2)+ to port B(N+1)+ through the path of resistors R27 and C28 in the discharge module 61, thereby achieving cell voltage equalization. Exemplarily, equalization discharge is performed on the S-terminal pin by controlling the equalization switch of a cell inside the chip; in terms of mode, autonomous equalization and command equalization can be performed.

[0174] Capacitor C29 is a protection module used to provide surge protection for the output current of the battery cell, prevent high current from breaking down the circuit, and improve circuit safety.

[0175] In this embodiment, when the host detects that the battery pack cells need to be balanced, it activates the balancing circuit to achieve voltage balancing of the cells, thereby improving the safety of battery pack management and further enhancing the reliability of the battery management system.

[0176] The battery management system provided in this embodiment includes a main control unit and a package connected to the main control unit. A substrate is encapsulated within the package, and the substrate integrates an analog front-end chip, a power supply circuit, a sampling circuit, and a differential communication circuit. Powered by the power supply circuit, the analog front-end chip transmits the state data of each cell in the vehicle battery pack collected by the sampling circuit to the main control unit via the differential communication circuit, thus achieving communication with the main control unit. This application's solution integrates and packages a front-end unit for collecting battery state data—comprising an analog front-end chip, its peripheral power supply circuit, a sampling circuit for sampling cell state data, and a differential communication circuit—into a package. This reduces the area of ​​the front-end acquisition hardware circuit, significantly miniaturizing and thinning the battery management system, achieving ultra-high functional density, and enabling signal transmission to achieve higher quality, faster speed, lower latency, and lower power consumption, thereby improving the reliability of the battery management system.

[0177] This application also provides a vehicle that includes the battery management system described above.

[0178] The embodiments or implementation methods described in this specification are presented in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. The terms "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with an embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described can be combined in any suitable manner in one or more embodiments or examples.

[0179] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A battery management system, characterized in that, include: The main control unit and the package connected to the main control unit; the package contains a substrate, and the substrate integrates an analog front-end chip, a power supply circuit, a sampling circuit and a differential communication circuit; The analog front-end chip, powered by the power supply circuit, transmits the status data of each cell in the vehicle battery pack collected by the sampling circuit to the main control unit through the differential communication circuit, thereby realizing communication with the main control unit.

2. The system according to claim 1, characterized in that, The substrate also integrates an equalization circuit. The equalization circuit is used to equalize the voltage of the battery cells in the vehicle battery pack when the voltages are uneven.

3. The battery management system according to claim 2, characterized in that, The substrate includes multiple conductive layers and multiple insulating layers; The multilayer conductive layer and the multilayer insulating layer are stacked alternately; The analog front-end chip, as well as the power supply circuit, the sampling circuit, the differential communication circuit, and the equalization circuit, are all disposed on the surface of the substrate; The electrical connection traces between the analog front-end chip and the power supply circuit, the sampling circuit, the differential communication circuit, and the equalization circuit are formed in the multilayer conductive layer; The multiple conductive layers are connected by through holes that penetrate the insulating layer.

4. The system according to claim 1, characterized in that, The thickness of the substrate is not less than a first preset value, the roughness of the substrate is not less than a second preset value, and the glass transition temperature of the substrate material is not less than a third preset value.

5. The system according to claim 1, characterized in that, The lower surface of the substrate is provided with a solder ball array, which extends through the lower surface of the substrate to the outside of the package.

6. The system according to claim 1, characterized in that, The power supply circuit includes: a first protection module, a first filtering module, a voltage divider module, a drive module, and a second filtering module; The first end of the first protection module is connected to the battery pack, and the second end of the first protection module is connected to the first end of the first filter module, for overcurrent protection of the output voltage of the battery pack; The second terminal of the first filtering module is connected to the input terminal of the voltage divider module, and is used to filter the output voltage of the battery pack; The first output terminal of the voltage divider module is connected to the analog front-end chip, and the second output terminal of the voltage divider module is connected to the analog front-end chip through the driving module. The voltage divider module is used to divide the output voltage after filtering by the first filtering module, and generate the start-up voltage of the analog front-end chip according to the voltage signal after voltage division, so that the first output terminal of the voltage divider module outputs the start-up voltage to the analog front-end chip. The driving module receives the driving voltage signal after the analog front-end chip is started, and in response to the driving voltage signal, generates the analog power supply voltage of the analog front-end chip according to the voltage signal after voltage division by the voltage divider module, so that the second output terminal of the voltage divider module outputs the analog power supply voltage to the analog front-end chip; The first end of the second filtering module is connected to the driving module, and the second end of the second filtering module is connected to the analog front-end chip, for filtering the analog power supply voltage.

7. The system according to claim 6, characterized in that, The driving module includes: a transistor and a first resistor; The collector of the transistor is connected to the first output terminal of the voltage divider module, the emitter of the transistor is connected to the first terminal of the second filter module, and the base of the transistor is connected to the first terminal of the first resistor. The second end of the first resistor is connected to the analog front-end chip.

8. The system according to claim 6, characterized in that, The first filtering module includes: a first ferrite bead and a first capacitor; The first end of the first magnetic bead is connected to the second end of the first protection module, and the second end of the first magnetic bead is connected to the first end of the first capacitor. The second terminal of the first capacitor is grounded.

9. The system according to claim 7, characterized in that, The second filtering module includes: a second ferrite bead, a second capacitor, and a third capacitor; The first end of the second magnetic bead is connected to the emitter of the transistor, and the second end of the second magnetic bead is connected to the first end of the second capacitor; The second terminal of the second capacitor is grounded; The third capacitor is connected in parallel with the second capacitor.

10. The system according to claim 1, characterized in that, The sampling circuit includes: a sensor sampling circuit and a voltage sampling circuit; The sensor sampling circuit is used to collect the operating status data of the cells in the battery pack and transmit it to the analog front-end chip; The voltage sampling circuit is used to collect the voltage signal of the cells in the battery pack and transmit it to the analog front-end chip.

11. The system according to claim 10, characterized in that, The sensor sampling circuit includes: multiple sensor acquisition units; the multiple sensor acquisition units are used to acquire the cell operating status data of the battery pack; the sensor acquisition unit includes: a sensor, a second protection module and a third filtering module; The sensor receives the measured input and outputs a corresponding analog voltage signal; The first end of the second protection module is connected to the sensor, and the second end of the second protection module is grounded, which is used to clamp the analog voltage signal. The first end of the third filtering module is connected to the sensor, and the second end of the third filtering module is grounded, for filtering the analog voltage signal.

12. The system according to claim 10, characterized in that, The voltage sampling circuit includes: a fourth filtering module; One end of the fourth filtering module is connected to the battery cell, and the fourth filtering module is connected to the analog front-end chip. It is used to filter the collected battery cell voltage signal so that the filtered battery cell voltage signal is transmitted to the analog front-end chip.

13. The system according to claim 1, characterized in that, The differential communication circuit includes at least one differential communication unit; the differential communication unit includes a fifth filtering module, a current limiting module, and a sixth filtering module. The first end of the fifth filtering module is connected to the differential communication interface of the main control unit, and the second end of the fifth filtering module is connected to the first end of the current limiting module, for filtering the differential voltage signal output by the main control unit; The second terminal of the current limiting module is connected to the first terminal of the sixth filtering module, and is used to limit the current of the filtered differential voltage signal. The second end of the sixth filtering module is connected to the analog front-end chip and is used to filter the differential voltage signal after current limiting.

14. The system according to claim 2, characterized in that, The equalization circuit includes: a discharge module and a third protection module; The first end of the discharge module is connected to the battery cell, and the second end of the discharge module is connected to the analog front-end chip. It is used to discharge the high-voltage battery cell to the low-voltage battery cell when the voltage of the battery cells is unbalanced. The first end of the third protection module is connected in parallel with the battery cell to provide surge protection for the output current of the battery cell.

15. A vehicle, characterized in that, include: The battery management system as described in any one of claims 1-14.

Images