Weight stacking method for digital power amplifier, digital power amplifier system, and radar device

Abstract

The application relates to a weight stacking method of a digital power amplifier, a digital power amplifier system and a radar device, wherein a digital power amplifier array in the digital power amplifier comprises a plurality of parallel digital power amplifier units; each digital power amplifier unit comprises a plurality of main power amplification units and at least two power allocation units which are in parallel and independently controlled; the rated output power of the main power amplification unit is greater than that of the power allocation unit; a weight combination scheme of the digital power amplifier unit is calculated according to a received target output power, and corresponding control coding is generated; the on and off states of the main power amplification units and the power allocation units are controlled based on the control coding, so that the input radio frequency input signal of the digital power amplifier is shunt weighted and amplified, the problem of insufficient power control performance is solved, power regulation is changed from load modulation in an analog domain to power unit combination in a digital domain, and nonlinear distortion introduced by analog regulation is avoided.

Description

Technical Field

[0001] This application relates to the field of power amplifier technology, and in particular to a weighted stacking method for digital power amplifiers, a digital power amplifier system, and radar equipment. Background Technology

[0002] In today's complex electromagnetic environment, radio frequency power amplifiers, as core components of detection, jamming, and communication systems, face increasingly demanding operating conditions. They need to be able to output multiple levels of power while maintaining high efficiency at each power level.

[0003] However, traditional analog power amplifiers face significant technical bottlenecks in achieving wide-range power control. Traditional analog power amplifiers achieve power back-off by adjusting the bias point of transistors or using variable matching networks, but this analog control method is often accompanied by severe nonlinear effects, making it difficult to achieve accurate power control over a wider range.

[0004] There is currently no effective solution to the problem of insufficient power control performance in related technologies. Summary of the Invention

[0005] This embodiment provides a weighted stacking method for a digital power amplifier, a digital power amplifier system, and a radar device to address the problem of insufficient power control performance in related technologies.

[0006] In a first aspect, this embodiment provides a method for use in a digital power amplifier, wherein the digital power amplifier array in the digital power amplifier includes a plurality of parallelly arranged digital power amplifier units; each digital power amplifier unit includes a plurality of parallel and independently controlled main power amplifier units and at least two power modulation units; the rated output power of a single main power amplifier unit is greater than the rated output power of a single power modulation unit; the method includes:

[0007] Calculate the weight combination scheme of the digital power amplifier unit based on the received target output power, and generate the corresponding control code;

[0008] The control code controls the on / off states of each of the main power amplifier units and the power matching units to perform weighted amplification of the radio frequency input signal to the digital power amplifier; wherein, after being turned on, the main power amplifier units and the power matching units operate in their respective saturation operating regions.

[0009] In some embodiments, the weight combination scheme of the digital power amplifier unit is calculated based on the received target output power, and corresponding control codes are generated, including:

[0010] Based on the received target output power, obtain the corresponding power weight-load performance mapping table; the power weight-load performance mapping table pre-stores recommended weight combination schemes corresponding to various degrees of load mismatch.

[0011] Obtain load mismatch parameters, which are used to characterize the current load mismatch condition of the digital power amplifier;

[0012] In the power weight-load performance mapping table, the corresponding recommended weight combination scheme is determined based on the load mismatch parameter, and the corresponding control code is generated.

[0013] In some embodiments, the calibration method for the power weight-load performance mapping table includes:

[0014] The digital power amplifier was tested under different load mismatch conditions.

[0015] During the actual measurement process, the efficiency values ​​of each weight combination scheme were recorded when different total output power requirements were met.

[0016] For the same load mismatch condition and the same total output power requirement, based on the maximum efficiency value, the corresponding recommended weight combination scheme is determined, and a power weight-load performance mapping table for different total output power requirements is obtained.

[0017] Secondly, this application also provides a digital power amplifier system, the system comprising: a digital controller and a digital power amplifier;

[0018] The digital power amplifier array in the digital power amplifier includes several parallel digital power amplifier units; each digital power amplifier unit includes several parallel and independently controlled main power amplifier units and at least two power matching units; the rated output power of a single main power amplifier unit is greater than the rated output power of a single power matching unit; the main power amplifier units and the power matching units are configured to operate in their respective saturation operating regions after being turned on.

[0019] The digital controller, connected to each of the main power amplifier units and the power modulation units, is used to implement the steps of the method described in any one of the first aspects.

[0020] In some embodiments, within the same digital power amplifier unit, the rated output power of each power distribution unit increases exponentially.

[0021] In some of these embodiments, the individual digital power amplifier units have the same structure;

[0022] Each of the aforementioned digital power amplifier units is provided with one of the aforementioned main power amplifier units and four of the aforementioned power distribution units;

[0023] The ratio of the rated output power of the four power distribution units is 1:2:4:8.

[0024] In some embodiments, the digital power amplifier further includes: an input power distribution network and an output transcell power combining network;

[0025] The input power distribution network is connected to each of the digital power amplifier units and is used to evenly distribute the radio frequency input signal to the activated digital power amplifier units.

[0026] The output intercellular power combining network is connected to each of the digital power amplifier units and is used to combine the signals output by the activated digital power amplifier units to obtain an amplified radio frequency output signal.

[0027] In some embodiments, the input power distribution network adopts a balanced branch structure, which includes a main input branch, multiple symmetrical distribution branches, and an isolation matching component. The input terminal of the main input branch is connected to an RF input signal, and the output terminal of the main input branch is connected to one end of each of the symmetrical distribution branches. The other ends of the multiple symmetrical distribution branches are connected to the input terminals of each of the digital power amplifier units. The multiple symmetrical distribution branches have the same line length and line characteristic impedance, and each symmetrical distribution branch is symmetrically arranged with respect to the central axis of the main input branch. The isolation matching component is connected between the output terminals of any two adjacent symmetrical distribution branches.

[0028] In some embodiments, the output intercellular power combining network includes cascaded Wilkinson couplers. Each stage of the Wilkinson coupler includes a main transmission branch, two symmetrical voltage divider branches, and an isolation resistor. The transmission line length and characteristic impedance parameters of the two symmetrical voltage divider branches of the same stage of the Wilkinson coupler are the same. The output terminal of each power matching unit is respectively connected to the branch combining point of each stage of the Wilkinson coupler.

[0029] Thirdly, this application also provides a radar device, which includes the digital power amplifier system described in any of the second aspects.

[0030] Compared with related technologies, the digital power amplifier weight stacking method, digital power amplifier system, and radar device provided in this application, wherein the digital power amplifier array in the digital power amplifier includes several parallel digital power amplifier units; each digital power amplifier unit includes several parallel and independently controlled main power amplifier units and at least two power matching units; the rated output power of a single main power amplifier unit is greater than the rated output power of a single power matching unit; the weight combination scheme of the digital power amplifier units is calculated according to the received target output power, and a corresponding control code is generated; the conduction and cutoff states of each main power amplifier unit and the power matching unit are controlled based on the control code, and the main power amplifier unit and the power matching unit are configured to operate in the corresponding saturation operating region after conduction, so as to perform weighted amplification of the RF input signal input to the digital power amplifier, which solves the problem of insufficient power control performance. By using the power weight stacking method, the power adjustment is transformed from load modulation in the analog domain to power unit combination selection in the digital domain, which fundamentally ensures high efficiency at all power levels and avoids nonlinear distortion introduced by analog adjustment.

[0031] Details of one or more embodiments of this application are set forth in the following drawings and description to make other features, objects and advantages of this application more readily apparent. Attached Figure Description

[0032] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0033] Figure 1 This is a hardware structure block diagram of the terminal of the weight stacking method for digital power amplifiers in the embodiments of this application;

[0034] Figure 2 This is a flowchart illustrating the weight stacking method for digital power amplifiers in an embodiment of this application.

[0035] Figure 3 This is a schematic diagram of different switch combinations for synthesizing a specific total output power in the embodiments of this application;

[0036] Figure 4 This is a schematic diagram of the structure of the digital power amplifier system in the embodiments of this application;

[0037] Figure 5 This is a schematic diagram of the structure of a digital power amplifier unit in an embodiment of this application;

[0038] Figure 6 This is a circuit diagram of the principle verification experiment in the embodiments of this application;

[0039] Figure 7 This is a schematic diagram of the angle of the circle with equal reflection coefficient in the principle verification experiment of this application embodiment.

[0040] Reference numerals: 102, processor; 104, memory; 106, transmission device; 108, input / output device; 41, digital controller; 42, digital power amplifier. Detailed Implementation

[0041] To better understand the purpose, technical solution, and advantages of this application, the application is described and illustrated below in conjunction with the accompanying drawings and embodiments.

[0042] Unless otherwise defined, the technical or scientific terms used in this application shall have the general meaning understood by one of ordinary skill in the art to which this application pertains. Words such as “a,” “an,” “an,” “the,” “the,” and “these” used in this application do not indicate quantitative limitation and may be singular or plural. The terms “comprising,” “including,” “having,” and any variations thereof used in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that comprises a series of steps or modules (units) is not limited to the listed steps or modules (units) but may include steps or modules (units) not listed, or may include other steps or modules (units) inherent to these processes, methods, products, or devices. Words such as “connected,” “linked,” and “coupled” used in this application are not limited to physical or mechanical connections but may include electrical connections, whether direct or indirect. “Multiple” used in this application refers to two or more. “And / or” describes the relationship between related objects, indicating that three relationships may exist; for example, “A and / or B” can represent: A alone, A and B simultaneously, and B alone. Normally, the character " / " indicates that the objects before and after it are in an "or" relationship. The terms "first," "second," "third," etc., used in this application are merely to distinguish similar objects and do not represent a specific order of objects.

[0043] The method embodiments provided in this example can be executed on a terminal, computer, or similar computing device. For example, it can run on a terminal. Figure 1 This is a hardware structure block diagram of the terminal of the weight stacking method for digital power amplifiers in this embodiment. For example... Figure 1 As shown, a terminal may include one or more ( Figure 1Only one is shown in the diagram. A processor 102 and a memory 104 for storing data are also included. The processor 102 may be, but is not limited to, a microprocessor (MCU) or a programmable logic device (FPGA). The terminal may also include a transmission device 106 for communication functions and an input / output device 108. Those skilled in the art will understand that… Figure 1 The structure shown is for illustrative purposes only and does not limit the structure of the terminal described above. For example, the terminal may also include components that are larger than... Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown are illustrated.

[0044] The memory 104 can be used to store computer programs, such as application software programs and modules, like the computer program corresponding to the weight stacking method of the digital power amplifier in this embodiment. The processor 102 executes various functional applications and data processing by running the computer programs stored in the memory 104, thereby implementing the above-described method. The memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include memory remotely located relative to the processor 102, and these remote memories can be connected to the terminal via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0045] The transmission device 106 is used to receive or send data via a network. This network includes a wireless network provided by the terminal's communication provider. In one example, the transmission device 106 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 106 can be a Radio Frequency (RF) module used for wireless communication with the Internet.

[0046] This embodiment provides a weighted stacking method for digital power amplifiers, specifically for controlling the digital power amplifier array within the digital power amplifier to achieve high-precision discrete power configuration. This method can be implemented by a digital control device built into the digital power amplifier or by an external processing device. The digital power amplifier array in the digital power amplifier includes several parallel-arranged digital power amplifier units; each digital power amplifier unit includes several parallel and independently controlled main power amplifier units and at least two power matching units; the rated output power of a single main power amplifier unit is greater than the rated output power of a single power matching unit. Figure 2This is a flowchart of the weight stacking method for the digital power amplifier in this embodiment, as shown below. Figure 2 As shown, the process includes the following steps:

[0047] Step S210: Calculate the weight combination scheme of the digital power amplifier unit based on the received target output power, and generate the corresponding control code.

[0048] Step S220: Based on the control code, control the on and off states of each main power amplifier unit and power matching unit to perform split-weighted amplification of the RF input signal of the input digital power amplifier. The main power amplifier unit and power matching unit operate in their respective saturation operating regions after being turned on.

[0049] Specifically, the total output power requirement of a single digital power amplifier unit (referred to as a power unit) is broken down into the sum of the power weights of a main power amplifier unit (referred to as a main unit) and multiple power matching units (referred to as matching units). The main power amplifier unit provides a baseline power weight, while the multiple power matching units each provide a series of binary or user-defined power weights. The digital control / processing unit directly generates a set of discrete control codes based on the required total output power level, precisely selecting a main power unit and a specific combination of power matching units to participate in the power output in a "switching" manner. In this process, each activated unit (whether a main unit or a matching unit) is configured in its respective high-efficiency saturation operating region, and their roles are equal "power contributors," which fundamentally ensures that the amplifier maintains near-peak efficiency at all discrete power levels.

[0050] In this embodiment, the problem of insufficient power control performance is solved. By using the power weight stacking method, the power regulation is transformed from load modulation in the analog domain to power unit combination selection in the digital domain, which fundamentally ensures high efficiency at all power levels and avoids the nonlinear distortion introduced by analog regulation.

[0051] In some embodiments, for step S210, the weight combination scheme of the digital power amplifier units is calculated based on the received target output power, and corresponding control codes are generated, including:

[0052] Step S211: Based on the received target output power, obtain the corresponding power weight-load performance mapping table; the power weight-load performance mapping table pre-stores recommended weight combination schemes corresponding to various degrees of load mismatch.

[0053] Specifically, the recommended weight combination scheme can be the optimal efficiency scheme obtained from actual measurements of the digital power amplifier, or a high-efficiency scheme calculated through software simulation. The specific implementation is not limited in this embodiment.

[0054] Step S212: Obtain the load mismatch parameters, which are used to characterize the current load mismatch condition of the digital power amplifier.

[0055] Specifically, the load mismatch parameter can be a value estimated based on actual conditions or prior experience before the digital power amplifier is designed, and the load mismatch parameter is fixed after the design is completed. In some implementations, the digital power amplifier is also suitable for operating conditions without mismatch. In this case, the load mismatch parameter cannot be obtained, and there is no need to use a power weight-load performance mapping table for power allocation. The goal can be to configure each digital power amplifier unit with equal contribution.

[0056] Step S213: In the power weight-load performance mapping table, determine the corresponding recommended weight combination scheme based on the load mismatch parameters, and generate the corresponding control code.

[0057] Specifically, by retrieving the pre-stored power weight-load performance mapping table, it was found that under the current mismatch state, each digital power amplifier unit adopts a different weight combination. Although the individual synthesized contribution power is different from the ideal state, after synthesis by the intercellular synthesis network connected to the output end of the digital power amplifier unit, the total output power can still accurately meet the requirements, and the overall synthesis efficiency of the system is significantly higher than that of the equal distribution scheme.

[0058] In this embodiment, under the complex operating conditions of load mismatch, the efficiency of power allocation is improved by using a power weight-load performance mapping table, which also avoids the low efficiency of the equal allocation scheme.

[0059] In some embodiments, the calibration method for the power weight-load performance mapping table includes:

[0060] Step S310: Perform actual measurements on the digital power amplifier under different load mismatch conditions;

[0061] Specifically, in an array antenna, different power elements may exhibit different optimal performance points (efficiency and power) when faced with the same antenna load mismatch due to factors such as layout and manufacturing tolerances. Because each power element is configured with independently controllable weighted stacking combinations, when the system needs to synthesize a specific total output power, there are multiple "cross-cell power combining" schemes composed of different weights or different switching combinations within different power elements, such as... Figure 3 The switch combination schemes (a) and (b) are shown in the figure. Among these options, the load conditions of each power unit can be monitored or preset, and a cross-cell synthesis configuration that maximizes the overall system efficiency or the most stable output power can be dynamically selected, thereby greatly improving the robustness and performance of the transmitter array under complex load environments.

[0062] Step S320: During the actual measurement process, record the efficiency values ​​of each weight combination scheme when different total output power requirements are met;

[0063] Step S330: For the same load mismatch condition and total output power demand, determine the corresponding recommended weight combination scheme based on the maximum efficiency value, and obtain the power weight-load performance mapping table for different total output power demands.

[0064] Specifically, to achieve automated scanning and optimization, an automated test and optimization script can be developed based on the MATLAB platform. This script controls the power supply and spectrum analyzer via TCP / IP protocol, realizing hardware closed-loop optimization and heat dissipation control. Based on the required output power, the main power amplifier units that need to be activated are fixed. All power configuration units among the required power amplifier units are arranged in a row. Different power configuration units are selected for scanning according to the required power configuration. During the scanning process, the maximum efficiency is recorded in real time. If the recorded maximum efficiency is greater than the previously recorded maximum efficiency, the configuration scheme is immediately updated to the optimal value under the current load mismatch condition and total output power requirement, and then the process switches to the next scheme. Furthermore, after all schemes have been scanned, the total efficiency improvement for this round is calculated. If the improvement is less than a preset threshold (e.g., 0.5%), the system is considered to have stabilized in the optimal state, and the test automatically stops to avoid unnecessary operation.

[0065] In this embodiment, by pre-calibrating the recommended weight combination scheme under the same load mismatch condition and total output power requirement, and fully combining the cross-cell synthesis to compensate for the power deviation, the total output power is kept stable, and the overall synthesis efficiency of the system under mismatch conditions is significantly improved.

[0066] This application also provides a digital power amplifier system. Figure 4 This is a schematic diagram of the digital power amplifier system in this embodiment, as shown below. Figure 4 As shown, the system includes a digital controller 41 and a digital power amplifier 42.

[0067] The digital power amplifier array in the digital power amplifier 42 includes several parallel-arranged digital power amplifier units DPA1-DPA. n . Figure 5 This is a schematic diagram of the structure of a digital power amplifier unit in this embodiment, as shown below. Figure 5 As shown, each digital power amplifier unit includes several parallel and independently controlled main power amplifier units and at least two power matching units; the rated output power of a single main power amplifier unit is greater than the rated output power of a single power matching unit.

[0068] The digital controller 41 is connected to each main power amplifier unit and power modulation unit to implement the steps of the weighted stacking method of the digital power amplifier described above.

[0069] For details, see Figure 4 The digital controller 41 includes a calculation module and a bias circuit. The calculation module is connected to the gate bias switch and drain bias switch in each digital power amplifier unit through the bias circuit. The calculation module is used to calculate control codes and output control signals. The bias circuit receives the control signals and converts them into the gate / drain bias voltages required by the power transistors in the digital power amplifier array, thereby determining which power transistors in the digital power amplifier array are turned on and which are turned off. Specifically, a saturation bias is applied when the transistors are on, causing the corresponding transistors to enter the high-efficiency operating region; a turn-off bias is applied when the transistors are off, causing the corresponding transistors to be completely turned off. The calculation module issues commands, the bias circuit executes the drive, and the digital power amplifier array outputs power. The three work together to achieve efficient power configuration through digital weighted stacking.

[0070] In this embodiment, true discretized and digital power control is achieved. By using the "power weight stacking" method, power regulation is transformed from load modulation in the analog domain to power unit combination selection in the digital domain, fundamentally ensuring high efficiency at all power levels and avoiding the nonlinear distortion introduced by analog regulation.

[0071] In some of these embodiments, the rated output power of each power distribution unit within the same digital power amplifier unit increases exponentially.

[0072] Specifically, within the same digital power amplifier unit, the rated output power of each power distribution unit is different, for example, units 2 and 3... The exponentially increasing strategy with a base value is adapted to design schemes with various precision and unit counts.

[0073] In some of these embodiments, the digital power amplifier units have the same structure; each digital power amplifier unit contains a main power amplifier unit and four power distribution units; the ratio of the rated output power of the four power distribution units is 1:2:4:8.

[0074] For example, each digital power amplifier unit uses only 4 units to cover all integer power levels from 1W to 15W (1+2+4+8). Combined with a 10W main power amplifier unit, it can achieve 16 precise outputs in 1W steps within the 10W-25W range, achieving a large power regulation density with fewer units.

[0075] In some embodiments, the digital power amplifier 42 further includes an input power distribution network and an output transcell power combining network.

[0076] An input power distribution network, connected to each digital power amplifier unit, is used to evenly distribute the RF input signal to the activated digital power amplifier units.

[0077] Specifically, the input power distribution network can adopt a balanced branch structure, which includes one main input branch, multiple symmetrical distribution branches, and isolation matching components. The input terminal of the main input branch is connected to the radio frequency input signal, and the output terminal of the main input branch is connected to one end of each symmetrical distribution branch. The other ends of the multiple symmetrical distribution branches are connected to the input terminals of each digital power amplifier unit. The multiple symmetrical distribution branches have the same line length and characteristic impedance, and each symmetrical distribution branch is symmetrically arranged with respect to the central axis of the main input branch. The isolation matching components are connected between the output terminals of any two adjacent symmetrical distribution branches.

[0078] The output intercellular power combining network is connected to each digital power amplifier unit and is used to combine the signals output by the digital power amplifier units that are turned on to obtain the amplified radio frequency output signal.

[0079] Specifically, the output intercell power combining network comprises cascaded Wilkinson couplers. Each Wilkinson coupler includes a main transmission branch, two symmetrical voltage divider branches, and an isolation resistor. The transmission line lengths and characteristic impedance parameters of the two symmetrical voltage divider branches within the same Wilkinson coupler stage are identical. The output terminals of each power distribution unit are connected to the branch combining points of each stage of the Wilkinson coupler. The key to this combining network lies in its "intercell" characteristic; it is not simply a node directly connecting all transistor outputs together, but rather a multi-stage, multi-node combining topology. This results in different impedance transformations at the output combining point of each power distribution unit relative to the output path of the main power amplifier unit.

[0080] In this embodiment, the combination of "digital power amplifier weight stacking" and "array cross-cell power synthesis" elevates the system's resistance to load mismatch to a whole new level. The performance deteriorated due to load mismatch is compensated by dynamic reconstruction across cells and across power weights, which is something that traditional technologies based on active load modulation within cells cannot anticipate.

[0081] This application also provides a radar device, which includes any of the digital power amplifier systems described above. It should be noted that specific examples in this embodiment can be found in the examples described in the above embodiments and optional implementations, and will not be repeated here.

[0082] In this embodiment, each digital power amplifier unit and its internal weight configuration can be reused and expanded to adapt to the full power level requirements from mobile devices to large ground radar stations, significantly reducing the development cycle and cost of multi-scenario radar systems.

[0083] The present embodiment will now be described and illustrated through preferred embodiments. See also...Figure 4 and Figure 5 This preferred embodiment provides a digital power amplifier system, which includes a digital controller 41 and a digital power amplifier 42.

[0084] The digital power amplifier 42 includes an input power distribution network, an output transcell power combining network, and a digital power amplifier array.

[0085] The digital power amplifier array includes several parallel-arranged digital power amplifier units; each digital power amplifier unit includes several parallel and independently controlled main power amplifier units and four power distribution units. The rated output power of a single main power amplifier unit is greater than the rated output power of a single power distribution unit. The four power distribution units and one main power amplifier unit employ power transistors with a rated output power ratio of 1:2:4:8:10.

[0086] The input power distribution network is used to distribute the RF input signal to all the possible power transistor inputs that may be turned on in each digital power amplifier unit.

[0087] The output intercell power combining network is used to combine the signals output by the activated digital power amplifier unit to obtain an amplified RF output signal. The output intercell power combining network includes a multi-stage combining coupler, transformer, or transmission line structure, with multiple combining nodes connected one-to-one to the output terminals of multiple power matching units, so that the output combining point of each power matching unit presents different impedance transformation characteristics to the output path of the main power amplifier unit.

[0088] The digital controller 41 includes a calculation module and a bias circuit. The calculation module is connected to the gate bias switch and drain bias switch in each digital power amplifier unit through the bias circuit. The calculation module is used to calculate the control code and output the control signal. The bias circuit receives the control signal and converts it into the gate / drain bias voltage required by the power transistors in the digital power amplifier array, thereby determining which power transistors in the digital power amplifier array are turned on and which are turned off. Specifically, when the transistors are turned on, a saturation bias is applied to put the corresponding transistors into the high-efficiency operating region; when the transistors are turned off, a turn-off bias is applied to completely turn off the corresponding transistors.

[0089] In this preferred embodiment, the specific steps for calculating the control code include:

[0090] S1, Perform actual measurements on the digital power amplifier 42 under different load mismatch conditions; during the actual measurement, record the efficiency values ​​of each weight combination scheme when meeting different total output power requirements;

[0091] S2. For the same load mismatch condition and total output power demand, based on the maximum efficiency value, determine the corresponding recommended weight combination scheme and obtain the power weight-load performance mapping table for different total output power demands.

[0092] S3. Based on the received target output power, obtain the corresponding power weight-load performance mapping table; the power weight-load performance mapping table pre-stores recommended weight combination schemes corresponding to various degrees of load mismatch.

[0093] S4, obtain the load mismatch parameters, which are used to characterize the current load mismatch condition of the digital power amplifier 42.

[0094] S5. In the power weight-load performance mapping table, determine the corresponding recommended weight combination scheme based on the load mismatch parameter, and generate the corresponding control code.

[0095] When faced with antenna load mismatch (e.g., VSWR=2), the aforementioned digital power amplifier system performs "intercellular power combining decision". Assume the system needs to maintain a fixed total output power level, for example, by combining the total power from two parallel digital power amplifier units, DPA_A and DPA_B. Under an ideal 50Ω load, the system can be configured to allow DPA_A and DPA_B to contribute power equally, with each unit using a specific weighting combination. However, when the load changes, due to subtle differences in the physical layout of the two power amplifier units, their respective effective load impedances may shift in different directions. In this case, the calculation module retrieves a pre-stored "power weight-load performance mapping table" and finds that, under the current mismatch state, if one set of power weighting combinations is used within DPA_A and another set within DPA_B, although the combined power contribution of each unit differs from the ideal state, the total output power still precisely meets the requirements after combining through the intercellular combining network, and the overall combining efficiency of the system is significantly higher than the equal allocation scheme. Figure 6 The principle verification experiment demonstrated this phenomenon: two independent 10W power amplifier branches with different performances achieved their optimal efficiency at different impedance points on the mismatch circle with VSWR=2. Figure 7 A schematic diagram of the angle of the circle with equal reflection coefficient in the principle verification experiment, as shown below. Figure 7 As shown, the light blue and dark blue straight lines and curves form the first branch. Figure 6 The power amplifier performance (above) is shown. The straight line represents its drain efficiency and output power of 71.8% and 42.1dBm at 50Ω, respectively; the curve represents its performance at various points on the impedance circle with VSWR=2. Similarly, the light red and dark red straight lines and curves represent the second branch ( Figure 6The power amplifier performance (see below) is shown. The straight line represents its drain efficiency and output power at 50Ω, which are 68.3% and 40.4dBm, respectively; the curve represents its performance at various points on the impedance circle with VSWR=2. By selecting different power amplifiers to operate at different mismatch points, it can be seen that the drain efficiency of the entire system under load mismatch conditions with VSWR=2 is 57.2%-72.3%, and the output power is 40.4dBm-42dBm. This improves the performance of the entire system when facing load mismatch. The dynamic load compensation technology experiment of transcell power synthesis was successfully completed, and the ability to resist load mismatch was formed.

[0096] This demonstrates that by combining "digital power amplifier weight stacking" with "array cross-cell power synthesis," the present invention elevates the system's resistance to load mismatch to a whole new level. It compensates for the performance degradation caused by load mismatch through dynamic reconstruction across cells and across power weights, an effect that cannot be anticipated by any existing technology based on active load modulation within cells.

[0097] In this preferred embodiment, the beneficial effects include: (1) Realized discrete and digital power control: Through the "power weight stacking" method, power regulation is transformed from load modulation in the analog domain to power unit combination selection in the digital domain, fundamentally ensuring high efficiency at all power levels and avoiding nonlinear distortion introduced by analog regulation. (2) Significantly improved array-level anti-load mismatch capability: Through the innovative "cross-cell power synthesis" strategy, the system-level problem of load mismatch is transformed into a mathematical problem of selecting the best among multiple unit-level high-efficiency operating point combinations. This enables the system to maintain high overall efficiency even under severe mismatch conditions of VSWR=2 by switching the most suitable power unit combination, a capability that existing single-cell load modulation technology cannot achieve. (3) Highly modular and platform-based architecture: Each digital power amplifier unit and its internal weight configuration can be reused and expanded to adapt to the full power level requirements from mobile terminals to large ground radar stations.

[0098] Furthermore, in conjunction with the weighting method for digital power amplifiers provided in the above embodiments, this embodiment can also provide a storage medium for implementation. This storage medium stores a computer program; when executed by a processor, the computer program implements any of the weighting methods for digital power amplifiers described in the above embodiments.

[0099] It should be understood that the specific embodiments described herein are merely illustrative of the application and not intended to limit it. All other embodiments derived by those skilled in the art based on the embodiments provided in this application without inventive effort are within the scope of protection of this application.

[0100] Obviously, the accompanying drawings are merely some examples or embodiments of this application. Those skilled in the art can apply this application to other similar situations based on these drawings without any creative effort. Furthermore, it is understood that although the work done in this development process may be complex and lengthy, for those skilled in the art, certain design, manufacturing, or production modifications made based on the technical content disclosed in this application are merely conventional technical means and should not be considered as insufficient disclosure of this application.

[0101] The term "embodiment" in this application refers to a specific feature, structure, or characteristic described in connection with an embodiment that may be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily imply the same embodiment, nor does it imply that it is mutually exclusive with or independent of other embodiments. It will be clearly or implicitly understood by those skilled in the art that the embodiments described in this application may be combined with other embodiments without conflict.

[0102] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of patent protection. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the appended claims.

Claims

1. A weight stacking method for a digital power amplifier, characterized in that, The method is applied to a digital power amplifier, wherein the digital power amplifier array in the digital power amplifier includes a plurality of parallelly arranged digital power amplifier units; each digital power amplifier unit includes a plurality of parallel and independently controlled main power amplifier units and at least two power matching units; the rated output power of a single main power amplifier unit is greater than the rated output power of a single power matching unit; the method includes: Calculate the weight combination scheme of the digital power amplifier unit based on the received target output power, and generate the corresponding control code; The control code controls the on / off states of each of the main power amplifier units and the power matching units to perform weighted amplification of the radio frequency input signal to the digital power amplifier; wherein, after being turned on, the main power amplifier units and the power matching units operate in their respective saturation operating regions.

2. The weight stacking method for digital power amplifiers according to claim 1, characterized in that, Calculate the weight combination scheme of the digital power amplifier unit based on the received target output power, and generate the corresponding control code, including: Based on the received target output power, obtain the corresponding power weight-load performance mapping table; the power weight-load performance mapping table pre-stores recommended weight combination schemes corresponding to various degrees of load mismatch. Obtain load mismatch parameters, which are used to characterize the current load mismatch condition of the digital power amplifier; In the power weight-load performance mapping table, the corresponding recommended weight combination scheme is determined based on the load mismatch parameter, and the corresponding control code is generated.

3. The weight stacking method for digital power amplifiers according to claim 2, characterized in that, The calibration method for the power weight-load performance mapping table includes: The digital power amplifier was tested under different load mismatch conditions. During the actual measurement process, the efficiency values ​​of each weight combination scheme were recorded when different total output power requirements were met. For the same load mismatch condition and the same total output power requirement, based on the maximum efficiency value, the corresponding recommended weight combination scheme is determined, and a power weight-load performance mapping table for different total output power requirements is obtained.

4. A digital power amplifier system, characterized in that, The system includes: a digital controller and a digital power amplifier; The digital power amplifier array in the digital power amplifier includes several parallel digital power amplifier units; each digital power amplifier unit includes several parallel and independently controlled main power amplifier units and at least two power modulation units; the rated output power of a single main power amplifier unit is greater than the rated output power of a single power modulation unit. The digital controller is connected to each of the main power amplifier units and the power modulation units, and is used to implement the steps of the method according to any one of claims 1 to 3.

5. The digital power amplifier system according to claim 4, characterized in that, Within the same digital power amplifier unit, the rated output power of each power distribution unit increases exponentially.

6. The digital power amplifier system according to claim 5, characterized in that, Each of the aforementioned digital power amplifier units has the same structure; Each of the aforementioned digital power amplifier units is provided with one of the aforementioned main power amplifier units and four of the aforementioned power distribution units; The ratio of the rated output power of the four power distribution units is 1:2:4:

8.

7. The digital power amplifier system according to claim 4, characterized in that, The digital power amplifier further includes: an input power distribution network and an output transcell power synthesis network; The input power distribution network is connected to each of the digital power amplifier units and is used to evenly distribute the radio frequency input signal to the activated digital power amplifier units. The output intercellular power combining network is connected to each of the digital power amplifier units and is used to combine the signals output by the activated digital power amplifier units to obtain an amplified radio frequency output signal.

8. The digital power amplifier system according to claim 7, characterized in that, The input power distribution network adopts a balanced branch structure, which includes one main input branch, multiple symmetrical distribution branches, and an isolation matching component. The input terminal of the main input branch is connected to the radio frequency input signal, and the output terminal of the main input branch is connected to one end of each of the symmetrical distribution branches. The other ends of the multiple symmetrical distribution branches are connected to the input terminals of each of the digital power amplifier units. The multiple symmetrical distribution branches have the same line length and line characteristic impedance, and each symmetrical distribution branch is symmetrically arranged with respect to the central axis of the main input branch. The isolation matching component is connected between the output terminals of any two adjacent symmetrical distribution branches.

9. The digital power amplifier system according to claim 7, characterized in that, The output intercellular power combining network includes cascaded Wilkinson couplers. Each stage of the Wilkinson coupler includes a main transmission branch, two symmetrical voltage divider branches, and an isolation resistor. The transmission line length and characteristic impedance parameters of the two symmetrical voltage divider branches of the same stage of the Wilkinson coupler are the same. The output terminal of each power matching unit is connected to the branch combining point of each stage of the Wilkinson coupler.

10. A radar device, characterized in that, The radar device includes the digital power amplifier system described in any one of claims 4 to 5.

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