Clock skew calibration method, apparatus, device and program product for analog-to-digital converter

Abstract

The application relates to the field of analog-digital converters, and provides a clock skew calibration method, device, equipment and program product of an analog-digital converter. The method comprises the following steps: acquiring an input frequency of a time-interleaved analog-digital converter; judging whether the input frequency is in a preset frequency point protection area according to a preset frequency reference point set; the preset frequency reference point set comprises several discrete reference frequency points; the preset frequency point protection area is a frequency band area which comprises the reference frequency points as the center and has a preset protection bandwidth; when the input frequency is in the preset frequency point protection area, an effective clock deviation estimation value or a limiting estimation value of the last time is used as a current clock deviation estimation value; and clock skew calibration is performed on each channel according to the current clock deviation estimation value. The technical scheme of the application can avoid incorrect deviation estimation at the preset frequency reference points.

Description

Technical Field

[0001] This application relates to the field of analog-to-digital converter technology, specifically to a clock skew calibration method, apparatus, device, and program product for an analog-to-digital converter. Background Technology

[0002] In related technologies, during the clock skew calibration process of Time-Interleaved Analog-to-Digital Converter (TIADC), there is a lack of effective identification and avoidance mechanisms for preset frequency points such as DC, integer multiples of the ratio of the total sampling rate to the number of channels of the time-interleaved ADC, and the Nyquist frequency, which makes it easy to generate incorrect bias estimates at these frequency points. Summary of the Invention

[0003] The technical problem solved by this application is to provide a clock skew calibration method, apparatus, device and program product for an analog-to-digital converter, which can avoid erroneous deviation estimation at a preset frequency reference point.

[0004] According to a first aspect of the present application, a clock skew calibration method for an analog-to-digital converter is provided. The method includes: acquiring the input frequency of a time-interleaved analog-to-digital converter; determining whether the input frequency is within a preset frequency protection zone based on a preset set of frequency reference points; the preset set of frequency reference points includes a plurality of discrete reference frequency points; the preset frequency protection zone includes a frequency band region centered on the reference frequency points and having a preset protection bandwidth; when the input frequency is within the preset frequency protection zone, using the previous valid clock skew estimate or a limiting estimate as the current clock skew estimate; and performing clock skew calibration on each channel based on the current clock skew estimate.

[0005] Compared with the prior art, the beneficial effects of this application are as follows: by determining whether the input frequency is in the preset frequency protection zone according to the preset frequency reference point set, the preset frequency point is effectively identified, and when the input frequency is in the preset frequency protection zone, the previous valid clock deviation estimate or limiting estimate is used as the current clock deviation estimate, which effectively avoids the erroneous deviation estimate at the preset frequency reference point.

[0006] In one embodiment, the method further includes: acquiring the output data of each channel of a time-interleaved analog-to-digital converter; constructing a clock skew detection formula based on the output data of each channel, the clock skew detection formula being used to characterize the relationship between the statistics of the sampled data between channels and the clock skew, the clock skew detection formula including a numerator and a denominator, wherein the numerator is composed of the difference in statistics between different channels, and the denominator is composed of a correlation energy term or an equivalent slope term for normalization; when the denominator is greater than or equal to an adaptive threshold and the input frequency is not within a preset frequency protection zone, calculating the current clock skew estimate according to the clock skew detection formula; when the denominator is less than the adaptive threshold, using the previous valid clock skew estimate or a limiting estimate as the current clock skew estimate.

[0007] Its beneficial effects are that by constructing a clock deviation detection formula, a quantitative relationship between inter-channel statistics and clock deviation is established, and the reliability of the estimation is judged in real time based on the comparison between the denominator term and the adaptive threshold. When the conditions are not met, a conservative estimation strategy is adopted, which effectively avoids erroneous estimation, ensures the continuity and stability of the calibration process, and significantly improves the accuracy and reliability of clock deviation estimation.

[0008] In one implementation, clock skew calibration is performed on each channel based on the current clock skew estimate, including: digital domain compensation or analog domain adjustment of the sampling clock phase of each channel based on the current clock skew estimate to eliminate clock skew between channels.

[0009] Its beneficial effect is that by compensating the sampling clock phase of each channel in the digital or analog domain based on the current clock deviation estimate, the clock skew between channels is directly eliminated, effectively improving the channel consistency and conversion accuracy of the time-interleaved analog-to-digital converter.

[0010] In one embodiment, acquiring the input frequency of the time-interleaved analog-to-digital converter and determining whether the input frequency is within a preset frequency protection zone based on a preset frequency reference point set further includes: performing a folding mapping on the input frequency to obtain a folded frequency within a single-channel sampling bandwidth, and establishing a preset frequency reference point set, the preset frequency reference point set containing preset frequency reference points; generating a preset frequency protection zone flag based on the distance between the folded frequency and the preset frequency reference points, the preset frequency protection zone flag being used to indicate whether the input frequency is within the preset frequency protection zone.

[0011] Its beneficial effect is that by converting the input frequency to a single-channel sampling bandwidth through folding mapping, and generating a protection zone marker based on the distance relationship between the folded frequency and the preset frequency reference point, it achieves accurate identification and status indication of sensitive frequency points, and provides a reliable frequency point judgment basis for clock skew calibration.

[0012] In one implementation, the preset frequency reference point set includes a 0 frequency point and a f frequency point. s The frequency points that are integer multiples of / (2M), the single-channel Nyquist frequency points, and the equivalent frequency points within the single-channel sampling bandwidth mapped to the above frequency points through spectral folding; where f s is the total sampling rate of the time-interleaved analog-to-digital converter, and M is the number of channels of the time-interleaved analog-to-digital converter.

[0013] Its beneficial effect is that at the 0-frequency point, i.e., the DC signal is not sensitive to clock skew and cannot provide effective deviation detection information; f s Frequency points that are integer multiples of 2M correspond to spectral mirror symmetry positions caused by the sampling phase difference between channels in the time-interleaved architecture. At these frequency points, the signal mismatch caused by clock skew is canceled out by spectral symmetry, making the deviation detection method based on statistical difference ineffective. The single-channel Nyquist frequency point serves as the boundary of the single-channel sampling bandwidth, and the spectral aliasing effect near it will cause statistical calculation distortion. The equivalent frequency points within the single-channel sampling bandwidth mapped by the above frequency points through spectral folding further cover the equivalent preset frequency points generated by spectral folding under high input frequency conditions. By incorporating these frequency points with clear physical meaning into the preset frequency reference point set, this implementation can accurately identify and avoid all frequency bands that may cause clock deviation estimation failure or unreliability, thereby ensuring that the calibration algorithm only works within the frequency range with sufficient sensitivity and reliability. This effectively avoids erroneous calibration or estimation divergence caused by improper frequency point selection, and significantly improves the robustness and applicability of the clock skew calibration method.

[0014] In one embodiment, the method further includes: acquiring at least one of the clock frequency, sampling rate, and number of channels of the time-interleaved analog-to-digital converter, and initializing an observation window; and determining the adaptive threshold based on at least one of the moving average of the denominator term, the variance of the denominator term, the amplitude of the input signal, the quantization noise estimate, and a preset safety factor within the observation window.

[0015] Its beneficial effects are as follows: the moving average of the denominator within the observation window can capture the long-term trend and baseline level of the statistic, ensuring that the threshold setting is statistically representative and avoiding misjudgments caused by instantaneous fluctuations; the variance of the denominator reflects the fluctuation characteristics and stability of the statistic, and automatically increases the threshold value when the variance is large, preventing unreliable bias estimation under unstable statistic conditions; the introduction of the input signal amplitude allows the threshold to be dynamically adjusted with the signal strength, lowering the threshold under strong signal conditions to improve detection sensitivity, and raising the threshold under weak signal conditions to avoid false triggering caused by noise interference; the consideration of quantization noise estimation ensures that the threshold setting can effectively distinguish between signal mismatch caused by real clock skew and inherent system noise, improving the signal-to-noise ratio and reliability of the estimation results; the introduction of the preset safety factor provides a configurable safety margin for the threshold setting, further enhancing the robustness of the calibration process under extreme conditions. Through this adaptive threshold mechanism that integrates multiple factors, this application can dynamically optimize the threshold value based on different input signal characteristics, noise levels, and statistical stability. This not only overcomes the problem of insufficient adaptability of fixed thresholds in complex and variable working environments, but also ensures that clock deviation estimation is adopted only when the statistical quantity has sufficient sensitivity and reliability. Thus, while ensuring calibration accuracy, it significantly improves the environmental adaptability and overall reliability of the clock skew calibration method.

[0016] In one implementation, the clock skew detection formula is: , , ; Where ΔT is the clock bias value of the time-interleaved analog-to-digital converter, A[n] is the numerator, B[n] is the denominator, and n is the calibration cycle index; the time-interleaved analog-to-digital converter includes a first channel, a second channel, and a third channel; D1 is the output data energy statistic of the first channel; D2 is the output data energy statistic of the second channel; D3 is the output data energy statistic of the third channel; M1 is the output data mean statistic of the first channel; and M2 is the output data mean statistic of the second channel.

[0017] Its beneficial effects lie in the fact that this clock skew detection method is built upon the statistical characteristics of the output data of a three-channel time-interleaved analog-to-digital converter. By comprehensively comparing the energy difference between the first and third channels and the mean difference between the first and second channels, and normalizing these differences, a sensitive criterion for clock skew is formed. The numerator integrates the difference between the energy statistics and the mean statistics, preserving the responsiveness to high-frequency signal changes while enhancing stability under low-frequency or DC-containing signals, effectively compensating for the sensitivity decrease of a single statistic at a specific frequency. The denominator uses the sum of the energies of the first two channels as a normalization factor, approximately reflecting the overall signal strength of the system, thereby suppressing interference caused by input signal amplitude fluctuations. This ensures that the detection result only characterizes the relative mismatch between channels, rather than being affected by absolute amplitude. This detection formula also possesses good common-mode rejection capability. When each channel is subjected to the same external interference, its impact is partially canceled out in the differential operation, improving the system's robustness in non-ideal environments. Most importantly, in a three-channel configuration, this detection method overcomes the zero-sensitivity frequency point problem caused by spectral symmetry in the traditional two-channel architecture, enabling reliable calibration over a wider input frequency range. Simultaneously, the entire calculation process involves only addition, subtraction, and one division, resulting in a simple structure, low computational overhead, and ease of real-time closed-loop calibration on hardware platforms. It balances high precision, strong adaptability, and engineering feasibility, providing a solid technical foundation for self-calibration of high-performance time-interleaved analog-to-digital converter systems.

[0018] In one implementation, the clock skew detection formula is: ; Where ΔT is the clock bias value of the time-interleaved analog-to-digital converter, A[n] is the numerator, B[n] is the denominator, ε[n] is the adaptive threshold, and n is the calibration cycle index.

[0019] Its beneficial effect lies in the fact that this clock skew detection method adopts a ratio structure where the numerator is a statistical component and the denominator is the maximum value of the corresponding denominator component. Its core advantage is that it significantly improves the stability and adaptability of the detection results through dynamic normalization. Specifically, the numerator reflects the feature quantity directly related to clock skew extracted by the system under the current calibration cycle index, while the denominator is taken from the maximum value among multiple candidate denominator components within the same cycle. A conservative normalization strategy is introduced. When a denominator component decreases abnormally due to noise disturbance or transient anomalies, the system automatically switches to a more robust reference benchmark, avoiding drastic divergence or false triggering of the detection value due to an excessively small denominator. This design effectively suppresses the numerical instability problem commonly found in traditional fixed denominator normalization methods, and is particularly suitable for practical application scenarios with large dynamic range of input signals and significant noise fluctuations. Furthermore, combined with the adaptive threshold mechanism described earlier, this detection value can be more accurately determined whether it falls within the reliable estimation range: calibration is only initiated when the normalized deviation exceeds a dynamic threshold determined by the moving average, variance, signal strength, and quantization noise. This significantly reduces the false alarm rate while maintaining sensitivity. Overall, this detection method not only enhances the ability to identify real clock skew but also improves the long-term operational reliability of the system under complex conditions through its inherent robust design.

[0020] In one implementation, when the denominator is less than the adaptive threshold or is within a preset frequency protection zone, the system enters a hold mode. In hold mode, the clock deviation register outputs the most recent valid clock deviation estimate obtained when the denominator is greater than or equal to the adaptive threshold and the frequency is not within the preset frequency protection zone.

[0021] Its beneficial effects lie in the fact that the hold-mode mechanism significantly improves the stability and reliability of the clock skew calibration system: when the denominator is less than the adaptive threshold, it indicates that the statistical signal-to-noise ratio within the current observation window is low, the fluctuation is severe, or the signal energy is insufficient. If the skew estimate is forcibly updated at this time, it is easy to introduce noise-dominated error correction, leading to system performance degradation. The preset frequency protection zone setting addresses the inherent spectral symmetry problem in time-interleaved analog-to-digital converters. At certain specific input frequencies, the characteristic response caused by channel mismatch approaches zero, and the detection sensitivity is lost. At this time, updating the skew will produce meaningless or even reverse correction. By automatically switching to hold mode under the above two unreliable conditions, the system can freeze and continuously output the previously verified and effective clock skew estimate, which is equivalent to building a robust filtering loop with memory function. This avoids oscillations and divergences in the calibration process and ensures the continuity and reliability of calibration results within the key operating frequency band. Especially in scenarios where the input signal changes dynamically, there is sudden interference, or frequency sweep testing, this strategy effectively prevents calibration failure caused by instantaneous anomalies, ensuring that the entire clock skew compensation loop operates smoothly and reliably under all operating conditions, providing a solid time reference guarantee for high-precision data acquisition systems.

[0022] In one implementation, when the denominator term is less than the adaptive threshold or is within a preset frequency protection zone, an auxiliary window estimation mode is entered. The auxiliary window estimation mode calculates the clock deviation estimate in at least two non-preset frequency observation windows adjacent to the target frequency, and performs weighted fusion according to the distance from the preset frequency, the magnitude of the relevant statistics, or the degree of spectral leakage.

[0023] Its beneficial effect lies in the fact that this auxiliary window estimation mode cleverly solves the limitations of the traditional hold-and-hold mode under special operating conditions. By constructing a multi-window collaborative observation mechanism in the neighborhood of the target frequency, it achieves intelligent interpolation and accurate reconstruction of clock deviation. When the system detects that the current operating point falls into the statistically unreliable region or the preset frequency protection zone, this mode does not simply freeze historical estimates. Instead, it actively calls multiple observation windows with clear signal characteristics and reliable statistics in adjacent frequency bands, calculates candidate clock deviation values ​​for each, and dynamically weights and fuses them based on multiple factors such as the frequency domain distance between each window and the target frequency, the amplitude of the corresponding statistics, and the degree of spectral leakage. This design fully utilizes the physical characteristic that clock skew usually exhibits continuous variation in the frequency domain, avoiding the hysteresis error that may occur when the hold-and-hold mode sweeps rapidly during frequency, and overcoming the random fluctuation problem of single-window estimation under low signal-to-noise ratio conditions. The distance factor in the weighting strategy ensures that frequency domain proximity dominates the estimation results, the statistical amplitude weight strengthens the contribution of the high-confidence window, and the consideration of spectral leakage further suppresses estimation bias caused by spectral aliasing. The synergistic effect of these three factors enables the fused results to maintain smoothness while possessing high local accuracy. Overall, this model significantly improves the adaptability and estimation continuity of the calibration system across the entire frequency band. Especially in dynamic application scenarios such as broadband scanning and frequency hopping communication, it can achieve seamless and robust clock skew tracking, providing a more intelligent solution for real-time self-calibration of high-performance time-interleaved analog-to-digital converters.

[0024] In one implementation, when the denominator term is less than the adaptive threshold or is within a preset frequency protection zone, the output limiting mode is entered. The output limiting mode sets a maximum change in the difference between the current clock deviation estimate and the historical valid estimate to prevent a sudden change in the compensation amount caused by a single observation window.

[0025] Its beneficial effect lies in the fact that this output limiting mode effectively ensures the smoothness and robustness of the clock deviation calibration process by introducing a rate-of-change constraint mechanism. When the system is in a condition with low statistical reliability, and the denominator is less than the adaptive threshold or the preset frequency protection zone, this mode does not completely freeze the calibration update, but rather imposes a strict limit on the jump amplitude between the current estimate and the historical effective value, which is equivalent to constructing a soft limiting filter in the time domain. This design balances the timeliness and stability of the calibration response: on the one hand, it allows the system to make small, incremental adjustments under abnormal conditions, avoiding the lag accumulation error that may be caused by the hold mode; on the other hand, by setting a maximum change threshold, it completely eliminates the drastic jump in compensation caused by noise spikes, signal transient anomalies, or spectral interference within a single observation window, preventing overshoot oscillations or divergence in the calibration loop. This limiting strategy is essentially a conservative incremental update principle, ensuring that the clock deviation compensation always evolves incrementally within a physically feasible and reasonable range, maintaining the dynamic tracking capability of the calibration system while significantly improving its anti-interference performance in harsh signal environments. Especially in application scenarios where the input signal has sudden pulse interference, drastic amplitude fluctuations, or rapid frequency switching, this mode can effectively suppress the "glitch" phenomenon in the calibration process, so that the clock skew compensation always maintains a smooth and controllable convergence trajectory, providing a key guarantee for the long-term stable operation of the high-precision time-interleaved analog-to-digital conversion system.

[0026] In one implementation, an adaptive threshold It has an upper limit and a lower limit. The upper limit is used to prevent the protection zone from being too wide, which would prevent the ordinary frequency points from being updated. The lower limit is used to prevent quantization noise or jitter noise from causing the denominator protection to fail.

[0027] Its beneficial effect lies in the fact that this dual-boundary adaptive threshold design achieves a fine balance between sensitivity and robustness in the calibration system by introducing a collaborative constraint mechanism of upper and lower limits. The upper limit effectively prevents the adaptive threshold from becoming excessively inflated due to abnormally high historical statistics, avoiding the unlimited expansion of the protected area and preventing a large number of normal operating frequency points from being incorrectly classified as "unreliable regions." This ensures that the system can maintain a normal calibration update frequency under normal signal conditions, maintaining the timeliness and accuracy of clock deviation estimation. Simultaneously, the introduction of the lower limit constructs a protective barrier against underlying noise interference. When the denominator term briefly drops due to quantization noise, clock jitter, or other weak random disturbances, this lower threshold prevents the system from misjudging a statistical failure state, avoiding the protection mechanism from being triggered by noise and frequently switching operating modes, ensuring the continuous and stable operation of the calibration loop in low-amplitude signal or high-precision application scenarios. This threshold architecture with coordinated upper and lower limits not only enhances the system's adaptability to the dynamic range of input signals, but also significantly improves the reliability of the entire clock deviation detection and calibration process through a dual insurance mechanism. This enables the system to not only keenly capture real clock skew changes, but also effectively filter out various noise interferences, providing a solid guarantee for the long-term stable operation of high-precision time-interleaved analog-to-digital converters in complex electromagnetic environments.

[0028] In one implementation, when the denominator is greater than or equal to an adaptive threshold and is not within a preset frequency protection zone, the current clock deviation estimate is calculated according to the clock deviation detection formula. This includes: generating a preset frequency protection zone flag based on the comparison result between the input frequency and a preset frequency reference point set, the preset frequency protection zone flag indicating whether the input frequency is within the preset frequency protection zone; generating a denominator threshold comparison result flag based on the comparison result between the denominator and the adaptive threshold, the denominator threshold comparison result flag indicating whether the denominator is greater than or equal to the adaptive threshold; generating an output limiting flag based on the judgment result of whether the current clock deviation estimate exceeds a preset limiting range, the output limiting flag indicating whether a limiting estimate is used; performing logical operations on the preset frequency protection zone flag, the denominator threshold comparison result flag, and the output limiting flag to generate an update enable signal, the update enable signal controlling whether to update the clock deviation estimate; when the update enable signal is valid, calculating the current clock deviation estimate according to the clock deviation detection formula; when the update enable signal is invalid, maintaining the previous valid clock deviation estimate or using a limiting estimate.

[0029] Its beneficial effects lie in the fact that this multi-flag logic control mechanism significantly improves the intelligence level and operational reliability of the clock deviation estimation system by constructing a hierarchical decision-making system. By generating an update enable signal through logical operations on the preset frequency protection zone flag, the denominator threshold comparison result flag, and the output limiting flag, the system achieves precise control over the clock deviation update conditions. This ensures that the deviation parameter is only allowed to be updated under multiple conditions: reliable statistics, safe frequency position, and reasonable estimated value. This effectively avoids the risk of erroneous updates that may be caused by a single judgment condition. This design decomposes the complex calibration decision process into multiple independent judgment modules, each focusing on a specific reliability verification task. This not only improves the modularity of the system, facilitating debugging and maintenance, but also achieves the organic integration of various judgment conditions through logical operations, forming a multi-layered insurance mechanism. When any condition is not met, the system can intelligently choose to maintain the historical valid value or adopt the limiting estimate, preventing abnormal data from contaminating the calibration results and ensuring the continuity and smoothness of the output. This mechanism is particularly suitable for practical application scenarios with dynamically changing input signals or complex working environments. It can significantly improve the system's anti-interference capability and long-term operational stability while ensuring calibration accuracy, providing a reliable logic control basis for the adaptive calibration of high-precision time-interleaved analog-to-digital converters.

[0030] In one implementation, a clock skew detection formula is constructed based on the output data of each channel, including: obtaining the observation window length, calculating the numerator and denominator of the clock skew detection formula within each observation window, and constructing the clock skew detection formula based on similar triangle relationships or Pearson correlation coefficient statistics.

[0031] Its beneficial effects are that by using similar triangle relationships or Pearson correlation coefficients to construct clock deviation detection formulas, it can adapt to different signal conditions and avoid estimation failure caused by preset frequency points; by synchronously calculating the numerator and denominator terms within the observation window, the statistics are made insensitive to changes in signal amplitude, thus improving detection robustness and accuracy.

[0032] In one embodiment, before acquiring the total sampling rate, number of channels, input frequency, and output data of each channel of the time-interleaved analog-to-digital converter, the method further includes: performing offset error calibration on each channel of the time-interleaved analog-to-digital converter to eliminate the DC offset component in the output of each channel and avoid interference of the DC offset component on the denominator; performing gain error calibration on each channel of the time-interleaved analog-to-digital converter to balance the conversion gain of each channel and avoid gain mismatch affecting the determination of whether the input frequency is within the preset frequency protection zone; wherein, offset error calibration and gain error calibration are used together to eliminate the interference of static mismatch between channels on the accuracy of clock skew detection.

[0033] According to a second aspect of the embodiments of this application, a clock skew calibration device for an analog-to-digital converter is provided, used to implement the method of any one of the first aspects. The device includes: a statistics calculation module, used to acquire the input frequency of a time-interleaved analog-to-digital converter, and determine whether the input frequency is within a preset frequency protection zone based on a preset frequency reference point set; the preset frequency reference point set includes a plurality of discrete reference frequency points; the preset frequency protection zone includes a frequency band region centered on the reference frequency points and having a preset protection bandwidth; an estimation update control module, used to use the previous effective clock skew estimate or a limiting estimate as the current clock skew estimate when the input frequency is within the preset frequency protection zone; and a compensation execution module, used to perform clock skew calibration on each channel based on the current clock skew estimate.

[0034] In one embodiment, the device further includes a hierarchical clock deviation calibration link, which comprises N cascaded clock deviation calibration stages. Each stage is equipped with an adaptive threshold generation module, a validity flag module, and a clock deviation holding register. The adaptive threshold generation module generates an adaptive threshold value based on the frequency band characteristics corresponding to its calibration stage, wherein the adaptive threshold values ​​of the N cascaded clock deviation calibration stages increase progressively. The validity flag module determines whether the clock deviation estimate of the current calibration stage is valid and generates a validity flag signal, and the validity determination of the subsequent calibration stage depends on the validity flag of the previous calibration stage. The clock deviation holding register stores and holds the valid clock deviation estimate of the current calibration stage, and updates it to the current clock deviation estimate when the validity flag is valid; otherwise, it retains the previous valid value. The hierarchical clock deviation calibration link is used for M-channel time-interleaved analog-to-digital converters, where M is a positive integer greater than 2, for hierarchical calibration of clock deviations in different frequency bands.

[0035] Its beneficial effects lie in the fact that this hierarchical clock skew calibration link achieves refined and progressive calibration of the clock skew of time-interleaved analog-to-digital converters through an N-level cascaded hierarchical calibration architecture. The design of progressively increasing adaptive threshold values ​​across four calibration levels constructs a calibration gradient from coarse to fine: the first level uses a lower threshold for rapid coarse calibration, quickly capturing a wide range of clock skew; subsequent levels gradually increase the threshold, focusing on fine correction of residual skew. This progressive calibration strategy ensures both calibration speed and final accuracy. The cascading dependency mechanism of the valid flag module forms a strict calibration quality control chain; the next level of calibration will only be initiated when the current level's calibration result is deemed valid. This "layer-by-layer check" design effectively prevents error accumulation and the propagation of invalid calibrations, significantly improving the reliability of the entire calibration link. The configuration of the clock skew holding register ensures the stability of each level's calibration results, maintaining valid calibration parameters even when detection conditions are not met within certain observation windows, avoiding parameter jitter during the calibration process. By configuring different adaptive threshold values ​​for different frequency band characteristics, the system can perform targeted calibration based on the signal statistical characteristics within different frequency ranges. This is particularly suitable for wideband time-interleaved analog-to-digital converters (ADCs) used in wide-band applications. This hierarchical calibration architecture not only significantly improves the accuracy and robustness of clock skew calibration but also enhances the system's maintainability and scalability through modular design, providing strong technical support for the stable operation of high-channel-count time-interleaved ADCs under complex operating conditions.

[0036] A third aspect of the present application provides an electronic device including a memory and a processor, wherein the memory stores a computer program executable by the processor; and the processor executes the computer program in the memory to implement the method described above.

[0037] According to a fourth aspect of the embodiments of this application, a computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, can implement the above-described method.

[0038] According to a fifth aspect of the embodiments of this application, a computer program product is provided, including a computer program that, when executed by a processor, implements the above-described method. Attached Figure Description

[0039] Figure 1 This is a flowchart illustrating a clock skew calibration method for an analog-to-digital converter according to an exemplary embodiment.

[0040] Figure 2 This is a schematic diagram comparing the logarithmic coordinate curves of the calculated coefficient k and the denominator D in a conventional method according to an exemplary embodiment.

[0041] Figure 3 This is a schematic diagram illustrating the variation curve of a parent statistic D[n] with sampling point n according to an exemplary embodiment.

[0042] Figure 4 This is a schematic diagram of a calibration coefficient update enable signal curve according to an exemplary embodiment.

[0043] Figure 5 This is a schematic diagram illustrating a comparison between a spurious-free dynamic range curve as a function of normalized input frequency and a conventional method, according to an exemplary embodiment.

[0044] Figure 6 This is a schematic diagram illustrating a comparison curve of effective number of bits performance with a conventional method, according to an exemplary embodiment.

[0045] Figure 7 This is a schematic diagram comparing the convergence curve of the calibration coefficient k of the traditional method with that of the traditional method.

[0046] Figure 8 This is a schematic diagram of the normalized input frequency versus amplitude curve using a traditional method.

[0047] Figure 9 This is a schematic diagram illustrating the relationship between normalized input frequency and amplitude according to an exemplary embodiment.

[0048] Figure 10 This is a block diagram illustrating a clock skew calibration device for an analog-to-digital converter according to an exemplary embodiment.

[0049] Figure 11 This is a block diagram illustrating an electronic device according to an exemplary embodiment. Detailed Implementation

[0050] Unless otherwise defined, the technical or scientific terms used in this specification and claims shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. Specific embodiments of this application will be described below in conjunction with the accompanying drawings. It should be noted that, in order to provide a concise description, this specification cannot exhaustively describe all features of the actual embodiments. Without departing from the spirit and scope of this application, those skilled in the art can modify and substitute the embodiments of this application, and the resulting embodiments are also within the protection scope of this application.

[0051] In related technologies, a digital calibration algorithm has been proposed to address the time skew error between channels in a time-interleaved analog-to-digital converter. However, when the input frequency is close to DC, f sWhen the frequency is a multiple of 2MHz, a single-channel Nyquist frequency, or falls near these specific reference points after folding, the correlation statistics in this type of detection formula become less sensitive, and the normalized denominator or equivalent slope term may be too small. Thus, The estimated value is easily amplified abnormally, and the performance of the analog-to-digital converter may actually decrease after calibration.

[0052] This decline is not solely due to insufficient divider precision; the primary reason is the unique periodicity of the input sequence at the preset frequency. At this point, adjacent or alternate channel sample values ​​may be approximately symmetrical, nearly identical, or the differential energy may significantly decrease. Consequently, the difference between statistics no longer stably represents the true time skew. If the calibration coefficients are still updated directly using the formula for ordinary frequency points, the clock bias register will be overwritten by abnormal estimates, and subsequent compensation modules will adjust the sampled data in the wrong direction or by an excessive amount. Ultimately, this results in a decrease in Spurious Free Dynamic Range (SFDR), Signal-to-Noise and Distortion Ratio (SNDR), and Effective Number of Bits (ENOB).

[0053] One intuitive approach is to increase the observation window, decrease the update rate, or avoid these preset frequencies during testing. However, these approaches are not ideal: an excessively large observation window reduces tracking speed; slower updates cannot determine the reliability of the estimates; and manually avoiding frequencies is unsuitable for broadband communication, frequency sweep testing, and adaptive calibration in the background. Therefore, a digital method is needed that can automatically identify preset frequencies and protect them within the detection mechanism.

[0054] To address the aforementioned technical issues, this application proposes a clock skew calibration method, apparatus, device, and program product for an analog-to-digital converter. This method effectively overcomes the defects of preset frequency calibration failure, insufficient statistical adaptability, poor robustness of fixed thresholds, and incomplete single-domain compensation, thereby significantly improving clock synchronization accuracy and signal reconstruction quality.

[0055] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0056] like Figure 1 As shown, the first embodiment of this application provides a clock skew calibration method for an analog-to-digital converter, the method comprising the following steps: S1 acquires the total sampling rate, number of channels, input frequency, and output data of each channel of the time-interleaved analog-to-digital converter.

[0057] S2, perform folding mapping on the input frequency to obtain the folded frequency within the single-channel sampling bandwidth, and determine whether the input frequency is within the preset frequency protection zone based on the preset frequency reference point set; the preset frequency reference point set contains several discrete reference frequency points; the preset frequency protection zone includes a frequency band area centered on the reference frequency points and having a preset protection bandwidth.

[0058] S3. A clock deviation detection formula is constructed based on the output data of each channel. The clock deviation detection formula is used to characterize the relationship between the sampling data statistics between channels and the clock deviation. The clock deviation detection formula includes a numerator and a denominator. The numerator is composed of the difference in statistics between different channels, and the denominator is composed of the relevant energy term or equivalent slope term used for normalization.

[0059] S4. When the denominator is greater than or equal to the adaptive threshold and is not within the preset frequency protection zone, calculate the current clock deviation estimate based on the clock deviation detection formula. When the denominator is less than the adaptive threshold or is within the preset frequency protection zone, use the previous valid clock deviation estimate or the limiting estimate as the current clock deviation estimate.

[0060] S5, perform clock skew calibration on each channel based on the current clock skew estimate. Clock skew calibration includes: performing digital domain compensation or analog domain adjustment on the sampling clock phase of each channel based on the current clock skew estimate to eliminate clock skew between channels.

[0061] In some specific embodiments, this application first folds the input frequency into a single-channel sampling bandwidth and establishes a preset set of frequency reference points. Then, based on the distance between the folded frequency and the preset frequency reference points, a protected area marker is generated.

[0062] For the original algorithm detection formula In this application, the numerator term is defined as Define the denominator as An adaptive threshold is generated based on the signal energy, noise estimate, and sliding statistic of B within the observation window. .

[0063] when Furthermore, if the input frequency is not within the preset frequency protection zone, the system will update according to the original detection method. .when If the input frequency is within a preset frequency protection zone, the system will not directly use the current detection value, but will retain the previous valid value. Limit the current estimate or combine it with nearby non-preset frequency observation windows to form an auxiliary estimate.

[0064] This application does not change the main detection path of the original algorithm, but adds a confidence determination path between the statistical calculation and the division output. The clock bias register is only allowed to be updated when the following conditions are met: the current frequency is close to the preset frequency point, the denominator has sufficient energy, and the current estimated value jumps too much relative to the historical effective value.

[0065] like Figure 2 As shown, Figure 2 The advantages of the adaptive threshold protection mechanism proposed in this application in terms of numerical stability are intuitively demonstrated in logarithmic coordinates. Figure 2 The horizontal axis represents the key denominator statistic D in clock skew detection, i.e., the normalized value of B[n]. The vertical axis represents the calculation coefficient k, using a logarithmic scale. The calculation coefficient k is the core parameter in the clock skew calibration algorithm, directly determining the magnitude of the estimated clock deviation. In traditional algorithms, k is calculated by the formula k = N divided by D, where N is the numerator statistic. Traditional methods rapidly diverge to infinity when D approaches 0, leading to estimation collapse at preset frequency points due to an excessively small denominator. The dashed line represents the method in this application, where k equals N divided by max(D,ε). When D is greater than ε, it is consistent with the traditional method. Once D is less than or equal to ε, the denominator is clamped to a fixed minimum value ε at the threshold position indicated by the vertical dashed line, thus ensuring that k remains bounded to the upper limit N divided by ε, maintaining bounded stability. The critical interval for failure of the traditional method is the interval where D is less than ε. This method effectively avoids the risk of division by zero and numerical overflow by introducing an adaptive threshold, providing robust protection for clock skew estimation.

[0066] In one implementation, the preset frequency reference point set includes a 0 frequency point and a f frequency point. s The frequency points that are integer multiples of / (2M), the single-channel Nyquist frequency points, and the equivalent frequency points within the single-channel sampling bandwidth mapped by the above frequency points through spectral folding. Where f s is the total sampling rate of the time-interleaved analog-to-digital converter, and M is the number of channels of the time-interleaved analog-to-digital converter.

[0067] In some specific embodiments, the single-channel sampling rate of the time-interleaved analog-to-digital converter is f. s / M. For the input calibration frequency f in The sample is folded into a single-channel sampling bandwidth according to the aliasing relationship to obtain the folding frequency f. fold The preset frequency reference point set S and the minimum distance criterion. satisfy:

[0068]

[0069] Among them, the minimum distance criterion Defined as the minimum absolute distance between the folded frequency and all points in the preset frequency set within the nth observation window. Not greater than the protection threshold If the input frequency falls within a preset frequency protection zone, it is determined that the frequency falls within the normal frequency range. Otherwise, it is considered to be in the normal frequency range. Protection threshold. It can be determined by combining frequency resolution, observation window length, noise margin, and the system's allowable estimation error.

[0070] In some examples, the protection threshold may not be fixed. If the number of sampling points is small, the input signal-to-noise ratio is low, or the jitter noise is large, the protection threshold can be appropriately relaxed to reduce erroneous updates. If the input frequency is known and the observation window is long, the protection threshold can be set narrower to avoid over-protecting common frequency points.

[0071] In one implementation, the clock skew detection formula is: , , .

[0072] Where ΔT is the clock bias value of the time-interleaved analog-to-digital converter, A[n] is the numerator, B[n] is the denominator, and n is the calibration period index. The time-interleaved analog-to-digital converter includes a first channel, a second channel, and a third channel. D1 is the output data energy statistic of the first channel. D2 is the output data energy statistic of the second channel. D3 is the output data energy statistic of the third channel. M1 is the mean output data statistic of the first channel. M2 is the mean output data statistic of the second channel.

[0073] In some specific embodiments, the effective value of B[n] may decrease near a preset frequency point, and the ratio between A[n] and B[n] may also be distorted. If division is still performed directly in this case, a sudden change may easily occur.

[0074] In one implementation, the clock skew detection formula is: .

[0075] Where ΔT is the clock bias value of the time-interleaved analog-to-digital converter, A[n] is the numerator, B[n] is the denominator, ε[n] is the adaptive threshold, and n is the calibration cycle index.

[0076] In some specific embodiments, when B[n] is less than At this time, the protection flag is set to an active state, used to prohibit the current Directly overwrite the clock skew register.

[0077] It is worth noting that near the preset frequency point, the effective value of B[n] may decrease, and the proportional relationship between A[n] and B[n] may also be distorted. If division is still performed directly in this case... Mutations are more likely to occur.

[0078] In one implementation, the adaptive threshold is determined based on at least one of the following: the moving average of the denominator term within the observation window, the variance of the denominator term, the amplitude of the input signal, the quantization noise estimate, and a preset safety factor.

[0079] In some examples, the adaptive threshold can use a fixed safety threshold, which is a minimum denominator energy value given by system simulation or post-silicon testing.

[0080] In other examples, adaptive thresholds can also use sliding statistical thresholds, which calculate the moving average of the denominator over several observation windows and then multiply it by a safety factor to obtain the current threshold.

[0081]

[0082] in The lower limit threshold, Let B[n] be the moving average. Let B[n] be the sliding standard deviation. and A configurable safety factor is provided. With this approach, the threshold can adapt to changes in input amplitude and statistical stability, reducing erroneous updates even in low-amplitude or high-noise scenarios.

[0083] In some other examples, the adaptive threshold can also use a noise-dependent threshold to determine the lowest credible energy of the denominator based on quantization noise, thermal noise, or sampling jitter estimates.

[0084] In one implementation, when the denominator is less than the adaptive threshold or is within a preset frequency protection zone, the system enters a hold mode. In hold mode, the clock deviation register outputs the most recent valid clock deviation estimate obtained when the denominator is greater than or equal to the adaptive threshold and the frequency is not within the preset frequency protection zone.

[0085] In some specific embodiments, when the input frequency falls within a preset frequency protection zone or In this case, this application prioritizes the hold mode, that is, outputting the condition that was met in the previous observation window. And not within the effective frequency protection zone of the preset frequency point The clock skew correction value ΔT output by the nth observation window. OUT [n] satisfies:

[0086] in, For the nth A valid clock skew estimate obtained from a single window.

[0087] It's worth noting that the hold mode is suitable for scenarios where clock skew changes slowly, such as slow changes in chip temperature, slow drift in supply voltage, or long-term operation of the communication receiver link during background calibration. In these scenarios, using the previous valid estimate for a short period will not introduce significant residual error, but it can prevent abnormal estimates at a preset frequency from entering the compensation link.

[0088] In one implementation, when the denominator term is less than the adaptive threshold or is within a preset frequency protection zone, an auxiliary window estimation mode is entered. The auxiliary window estimation mode calculates the clock deviation estimate in at least two non-preset frequency observation windows adjacent to the target frequency, and performs weighted fusion according to the distance from the preset frequency, the magnitude of the relevant statistics, or the degree of spectral leakage.

[0089] In some specific embodiments, during front-end calibration or back-end calibration where a pool of available candidate frequencies exists, this application can select auxiliary windows with non-preset frequencies on both sides of the target preset frequency, and calculate the clock skew estimate independently calculated by the q-th auxiliary window. And based on the distance from the preset frequency point, the distance between each window and the target frequency point, and the statistical confidence level as shown in B. q Amplitude and spectral leakage are weighted and fused. The fused auxiliary clock skew estimate ΔT aux satisfy:

[0090] Among them, w q Let q be the fusion weight of the q-th auxiliary window.

[0091] It is worth noting that the auxiliary window estimation mode is suitable for front-end frequency sweep calibration or scenarios where there are multiple candidate frequency observation windows on the chip. The clock deviation between actual channels is mainly determined by the physical path, and the difference is usually small at adjacent frequency points. Therefore, the compensation amount of the target frequency point can be inferred by using reliable estimates on both sides of the preset frequency point, avoiding unreliable division directly at the target preset frequency point.

[0092] In one implementation, when the denominator term is less than the adaptive threshold or is within a preset frequency protection zone, the output limiting mode is entered. The output limiting mode sets a maximum change in the difference between the current clock deviation estimate and the historical valid estimate to prevent a sudden change in the compensation amount caused by a single observation window.

[0093] In some specific embodiments, to avoid a compensation step when the input frequency slowly sweeps across a preset frequency point, this application can also set an output limiting mode to limit the current frequency. Effective with history The difference between them sets the maximum change. The maximum allowable single-step change ΔT. max satisfy:

[0094] in, This is the clock skew correction value output in the nth window. For the nth A valid clock skew estimate obtained from a single window.

[0095] It's worth noting that the clipping mode is suitable for scenarios where the input frequency sweeps through a preset frequency point or where the system state changes rapidly. This mode does not completely freeze the calibration results, but rather allows the estimated value to change at a controlled rate, balancing stability and tracking capability. The clipping threshold can be determined based on the minimum step size of the clock adjustment unit, the quantization bit width of the digital fractional delay filter coefficients, and the allowable transient error.

[0096] like Figure 3 As shown, the curve of the denominator statistic D[n] varies with the sampling point n, with the vertical axis ranging from 0 to 0.5. The figure contains a horizontal dashed line, which represents the preset threshold value ε. When D[n] is lower than this threshold, the system triggers a protection action. The figure is marked with the "Activate Protection" area to indicate the location where the event occurs.

[0097] like Figure 4 As shown, the curve of the calibration coefficient update enable signal is shown. The vertical axis is a binary signal, which takes the value 0 or 1 to represent the start and stop status of the protection mechanism: when D[n] is higher than the threshold ε, the control signal is 0, indicating that the protection is not enabled; when D[n] drops below the threshold, the control signal jumps to 1, and after a period of time, it returns to 0, corresponding to the activation and deactivation process of the protection mechanism. Figure 3 and Figure 4 The horizontal axis represents sampling point n, ranging from 0 to 200, reflecting the causal relationship between the protection triggered by the decrease of D[n] and the synchronous response of the control signal. The overall waveform exhibits periodic fluctuation characteristics, reflecting the real-time adaptive behavior of the threshold protection mechanism under dynamic input conditions.

[0098] In summary, this application retains the low complexity and rapid update capability of the original algorithm at ordinary frequency points, and automatically switches to threshold, limiting, or hold modes near preset frequency points, thereby reducing the risk of SFDR, SNDR, and ENOB degradation caused by erroneous calibration. The threshold, limiting, and hold modes of this application can all be configured via registers, making it suitable for both front-end pilot calibration and back-end adaptive calibration, exhibiting good engineering adaptability.

[0099] like Figure 5 and Figure 6 As shown, the performance comparison results of the 16-channel TIADC system across the entire frequency band are presented. Figure 5 The graph shows the spurious-free dynamic range (SFDR) as a function of the normalized input frequency. The vertical axis is in decibels (dB), and the horizontal axis is the normalized input frequency f_in / f_s, ranging from 0 to 0.5. Two broken lines are plotted: one connected by hollow circles, representing the traditional method; the other connected by hollow squares, representing the method proposed in this application. Both curves exhibit periodic fluctuations, showing a significant performance degradation at several specific frequency points. However, the SFDR value of this method is consistently higher than that of the traditional method at these points, with a particularly significant advantage in the low and high frequency ranges. The overall fluctuation amplitude is smaller, indicating stronger robustness to frequency-sensitive points.

[0100] like Figure 6 The figure shows a comparison of effective number of bits (ENOB) performance, with the vertical axis representing bits and the horizontal axis representing the normalized input frequency f_in / f_s. In addition to the two methods mentioned above, a horizontal dashed line is added to the figure to represent the limit of the ideal ENOB. It can be seen that the traditional method experiences a sharp drop in ENOB at multiple frequency points, reaching a minimum of close to 6 bits; while the proposed method maintains a high and stable ENOB across the entire frequency band, approaching 9-10 bits in most intervals, significantly outperforming the traditional method and closer to the theoretical upper limit. Both figures together illustrate that the proposed method effectively suppresses performance degradation caused by clock skew calibration failure across the entire frequency band, improving the overall accuracy and stability of the TIADC system.

[0101] like Figure 7 As shown, Figure 7 This paper compares the convergence processes of the calibration coefficient k of the traditional method and the proposed method. The horizontal axis represents the number of iterations, ranging from 0 to 500; the vertical axis represents the value of the calibration coefficient k, ranging from 0.00 to 0.05, with the ideal value being constant at 0.05. The curve of the traditional method starts near zero, rises rapidly, and reaches a stable value within about 50 steps, but its steady-state value is slightly lower than the ideal value. The curve of the proposed method also starts near zero, with an initial rate of increase similar to that of the traditional method, but flattens out after about 100 steps, eventually stabilizing at 0.05, consistent with the ideal value, without overshoot or oscillation. Both convergence curves enter the steady-state region after about 150 steps, with two vertical dashed lines marking the key transition interval to emphasize the temporal characteristics of convergence completion. Overall, the proposed method not only achieves a final convergence result completely consistent with the ideal value but also outperforms the traditional method in steady-state accuracy, verifying its accuracy and reliability in parameter estimation.

[0102] like Figure 8 The figure shows the normalized input frequency versus amplitude curve of the traditional method, as shown below. Figure 9 The figure shows the relationship between the normalized input frequency and amplitude of this method. Figure 8 and Figure 9The horizontal axis represents the normalized input frequency f_in / f_s, ranging from 0 to 0.5, and the vertical axis represents the amplitude (dB), ranging from... 100dB to 0dB. In Figure 8 In the figure, a vertical solid line marks the position where f_in=f_s / 16, and SFDR≈40.0dB. This indicates that at this frequency, the traditional method results in significant harmonic or spurious components due to calibration failure, and the spurious-free dynamic range is low. The spectrum shows a significant energy rise near this point, and there are strong sidelobes outside the main frequency. Figure 9 In the image, the same location is marked with a vertical solid line. SFDR≈75.0dB, indicating that this method achieves a significant performance improvement at this critical frequency point. The spectral peak is sharp, the sidelobes are extremely low, and the overall background noise level is significantly reduced, approaching the ideal situation. This clearly demonstrates that this method effectively overcomes the calibration collapse problem at specific frequency points, ensuring the system's high-precision operation capability at this sensitive frequency.

[0103] In one implementation, an adaptive threshold It has an upper limit and a lower limit. The upper limit is used to prevent the protection zone from being too wide, which would prevent the ordinary frequency points from being updated. The lower limit is used to prevent quantization noise or jitter noise from causing the denominator protection to fail.

[0104] In some specific embodiments, the setting of the upper limit needs to comprehensively consider factors such as sampling rate, number of channels, and spectral resolution. Typically, the upper limit is two to three percent of the preset frequency point spacing. This ensures that the preset frequency points are adequately protected without excessively expanding the protection zone and affecting the normal calibration of ordinary frequency points. If the upper limit is set too high, the system may misclassify a large number of non-preset frequency points as dangerous areas, causing the calibration algorithm to remain in hold mode for extended periods, unable to track real skew changes in a timely manner. Ultimately, this leads to a significant decrease in the system's convergence speed or even a complete loss of self-calibration capability.

[0105] In other specific embodiments, the lower limit value needs to fully consider the noise characteristics of the system, including the impact of quantization noise and clock jitter. The lower limit value should be at least three times the standard deviation of the quantization noise, or at least five times the frequency error caused by clock jitter. Such a setting can effectively prevent minor noise fluctuations from triggering the protection mode, thereby ensuring the reliability of the denominator protection mechanism. If the lower limit value is set too low, the system will be overly sensitive to noise and frequently enter the protection mode, which will not only reduce the stability of the system but may also cause random fluctuations in the calibration results.

[0106] In one implementation, when the denominator is greater than or equal to an adaptive threshold and is not within a preset frequency protection zone, the current clock deviation estimate is calculated according to the clock deviation detection formula. This includes: generating a preset frequency protection zone flag based on the comparison result between the input frequency and a preset frequency reference point set, the preset frequency protection zone flag indicating whether the input frequency is within the preset frequency protection zone; generating a denominator threshold comparison result flag based on the comparison result between the denominator and the adaptive threshold, the denominator threshold comparison result flag indicating whether the denominator is greater than or equal to the adaptive threshold; generating an output limiting flag based on the judgment result of whether the current clock deviation estimate exceeds a preset limiting range, the output limiting flag indicating whether a limiting estimate is used; performing logical operations on the preset frequency protection zone flag, the denominator threshold comparison result flag, and the output limiting flag to generate an update enable signal, the update enable signal controlling whether to update the clock deviation estimate. When the update enable signal is valid, the current clock deviation estimate is calculated according to the clock deviation detection formula. When the update enable signal is invalid, the previously valid clock deviation estimate is maintained or a limiting estimate is used.

[0107] In one implementation, a clock deviation detection formula is constructed based on the output data of each channel, including: obtaining the observation window length, calculating the numerator and denominator of the clock deviation detection formula within each observation window, and constructing the clock deviation detection formula based on similar triangle relationships or Pearson correlation coefficient statistics.

[0108] It is worth noting that the specific construction of clock deviation detection can be based on two different theoretical foundations.

[0109] In some examples, a geometric method based on similar triangle relationships is used to construct clock skew detection formulas. This method uses the geometric relationship formed by the phase difference generated by clock skew in the output data of different channels to derive the detection formula.

[0110] In other examples, a statistical method based on the Pearson correlation coefficient is used to construct the clock skew detection formula. This method constructs the formula by analyzing the correlation between the output data of different channels. Regardless of the construction method used, the core objective is to link the clock skew with the observable data characteristics through mathematical relationships, thereby achieving an accurate estimation of the clock skew. The selection of the observation window length needs to comprehensively consider the system's real-time requirements and estimation accuracy. A window that is too short may lead to high estimation noise, while a window that is too long will affect the system's dynamic response speed.

[0111] In one implementation, before acquiring the total sampling rate, number of channels, input frequency, and output data of each channel of the time-interleaved analog-to-digital converter (ADC), the method further includes: performing offset error calibration on each channel of the time-interleaved ADC to eliminate the DC offset component in the output of each channel and avoid interference from the DC offset component on the denominator B[n] statistic. Performing gain error calibration on each channel of the time-interleaved ADC to balance the conversion gain of each channel and avoid the impact of gain mismatch on the preset frequency point determination. The offset error calibration and gain error calibration are used together to eliminate the interference of static mismatch between channels on the accuracy of clock skew detection.

[0112] In some specific embodiments, offset error calibration typically employs zero-input testing or reference voltage injection, using multiple samples and averaging to improve the accuracy of DC offset estimation. Temperature compensation can be combined with temperature sensor data to further enhance the calibration effect. Gain error calibration can use single-frequency sine wave testing or multi-frequency test signals, using frequency domain analysis or time domain correlation calculation to accurately estimate the gain coefficient of each channel. In practical implementation, these two calibrations can be performed iteratively, i.e., a coarse calibration is performed first, followed by a fine calibration during system operation based on actual operating conditions, forming a closed-loop adaptive calibration mechanism. Furthermore, calibration parameters can be stored in non-volatile memory, supporting rapid power-on recovery, and can also be dynamically adjusted according to environmental parameters such as operating temperature and power supply voltage to ensure good calibration results under various operating conditions.

[0113] like Figure 10As shown, the second embodiment of this application provides a clock skew calibration device 7 for an analog-to-digital converter, used to implement the method of any of the above embodiments, including: a statistics calculation module 1, used to acquire the total sampling rate, number of channels, input frequency, and output data of each channel of the time-interleaved analog-to-digital converter; a frequency folding module 2, used to perform folding mapping on the input frequency to obtain the folded frequency within the sampling bandwidth of a single channel; a preset frequency point determination module 3, used to determine whether the input frequency is within a preset frequency point protection zone according to a preset frequency reference point set; the preset frequency reference point set includes several discrete reference frequency points; the preset frequency point protection zone includes a frequency band region centered on the reference frequency points and having a preset protection bandwidth; and a detection formula construction module 4, used to construct a clock skew detection formula based on the output data of each channel. The clock skew detection formula is used to characterize the relationship between the statistics of the sampling data between channels and the clock skew. The clock skew detection formula includes a numerator and a denominator, wherein the numerator is composed of the difference in statistics between different channels, and the denominator is composed of a correlation energy term or an equivalent slope term used for normalization. The estimation update control module 5 calculates the current clock deviation estimate based on the clock deviation detection formula when the denominator is greater than or equal to the adaptive threshold and not within the preset frequency protection zone. When the denominator is less than the adaptive threshold or within the preset frequency protection zone, the previous valid clock deviation estimate or limiting estimate is used as the current clock deviation estimate. The compensation execution module 6 performs clock skew calibration on each channel based on the current clock deviation estimate. The clock skew calibration includes digital domain compensation or analog domain adjustment of the sampling clock phase of each channel based on the current clock deviation estimate to eliminate clock skew between channels.

[0114] In one embodiment, the device further includes a hierarchical clock skew calibration link, comprising N cascaded clock skew calibration stages. Each stage is equipped with an adaptive threshold generation module, a validity flag module, and a clock skew holding register. The adaptive threshold generation module generates an adaptive threshold value based on the frequency band characteristics corresponding to its calibration stage, wherein the adaptive threshold values ​​of the N cascaded clock skew calibration stages increase progressively. The validity flag module determines whether the clock skew estimate of the current calibration stage is valid and generates a validity flag signal, with the validity determination of the subsequent calibration stage depending on the validity flag of the previous calibration stage. The clock skew holding register stores and holds the valid clock skew estimate of the current calibration stage, updating it to the current clock skew estimate when the validity flag is valid, otherwise retaining the previous valid value. The hierarchical clock skew calibration link is used for M-channel time-interleaved analog-to-digital converters, where M is a positive integer greater than 2, for hierarchical calibration of clock skew in different frequency bands.

[0115] In some specific embodiments, it is worth noting that, in this embodiment, the device provides a set of configurable parameters at the register level, including a protection threshold. The parameters include the threshold safety factor, hold window length, limit step size, number of auxiliary windows, and protection mode priority. These parameters are stored and accessed through dedicated configuration registers and can be dynamically adjusted online.

[0116] Specifically, the protection threshold η is used to determine whether the folding frequency falls within the preset frequency protection zone. The threshold safety factor α is used to adjust the judgment boundary for the validity of the statistics. The maintenance window length defines the smoothing window size of the skew estimation results. The amplitude limiting step size limits the maximum correction amount in a single calibration iteration to prevent overshoot. The number of auxiliary windows configures the number of additional observation windows used to enhance robustness. The protection mode priority determines the processing order when multiple protection conditions are triggered simultaneously.

[0117] Through flexible configuration of the above parameters, this method can seamlessly switch between test modes for factory verification and functional debugging, foreground calibration modes that actively perform skew compensation during idle periods, and background operation modes that monitor and fine-tune in real time during normal data acquisition. The same hardware architecture can be adapted to multiple application scenarios without modification, significantly improving versatility and deployment flexibility.

[0118] In foreground calibration mode, the input calibration frequency is typically generated by a test signal or on-chip pilot, and the frequency information can be directly provided by the control register. In background calibration mode, the frequency information can be estimated through spectrum peak search, zero-crossing statistics, phase accumulator, or provided by the upper-layer communication system. When the input frequency cannot be accurately obtained, a protection zone indicator can also be generated based on the degradation of statistics: for example, if the denominator term decreases significantly within multiple consecutive observation windows, and the estimated value changes dramatically, the current operating point can be considered to have entered the equivalent preset frequency protection zone.

[0119] In other specific embodiments, in a 16-channel TIADC, the hierarchical calibration logic of the original algorithm can be used to set up a four-level clock skew calibration link. Each level includes statistical calculation, moving average, adaptive threshold comparison, pipelined division, RMS value preservation, and compensation execution unit.

[0120] In engineering implementation, offset error calibration and gain error calibration are performed first to reduce the impact of offset and gain mismatch on the D1, D2, D3, M1, and M2 statistics. Subsequently, each clock skew calibration module selects from the current division result, historical valid results, and auxiliary estimation results based on protection flags, and uses second-order differential filtering or an equivalent digital compensation structure to complete time skew error compensation.

[0121] Taking a 16-channel, four-level calibration as an example, the first level calibrates channel pairs spaced 8 channels apart, the second level calibrates channel pairs spaced 4 channels apart in an equivalent 8-channel structure, and the third and fourth levels further reduce the equivalent channel spacing. The calculation method for statistics at each level remains consistent with the original algorithm, but each level independently stores its effective clock offset estimate and protection flag. Therefore, even if a level enters a hold-up state at a preset frequency, it will not force other levels to stop updating, minimizing the impact on the overall calibration link.

[0122] In the Register Transfer Level (RTL) implementation, the statistics calculation module can consist of a delayed First In First Out (FIFO) queue, a squared difference multiplier, and a moving average accumulator. The denominator protection module receives the denominator term and an adaptive threshold, outputs the valid denominator, and an update enable signal. The division module can continue to use a pipelined divider. The output selection module selects between the current division result, historical valid results, and auxiliary window results based on the update enable signal. This architecture is compatible with conventional Field Programmable Gate Array (FPGA) or Application Specific Integrated Circuit (ASIC) digital back-end processes, facilitating synthesis and timing closure.

[0123] This application can also provide configurable parameters at the register level, including protection threshold, threshold safety factor, hold window length, limiting step size, number of auxiliary windows, and protection mode priority. These parameters allow the chip to switch between test mode, foreground calibration mode, and background operation mode, enabling the same hardware architecture to adapt to different application scenarios.

[0124] In some specific embodiments, after the device is powered on, offset error calibration and gain error calibration are first performed on the TIADC output data to obtain multi-channel data with better amplitude consistency. Then, the clock deviation calibration stage begins, where the system continuously acquires the output data of each channel according to the observation window and calculates the statistics required by the original algorithm.

[0125] At the end of each observation window, the preset frequency point determination module generates a protected area marker based on the folding frequency or statistical degradation status. The threshold generation module generates an adaptive threshold based on the current and historical denominator terms. The update control module integrates the protected area marker, denominator comparison results, and amplitude limit comparison results to generate a clock deviation register write enable.

[0126] If write enable is active, the current stable detection value is written to the register and used as a valid estimate for subsequent compensation. If write enable is inactive, the register retains its original value, or an auxiliary estimate is written in auxiliary window estimation mode. The compensation execution module performs digital filtering compensation on the sampled data based on the final output clock deviation estimate, or it can convert the estimate into a sampling phase control word and output it to the clock adjustment unit.

[0127] It is worth noting that this application can reuse the cumulative averaging unit, square difference statistics unit, and pipeline divider in the prior art. The newly added parts are only the threshold generation unit, comparator, update enable logic, historical effective value register, and limit selector, without requiring additional analog-to-digital converter channels or complex analog phase detection circuitry.

[0128] The method embodiments and apparatus embodiments of this application can complement each other. Regarding the apparatus in the above embodiments, the specific manner in which the processor performs operations has been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0129] A third embodiment of this application also proposes an electronic device, including a processor and a memory; the memory is used to store a computer program executable by the processor; the processor is used to execute the computer program in the memory to implement the clock skew calibration method of the analog-to-digital converter in any of the above embodiments.

[0130] like Figure 11 As shown, the electronic device 600 includes a memory 601 and a processor 602. The memory 601 is used to store computer programs executable by the processor 602; the processor 602 is used to execute the computer programs in the memory 601 to implement the clock skew calibration method for the analog-to-digital converter provided in any of the above embodiments.

[0131] The electronic device 600 also includes a communication interface 603. The processor 602, memory 601, and communication interface 603 are connected via a communication bus and communicate with each other.

[0132] The processor 602 may be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits used to control the execution of the above scheme.

[0133] Communication interface 603 is used to communicate with other devices or communication networks, such as Ethernet, Radio Access Network (RAN), and Wireless Local Area Network (WLAN).

[0134] The memory 601 may be a read-only memory (ROM) or other type of static storage device capable of storing static information and instructions, random access memory (RAM) or other type of dynamic storage device capable of storing information and instructions, or electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, optical disk storage, magnetic disk storage media or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but not limited thereto. The memory may exist independently and be connected to the processor via a bus. The memory may also be integrated with the processor.

[0135] A fourth embodiment of this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, can implement the above-described method.

[0136] A fifth embodiment of this application provides a computer program product, including a computer program that, when executed by a processor, implements the above-described method.

[0137] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "multiple" refers to two or more unless otherwise expressly defined.

[0138] The above description of the embodiments is intended to enable those skilled in the art to understand and apply this application. It will be apparent to those skilled in the art that various modifications can be easily made to these embodiments, and the general principles described herein can be applied to other embodiments without creative effort. Therefore, this application is not limited to the embodiments described herein, and any improvements and modifications made by those skilled in the art based on the disclosure of this application without departing from the scope and spirit of this application are within the scope of this application.

Claims

1. A clock skew calibration method for an analog-to-digital converter, characterized in that, The method includes: The input frequency of the time-interleaved analog-to-digital converter is obtained, and it is determined whether the input frequency is within a preset frequency protection zone based on a preset set of frequency reference points. The preset set of frequency reference points includes several discrete reference frequency points. The preset frequency protection zone includes a frequency band region centered on the reference frequency points and having a preset protection bandwidth. When the input frequency is within the preset frequency protection zone, the previous valid clock deviation estimate or the limiting estimate is used as the current clock deviation estimate; wherein, the limiting estimate is the clock deviation estimate obtained after limiting the clock deviation estimate to be output, and the limiting process ensures that the absolute value of the difference between the processed clock deviation estimate and the historical valid clock deviation estimate does not exceed the preset maximum allowable single-step change. Perform clock skew calibration on each channel based on the current clock skew estimate.

2. The clock skew calibration method as described in claim 1, characterized in that, The method also includes: Acquire the output data of each channel of the time-interleaved analog-to-digital converter; A clock deviation detection formula is constructed based on the output data of each channel. The clock deviation detection formula is used to characterize the relationship between the sampling data statistics between channels and the clock deviation. The clock deviation detection formula includes a numerator and a denominator, wherein the numerator is composed of the difference in statistics between different channels, and the denominator is composed of the relevant energy term or equivalent slope term used for normalization. When the denominator term is greater than or equal to the adaptive threshold and the input frequency is not within the preset frequency protection zone, the current clock deviation estimate is calculated according to the clock deviation detection formula; when the denominator term is less than the adaptive threshold, the previous valid clock deviation estimate or the limiting estimate is used as the current clock deviation estimate.

3. The clock skew calibration method as described in claim 1, characterized in that, Perform clock skew calibration on each channel based on the current clock skew estimate, including: Based on the current clock offset estimate, the sampling clock phase of each channel is compensated in the digital domain or adjusted in the analog domain to eliminate clock skew between channels.

4. The clock skew calibration method as described in claim 1, characterized in that, The step of acquiring the input frequency of the time-interleaved analog-to-digital converter and determining whether the input frequency is within a preset frequency protection zone based on a preset set of frequency reference points further includes: The input frequency is folded and mapped to obtain the folded frequency within the single-channel sampling bandwidth, and a preset frequency reference point set is established, which contains preset frequency reference points; a preset frequency protection zone marker is generated based on the distance between the folded frequency and the preset frequency reference points, and the preset frequency protection zone marker is used to indicate whether the input frequency is within the preset frequency protection zone.

5. The clock skew calibration method as described in claim 1, characterized in that, The preset frequency reference point set includes the 0 frequency point, f s The frequency points that are integer multiples of / (2M), the single-channel Nyquist frequency points, and the equivalent frequency points within the single-channel sampling bandwidth mapped to the above frequency points through spectral folding; where f s M represents the total sampling rate of the time-interleaved analog-to-digital converter, and M represents the number of channels of the time-interleaved analog-to-digital converter.

6. The clock skew calibration method as described in claim 2, characterized in that, The method further includes: acquiring at least one of the clock frequency, sampling rate, and number of channels of the time-interleaved analog-to-digital converter, and initializing the observation window; The adaptive threshold is determined based on at least one of the following: the moving average of the denominator term within the observation window, the variance of the denominator term, the amplitude of the input signal, the quantization noise estimate, and a preset safety factor.

7. The clock skew calibration method as described in claim 2, characterized in that, The clock deviation detection formula is: ， ， ； Wherein, ΔT is the clock bias value of the time-interleaved analog-to-digital converter, A[n] is the numerator, B[n] is the denominator, and n is the calibration cycle index; the time-interleaved analog-to-digital converter includes a first channel, a second channel, and a third channel; D1 is the output data energy statistic of the first channel; D2 is the output data energy statistic of the second channel; D3 is the output data energy statistic of the third channel; M1 is the average output data statistic of the first channel; and M2 is the average output data statistic of the second channel.

8. The clock skew calibration method as described in claim 2, characterized in that, The clock deviation detection formula is: ； Where ΔT is the clock bias value of the time-interleaved analog-to-digital converter, A[n] is the numerator, B[n] is the denominator, ε[n] is the adaptive threshold, and n is the calibration cycle index.

9. The clock skew calibration method as described in claim 2, characterized in that, When the denominator is less than the adaptive threshold or is within the preset frequency protection zone, the system enters hold mode. In hold mode, the clock deviation register outputs the most recent valid clock deviation estimate obtained when the denominator is greater than or equal to the adaptive threshold and the frequency is not within the preset frequency protection zone.

10. The clock skew calibration method as described in claim 2, characterized in that, When the denominator term is less than the adaptive threshold or is within the preset frequency protection zone, the auxiliary window estimation mode is entered. The auxiliary window estimation mode calculates the clock deviation estimate in at least two non-preset frequency observation windows adjacent to the target frequency, and performs weighted fusion according to the distance from the preset frequency, the magnitude of the relevant statistics, or the degree of spectral leakage.

11. The clock skew calibration method as described in claim 2, characterized in that, When the denominator term is less than the adaptive threshold or is within the preset frequency protection zone, the output limiting mode is entered. The output limiting mode sets the maximum change in the difference between the current clock deviation estimate and the historical valid estimate to prevent a sudden change in the compensation amount caused by a single observation window.

12. The clock skew calibration method as described in claim 2, characterized in that, The adaptive threshold It has an upper limit and a lower limit. The upper limit is used to prevent the protection zone from being too wide, which would prevent the ordinary frequency points from being updated. The lower limit is used to prevent quantization noise or jitter noise from causing the denominator protection to fail.

13. The clock skew calibration method according to claim 2, characterized in that, When the denominator term is greater than or equal to the adaptive threshold and is not within the preset frequency protection zone, the current clock deviation estimate is calculated according to the clock deviation detection formula, including: Based on the comparison result between the input frequency and the preset frequency reference point set, a preset frequency protection zone flag is generated. The preset frequency protection zone flag is used to indicate whether the input frequency is within the preset frequency protection zone. Based on the comparison result between the denominator term and the adaptive threshold, a denominator threshold comparison result flag is generated, which is used to indicate whether the denominator term is greater than or equal to the adaptive threshold. Based on the judgment result of whether the current clock deviation estimate exceeds the preset limit range, an output limiting flag is generated, which is used to indicate whether to use the limiting estimate; Logical operations are performed on the preset frequency protection zone flag, the denominator threshold comparison result flag, and the output limiting flag to generate an update enable signal. The update enable signal is used to control whether to update the clock deviation estimate. When the update enable signal is valid, the current clock deviation estimate is calculated according to the clock deviation detection formula; When the update enable signal is invalid, the previous valid clock offset estimate is retained or a limiting estimate is used.

14. The clock skew calibration method according to claim 2, characterized in that, A clock skew detection formula is constructed based on the output data of each channel, including: The observation window length is obtained, and the numerator and denominator of the clock deviation detection formula are calculated within each observation window. The clock deviation detection formula is constructed based on similar triangle relationships or Pearson correlation coefficient statistics.

15. The clock skew calibration method according to claim 2, characterized in that, Before obtaining the input frequency of the time-interleaved analog-to-digital converter, the method further includes: Offset error calibration is performed on each channel of the time-interleaved analog-to-digital converter to eliminate the DC offset component in the output of each channel and avoid the interference of the DC offset component on the denominator term; Gain error calibration is performed on each channel of the time-interleaved analog-to-digital converter to balance the conversion gain of each channel and avoid gain mismatch affecting the determination of whether the input frequency is within the preset frequency protection zone; The offset error calibration and gain error calibration are used together to eliminate the interference of static mismatch between channels on the accuracy of clock skew detection.

16. A clock skew calibration device for an analog-to-digital converter, characterized in that, For implementing the method of any one of claims 1 to 15, the apparatus comprises: The statistical calculation module is used to obtain the input frequency of the time-interleaved analog-to-digital converter and determine whether the input frequency is within a preset frequency protection zone based on a preset set of frequency reference points. The preset set of frequency reference points includes several discrete reference frequency points. The preset frequency protection zone includes a frequency band area centered on the reference frequency points and having a preset protection bandwidth. The estimation update control module is used to use the previous valid clock deviation estimate or the limiting estimate as the current clock deviation estimate when the input frequency is in the preset frequency protection zone. The compensation execution module is used to perform clock skew calibration on each channel based on the current clock deviation estimate.

17. The apparatus according to claim 16, characterized in that, The device also includes a hierarchical clock skew calibration link, which includes N cascaded clock skew calibration stages, each stage being equipped with an adaptive threshold generation module, a valid flag module, and a clock skew holding register. The adaptive threshold generation module is used to generate an adaptive threshold value according to the frequency band characteristics corresponding to the calibration level, wherein the adaptive threshold value of the N-level cascaded clock deviation calibration level increases step by step. The valid flag module is used to determine whether the clock deviation estimate of the current calibration level is valid and to generate a valid flag signal. The validity determination of the subsequent calibration level depends on the valid flag of the previous calibration level. The clock bias hold register is used to store and hold the valid clock bias estimate of the current calibration level, and is updated to the current clock bias estimate when the validity flag is valid, otherwise it holds the previous valid value. The graded clock deviation calibration link is used for time-interleaved analog-to-digital converters with M channels, where M is a positive integer greater than 2, to perform graded calibration of clock deviations in different frequency bands.

18. An electronic device, characterized in that, The system includes a memory and a processor, wherein the memory stores a computer program executable by the processor; and the processor executes the computer program in the memory to implement the method as described in any one of claims 1 to 15.

19. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the executable computer program in the storage medium is executed by a processor, it can implement the method as described in any one of claims 1 to 12.

20. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the method as described in any one of claims 1 to 15.

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