Preparation method of TOPCon cell and TOPCon cell

Abstract

The application discloses a preparation method of a TOPCon cell and the TOPCon cell. The preparation method comprises the following steps: providing a TOPCon cell process sheet, performing laser slotting treatment on a first preset fine grid line area and a second preset fine grid line area respectively, forming a first transparent conductive material in the slotting structure corresponding to the first preset fine grid line area to form a first fine grid line, forming a second transparent conductive material in the slotting structure corresponding to the second preset fine grid line area to form a second fine grid line, performing silk screen printing and sintering treatment in the first preset main grid line area to form a first main grid line, and performing silk screen printing and sintering treatment in the second preset main grid line area to form a second main grid line, thereby obtaining the TOPCon cell. The above method solves the problem that the fine grid line blocks sunlight from irradiating on the surface of the cell sheet, thereby affecting the photoelectric conversion efficiency of the TOPCon cell.

Description

Technical Field

[0001] This invention relates to the field of solar cell technology, and more particularly to a method for preparing a TOPCon cell and the TOPCon cell itself. Background Technology

[0002] TOPCon (Tunnel Oxide Passivation Contact) cells are characterized by an ultra-thin tunneling oxide layer and a doped polycrystalline silicon layer on the back side. These two layers together form the passivation contact structure. This structure not only provides effective chemical passivation using the ultra-thin tunneling oxide layer, but also achieves excellent field-effect passivation through the potential energy difference between the doped polycrystalline silicon layer and the N-type silicon substrate. Furthermore, the structure allows majority carriers to pass through the tunneling oxide layer while blocking minority carriers through band bending, effectively achieving selective carrier passage and significantly reducing minority carrier recombination, thus improving the photoelectric conversion efficiency of TOPCon cells.

[0003] For existing TOPCon cells, the main conductivity methods are either screen printing of metal pastes such as silver paste onto the cell surface to form grid electrodes, or electroplating to deposit copper or other metals onto the cell surface. However, grid electrodes are generally made of opaque metals, and the positions corresponding to the grid electrodes cannot contribute to light utilization efficiency. Both conductivity methods will affect the amount of sunlight reaching the cell surface due to the shading of the grid electrodes, thus affecting the photoelectric conversion efficiency of the TOPCon cell. Summary of the Invention

[0004] This invention provides a method for preparing a TOPCon battery and a TOPCon battery. It uses a transparent conductive material with higher light transmittance, better conductivity, and better high temperature resistance to replace the existing opaque metal printing paste or metal electroplating material, which solves the problem that the shading of fine grid lines affects the sunlight to the surface of the battery cell and thus affects the photoelectric conversion efficiency of the TOPCon battery.

[0005] In a first aspect, embodiments of the present invention provide a method for preparing a TOPCon battery, comprising:

[0006] A TOPCon battery process wafer is provided; wherein the TOPCon battery process wafer includes a first surface and a second surface that are opposite to each other, the first surface includes a first preset main grid line region and a first preset fine grid line region, and the second surface includes a second preset main grid line region and a second preset fine grid line region;

[0007] Laser grooving is performed on the first preset fine grid line region and the second preset fine grid line region respectively;

[0008] A first transparent conductive material is deposited in the slotted structure corresponding to the first preset fine grid line region to form a first fine grid line, and a second transparent conductive material is deposited in the slotted structure corresponding to the second preset fine grid line region to form a second fine grid line.

[0009] The TOPCon battery is fabricated by performing screen printing and sintering in the first preset main grid area to form a first main grid line, and by performing screen printing and sintering in the second preset main grid area to form a second main grid line.

[0010] Optionally, depositing a first transparent conductive material in the slotted structure corresponding to the first preset fine gate line region to form a first fine gate line, and depositing a second transparent conductive material in the slotted structure corresponding to the second preset fine gate line region to form a second fine gate line, includes:

[0011] The first transparent conductive material is deposited multiple times in the trench structure corresponding to the first preset fine gate line region using PECVD deposition process and multiple deposition process to form the first fine gate line; and the second transparent conductive material is deposited multiple times in the trench structure corresponding to the second preset fine gate line region to form the second fine gate line.

[0012] Optionally, depositing a first transparent conductive material in the slotted structure corresponding to the first preset fine gate line region to form a first fine gate line, and depositing a second transparent conductive material in the slotted structure corresponding to the second preset fine gate line region to form a second fine gate line, includes:

[0013] A PECVD deposition process is used to deposit a solid layer of the first transparent conductive material on the first surface, and to deposit a solid layer of the second transparent conductive material on the second surface.

[0014] Laser etching is performed on the area outside the first preset fine gate line area on the first surface, and the first transparent conductive material corresponding to the retained first preset fine gate line area is defined as the first fine gate line. Similarly, laser etching is performed on the area outside the second preset fine gate line area on the second surface, and the second transparent conductive material corresponding to the retained second preset fine gate line area is defined as the second fine gate line.

[0015] Optionally, the deposition time of the first transparent conductive material is in the range of 10-30 min, and the deposition time of the second transparent conductive material is in the range of 10-30 min.

[0016] Optionally, the deposition temperature range of the first transparent conductive material is 200-800℃, and the deposition temperature range of the second transparent conductive material is 200-800℃.

[0017] Optionally, the deposition thickness of the first transparent conductive material ranges from 5 to 6 μm, and the deposition thickness of the second transparent conductive material ranges from 5 to 6 μm.

[0018] Optionally, the first transparent conductive material includes at least one of ITO, AZO, FTO, ATO, GZO, ZnO and TiO2, and the second transparent conductive material includes at least one of ITO, AZO, FTO, ATO, GZO, ZnO and TiO2.

[0019] Optionally, TOPCon battery process chips are provided, including:

[0020] An N-type silicon substrate is provided, and a tunneling oxide layer and a polycrystalline silicon layer are sequentially formed on one side of the fourth surface of the N-type silicon substrate; wherein the N-type silicon substrate includes a third surface and the fourth surface that are opposite to each other, the third surface is the side surface of the N-type silicon substrate that is closer to the first surface, and the fourth surface is the side surface of the N-type silicon substrate that is closer to the second surface.

[0021] The third surface of the N-type silicon substrate is subjected to boron diffusion doping, and the side of the polycrystalline silicon layer away from the tunneling oxide layer is subjected to phosphorus diffusion doping.

[0022] A first passivation film is formed on the third surface, and a second passivation film is formed on the side of the polysilicon layer away from the tunneling oxide layer;

[0023] The side of the first passivation film layer away from the third surface is divided into regions to obtain the first preset main gate line region and the first preset fine gate line region. Similarly, the side of the second passivation film layer away from the polysilicon layer is divided into regions to obtain the second preset main gate line region and the second preset fine gate line region.

[0024] Optionally, the first passivation film layer includes an anti-ultraviolet attenuation film layer and a first anti-reflection layer; the second passivation film layer includes a second anti-reflection layer;

[0025] Forming a first passivation film layer on the third surface, and forming a second passivation film layer on the side of the polysilicon layer away from the tunneling oxide layer, includes:

[0026] The anti-UV attenuation film layer is formed on the third surface;

[0027] The first antireflection layer is formed on the side of the anti-UV attenuation film layer away from the third surface;

[0028] A second antireflection layer is formed on the side of the polycrystalline silicon layer away from the tunneling oxide layer.

[0029] Secondly, embodiments of the present invention also provide a TOPCon battery, which is prepared using the TOPCon battery preparation method as described in any one of the first aspects.

[0030] This invention provides a method for fabricating a TOPCon battery and the TOPCon battery itself. The method first provides a TOPCon battery process sheet. The TOPCon battery process sheet includes a first surface and a second surface that are opposite to each other. The first surface includes a first preset main grid line region and a first preset fine grid line region. The second surface includes a second preset main grid line region and a second preset fine grid line region. Then, laser grooving is performed on the first preset fine grid line region and the second preset fine grid line region, respectively. Next, a first transparent conductive material is formed in the grooving structure corresponding to the first preset fine grid line region to form the first fine grid line. Similarly, a second transparent conductive material is formed in the grooving structure corresponding to the second preset fine grid line region to form the second fine grid line. Finally, screen printing and sintering are performed in the first preset main grid line region to form the first main grid line, and screen printing and sintering are performed in the second preset main grid line region to form the second main grid line, thus obtaining the TOPCon battery. Using the above method, a transparent conductive material with higher light transmittance, better conductivity, and better high-temperature resistance is used to replace the existing opaque metal printing paste or metal electroplating material. This solves the problem that the shading of fine grid lines affects the sunlight reaching the surface of the solar cell and thus affects the photoelectric conversion efficiency of the TOPCon cell. It also reduces optical losses on the surface of the solar cell and provides a new grid line metallization preparation scheme that is compatible with existing packaging processes, thereby improving the yield and reliability of TOPCon cells. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a schematic diagram of a method for preparing a TOPCon battery according to an embodiment of the present invention;

[0033] Figure 2This is a schematic diagram of another method for preparing a TOPCon battery according to an embodiment of the present invention;

[0034] Figure 3 This is a schematic diagram of another method for preparing a TOPCon battery according to an embodiment of the present invention;

[0035] Figure 4 This is a schematic diagram of another method for preparing a TOPCon battery according to an embodiment of the present invention. Detailed Implementation

[0036] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0037] The terminology used in the embodiments of this invention is for the purpose of describing specific embodiments only and is not intended to limit the invention. It should be noted that directional terms such as "upper," "lower," "left," and "right" described in the embodiments of this invention are used to describe the angles shown in the accompanying drawings and should not be construed as limiting the embodiments of this invention. Furthermore, in the context, it should be understood that when referring to an element being formed "on" or "below" another element, it can be formed not only directly on or below the other element, but also indirectly on or below it through intermediate elements. The terms "first," "second," etc., are used for descriptive purposes only and do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0038] The term "comprising" and its variations as used in this invention are open-ended, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment".

[0039] It should be noted that the concepts of "first" and "second" mentioned in this invention are only used to distinguish the corresponding contents and are not used to limit the order or interdependence.

[0040] It should be noted that the terms "a" and "a plurality of" used in this invention are illustrative rather than restrictive. Those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0041] Figure 1This is a schematic diagram of a method for fabricating a TOPCon battery according to an embodiment of the present invention. This method is applicable to the fabrication process of TOPCon batteries and can be used to fabricate TOPCon batteries. Figure 1 As shown, the preparation method includes:

[0042] S110. Provide a TOPCon battery process sheet; wherein the TOPCon battery process sheet includes a first surface and a second surface that are opposite to each other, the first surface includes a first preset main grid line region and a first preset fine grid line region, and the second surface includes a second preset main grid line region and a second preset fine grid line region.

[0043] Specifically, compared to other types of photovoltaic solar cells, TOPCon cells have the following advantages: they employ tunneling oxide to passivate the crystalline silicon surface, achieving surface passivation and effectively reducing the surface recombination rate; and they utilize highly doped silicon thin films to achieve selective contact, thus reducing the manufacturing cost of the cell. The TOPCon cell process sheet mentioned in this embodiment can be understood as a TOPCon cell before the fabrication of the grid electrodes. This TOPCon cell process sheet has completed the dopant diffusion and film deposition steps and can be considered prior art, which will be described in detail in the following embodiments. Exemplarily, in one specific embodiment, the TOPCon cell process sheet includes an N-type silicon substrate, a tunneling oxide layer, a polycrystalline silicon layer, a first passivation film layer, and a second passivation film layer. The tunneling oxide layer and the polycrystalline silicon layer can be sequentially disposed on one side surface of the N-type silicon substrate. The second passivation film layer is disposed on the side surface of the polycrystalline silicon layer away from the tunneling oxide layer. The first passivation film layer is disposed on the side surface of the N-type silicon substrate away from the tunneling oxide layer. Furthermore, the TOPCon cell process sheet also includes a front surface field, which can be disposed between the N-type silicon substrate and the first passivation film layer. For example, the surface of the N-type silicon substrate near the first passivation layer can be textured, and the surface of the N-type silicon substrate near the second passivation layer can be polished. This embodiment will not provide further examples.

[0044] The TOPCon battery process wafer includes a first surface and a second surface that are opposite to each other. Exemplarily, the first surface can be understood as the front side of the TOPCon battery process wafer, and the second surface can be understood as the back side of the TOPCon battery process wafer. The first surface includes a first preset main grid line region and a first preset fine grid line region. The first preset main grid line region is the region subsequently used to fabricate the front-side main grid line, and the first preset fine grid line region is the region subsequently used to fabricate the front-side fine grid line. Exemplarily, the front-side fine grid line is a metal grid line on the front side of the TOPCon battery used to collect photocurrent, and the front-side main grid line is a metal wire on the front side of the TOPCon battery used to collect and conduct current. The front-side main grid line and the front-side fine grid line together constitute the current collection network of the TOPCon battery. The front-side main grid line is typically wider than the front-side fine grid line, serving to collect the photocurrent transmitted by the front-side fine grid line and guide the photocurrent into the external circuit. Exemplarily, the front-side main grid line and the front-side fine grid line can be a mutually perpendicular structure. For example, the division of the first preset main grid line region and the first preset fine grid line region in the first surface can be determined according to the fabrication needs of the TOPCon cell. The second surface includes a second preset main grid line region and a second preset fine grid line region. The second preset main grid line region is the region subsequently used to fabricate the back main grid line, and the second preset fine grid line region is the region subsequently used to fabricate the back fine grid line. For example, the back fine grid line is a metal grid line on the back of the TOPCon cell used to collect photocurrent, and the back main grid line is a metal wire on the back of the TOPCon cell used to collect and conduct current. The back main grid line and the back fine grid line together constitute the current collection network of the TOPCon cell. The back main grid line is usually wider than the back fine grid line, serving to collect the photocurrent transmitted by the back fine grid line and guide the photocurrent into the external circuit. For example, the back main grid line and the back fine grid line can be mutually perpendicular. For example, the division of the second preset main grid line region and the second preset fine grid line region in the second surface can be determined according to the fabrication needs of the TOPCon cell.

[0045] S120. Laser grooving is performed on the first preset fine grid line area and the second preset fine grid line area respectively.

[0046] Specifically, the first preset fine grid line region is the area subsequently used to fabricate the front-side fine grid lines. Laser grooving is performed on this region to facilitate the formation of relevant metal paste or metal material within the corresponding grooved structure. This facilitates the fabrication of the front-side fine grid lines. Laser technology can achieve very fine grooving structures, allowing for finer linewidths in the fabricated front-side fine grid lines. This reduces the light-blocking area of ​​the fabricated front-side fine grid lines while ensuring good conductivity. Furthermore, by rationally designing the depth of the grooving structure during the laser grooving process in the first preset fine grid line region, the metal paste or metal material formed within the grooved structure can form good contact with the interior of the TOPCon battery process sheet, reducing contact ohmic resistance and promoting the metallization of the front-side fine grid lines.

[0047] Similarly, the second preset fine grid line region is the area subsequently used to fabricate the back fine grid lines. Laser grooving is performed on this region to facilitate the formation of relevant metal paste or metal material within the corresponding grooved structure. This is beneficial for the fabrication of the back fine grid lines. Laser technology can achieve very fine grooving structures, allowing for finer linewidths in the fabricated back fine grid lines. This reduces the light-blocking area of ​​the fabricated back fine grid lines while ensuring good conductivity. Furthermore, by rationally designing the depth of the grooving structure during the laser grooving process in the second preset fine grid line region, the metal paste or metal material formed within the grooved structure can form good contact with the interior of the TOPCon cell process sheet, reducing contact ohmic resistance and facilitating the metallization of the back fine grid lines.

[0048] It should also be noted that this embodiment does not impose specific requirements or limitations on the preparation order of laser grooving processing of the first preset fine grid line region and the second preset fine grid line region. For example, the first preset fine grid line region can be laser grooved first, and then the second preset fine grid line region can be laser grooved; or the second preset fine grid line region can be laser grooved first, and then the first preset fine grid line region can be laser grooved; or the first preset fine grid line region and the second preset fine grid line region can be laser grooved simultaneously.

[0049] S130. A first transparent conductive material is deposited in the slotted structure corresponding to the first preset fine grid line region to form a first fine grid line, and a second transparent conductive material is deposited in the slotted structure corresponding to the second preset fine grid line region to form a second fine grid line.

[0050] Specifically, the first predetermined fine gate line region is the region subsequently used to fabricate the front-side fine gate line. A first transparent conductive material can be deposited in the trench structure corresponding to the first predetermined fine gate line region. The deposited first transparent conductive material can then form the desired first fine gate line, i.e., the front-side fine gate line. The first transparent conductive material is a thin film material with high transmittance, low resistivity, and good high-temperature resistance in the visible light spectrum. For example, the first transparent conductive material can be a transparent conductive oxide (TCO), and the visible light spectrum range can be 380nm-780nm. For example, atomic layer deposition (ALD), low-pressure chemical vapor deposition (LPCVD), and plasma-enhanced chemical vapor deposition (PECVD) can be used to deposit the first transparent conductive material in the trench structure corresponding to the first predetermined fine gate line region. Furthermore, by rationally designing the depth of the grooving structure during the laser grooving process of the first preset fine grid line area, the first transparent conductive material deposited in the grooving structure can be directly deposited into the interior of the TOPCon battery process sheet, forming a certain passivation effect, reducing electron recombination, and ensuring good contact between the formed first fine grid line and the interior of the TOPCon battery process sheet, reducing contact ohmic resistance, which is beneficial to the metallization of the front fine grid line.

[0051] Similarly, the second preset fine gate line region is the region subsequently used to fabricate the back fine gate line. A second transparent conductive material can be deposited in the grooved structure corresponding to the second preset fine gate line region. The deposited second transparent conductive material can then form the desired second fine gate line, i.e., the back fine gate line. The second transparent conductive material is a thin film material with high transmittance, low resistivity, and good high-temperature resistance in the visible light spectrum. For example, the second transparent conductive material can be a transparent conductive oxide (TCO), and the visible light spectrum range can be 380nm-780nm. For example, atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), and plasma enhanced chemical vapor deposition (PECVD) can be used to deposit the second transparent conductive material in the grooved structure corresponding to the second preset fine gate line region. Furthermore, by rationally designing the depth of the grooving structure during the laser grooving process of the second preset fine grid line region, the second transparent conductive material deposited in the grooving structure can be directly deposited into the interior of the TOPCon battery process sheet, forming a certain passivation effect, reducing electron recombination, and ensuring good contact between the formed second fine grid line and the interior of the TOPCon battery process sheet, reducing contact ohmic resistance, which is beneficial to the metallization of the back fine grid line.

[0052] Compared to the metal paste used in existing screen printing processes or the metal materials used in coating processes, the first fine grid lines prepared from the first transparent conductive material and the second fine grid lines prepared from the second transparent conductive material in this embodiment have good conductivity, with a conductivity range of 10. 4 -10 6The light transmittance remains above 80%, while the area of ​​the fine grid lines in a conventional TOPCon cell accounts for approximately 2%-2.2% of the surface area. After replacing the area with the first and second transparent conductive materials in this embodiment, the transmitted light energy is converted into electrical energy. Referring to the 26% photoelectric conversion efficiency of a conventional TOPCon cell, the first fine grid lines prepared with the first transparent conductive material and the second fine grid lines prepared with the second transparent conductive material can contribute 0.416% to the photoelectric conversion efficiency, increasing the overall photoelectric conversion efficiency of the TOPCon cell to 26.416%, a 1.6% increase. That is, the TOPCon cell prepared in this embodiment, including the first and second fine grid lines, can achieve the same or even higher photoelectric conversion efficiency as existing TOPCon cells, and can also effectively reduce the production cost of TOPCon cells, achieving cost reduction and efficiency improvement. Furthermore, exemplarily, the raw materials corresponding to the first and second transparent conductive materials can be the same or different; this embodiment does not impose specific requirements or limitations.

[0053] It should also be noted that this embodiment does not impose specific requirements or limitations on the order of depositing the first transparent conductive material in the slotted structure corresponding to the first preset fine grid line region and depositing the second transparent conductive material in the slotted structure corresponding to the second preset fine grid line region. For example, the first transparent conductive material can be deposited in the slotted structure corresponding to the first preset fine grid line region first, and then the second transparent conductive material can be deposited in the slotted structure corresponding to the second preset fine grid line region. Alternatively, the second transparent conductive material can be deposited in the slotted structure corresponding to the second preset fine grid line region first, and then the first transparent conductive material can be deposited in the slotted structure corresponding to the first preset fine grid line region. Alternatively, the first transparent conductive material can be deposited in the slotted structure corresponding to the first preset fine grid line region and the second transparent conductive material can be deposited in the slotted structure corresponding to the second preset fine grid line region simultaneously.

[0054] S140. Screen printing and sintering are performed in the first preset main grid area to form the first main grid line, and screen printing and sintering are performed in the second preset main grid area to form the second main grid line, thereby obtaining a TOPCon battery.

[0055] Specifically, after the first fine gate line is fabricated in the first preset fine gate line region, screen printing and sintering processes are performed in the first preset main gate line region to form the first main gate line, thereby bonding the first fine gate line with the first main gate line for subsequent packaging. Similarly, after the second fine gate line is fabricated in the second preset fine gate line region, screen printing and sintering processes are performed in the second preset main gate line region to form the second main gate line, thereby bonding the second fine gate line with the second main gate line for subsequent packaging.

[0056] Screen printing is one of the core processes in solar cell manufacturing, primarily used for electrode forming. This process utilizes the principle that the paste passes through the mesh openings of the screen in the patterned areas, while the paste does not pass through the non-patterned areas. During printing, the paste is precisely squeezed onto the TOPCon cell wafer through the mesh openings, and the paste is evenly distributed on the surface of the solar cell in the form of conductive lines, forming the desired electrode pattern. Typically, the paste used for screen printing can include, but is not limited to, silver paste. The pattern formed by screen printing includes the main grid lines. High-temperature sintering is used to process the electrode material screen-printed onto the cell surface at high temperatures, drying the paste on the TOPCon cell wafer, burning off the organic components of the paste, and allowing the paste to corrode through the passivation film layer, connecting with the PN junction. This ensures good ohmic contact between the main grid lines and the TOPCon cell wafer, achieving the purpose of collecting and discharging current. Furthermore, exemplarily, after sintering in the first preset main grid region, light injection and laser-induced sintering can be sequentially performed in the first preset main grid region. This can induce silver-silicon interdiffusion, thereby significantly reducing contact resistance, increasing the fill factor of the TOPCon cell, and effectively improving the efficiency of the front side of the TOPCon cell. Similarly, after sintering in the second preset main grid region, light injection and laser-induced sintering can be sequentially performed in the second preset main grid region. This can induce silver-silicon interdiffusion, thereby significantly reducing contact resistance, increasing the fill factor of the TOPCon cell, and effectively improving the efficiency of the back side of the TOPCon cell.

[0057] It should also be noted that this embodiment does not impose specific requirements or limitations on the preparation order of screen printing and sintering in the first preset main grid area and the second preset main grid area. For example, the screen printing and sintering process can be performed first in the first preset main grid area and then in the second preset main grid area; or the screen printing and sintering process can be performed first in the second preset main grid area and then in the first preset main grid area; or the screen printing and sintering process can be performed simultaneously in both the first and second preset main grid areas.

[0058] The technical solution in this embodiment of the invention involves a fabrication method that first provides a TOPCon battery process sheet. The TOPCon battery process sheet includes a first surface and a second surface that are mutually opposed. The first surface includes a first preset main grid line region and a first preset fine grid line region. The second surface includes a second preset main grid line region and a second preset fine grid line region. Then, laser grooving is performed on the first preset fine grid line region and the second preset fine grid line region, respectively. Next, a first transparent conductive material is formed in the grooving structure corresponding to the first preset fine grid line region to form the first fine grid line. A second transparent conductive material is formed in the grooving structure corresponding to the second preset fine grid line region to form the second fine grid line. Finally, screen printing and sintering are performed in the first preset main grid line region to form the first main grid line, and screen printing and sintering are performed in the second preset main grid line region to form the second main grid line, thus obtaining a TOPCon battery. Using the above method, a transparent conductive material with higher light transmittance, better conductivity, and better high-temperature resistance is used to replace the existing opaque metal printing paste or metal electroplating material. This solves the problem that the shading of fine grid lines affects the sunlight reaching the surface of the solar cell and thus affects the photoelectric conversion efficiency of the TOPCon cell. It also reduces optical losses on the surface of the solar cell and provides a new grid line metallization preparation scheme that is compatible with existing packaging processes, thereby improving the yield and reliability of TOPCon cells.

[0059] This embodiment describes several deposition parameters corresponding to the first and second transparent conductive materials. Optionally, the deposition time ranges for both the first and second transparent conductive materials, from 10 to 30 minutes. The deposition times for the first and second transparent conductive materials can be the same or different, and this embodiment does not impose any limitations on this. Optionally, the deposition temperature ranges for both the first and second transparent conductive materials, from 200 to 800°C. The deposition temperatures for both the first and second transparent conductive materials can be the same or different, and this embodiment does not impose any limitations on this. Optionally, the deposition thickness ranges for both the first and second transparent conductive materials, from 5 to 6 μm. The deposition thickness for both the first and second transparent conductive materials can be the same or different, and this embodiment does not impose any limitations on this.

[0060] Understandably, during the deposition of the first and second transparent conductive materials, it is necessary to control parameters such as the reaction gas flow rate ratio, reaction temperature, radio frequency power, and deposition time, and to reasonably adjust the deposition rate of the film in order to better control the specific film quality and thickness.

[0061] Optionally, the first transparent conductive material includes at least one of ITO (indium tin oxide), AZO (aluminum-doped zinc oxide), FTO (fluorine-doped tin oxide), ATO (antimony-doped tin oxide), GZO (gallium-doped zinc oxide), ZnO (zinc oxide), and TiO2 (titanium oxide), and the second transparent conductive material includes at least one of ITO (indium tin oxide), AZO (aluminum-doped zinc oxide), FTO (fluorine-doped tin oxide), ATO (antimony-doped tin oxide), GZO (gallium-doped zinc oxide), ZnO (zinc oxide), and TiO2 (titanium oxide). The types and proportions of raw materials corresponding to the first transparent conductive material and the second transparent conductive material can be the same or different, and this embodiment does not limit this.

[0062] Figure 2 This is a schematic diagram of another method for fabricating a TOPCon battery according to an embodiment of the present invention. This embodiment is an optimization based on the above embodiment. Optionally, a first transparent conductive material is deposited in the trench structure corresponding to the first preset fine grid line region to form the first fine grid line, and a second transparent conductive material is deposited in the trench structure corresponding to the second preset fine grid line region to form the second fine grid line, including:

[0063] The first transparent conductive material is deposited multiple times in the trench structure corresponding to the first preset fine gate line region using PECVD deposition process and multiple deposition process to form the first fine gate line. The second transparent conductive material is deposited multiple times in the trench structure corresponding to the second preset fine gate line region to form the second fine gate line.

[0064] For details not covered in this embodiment, please refer to the above embodiments. Figure 2 As shown, the preparation method includes:

[0065] S210. Provide a TOPCon battery process sheet; wherein the TOPCon battery process sheet includes a first surface and a second surface that are opposite to each other, the first surface includes a first preset main grid line region and a first preset fine grid line region, and the second surface includes a second preset main grid line region and a second preset fine grid line region.

[0066] S220. Laser grooving is performed on the first preset fine grid line area and the second preset fine grid line area respectively.

[0067] S230. Using PECVD deposition process and multiple deposition process, a first transparent conductive material is deposited multiple times in the slotted structure corresponding to the first preset fine gate line region to form a first fine gate line, and a second transparent conductive material is deposited multiple times in the slotted structure corresponding to the second preset fine gate line region to form a second fine gate line.

[0068] Specifically, PECVD deposition is a chemical vapor deposition technique performed in a plasma environment. It can be used to deposit a thin film of a first transparent conductive material in a trench structure corresponding to a first preset fine grid line region, and a thin film of a second transparent conductive material in a trench structure corresponding to a second preset fine grid line region. It is understood that since the thickness of both the first and second transparent conductive materials deposited in a single PECVD deposition process is limited, multiple deposition processes can be employed. That is, the first transparent conductive material film is deposited multiple times using PECVD deposition in the trench structure corresponding to the first preset fine grid line region; in other words, multiple thin films of the first transparent conductive material are deposited using PECVD deposition. Similarly, the second transparent conductive material film is deposited multiple times using PECVD deposition in the trench structure corresponding to the second preset fine grid line region; in other words, multiple thin films of the second transparent conductive material are deposited using PECVD deposition. For example, the first transparent conductive material can be deposited 2-3 times, or more than 3 times, and the second transparent conductive material can be deposited 2-3 times, or more than 3 times. The deposition time range, deposition temperature range, and deposition thickness range of the first transparent conductive material mentioned above can correspond to any one of the deposition processes, and the deposition time range, deposition temperature range, and deposition thickness range of the second transparent conductive material can correspond to any one of the deposition processes.

[0069] It should also be noted that this embodiment does not impose specific requirements or limitations on the preparation order of the PECVD multiple deposition processes corresponding to the first preset fine grid line region and the second preset fine grid line region. For example, the first transparent conductive material can be deposited multiple times in the trench structure corresponding to the first preset fine grid line region first, and then the second transparent conductive material can be deposited multiple times in the trench structure corresponding to the second preset fine grid line region. Alternatively, the second transparent conductive material can be deposited multiple times in the trench structure corresponding to the second preset fine grid line region first, and then the first transparent conductive material can be deposited multiple times in the trench structure corresponding to the first preset fine grid line region. Alternatively, the first transparent conductive material can be deposited multiple times in the trench structure corresponding to the first preset fine grid line region and the second transparent conductive material can be deposited multiple times in the trench structure corresponding to the second preset fine grid line region simultaneously.

[0070] S240, screen printing and sintering are performed in the first preset main grid area to form the first main grid line, and screen printing and sintering are performed in the second preset main grid area to form the second main grid line, thereby obtaining a TOPCon battery.

[0071] Figure 3This is a schematic diagram of a method for fabricating a TOPCon battery according to an embodiment of the present invention. This embodiment is an optimization based on the above embodiment. Optionally, a first transparent conductive material is deposited in the trench structure corresponding to the first preset fine grid line region to form the first fine grid line, and a second transparent conductive material is deposited in the trench structure corresponding to the second preset fine grid line region to form the second fine grid line, including:

[0072] A first transparent conductive material is deposited on a first surface to form an entire layer using a PECVD deposition process, and a second transparent conductive material is deposited on a second surface to form an entire layer.

[0073] Laser etching is performed on the area outside the first preset fine gate line area on the first surface, and the first transparent conductive material corresponding to the retained first preset fine gate line area is defined as the first fine gate line. On the second surface, laser etching is performed on the area outside the second preset fine gate line area, and the second transparent conductive material corresponding to the retained second preset fine gate line area is defined as the second fine gate line.

[0074] For details not covered in this embodiment, please refer to the above embodiments. Figure 3 As shown, the preparation method includes:

[0075] S310. Provide a TOPCon battery process sheet; wherein the TOPCon battery process sheet includes a first surface and a second surface that are opposite to each other, the first surface includes a first preset main grid line region and a first preset fine grid line region, and the second surface includes a second preset main grid line region and a second preset fine grid line region.

[0076] S320. Laser grooving is performed on the first preset fine grid line area and the second preset fine grid line area respectively.

[0077] S330. Using a PECVD deposition process, a first transparent conductive material is deposited on a first surface to form an integral layer, and a second transparent conductive material is deposited on a second surface to form an integral layer.

[0078] Specifically, PECVD deposition is a technique that uses chemical vapor deposition in a plasma environment to deposit a first transparent conductive material on a first surface to form an entire layer, and to deposit a second transparent conductive material on a second surface to form an entire layer.

[0079] It should also be noted that this embodiment does not impose specific requirements or limitations on the preparation order of the first transparent conductive material deposited on the first surface to form an integral layer and the second transparent conductive material deposited on the second surface to form an integral layer. For example, the first transparent conductive material can be deposited on the first surface first, and then the second transparent conductive material can be deposited on the second surface. Alternatively, the second transparent conductive material can be deposited on the second surface first, and then the first transparent conductive material can be deposited on the first surface. Or, the first transparent conductive material can be deposited on the first surface and the second transparent conductive material can be deposited on the second surface simultaneously.

[0080] S340. Laser etching is performed on the area outside the first preset fine gate line area on the first surface, and the first transparent conductive material corresponding to the retained first preset fine gate line area is defined as the first fine gate line. Laser etching is performed on the area outside the second preset fine gate line area on the second surface, and the second transparent conductive material corresponding to the retained second preset fine gate line area is defined as the second fine gate line.

[0081] Specifically, the area outside the first preset fine grid line region on the first surface can also be understood as a non-fine grid line region. In this region, picosecond laser etching can be used to avoid the excess first transparent conductive material deposited in the non-fine grid line region affecting the light entering the front of the TOPCon cell process sheet, thus reducing the photon energy received by the TOPCon cell. The picosecond laser energy needs to be determined comprehensively based on the entire layer of deposited first transparent conductive material. If the picosecond laser energy is too low, the first transparent conductive material in the non-fine grid line region will not be completely etched, affecting the light absorption of the TOPCon cell. If the picosecond laser energy is too high, it will damage the passivation layers such as the antireflection film inside the TOPCon cell, affecting the structural stability of the TOPCon cell. Similarly, the area outside the second preset fine grid line region on the second surface can also be understood as a non-fine grid line region. In this region, picosecond laser etching can be used to avoid the excess second transparent conductive material deposited in the non-fine grid line region affecting the light entering the back of the TOPCon cell process sheet, thus reducing the photon energy received by the TOPCon cell. The laser energy of the picosecond laser needs to be determined comprehensively based on the entire layer of the second transparent conductive material deposited. If the laser energy of the picosecond laser is too low, the second transparent conductive material in the non-fine grid area will not be completely etched, affecting the light absorption of the TOPCon cell. If the laser energy of the picosecond laser is too high, it will damage the passivation film layer such as the antireflection film layer inside the TOPCon cell, affecting the structural stability of the TOPCon cell.

[0082] It should also be noted that, in this embodiment, the order of laser etching processing on the areas outside the first preset fine gate line area and the areas outside the second preset fine gate line area is not specifically required or limited. For example, the areas outside the first preset fine gate line area can be laser etched on the first surface first, and then the areas outside the second preset fine gate line area can be laser etched on the second surface. Alternatively, the areas outside the second preset fine gate line area can be laser etched on the second surface first, and then the areas outside the first preset fine gate line area can be laser etched on the first surface. Alternatively, the areas outside the first preset fine gate line area can be laser etched on the first surface and the areas outside the second preset fine gate line area can be laser etched on the second surface simultaneously.

[0083] S350, screen printing and sintering are performed in the first preset main grid area to form the first main grid line, and screen printing and sintering are performed in the second preset main grid area to form the second main grid line, thereby obtaining a TOPCon battery.

[0084] Figure 4 This is a schematic diagram of another method for fabricating a TOPCon battery according to an embodiment of the present invention. This embodiment is an optimization based on the above embodiment. Optionally, a TOPCon battery process sheet is provided, including:

[0085] An N-type silicon substrate is provided, and a tunneling oxide layer and a polycrystalline silicon layer are sequentially formed on one side of the fourth surface of the N-type silicon substrate; wherein, the N-type silicon substrate includes a third surface and a fourth surface that are opposite to each other, the third surface is the side surface of the N-type silicon substrate that is closer to the first surface, and the fourth surface is the side surface of the N-type silicon substrate that is closer to the second surface.

[0086] Boron diffusion doping is performed on one side of the third surface of the N-type silicon substrate, and phosphorus diffusion doping is performed on the side of the polycrystalline silicon layer away from the tunneling oxide layer.

[0087] A first passivation film is formed on the third surface, and a second passivation film is formed on the side of the polysilicon layer away from the tunneling oxide layer.

[0088] The side of the first passivation film layer away from the third surface is divided into regions to obtain a first preset main gate line region and a first preset fine gate line region. Similarly, the side of the second passivation film layer away from the polysilicon layer is divided into regions to obtain a second preset main gate line region and a second preset fine gate line region.

[0089] For details not covered in this embodiment, please refer to the above embodiments. Figure 4 As shown, the preparation method includes:

[0090] S410. An N-type silicon substrate is provided, and a tunneling oxide layer and a polycrystalline silicon layer are sequentially formed on one side of the fourth surface of the N-type silicon substrate; wherein the N-type silicon substrate includes a third surface and a fourth surface that are opposite to each other, the third surface is the side surface of the N-type silicon substrate that is closer to the first surface, and the fourth surface is the side surface of the N-type silicon substrate that is closer to the second surface.

[0091] Specifically, an N-type silicon substrate is provided, comprising a third surface and a fourth surface that are opposite to each other. Exemplarily, the third surface can be understood as the front side of the N-type silicon substrate, and is the side surface of the N-type silicon substrate adjacent to the first surface of the TOPCon cell process wafer. The fourth surface can be understood as the back side of the N-type silicon substrate, and is the side surface of the N-type silicon substrate adjacent to the second surface of the TOPCon cell process wafer. In other words, the front side of the N-type silicon substrate is on the same side as the front side of the TOPCon cell process wafer, and the back side of the N-type silicon substrate is on the same side as the back side of the TOPCon cell process wafer. Furthermore, exemplaryly, the third surface of the N-type silicon substrate can be a textured surface, and the fourth surface of the N-type silicon substrate can be a polished surface.

[0092] Furthermore, the tunneling oxide layer and the polycrystalline silicon layer allow majority carriers (electrons) to pass smoothly through the tunneling effect while preventing the recombination of minority carriers (holes), thus achieving selective carrier collection, reducing surface recombination, increasing the open-circuit voltage and fill factor of the cell, and thereby improving the overall photoelectric conversion efficiency of the solar cell. The composite layer of the tunneling oxide layer and the polycrystalline silicon layer together forms a passivation contact structure, which can effectively reduce surface recombination and metal contact recombination of the overall solar cell. In other words, depositing an ultrathin tunneling oxide layer on the fourth surface of the N-type silicon substrate can provide good interface passivation and provide tunneling barriers for different carriers. Depositing a polycrystalline silicon layer on this tunneling oxide layer can increase the electron migration rate while suppressing the hole migration rate. In addition, the polycrystalline silicon layer contacts the subsequent metal electrode, acting as an electron transport bridge. For example, low-pressure chemical vapor deposition (LPCVD) technology can be used to first prepare an ultrathin silicon dioxide layer on the fourth surface of an N-type silicon substrate as the aforementioned tunneling oxide layer, and then deposit a polycrystalline silicon thin layer on the ultrathin silicon dioxide layer to form a polycrystalline silicon layer that satisfies the passivation effect.

[0093] S420, performing boron diffusion doping on one side of the third surface of the N-type silicon substrate, and performing phosphorus diffusion doping on the side of the polycrystalline silicon layer away from the tunneling oxide layer.

[0094] For example, the third surface of the N-type silicon substrate can be understood as the front side of the N-type silicon substrate, and the fourth surface of the N-type silicon substrate can be understood as the back side of the N-type silicon substrate. Specifically, boron diffusion doping is performed on one side of the third surface of the N-type silicon substrate to form a PN junction on the third surface of the N-type silicon substrate. The junction formation process involves generating semiconductor layers with different conductivity types on a semiconductor substrate material. Phosphorus diffusion doping is performed on the side of the polycrystalline silicon layer away from the tunneling oxide layer to form a PN junction on the third surface of the N-type silicon substrate. The junction formation process involves generating semiconductor layers with different conductivity types on a semiconductor substrate material.

[0095] S430, a first passivation film is formed on the third surface, and a second passivation film is formed on the side of the polysilicon layer away from the tunneling oxide layer.

[0096] Optionally, the first passivation film layer includes an anti-ultraviolet attenuation film layer and a first anti-reflection layer; the second passivation film layer includes a second anti-reflection layer; the first passivation film layer is formed on the third surface, and the second passivation film layer is formed on the side of the polysilicon layer away from the tunneling oxide layer, including: forming an anti-ultraviolet attenuation film layer on the third surface; forming a first anti-reflection layer on the side of the anti-ultraviolet attenuation film layer away from the third surface; and forming a second anti-reflection layer on the side of the polysilicon layer away from the tunneling oxide layer.

[0097] Specifically, passivation films can be formed on the third and fourth surfaces of the N-type silicon substrate using processes such as atomic layer deposition (ALD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), and coating. Optionally, the material for the anti-UV degradation film includes aluminum oxide. Optionally, the material for the first anti-reflection layer includes silicon nitride. Optionally, the material for the second anti-reflection layer includes silicon nitride. It is understood that the first and second passivation films possess passivation and anti-UV degradation properties, effectively preventing the entire solar cell from being affected by ultraviolet and infrared radiation, further ensuring the operational reliability of the entire solar cell.

[0098] S440. Divide the side of the first passivation film away from the third surface into a region to obtain a first preset main gate line region and a first preset fine gate line region. Also, divide the side of the second passivation film away from the polysilicon layer into a region to obtain a second preset main gate line region and a second preset fine gate line region.

[0099] Specifically, the side of the first passivation film layer away from the third surface of the N-type silicon substrate is divided into regions, that is, the first surface of the TOPCon cell process wafer is divided into regions. For example, the division of the first preset main grid line region and the first preset fine grid line region in the first surface can be determined according to the fabrication requirements of the TOPCon cell. Similarly, the side of the second passivation film layer away from the polycrystalline silicon layer is divided into regions, that is, the second surface of the TOPCon cell process wafer is divided into regions. For example, the division of the second preset main grid line region and the second preset fine grid line region in the second surface can be determined according to the fabrication requirements of the TOPCon cell.

[0100] S450, Laser grooving is performed on the first preset fine grid area and the second preset fine grid area respectively.

[0101] S460. A first transparent conductive material is deposited in the slotted structure corresponding to the first preset fine grid line region to form a first fine grid line, and a second transparent conductive material is deposited in the slotted structure corresponding to the second preset fine grid line region to form a second fine grid line.

[0102] S470. Screen printing and sintering are performed in the first preset main grid line area to form the first main grid line, and screen printing and sintering are performed in the second preset main grid line area to form the second main grid line, thereby obtaining a TOPCon battery.

[0103] Based on the same inventive concept, embodiments of the present invention also provide a TOPCon battery. This TOPCon battery is prepared using the TOPCon battery preparation method provided in any of the embodiments of the present invention. Therefore, this TOPCon battery possesses the functional modules and beneficial effects corresponding to the TOPCon battery preparation method.

[0104] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, combinations, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A method for preparing a TOPCon battery, characterized in that, include: A TOPCon battery process wafer is provided; wherein the TOPCon battery process wafer includes a first surface and a second surface that are opposite to each other, the first surface includes a first preset main grid line region and a first preset fine grid line region, and the second surface includes a second preset main grid line region and a second preset fine grid line region; Laser grooving is performed on the first preset fine grid line region and the second preset fine grid line region respectively; A first transparent conductive material is deposited in the slotted structure corresponding to the first preset fine grid line region to form a first fine grid line, and a second transparent conductive material is deposited in the slotted structure corresponding to the second preset fine grid line region to form a second fine grid line. The TOPCon battery is fabricated by performing screen printing and sintering in the first preset main grid area to form a first main grid line, and by performing screen printing and sintering in the second preset main grid area to form a second main grid line.

2. The preparation method according to claim 1, characterized in that, Depositing a first transparent conductive material in a slotted structure corresponding to the first preset fine gate line region to form a first fine gate line, and depositing a second transparent conductive material in a slotted structure corresponding to the second preset fine gate line region to form a second fine gate line, includes: The first transparent conductive material is deposited multiple times in the trench structure corresponding to the first preset fine gate line region using PECVD deposition process and multiple deposition process to form the first fine gate line; and the second transparent conductive material is deposited multiple times in the trench structure corresponding to the second preset fine gate line region to form the second fine gate line.

3. The preparation method according to claim 1, characterized in that, Depositing a first transparent conductive material in a slotted structure corresponding to the first preset fine gate line region to form a first fine gate line, and depositing a second transparent conductive material in a slotted structure corresponding to the second preset fine gate line region to form a second fine gate line, includes: A PECVD deposition process is used to deposit a solid layer of the first transparent conductive material on the first surface, and to deposit a solid layer of the second transparent conductive material on the second surface. Laser etching is performed on the area outside the first preset fine gate line area on the first surface, and the first transparent conductive material corresponding to the retained first preset fine gate line area is defined as the first fine gate line. Similarly, laser etching is performed on the area outside the second preset fine gate line area on the second surface, and the second transparent conductive material corresponding to the retained second preset fine gate line area is defined as the second fine gate line.

4. The preparation method according to claim 1, characterized in that, The deposition time range of the first transparent conductive material is 10-30 min, and the deposition time range of the second transparent conductive material is 10-30 min.

5. The preparation method according to claim 1, characterized in that, The deposition temperature range of the first transparent conductive material is 200-800℃, and the deposition temperature range of the second transparent conductive material is 200-800℃.

6. The preparation method according to claim 1, characterized in that, The deposition thickness of the first transparent conductive material ranges from 5 to 6 μm, and the deposition thickness of the second transparent conductive material ranges from 5 to 6 μm.

7. The preparation method according to claim 1, characterized in that, The first transparent conductive material includes at least one of ITO, AZO, FTO, ATO, GZO, ZnO and TiO2, and the second transparent conductive material includes at least one of ITO, AZO, FTO, ATO, GZO, ZnO and TiO2.

8. The preparation method according to claim 1, characterized in that, TOPCon battery process chips are provided, including: An N-type silicon substrate is provided, and a tunneling oxide layer and a polycrystalline silicon layer are sequentially formed on one side of the fourth surface of the N-type silicon substrate; wherein the N-type silicon substrate includes a third surface and the fourth surface that are opposite to each other, the third surface is the side surface of the N-type silicon substrate that is closer to the first surface, and the fourth surface is the side surface of the N-type silicon substrate that is closer to the second surface. The third surface of the N-type silicon substrate is subjected to boron diffusion doping, and the side of the polycrystalline silicon layer away from the tunneling oxide layer is subjected to phosphorus diffusion doping. A first passivation film is formed on the third surface, and a second passivation film is formed on the side of the polysilicon layer away from the tunneling oxide layer; The side of the first passivation film layer away from the third surface is divided into regions to obtain the first preset main gate line region and the first preset fine gate line region. Similarly, the side of the second passivation film layer away from the polysilicon layer is divided into regions to obtain the second preset main gate line region and the second preset fine gate line region.

9. The preparation method according to claim 8, characterized in that, The first passivation film layer includes an anti-ultraviolet attenuation film layer and a first anti-reflection layer; the second passivation film layer includes a second anti-reflection layer; Forming a first passivation film layer on the third surface, and forming a second passivation film layer on the side of the polysilicon layer away from the tunneling oxide layer, includes: The anti-UV attenuation film layer is formed on the third surface; The first antireflection layer is formed on the side of the anti-UV attenuation film layer away from the third surface; A second antireflection layer is formed on the side of the polycrystalline silicon layer away from the tunneling oxide layer.

10. A TOPCon battery, characterized in that, The TOPCon battery was prepared using the method described in any one of claims 1-9.

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