A preparation method of a bc battery solving the problem of front side wrap plating, the bc battery and a photovoltaic system

Abstract

The application provides a preparation method of a BC battery solving a front side wrap plating problem, a BC battery and a photovoltaic system, and relates to the technical field of photovoltaic cells. The method comprises the following steps: after polishing a silicon wafer, a first tunneling layer and a first poly layer are arranged on one side of the silicon wafer in sequence, a boron-doped passivation layer is arranged on the first poly layer, and a first laser opening mold is performed to obtain a first silicon wafer; a second tunneling layer, a second poly layer and a phosphorus-doped passivation layer are arranged on an N+ region of the first silicon wafer; a gap region is divided, a second laser opening mold is performed on the gap region by using a second laser to obtain a second silicon wafer; the second silicon wafer is subjected to rough polishing treatment and texturing treatment in sequence to obtain a third silicon wafer; an aluminum oxide layer is arranged on the surface of the third silicon wafer, and a silicon oxynitride layer is arranged on the surface of the aluminum oxide layer. The method can effectively remove the edge wrap plating layer by adding rough polishing treatment before texturing, so that the edge wrap plating layer can be effectively removed, and a normal textured surface can be prepared.

Description

Technical Field

[0001] This application relates to the field of photovoltaic cell technology, and in particular to a method for preparing a BC cell that solves the problem of front-side coating, as well as the BC cell and photovoltaic system. Background Technology

[0002] BC (Browser-Contact) cells, as representatives of all-back-electrode crystalline silicon solar cells, possess significant advantages in the photovoltaic field due to their unique front-side gridless design and back-side finger-like interlaced metal grid structure. However, existing texturing processes for BC cells face numerous technical bottlenecks. Currently, the industry commonly employs a chain-like acid etching process to treat the front side of the cell, aiming to remove the PSG layer and the edge-coated polycrystalline silicon layer, followed by a post-texturing process. While this process can achieve front-side texturing, it faces severe technical challenges in practice. First, the mixed etching solution used in the acid etching process requires extremely stringent temperature control; temperature fluctuations lead to unstable etching rates, directly affecting process repeatability and product consistency. Second, the etchant is highly volatile, causing not only material waste but also safety hazards. More seriously, the wastewater generated by this process is difficult to treat and has stringent emission standards. Failure to meet these standards will result in ineffective removal of the front-side PSG and edge-coated layers, severely impacting the appearance quality of the textured cell. These problems ultimately make it difficult for the finished cell's appearance yield to meet stringent quality inspection standards, hindering the large-scale industrial application of BC cells. There is a lack of existing technologies for BC battery preparation methods that can stably control process parameters, reduce environmental impact, and ensure product quality. Summary of the Invention

[0003] The purpose of this application is to provide a method for preparing a BC cell that solves the problem of front-side coating, as well as a BC cell and photovoltaic system, to solve the above-mentioned problem.

[0004] To achieve the above objectives, this application adopts the following technical solution: This application discloses a method for preparing a BC battery that solves the problem of front-side coating, comprising: After polishing the silicon wafer, a first tunneling layer is formed on one side. A first poly layer is formed on the first tunneling layer. Boron diffusion is performed on the first poly layer to convert a portion of it into a boron-doped passivation layer, and a BSG layer is formed on the surface of the boron-doped passivation layer. A first laser is used to perform first laser molding on the BSG layer to divide it into P+ and N+ regions. The first tunneling layer, the first poly layer, the boron-doped passivation layer, and the BSG layer on the N+ region are removed. After alkaline etching and polishing, a first silicon wafer is obtained. A second tunneling layer is formed on the N+ region of the first silicon wafer, and a second poly layer is formed on the surface of the second tunneling layer. Phosphorus diffusion is performed on the second poly layer to convert a portion of it into a phosphorus-doped passivation layer, and a PSG layer is formed on the surface of the phosphorus-doped passivation layer. A gap region is defined, and a second laser is used to perform second laser mold opening on the gap region to remove the second tunneling layer, the second poly layer, the phosphorus-doped passivation layer, and the PSG layer on the gap region, thereby obtaining a second silicon wafer. The second silicon wafer is subjected to rough polishing and texturing processes in sequence to obtain a third silicon wafer; after an aluminum oxide layer is formed on the surface of the third silicon wafer, a silicon oxynitride layer is formed on the surface of the aluminum oxide layer.

[0005] Optionally, the preparation methods of the first tunneling layer and the second tunneling layer each independently include: using LPCVD method, at a temperature of 560-600℃, and a deposition time of 10-30 min.

[0006] Optionally, the preparation methods of the first poly layer and the second poly layer each independently include: depositing an ultrathin silicon oxide layer and a stacked structure of amorphous silicon layers on the surface of a polished silicon wafer; Using LPCVD, with O2 as the reaction gas and a flow rate of 10-30 L, a silicon oxide layer with a thickness of 1-2 nm was obtained. Then, using segmented low-pressure deposition, with silane as the reaction gas and a flow rate of 100-400 sccm, an amorphous silicon layer with a thickness of 200-400 nm was obtained at a temperature of 550-600 °C.

[0007] Optionally, the method for preparing the alumina layer includes: using ALD technology, with a volume ratio of trimethylaluminum to water vapor of 1:1-3, a process temperature of 200-300℃, and a deposition time of 7-12 min.

[0008] Optionally, the method for preparing the silicon oxynitride layer includes: using PECVD (phase vapor deposition) technology, with a volume ratio of silane, ammonia, and nitrous oxide of 1:3-5:5-8, a process temperature of 480-600℃, and a deposition time of 5-8 min.

[0009] Optionally, the conditions for boron diffusion are: a volume ratio of BBr3 to BCl3 of 1:1-4, a reaction temperature of 900-1000℃, and a reaction time of 10-20 min.

[0010] Optionally, the phosphorus diffusion conditions are: a flow rate of 1000-1500 ccm of phosphorus oxychloride, a reaction temperature of 800-950℃, and a deposition time of 25-40 min.

[0011] Optionally, the conditions for the first laser mold opening are as follows: the range of the P+ region is 500-600μm, the range of the N+ region is 400-500μm, BSG mold opening is performed on the N+ region, the laser frequency of the first laser is 400-600kHz, the speed is 44000-55000mm / s, the power is 73-80W, and the spot overlap rate is 50-70%.

[0012] Optionally, the conditions for the second laser mold opening are: controlling the range of the gap area to be 100-150μm, the laser frequency of the second laser to be 400-600kHz, the speed to be 44000-55000mm / s, the power to be 73-80W, and the spot overlap rate to be 50-70%.

[0013] Optionally, the alkaline etching and polishing includes pre-cleaning, alkaline solution texturing, and acid solution treatment performed sequentially. The pre-cleaning cleaning solution includes a first alkaline reagent and H2O2, wherein the first alkaline reagent is either NaOH or KOH; the volume ratio of the first alkaline reagent to the H2O2 is 1:3-5. The polishing solution used for texturing with alkaline solution includes a second alkaline reagent and ADD, wherein the second alkaline reagent is one of NaOH and KOH; the ratio of the second alkaline reagent to the ADD is 3-5:1. The polishing solution used in the acid solution treatment is HF and HCl in a ratio of 1-3:1.

[0014] Optionally, the coarse polishing solution used in the coarse polishing process includes a third alkaline reagent and ADD, wherein the third alkaline reagent is one of NaOH and KOH; the ratio of the third alkaline reagent to the ADD is 12-15:1.

[0015] Optionally, the texturing process includes pre-cleaning, alkaline solution treatment, and acid solution treatment performed sequentially; The pre-cleaning cleaning solution includes a fourth alkaline reagent and H2O2, wherein the fourth alkaline reagent is one of NaOH and KOH; the ratio of the fourth alkaline reagent to the H2O2 is 1:3-5. The polishing solution used in the alkaline solution treatment is a fifth alkaline reagent and ADD. The fifth alkaline reagent includes one of NaOH and KOH. The ratio of the fifth alkaline reagent to ADD is 2-5:1. The polishing solution used for the acid solution treatment is HF and HCl in a volume ratio of 1:1-1.5.

[0016] Optionally, the method further includes: screen printing positive and negative electrode pastes and then sintering them to obtain the BC battery; wherein the sintering temperature is 780-900℃.

[0017] This application also provides a BC battery, which is prepared according to the method for preparing a BC battery that solves the problem of front-side plating.

[0018] Optionally, the thickness of the first tunneling layer and the second tunneling layer are each 1-3 nm.

[0019] Optionally, the thickness of the first poly layer is 300-350 nm; the thickness of the second poly layer is 200 nm-250 nm.

[0020] Optionally, the thickness of the boron-doped passivation layer is 300-350 nm.

[0021] Optionally, the thickness of the phosphorus-doped passivation layer is 200-250 nm.

[0022] Optionally, the thickness of the alumina layer is 4-6 nm.

[0023] Optionally, the thickness of the silicon oxynitride layer is 70-80 nm.

[0024] This application also provides a photovoltaic system including the BC cell.

[0025] Compared with the prior art, the beneficial effects of this application include: The preparation method provided in this application can effectively remove the edge-wrap coating by adding a rough polishing treatment before texturing. This effectively removes the edge-wrap coating to prepare an abnormal textured surface, which can strongly protect the PSG or BSG components on the back side and increase the alkali-to-polysilicon etching rate on the front side. In the rough polishing tank, the edge-wrap polysilicon is etched by a mixed solution of alkali and additives, removing the edge-wrap polysilicon and silicon oxide before entering the texturing tank. In this way, the front side can achieve a normal textured surface structure after texturing in the texturing tank. It does not require an additional chain acid etching machine, which can reduce costs and avoid the troublesome acid discharge treatment and the pollution problems caused by the discharge.

[0026] The BC battery provided in this application effectively solves the problem of abnormal front appearance caused by the instability of acid etching in traditional processes. At the same time, it avoids the formation of the coating layer through structural design, significantly improving the battery appearance yield. The synergistic effect of the alumina and silicon oxynitride layers further reduces the surface recombination rate and improves the battery conversion efficiency without relying on the high-pollution etching process. Attached Figure Description

[0027] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation on the scope of this application.

[0028] Figure 1 A schematic diagram of the BC battery provided for an embodiment; Figure 2 This is a diagram showing the effect of texturing after the preparation method provided in Example 1; Figure 3 The image shows the effect of texturing in the preparation scheme provided for Comparative Example 2.

[0029] The main marking information in the attached diagram is as follows: 11-First tunneling layer; 12-First poly layer; 13-Boron-doped passivation layer; 14-Alumina layer; 15-Silicon oxynitride layer; 21-Second tunneling layer; 22-Second poly layer; 23-Phosphorus-doped passivation layer; 24-Alumina layer; 25-Silicon oxynitride layer; 31-Alumina layer; 32-Silicon oxynitride layer. Detailed Implementation

[0030] As used in this article: "Prepared from" is synonymous with "comprising". The terms "comprising", "including", "having", "containing", or any other variations thereof as used herein are intended to cover non-exclusive inclusion. For example, a composition, step, method, article, or apparatus that includes the listed elements is not necessarily limited to those elements, but may include other elements not expressly listed or elements inherent to such composition, step, method, article, or apparatus.

[0031] The conjunction "composed of..." excludes any unspecified elements, steps, or components. If used in a claim, this phrase makes the claim closed, excluding materials other than those described, except for associated conventional impurities. When the phrase "composed of..." appears in a clause of the body of a claim rather than immediately following it, it limits only the elements described in that clause; other elements are not excluded from the claim as a whole.

[0032] When a quantity, concentration, or other value or parameter is expressed as a range, a preferred range, or a range defined by a series of upper and lower preferred values, this should be understood as specifically disclosing all ranges formed by any pair of any upper or preferred value with any lower or preferred value, regardless of whether the range is disclosed individually. For example, when the range “1–5” is disclosed, the described range should be interpreted as including ranges “1–4”, “1–3”, “1–2”, “1–2 and 4–5”, “1–3 and 5”, etc. When numerical ranges are described herein, unless otherwise stated, the range is intended to include its endpoints and all integers and fractions within that range.

[0033] In these embodiments, unless otherwise specified, the portions and percentages are all by weight.

[0034] "Parts by mass" refers to the basic unit of measurement that expresses the mass ratio of multiple components. One part can represent any unit mass, such as 1g or 2.689g. If we say that component A has "a" parts by mass and component B has "b" parts by mass, it means the ratio of the mass of component A to the mass of component B is a:b. Alternatively, it can mean that the mass of component A is aK and the mass of component B is bK (where K is any number representing a multiplier). It is important to understand that, unlike parts by mass, the sum of the mass parts of all components is not limited to 100 parts.

[0035] "And / or" is used to indicate that one or both of the described situations may occur, for example, A and / or B includes (A and B) and (A or B).

[0036] To better explain the technical solution provided in this application, the technical solution will be described in its entirety before proceeding with specific implementation methods.

[0037] In existing technologies, the fabrication process of full back electrode contact crystalline silicon solar cells typically employs a chain-like acid etching process to remove the phosphosilicate glass layer and edge coating on the front side of the cell. This process relies on the corrosive effect of a mixed acid solution, which presents challenges such as difficulty in temperature control, poor stability of the etching solution, and high volatility. Because the acid components are highly volatile and emission standards are stringent, improper handling can easily lead to fluctuations in the amount of corrosion, thereby affecting the appearance of the front side of the texturized cell and resulting in a decrease in the yield of the finished product.

[0038] To address the aforementioned issues, an alternative process to acid etching needs to be developed. This involves optimizing the doped passivation layer structure and introducing laser-based die-cutting technology to achieve precise control of the coating area. Considering the non-contact and high-precision characteristics of laser processing, its application in the area delineation stage can be explored. Simultaneously, leveraging the stability advantages of alkaline etching, the feasibility of selectively removing the coating in specific areas should be investigated.

[0039] In a first aspect, this application discloses a method for preparing a BC battery that solves the problem of front-side coating, comprising: After polishing the silicon wafer, a first tunneling layer is formed on one side. A first poly layer is formed on the first tunneling layer. Boron diffusion is performed on the first poly layer to convert a portion of it into a boron-doped passivation layer, and a BSG layer is formed on the surface of the boron-doped passivation layer. A first laser is used to perform first laser molding on the BSG layer to divide it into P+ and N+ regions. The first tunneling layer, the first poly layer, the boron-doped passivation layer, and the BSG layer on the N+ region are removed. After alkaline etching and polishing, a first silicon wafer is obtained. A second tunneling layer is formed on the N+ region of the first silicon wafer, and a second poly layer is formed on the surface of the second tunneling layer. Phosphorus diffusion is performed on the second poly layer to convert a portion of it into a phosphorus-doped passivation layer, and a PSG layer is formed on the surface of the phosphorus-doped passivation layer. A gap region is defined, and a second laser is used to perform second laser mold opening on the gap region to remove the second tunneling layer, the second poly layer, the phosphorus-doped passivation layer, and the PSG layer on the gap region, thereby obtaining a second silicon wafer. The second silicon wafer is subjected to rough polishing and texturing processes in sequence to obtain a third silicon wafer; after an aluminum oxide layer is formed on the surface of the third silicon wafer, a silicon oxynitride layer is formed on the surface of the aluminum oxide layer.

[0040] In one optional embodiment, the preparation methods of the first tunneling layer and the second tunneling layer each independently include: using LPCVD at a temperature of 560-600℃ and a deposition time of 10-30 min.

[0041] In one optional embodiment, during the preparation of the first tunneling layer and the second tunneling layer, the temperature can be 560°C, 565°C, 570°C, 575°C, 580°C, 585°C, 590°C, 595°C, 600°C, or any value between 560°C and 600°C; optionally, the deposition time can be 10 min, 12 min, 14 min, 16 min, 18 min, 20 min, 22 min, 24 min, 26 min, 28 min, 30 min, or any value between 10 min and 30 min.

[0042] In an optional embodiment, the preparation methods of the first poly layer and the second poly layer each independently include: depositing an ultrathin silicon oxide layer and a stacked structure of amorphous silicon layers on the surface of a polished silicon wafer; The LPCVD method was used, with O2 as the reaction gas and a dosage of 10-30 L, to obtain a silicon oxide layer with a thickness of 1-2 nm. Then, a segmented low-pressure deposition method was used, with silane as the reaction gas and a flow rate of 100-400 sccm, to obtain an amorphous silicon layer with a thickness of 200-400 nm at a temperature of 550-600 °C.

[0043] Optionally, the amount of O2 can be 10L, 12L, 14L, 16L, 18L, 20L, 22L, 24L, 26L, 28L, 30L, or any value between 10-30L; the thickness of the silicon oxide layer can be 1nm, 1.1nm, 1.2nm, 1.3nm, 1.4nm, 1.5nm, 1.6nm, 1.7nm, 1.8nm, 1.9nm, 2nm, or any value between 1-2nm. Optionally, the silane flow rate can be 100 sccm, 150 sccm, 200 sccm, 250 sccm, 300 sccm, 350 sccm, 400 sccm, or any value between 100 and 400 sccm; the deposition temperature can be 550℃, 560℃, 570℃, 580℃, 590℃, 600℃, or any value between 550 and 600℃; the thickness of the resulting amorphous silicon layer can be 200 nm, 220 nm, 240 nm, 260 nm, 280 nm, 300 nm, 320 nm, 340 nm, 360 nm, 380 nm, 400 nm, or any value between 200 and 400 nm.

[0044] In an optional embodiment, the method for preparing the alumina layer includes: using ALD technology, with a volume ratio of trimethylaluminum to water vapor of 1:1-3, a process temperature of 200-300℃, and a deposition time of 7-12 min.

[0045] Optionally, during the preparation of the alumina layer by the ALD method, the process temperature can be 200℃, 210℃, 220℃, 230℃, 240℃, 250℃, 260℃, 270℃, 280℃, 290℃, 300℃, or any value between 200℃ and 300℃; the deposition time can be 7 min, 8 min, 9 min, 10 min, 11 min, 12 min, or any value between 7 and 12 min.

[0046] In an optional embodiment, the method for preparing the silicon oxynitride layer includes: using PECVD (phase vapor deposition) technology, with a volume ratio of silane, ammonia, and nitrous oxide of 1:3-5:5-8, a process temperature of 480-600℃, and a deposition time of 5-8 min.

[0047] Optionally, during the preparation of the silicon oxynitride layer using the PECVD method, the process temperature can be 480℃, 490℃, 500℃, 510℃, 520℃, 530℃, 540℃, 550℃, 560℃, 570℃, 580℃, 590℃, 600℃, or any value between 480℃ and 600℃; the deposition time can be 5 min, 6 min, 7 min, 8 min, or any value between 5 and 8 min.

[0048] In one optional embodiment, the boron diffusion conditions are: a volume ratio of BBr3 to BCl3 of 1:1-4, a reaction temperature of 900-1000℃, and a reaction time of 10-20 min.

[0049] Optionally, during the boron diffusion process, the reaction temperature can be 900℃, 910℃, 920℃, 930℃, 940℃, 950℃, 960℃, 970℃, 980℃, 990℃, 1000℃, or any value between 900℃ and 1000℃; the reaction time can be 10 min, 11 min, 12 min, 13 min, 14 min, 15 min, 16 min, 17 min, 18 min, 19 min, 20 min, or any value between 10 min and 20 min.

[0050] In one optional embodiment, the phosphorus diffusion conditions are: phosphorus oxychloride with a flow rate of 1000-1500 sccm, a reaction temperature of 800-950°C, and a reaction time of 25-40 min.

[0051] Optionally, during phosphorus diffusion, the reaction temperature can be 800℃, 810℃, 820℃, 830℃, 840℃, 850℃, 860℃, 870℃, 880℃, 890℃, 900℃, 910℃, 920℃, 930℃, 940℃, 950℃, or any value between 800℃ and 950℃.

[0052] In an optional embodiment, the conditions for the first laser mold opening are as follows: the range of the P+ region is 500-600μm, the range of the N+ region is 400-500μm, BSG mold opening is performed on the N+ region, the laser frequency of the first laser is 400-600kHz, the speed is 44000-55000mm / s, the power is 73-80W, and the spot overlap rate is 50-70%.

[0053] Optionally, during the first laser mold-opening process, the range of the P+ region can be 500μm, 510μm, 520μm, 530μm, 540μm, 550μm, 560μm, 570μm, 580μm, 590μm, 600μm, or any value between 500μm and 600μm; the range of the N+ region can be 400μm, 410μm, 420μm, 430μm, 440μm, 450μm, 460μm, 470μm, 480μm, 490μm, 500μm, or any value between 400μm and 500μm. The laser frequency of the first laser can be any value between 400 kHz, 410 kHz, 420 kHz, 430 kHz, 440 kHz, 450 kHz, 460 kHz, 470 kHz, 480 kHz, 490 kHz, 500 kHz, 510 kHz, 520 kHz, 530 kHz, 540 kHz, 550 kHz, 560 kHz, 570 kHz, 580 kHz, 590 kHz, 600 kHz, or any value between 400 and 600 kHz; the scanning speed can be 44000. The speeds are 45000 mm / s, 46000 mm / s, 47000 mm / s, 48000 mm / s, 49000 mm / s, 50000 mm / s, 51000 mm / s, 52000 mm / s, 53000 mm / s, 54000 mm / s, 55000 mm / s, or any value between 44000 and 55000 mm / s; the power can be 73W, 74W, 75W, 76W, 77W, 78W, 79W, 80W, or any value between 73 and 80W; the overlap rate of the light plate can be 50%, 55%, 60%, 65%, 70%, or any value between 50 and 70%.

[0054] In an optional embodiment, the conditions for the second laser mold opening are: controlling the range of the gap area to be 100-150μm, the laser frequency of the second laser to be 400-600kHz, the speed to be 44000-55000mm / s, the power to be 73-80W, and the spot overlap rate to be 50-70%.

[0055] Optionally, during the second laser mold-opening process, the range of the gap area can be 100μm, 105μm, 110μm, 115μm, 120μm, 125μm, 130μm, 135μm, 140μm, 145μm, 150μm, or any value between 100-150μm; the laser frequency of the second laser can be 400kHz, 410kHz, 420kHz, 430kHz, or 4... 40kHz, 450kHz, 460kHz, 470kHz, 480kHz, 490kHz, 500kHz, 510kHz, 520kHz, 530kHz, 540kHz, 550kHz, 560kHz, 570kHz, 580kHz, 590kHz, 600kHz, or any value between 400 and 600kHz; the scan speed can be 44000. The speeds are 45000 mm / s, 46000 mm / s, 47000 mm / s, 48000 mm / s, 49000 mm / s, 50000 mm / s, 51000 mm / s, 52000 mm / s, 53000 mm / s, 54000 mm / s, 55000 mm / s, or any value between 44000 and 55000 mm / s; the power can be 73W, 74W, 75W, 76W, 77W, 78W, 79W, 80W, or any value between 73 and 80W; the overlap rate of the light plate can be 50%, 55%, 60%, 65%, 70%, or any value between 50 and 70%.

[0056] The P+ region refers to the heavily doped region formed by boron diffusion. Specifically, selective laser stenciling can be used to locally remove the passivation layer, thereby limiting the carrier transport path. The N+ region refers to the heavily doped region formed by phosphorus diffusion. Laser stenciling can precisely control the boundary of the conductive region. The gap region is the isolation band between the P+ and N+ regions. By controlling its width, lateral recombination of carriers can be avoided. For the second laser stenciling of the gap region, by controlling the width of the isolation band to, for example, a range of 100-150 μm, the electrode region can be effectively isolated while maximizing the retention of the effective power generation area.

[0057] In one optional embodiment, the alkaline etching and polishing includes pre-cleaning, alkaline solution texturing, and acid solution treatment performed sequentially. The pre-cleaning cleaning solution includes a first alkaline reagent and H2O2, wherein the first alkaline reagent is either NaOH or KOH; the volume ratio of the first alkaline reagent to the H2O2 is 1:3-5. The polishing solution used for texturing with alkaline solution includes a second alkaline reagent and ADD, wherein the second alkaline reagent is one of NaOH and KOH; the ratio of the second alkaline reagent to the ADD is 3-5:1. The polishing solution used in the acid solution treatment is HF and HCl in a ratio of 1-3:1.

[0058] In an optional embodiment, the coarse polishing solution used in the coarse polishing process comprises a third alkaline reagent and an ADD, wherein the third alkaline reagent is one of NaOH and KOH; and the ratio of the third alkaline reagent to the ADD is 12-15:1.

[0059] In one optional embodiment, the texturing process includes pre-washing, alkaline solution treatment, and acid solution treatment performed sequentially. The pre-cleaning cleaning solution includes a fourth alkaline reagent and H2O2, wherein the fourth alkaline reagent is one of NaOH and KOH; the ratio of the fourth alkaline reagent to the H2O2 is 1:3-5. The polishing solution used in the alkaline solution treatment is a fifth alkaline reagent and ADD. The fifth alkaline reagent includes one of NaOH and KOH. The ratio of the fifth alkaline reagent to ADD is 2-5:1. The polishing solution used for the acid solution treatment is HF and HCl in a volume ratio of 1:1-1.5.

[0060] Optionally, the volume ratio of HF to HCl can be any value between 1:1, 1:1.1, 1:1.2, 1:1.3, 1:1.4, 1:1.5, or 1:15.

[0061] Pre-cleaning refers to the process of removing impurities from the silicon wafer surface using a chemical solution, specifically a mixture of NaOH or KOH and H₂O₂. This step effectively removes surface residues and provides a clean substrate for subsequent processing. Alkaline texturing refers to the process of etching the silicon wafer surface with an alkaline solution to form a textured surface, specifically using a mixture of NaOH and the additive ADD. The additive adjusts the etching rate and texture uniformity. Acid treatment refers to the process of removing the surface oxide layer and residues using an acidic solution, specifically using a mixture of HF and HCl. This combination balances etching efficiency and surface passivation. Coarse polishing solution refers to the chemical reagents used for preliminary polishing of the silicon wafer surface, specifically a mixture of NaOH or KOH and additives. The additives enhance the selective removal capability of the polishing solution on the polycrystalline silicon layer.

[0062] Specifically, alkaline etching and polishing achieves surface cleaning and structural optimization through a phased chemical treatment. The pre-cleaning stage uses a mixture of alkaline oxidants to remove organic matter and metallic contaminants. The alkaline texturing stage forms a uniform textured surface through controlled etching. The acid treatment stage further removes the oxide layer and passivates the surface. The rough polishing process uses a specially formulated alkaline polishing slurry, which removes the coating while minimizing damage to the substrate material. The texturing process continues the phased cleaning and etching strategy, forming a textured surface with an alkaline solution followed by final surface treatment with an acid solution, ensuring both texture quality and passivation effectiveness.

[0063] Through the aforementioned technical features, this application solves the problems of unstable corrosion and high emission standards in existing acid etching processes, which lead to poor texturing appearance. The staged chemical treatment optimizes the cleaning and etching sequence, achieving efficient removal of the coating layer and control of texturing surface uniformity. The use of alkaline polishing solution reduces environmental treatment costs, ultimately improving the yield of solar cells and the reliability of the process.

[0064] In an optional embodiment, the method further includes: screen printing positive and negative electrode pastes and then sintering them to obtain the BC battery; wherein the sintering temperature is 780-900℃.

[0065] Optionally, the sintering temperature can be 780℃, 790℃, 800℃, 810℃, 820℃, 830℃, 840℃, 850℃, 860℃, 870℃, 880℃, 890℃, 900℃, or any value between 780℃ and 900℃.

[0066] Secondly, this application also provides a BC battery, which is prepared according to the method for preparing a BC battery that solves the problem of front-side plating.

[0067] In one optional implementation, the thickness of the first tunneling layer and the second tunneling layer are each independently 1-3 nm.

[0068] Optionally, the thickness of the first tunneling layer and the second tunneling layer can be 1nm, 2nm, 3nm, or any value between 1 and 3nm.

[0069] In one optional implementation, the thickness of the first poly layer is 300-350 nm; the thickness of the second poly layer is 200 nm-250 nm.

[0070] Optionally, the thickness of the first poly layer can be 300 nm, 310 nm, 320 nm, 330 nm, 340 nm, 350 nm, or any value between 300 and 350 nm. The thickness of the second first poly layer can be 200 nm, 210 nm, 220 nm, 230 nm, 240 nm, 250 nm, or any value between 200 and 250 nm.

[0071] In one optional embodiment, the thickness of the boron-doped passivation layer is 300-350 nm.

[0072] Optionally, the thickness of the boron-doped passivation layer can be 300 nm, 210 nm, 320 nm, 330 nm, 340 nm, 350 nm, or any value between 300 and 350 nm.

[0073] In one optional embodiment, the thickness of the phosphorus-doped passivation layer is 200-250 nm.

[0074] Optionally, the thickness of the phosphorus-doped passivation layer can be 200 nm, 210 nm, 220 nm, 230 nm, 240 nm, 250 nm, or any value between 200 and 250 nm.

[0075] In one alternative embodiment, the thickness of the alumina layer is 4-6 nm.

[0076] Optionally, the thickness of the alumina layer can be 4 nm, 5 nm, 6 nm, or any value between 4 and 6 nm.

[0077] In one optional embodiment, the thickness of the silicon nitride layer is 70-80 nm.

[0078] Optionally, the thickness of the silicon nitride layer can be 70 nm, 71 nm, 72 nm, 73 nm, 74 nm, 75 nm, 76 nm, 77 nm, 78 nm, 79 nm, 80 nm, or any value between 70 and 80 nm.

[0079] Thirdly, this application also provides a photovoltaic system including the BC battery.

[0080] The implementation schemes of this application will be described in detail below with reference to specific embodiments. However, those skilled in the art will understand that the following embodiments are only for illustrating this application and should not be regarded as limiting the scope of this application. Unless otherwise specified in the embodiments, conventional conditions or conditions recommended by the manufacturer shall apply. Reagents or instruments used without specified manufacturers are all conventional products that can be purchased commercially.

[0081] Example 1 This embodiment provides a method for preparing a BC battery that solves the problem of front-side coating. The specific steps are as follows: Double-sided polishing: The silicon wafers were polished on both sides using a Jiejiachuang double-sided grinding and polishing machine. The pre-cleaning tank contained a mixed solution of NaOH and H2O2, with a treatment time of 4 minutes. The volume ratio of NaOH to H2O2 in the mixed solution was 1:4. The alkaline solution polishing tank contained a 4% (w / w) NaOH solution, with a treatment time of 15 minutes. The acid solution tank contained a mixed solution of HF and HCl, with a treatment time of 5 minutes. The volume ratio of HF to HCl in the mixed solution was 1:1.5.

[0082] Preparation of the first tunneling layer 11: LPCVD deposition technology is used on the back side of the silicon wafer. In Huachuang LPCVD furnace, the deposition temperature is 565℃ and the deposition time is 30-38min to obtain the first tunneling layer.

[0083] Preparation of the first poly layer 12: The reactant is SiH4, and the deposition temperature is 560℃.

[0084] Boron diffusion: The battery was boron doped using a high-temperature tubular thermal decomposition technique with a volume ratio of BBr3 to BCl3 of 1:2, a reaction temperature of 910℃, and a reaction time of 19 min, resulting in a boron-doped passivation layer 13. A BSG layer was formed on the surface of the boron-doped layer 13.

[0085] Patterning and First Deformation: The P+ and N+ regions are defined, with each region measuring 500 μm. The N+ region is then deformed using a BSG laser at a frequency of 400 kHz, a velocity of 44000 mm / s, a power of 83 W, and a spot overlap rate of 50%. The first tunneling layer 11, the first poly layer 13, the boron-doped passivation layer 13, and the BSG layer on the N+ region are then removed.

[0086] Alkaline etching and polishing: The pre-cleaning tank contains a mixed solution of NaOH and H₂O₂, with a treatment time of 4 minutes. The volume ratio of NaOH to H₂O₂ in the mixed solution is 1:4. The alkaline polishing tank contains a mixed solution of NaOH and ADD (purchased from Xiamen Jiaxin Chuangke Management Partnership), with a NaOH to ADD ratio of 4.8:1. The treatment time in the alkaline polishing tank is 4 minutes. The acid solution tank contains HF and HCl, with a treatment time of 30 seconds. The volume ratio of HF to HCl in the mixed solution is 1:5.

[0087] Preparation of the second tunneling layer 21: LPCVD deposition technology is used on the back side of the silicon wafer. In Huachuang LPCVD furnace, the deposition temperature is 600℃ and the deposition time is 15-18min to obtain the first flint layer.

[0088] Preparation of the second poly layer 22: The reactant is SiH4, and the deposition temperature is 575℃.

[0089] Phosphorus diffusion: High-temperature tubular thermal decomposition of POCL3 was used to diffuse phosphorus into the battery. The raw material was POCL3, the amount was 14 ml, the reaction temperature was 900℃, the reaction time was 30 min, and a PSG layer was formed on the surface of the phosphorus-doped passivation layer 23.

[0090] Patterning and Second Mold Opening: A gap region with a range of 150 μm is defined. PSG laser mold opening is performed on the gap region with a laser frequency of 400 kHz, a velocity of 44000 m / s, a power of 63 W, and a spot overlap rate of 50%. The second tunneling layer 21, the second poly layer 22, the phosphorus-doped passivation layer 23, and the PSG layer on the gap region are removed.

[0091] Rough polishing: In the Jiejia Creation velvet cleaning machine, the rough polishing solution used is a mixed solution of NaOH and ADD, with a mixing ratio of NaOH to ADD of 4-6:1, and the processing time is 3 minutes.

[0092] Texturing process: In the Jiejiachuang texturing and cleaning machine, the texturing process consists of pre-cleaning, alkaline solution treatment, and acid solution treatment in sequence; The pre-cleaning tank contains a mixed solution of NaOH and H₂O₂, with a treatment time of 5 minutes. The volume ratio of NaOH to H₂O₂ in the mixed solution is 1:4-6. The alkaline solution texturing tank contains a mixed solution of NaOH and ADD (mass ratio 2-5:1), with a treatment time of 8 minutes. The acid solution tank contains a mixed solution of HF and HCl, with a treatment time of 5 minutes. The volume ratio of HF to HCl in the mixed solution is 1:1-1.5.

[0093] Preparation of alumina layer 14: An alumina layer was deposited in the Songyu atomic layer deposition system using atomic layer deposition (ALD) technology. The volume ratio of trimethylaluminum to water vapor was 1:3, the temperature was 200℃, and the deposition time was 10 min.

[0094] Preparation of silicon oxynitride layer 15: Silicon oxynitride layer was deposited using PECVD (phase vapor deposition) technology, with a volume ratio of silane, ammonia and nitrous oxide of 1:3.7:6.7, a process temperature of 600℃ and a deposition time of 8 min.

[0095] Sintering: Using silver paste as raw material, the back electrode and electric field of the battery were prepared by screen printing technology. The battery was then subjected to high-temperature sintering at 720℃ and low-temperature annealing by light injection at 540℃. This yielded a BC battery.

[0096] This embodiment also provides a BC battery, the structure of which is as follows: Figure 1 As shown, the suede surface is as follows Figure 2 As shown: The back side of the silicon wafer includes the P+ region, the N+ region, and the gap region.

[0097] In the P+ region, the following are arranged sequentially in the direction away from the silicon wafer: First tunneling layer 11: thickness is 2nm; First poly layer 12: thickness is 300nm; Boron-doped passivation layer 13: 300 nm thick; Alumina layer 14: thickness is 5.5 nm; Silicon oxynitride layer 15: 80 nm thick.

[0098] In the N+ region, the following are arranged sequentially in the direction away from the silicon wafer: Second tunneling layer 21: thickness is 2nm; The second poly layer 22 has a thickness of 200nm; Phosphorus-doped passivation layer 23: 200 nm thick; Alumina layer 14: thickness is 5.5 nm; Silicon oxynitride layer 15: 80 nm thick.

[0099] In the gap region, the following are arranged sequentially in the direction away from the silicon wafer: Alumina layer 14: thickness is 5.5 nm; Silicon oxynitride layer 15: 80 nm thick.

[0100] Example 2 This embodiment provides a method for preparing a BC battery that solves the problem of front-side coating. The specific steps are as follows: Double-sided polishing: A Jiejiachuang texturing cleaning machine is used. The pre-cleaning tank contains a mixed solution of NaOH and H2O2, with a treatment time of 4 minutes. The volume ratio of NaOH to H2O2 in the mixed solution is 1:4. The alkaline polishing tank contains a 4% (w / w) NaOH solution, with a treatment time of 15 minutes. The acid solution tank contains a mixed solution of HF and HCl, with a treatment time of 5 minutes. The volume ratio of HF to HCl in the mixed solution is 1:1.5.

[0101] Preparation of the first tunneling layer 11: LPCVD deposition technology is used on the back of the silicon wafer at a deposition temperature of 565℃, an O2 volume of 20L / min is introduced, and a deposition time of 30-38min to obtain the first flint layer.

[0102] Preparation of the first poly layer 12: The reactant is SiH4, and the deposition temperature is 560℃. Boron diffusion: The battery was boron doped using a high-temperature tubular thermal decomposition technique with a volume ratio of BBr3 to BCl3 of 1:1-4, a reaction temperature of 910℃, and a reaction time of 19 min to obtain a boron-doped passivation layer 13. A BSG layer was formed on the surface of the boron-doped layer 13.

[0103] Patterning and First Deformation: P+ and N+ regions were defined, with each region measuring 500 μm. BSG laser deformation was performed on the N+ region at a frequency of 400 kHz, a velocity of 44000 mm / s, a power of 83 W, and a spot overlap rate of 50%. The first tunneling layer, first poly layer, boron-doped passivation layer, and BSG layer on the N+ region were then removed.

[0104] Alkaline etching and polishing: The pre-cleaning tank contains a mixed solution of NaOH and H₂O₂, with a treatment time of 4 minutes. The volume ratio of NaOH to H₂O₂ in the mixed solution is 1:4. The alkaline polishing tank contains a mixed solution of NaOH and ADD, with a NaOH to ADD ratio of 5:1. The treatment time in the alkaline polishing tank is 4 minutes. The acid solution tank contains HF and HCl, with a treatment time of 30 seconds. The volume ratio of HF to HCl in the mixed solution is 1:5.

[0105] Preparation of the second tunneling layer 21: LPCVD deposition technology is used on the back of the silicon wafer at a deposition temperature of 575℃, an O2 flow rate of 20L / min, and a deposition time of 15-18min to obtain the first flint layer.

[0106] Preparation of the second poly layer 22: The reactant is SiH4, and the deposition temperature is 575℃.

[0107] Phosphorus diffusion: High-temperature tubular thermal decomposition of POCL3 was used to diffuse phosphorus into the battery. The raw material was POCL3, the amount was 14 ml, the reaction temperature was 900℃, the reaction time was 30 min, and a PSG layer was formed on the surface of the phosphorus-doped passivation layer 23.

[0108] Patterning and Second Mold Opening: A gap region with a range of 150 μm is defined. PSG laser mold opening is performed on the gap region with a laser frequency of 400 kHz, a velocity of 44000 m / s, a power of 63 W, and a spot overlap rate of 50%. The second tunneling layer, the second poly layer, the phosphorus-doped passivation layer, and the PSG layer on the gap region are removed.

[0109] Rough polishing: In the Jiejia Creation velvet cleaning machine, the rough polishing solution used is a mixed solution of NaOH and ADD, with a mixing ratio of NaOH to ADD of 5:1, and the processing time is 3 minutes.

[0110] Texturing process: In the Jiejiachuang texturing and cleaning machine, the texturing process consists of pre-cleaning, alkaline solution treatment, and acid solution treatment in sequence; The pre-cleaning tank contains a mixed solution of NaOH and H₂O₂, with a treatment time of 5 minutes. The volume ratio of NaOH to H₂O₂ in the mixed solution is 1:5. The alkaline solution texturing tank contains a mixed solution of NaOH and ADD (mass ratio 3:1), with a treatment time of 8 minutes. The acid solution tank contains a mixed solution of HF and HCl, with a treatment time of 5 minutes. The volume ratio of HF to HCl in the mixed solution is 1:1.5.

[0111] Preparation of alumina layer 14: An alumina layer was deposited in the Songyu atomic layer deposition system using atomic layer deposition (ALD) technology. The volume ratio of trimethylaluminum to water vapor was 1:1.25, the temperature was 200℃, and the deposition time was 10 min.

[0112] Preparation of silicon oxynitride layer 15: Silicon oxynitride layer was deposited in Jiejia Weichuang PECVD using vapor phase deposition technology. The volume ratio of silane, ammonia and nitrous oxide was 1:3.7:6.7. The process temperature was 600℃ and the deposition time was 8min.

[0113] Sintering: Using silver paste as raw material, the back electrode and electric field of the battery were prepared by screen printing technology. The battery was then subjected to high-temperature sintering at 720℃ and low-temperature annealing by light injection at 540℃. This yielded a BC battery.

[0114] This embodiment also provides a BC battery: The back side of the silicon wafer includes the P+ region, the N+ region, and the gap region.

[0115] In the P+ region, the following are arranged sequentially in the direction away from the silicon wafer: First tunneling layer 11: thickness is 2nm; First poly layer 12: thickness is 300nm; Boron-doped passivation layer 13: 300 nm thick; Alumina layer 14: 5nm thick; Silicon oxynitride layer 15: 80 nm thick.

[0116] In the N+ region, the following are arranged sequentially in the direction away from the silicon wafer: Second tunneling layer 21: thickness is 2nm; The second poly layer 22 has a thickness of 200nm; Phosphorus-doped passivation layer 23: 200 nm thick; Alumina layer 14: 5nm thick; Silicon oxynitride layer 15: 80 nm thick.

[0117] In the gap region, the following are arranged sequentially in the direction away from the silicon wafer: Alumina layer 14: 5nm thick; Silicon oxynitride layer 15: 80 nm thick.

[0118] Example 3 This embodiment provides a method for preparing a BC battery that solves the problem of front-side coating. The specific steps are as follows: Double-sided polishing: A Jiejiachuang texturing cleaning machine is used. The pre-cleaning tank contains a mixed solution of NaOH and H2O2, with a treatment time of 4 minutes. The volume ratio of NaOH to H2O2 in the mixed solution is 1:4. The alkaline polishing tank contains a 4% (w / w) NaOH solution, with a treatment time of 15 minutes. The acid solution tank contains a mixed solution of HF and HCl, with a treatment time of 5 minutes. The volume ratio of HF to HCl in the mixed solution is 1:1.5.

[0119] Preparation of the first tunneling layer 11: LPCVD deposition technology was used on the back of the silicon wafer. In the Huachuang equipment, the deposition temperature was 565℃, the O2 flow rate was 20L / min, and the deposition time was 35min to obtain the first flint layer.

[0120] Preparation of the first poly layer 12: The reactant is SiH4, and the deposition temperature is 560℃. Boron diffusion: The battery was boron doped using a high-temperature tubular thermal decomposition technique with a volume ratio of BBr3 to BCl3 of 1:1.5, a reaction temperature of 910℃, and a reaction time of 19 min to obtain a boron-doped passivation layer 13. A BSG layer was formed on the surface of the boron-doped layer 13.

[0121] Patterning and First Deformation: P+ and N+ regions were defined, with each region measuring 500 μm. BSG laser deformation was performed on the N+ region at a frequency of 400 kHz, a velocity of 44000 mm / s, a power of 83 W, and a spot overlap rate of 50%. The first tunneling layer, first poly layer, boron-doped passivation layer, and BSG layer on the N+ region were then removed.

[0122] Alkaline etching and polishing: The pre-cleaning tank contains a mixed solution of NaOH and H₂O₂, with a treatment time of 4 minutes. The volume ratio of NaOH to H₂O₂ in the mixed solution is 1:4. The alkaline polishing tank contains a mixed solution of NaOH and ADD (purchased from Xiamen Jiaxin Chuangke Management Partnership), with a NaOH to ADD ratio of 5:1. The treatment time in the alkaline polishing tank is 4 minutes. The acid solution tank contains HF and HCl, with a treatment time of 30 seconds. The volume ratio of HF to HCl in the mixed solution is 1:5.

[0123] Preparation of the second tunneling layer 21: LPCVD deposition technology is used on the back of the silicon wafer. In Huachuang LPCVD, the deposition temperature is 600℃, the O2 flow rate is 20L / min, and the deposition time is 15min to obtain the second flint layer.

[0124] Preparation of the second poly layer 22: The reactant is SiH4, and the deposition temperature is 575℃.

[0125] Phosphorus diffusion: High-temperature tubular thermal decomposition of POCL3 was used to diffuse phosphorus into the battery. The raw material was POCL3, the amount was 14 ml, the reaction temperature was 900℃, the reaction time was 30 min, and a PSG layer was formed on the surface of the phosphorus-doped passivation layer 23.

[0126] Patterning and Second Mold Opening: A gap region with a range of 150 μm is defined. PSG laser mold opening is performed on the gap region with a laser frequency of 400 kHz, a velocity of 44000 m / s, a power of 63 W, and a spot overlap rate of 50%. The second tunneling layer, the second poly layer, the phosphorus-doped passivation layer, and the PSG layer on the gap region are removed.

[0127] Rough polishing: In the Jiejia Creation velvet cleaning machine, the rough polishing solution used is a mixed solution of NaOH and ADD, with a mixing ratio of NaOH to ADD of 5:1, and the processing time is 3 minutes.

[0128] Texturing process: Pre-cleaning, alkaline solution treatment, and acid solution treatment are performed sequentially; The pre-cleaning tank contains a mixed solution of NaOH and H₂O₂, with a treatment time of 5 minutes. The volume ratio of NaOH to H₂O₂ in the mixed solution is 1:4. The alkaline solution texturing tank contains a mixed solution of NaOH and ADD (mass ratio 3:1), with a treatment time of 8 minutes. The acid solution tank contains a mixed solution of HF and HCl, with a treatment time of 5 minutes. The volume ratio of HF to HCl in the mixed solution is 1:1.5.

[0129] Preparation of alumina layer 14: An alumina layer was deposited in the Songyu atomic layer deposition system using atomic layer deposition (ALD) technology. The volume ratio of trimethylaluminum to water vapor was 1:1.25, the temperature was 200℃, and the deposition time was 10 min.

[0130] Preparation of silicon oxynitride layer 15: Silicon oxynitride layer was deposited in Jiejia Weichuang PECVD using vapor phase deposition technology. The volume ratio of silane, ammonia and nitrous oxide was 1:3.7:6.7. The process temperature was 600℃ and the deposition time was 8min.

[0131] Sintering: Using silver paste as raw material, the back electrode and electric field of the battery were prepared by screen printing technology. The battery was then subjected to high-temperature sintering at 720℃ and low-temperature annealing by light injection at 540℃. This yielded a BC battery.

[0132] This embodiment also provides a BC battery: The back side of the silicon wafer includes the P+ region, the N+ region, and the gap region.

[0133] In the P+ region, the following are arranged sequentially in the direction away from the silicon wafer: First tunneling layer 11: thickness is 2nm; First poly layer 12: thickness is 300nm; Boron-doped passivation layer 13: 300 nm thick; Alumina layer 14: 5nm thick; Silicon oxynitride layer 15: 80 nm thick.

[0134] In the N+ region, the following are arranged sequentially in the direction away from the silicon wafer: Second tunneling layer 21: thickness is 2nm; The second poly layer 22 has a thickness of 200nm; Phosphorus-doped passivation layer 23: 200 nm thick; Alumina layer 14: 5nm thick; Silicon oxynitride layer 15: 80 nm thick.

[0135] In the gap region, the following are arranged sequentially in the direction away from the silicon wafer: Alumina layer 14: 5nm thick; Silicon oxynitride layer 15: 80 nm thick.

[0136] Comparative Example 1 This comparative example provides a conventional chain etching technique for removing PSG and edge plating: the chain etching solution uses a mixed solution of H2SO4, HNO3, and HF in equal proportions to remove PSG and edge plating.

[0137] Comparative Example 2 This comparative example provides a method for preparing a BC battery; compared with Example 1, only the rough polishing step is omitted, while other processes remain unchanged, resulting in a textured surface. Figure 3 As shown.

[0138] This comparative example also provides a BC battery: The back side of the silicon wafer includes the P+ region, the N+ region, and the gap region.

[0139] In the P+ region, the following are arranged sequentially in the direction away from the silicon wafer: First tunneling layer: thickness 2nm; First poly layer: 300nm thick; Boron-doped passivation layer: 300 nm thick; Alumina layer: 5.5 nm thick; Silicon oxynitride layer: 80nm thick.

[0140] In the N+ region, the following are arranged sequentially in the direction away from the silicon wafer: Second tunneling layer: 2nm thick; Second poly layer: 200nm thick; Phosphorus-doped passivation layer: 200 nm thick; Alumina layer: 5.5 nm thick; Silicon oxynitride layer: 80nm thick.

[0141] In the gap region, the following are arranged sequentially in the direction away from the silicon wafer: Alumina layer: 5.5 nm thick; Silicon oxynitride layer: 80nm thick.

[0142] Comparative Example 3 This comparative example provides a method for preparing a BC battery; compared with Example 1, no ADD additive is added in the alkaline etching polishing, rough polishing, and texturing processes.

[0143] This comparative example also provides a BC battery: The back side of the silicon wafer includes the P+ region, the N+ region, and the gap region.

[0144] In the P+ region, the following are arranged sequentially in the direction away from the silicon wafer: First tunneling layer: thickness 2nm; First poly layer: 300nm thick; Boron-doped passivation layer: 300 nm thick; Alumina layer: 5.5 nm thick; Silicon oxynitride layer: 80nm thick.

[0145] In the N+ region, the following are arranged sequentially in the direction away from the silicon wafer: Second tunneling layer: 2nm thick; Second poly layer: 200nm thick; Phosphorus-doped passivation layer: 300 nm thick; Alumina layer: 5.5 nm thick; Silicon oxynitride layer: 80nm thick.

[0146] In the gap region, the following are arranged sequentially in the direction away from the silicon wafer: Alumina layer: 5.5 nm thick; Silicon oxynitride layer: 80nm thick.

[0147] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

[0148] Furthermore, those skilled in the art will understand that although some embodiments herein include certain features included in other embodiments but not others, combinations of features from different embodiments are intended to be within the scope of this application and form different embodiments. For example, in the foregoing claims, any of the claimed embodiments can be used in any combination. The information disclosed in this background section is intended only to enhance the understanding of the general background of this application and should not be construed as an admission or in any way implying that such information constitutes prior art known to those skilled in the art.

Claims

1. A method for preparing a BC battery that solves the problem of front-side coating, characterized in that, include: After polishing the silicon wafer, a first tunneling layer is formed on one side, a first poly layer is formed on the first tunneling layer, boron diffusion is performed on the first poly layer to convert a portion of it into a boron-doped passivation layer, and a BSG layer is formed on the surface of the boron-doped passivation layer. The P+ region and N+ region are divided, and the BSG layer is opened using a first laser to remove the first tunneling layer, the first poly layer, the boron-doped passivation layer and the BSG layer on the N+ region; after alkaline etching and polishing, a first silicon wafer is obtained. A second tunneling layer is formed on the N+ region of the first silicon wafer, and a second poly layer is formed on the surface of the second tunneling layer. Phosphorus diffusion is performed on the second poly layer to convert a portion of it into a phosphorus-doped passivation layer, and a PSG layer is formed on the surface of the phosphorus-doped passivation layer. A gap region is defined, and a second laser is used to perform second laser mold opening on the gap region to remove the second tunneling layer, the second poly layer, the phosphorus-doped passivation layer, and the PSG layer on the gap region, thereby obtaining a second silicon wafer. The second silicon wafer is subjected to rough polishing and texturing processes in sequence to obtain a third silicon wafer; after an aluminum oxide layer is formed on the surface of the third silicon wafer, a silicon oxynitride layer is formed on the surface of the aluminum oxide layer.

2. The method for preparing a BC battery that solves the problem of front-side coating as described in claim 1, characterized in that, At least one of the following conditions must be met: A. The preparation methods of the first tunneling layer and the second tunneling layer are each independent of each other, including: using LPCVD method, temperature of 560-600℃, and deposition time of 10-30min; B. The preparation methods of the first poly layer and the second poly layer each independently include: depositing an ultrathin silicon oxide layer and a stacked structure of amorphous silicon layers on the surface of a polished silicon wafer; Using LPCVD, with O2 as the reaction gas and a dosage of 10-30 L, a silicon oxide layer with a thickness of 1-2 nm was obtained; then, a segmented low-pressure deposition was used, with silane as the reaction gas and a flow rate of 100-400 sccm, at a temperature of 550-600 °C, to obtain an amorphous silicon layer with a thickness of 200-400 nm. C. The method for preparing the alumina layer includes: using ALD technology, with a volume ratio of trimethylaluminum to water vapor of 1:1-3, a temperature of 200-300℃, and a deposition time of 7-12 min; D. The method for preparing the silicon oxynitride layer includes: using PECVD (phase vapor deposition) technology, with a volume ratio of silane, ammonia, and nitrous oxide of 1:3-5:5-8, a process temperature of 480-600℃, and a deposition time of 5-8 min.

3. The method for preparing a BC battery that solves the problem of front-side coating as described in claim 1, characterized in that, At least one of the following conditions must be met: E. The conditions for the boron diffusion are: a volume ratio of BBr3 to BCl3 of 1:1-4, a reaction temperature of 900-1000℃, and a reaction time of 10-20 min; F. The conditions for phosphorus diffusion are: phosphorus oxychloride with a flow rate of 1000-1500 sccm, a reaction temperature of 800-950℃, and a reaction time of 25-40 min.

4. The method for preparing a BC battery that solves the problem of front-side coating as described in claim 1, characterized in that, The conditions for the first laser mold opening are as follows: the range of the P+ region is 500-600μm, the range of the N+ region is 400-500μm, the N+ region is subjected to BSG mold opening, the laser frequency of the first laser is 400-600kHz, the speed is 44000-55000mm / s, the power is 73-80W, and the spot overlap rate is 50-70%.

5. The method for preparing a BC battery that solves the problem of front-side coating according to claim 1, characterized in that, The conditions for the second laser mold opening are as follows: the range of the gap area is controlled to be 100-150μm, the laser frequency of the second laser is 400-600kHz, the speed is 44000-55000mm / s, the power is 73-80W, and the spot overlap rate is 50-70%.

6. The method for preparing a BC battery that solves the problem of front-side coating according to claim 1, characterized in that, At least one of the following conditions must be met: H. The alkaline etching and polishing process includes pre-cleaning, alkaline solution texturing, and acid solution treatment performed sequentially. The pre-cleaning cleaning solution includes a first alkaline reagent and H2O2, wherein the first alkaline reagent is either NaOH or KOH; the volume ratio of the first alkaline reagent to the H2O2 is 1:3-5. The polishing solution used for texturing with alkaline solution includes a second alkaline reagent and ADD, wherein the second alkaline reagent is one of NaOH and KOH; the ratio of the second alkaline reagent to the ADD is 3-5:

1. The polishing solution used in the acid solution treatment is HF and HCl in a ratio of 1-3:1; I. The coarse polishing solution used in the coarse polishing process comprises a third alkaline reagent and ADD, wherein the third alkaline reagent is one of NaOH and KOH; the ratio of the third alkaline reagent to the ADD is 12-15:1; J. The texturing process includes pre-cleaning, alkaline solution treatment, and acid solution treatment performed sequentially. The pre-cleaning cleaning solution includes a fourth alkaline reagent and H2O2, wherein the fourth alkaline reagent is one of NaOH and KOH; the ratio of the fourth alkaline reagent to the H2O2 is 1:3-5. The polishing solution used in the alkaline solution treatment is a fifth alkaline reagent and ADD, wherein the fifth alkaline reagent includes one of NaOH and KOH; the ratio of the fifth alkaline reagent to ADD is 2-5:

1. The polishing solution used for the acid solution treatment is HF and HCl in a volume ratio of 1:1-1.

5.

7. The method for preparing a BC battery that solves the front-side coating problem according to any one of claims 1-6, characterized in that, The method further includes: screen printing positive and negative electrode pastes and then sintering them to obtain the BC battery; wherein the sintering temperature is 780-900℃.

8. A BC battery, characterized in that, The BC battery, which solves the problem of front-side coating, is prepared according to any one of claims 1-7.

9. The BC battery according to claim 8, characterized in that, At least one of the following conditions must be met: a. The thicknesses of the first tunneling layer and the second tunneling layer are each 1-3 nm independently; b. The thickness of the first poly layer is 300-350 nm; the thickness of the second poly layer is 200 nm-250 nm; c. The thickness of the boron-doped passivation layer is 300-350 nm; d. The thickness of the phosphorus-doped passivation layer is 200-250 nm; e. The thickness of the alumina layer is 4-6 nm; f. The thickness of the silicon oxynitride layer is 70-80 nm.

10. A photovoltaic system, characterized in that, Includes the BC battery as described in any one of claims 7-9.

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