Semiconductor device and method of manufacturing the same

Abstract

Provided is a semiconductor device capable of suppressing cracking of an insulating film of a lower layer of a pad opening portion even if the semiconductor device has a two-layer metal film. A semiconductor device (100) includes: a first wiring layer (151) formed on a surface of a semiconductor substrate (110); an insulating film (133) formed on an upper layer of the first wiring layer (151) and having a thick film portion (133a) and a thin film portion (133b); a metal film (152) formed on an upper layer of the insulating film (133); a protective film (160) formed on an upper layer of the metal film (152); and a pad opening portion (180) formed in the protective film (160) so as to expose a portion of the metal film (152) and formed at a position overlapping the thick film portion (133a) in plan view.

Description

Technical Field

[0001] This invention relates to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] To exchange electrical signals with external devices, semiconductor devices use wire bonding technology to connect the semiconductor device's pads to external terminals via metal leads. Wire bonding is a mechanical process that uses heat, ultrasound, and pressure to bond leads made of materials such as gold to the semiconductor device's pads. This mechanical stress is applied to the pads and the underlying layer. Due to this mechanical stress, cracks can sometimes form in the insulating film beneath the pads. Furthermore, sometimes the semiconductor components beneath the pads are damaged, leading to a decrease in the reliability of the semiconductor device.

[0003] In order to suppress the formation of cracks in the insulating film under the pad, for example, in the invention described in Patent Document 1, a semiconductor device is described in which a first conductive pad and a second conductive pad are provided on the outer contour of the pad opening of a third conductive pad provided with a pad opening on the lower layer.

[0004] Prior technology literature [Patent Documents] [Patent Document 1] Japanese Patent Application Publication No. 11-186320. Summary of the Invention

[0005] [The problem the invention aims to solve] However, in the invention described in Patent Document 1, there is room for improvement in terms of the need to form more than three layers of metal film.

[0006] The present invention was made in view of the above circumstances. One aspect of the object of the present invention is to provide a semiconductor device that, even if it is a semiconductor device with two metal films, can suppress the generation of cracks in the insulating film of the lower layer at the pad opening.

[0007] [Solution to the problem] A semiconductor device in one embodiment of the present invention includes: The first wiring layer is formed on the surface of the semiconductor substrate; An insulating film is formed on the upper layer of the aforementioned first wiring layer and has a thick film portion and a thin film portion; A metal film is formed on top of the aforementioned insulating film; A protective film, formed on top of the aforementioned metal film; and The pad opening is formed on the aforementioned protective film in such a way that a portion of the aforementioned metal film is exposed, and is formed at a position that overlaps with the aforementioned thick film portion when viewed from above.

[0008] A method for manufacturing a semiconductor device according to one embodiment of the present invention includes: The process of forming the first wiring layer on the surface of a semiconductor substrate; A process in which an insulating film is formed on the upper layer of the aforementioned first wiring layer, a photoresist film is formed on the upper layer of the aforementioned insulating film, and the aforementioned insulating film is etched using the aforementioned photoresist film as a mask, thereby forming a thick film portion and a thin film portion. The process of forming a metal film on top of the aforementioned insulating film; The process of forming a protective film on top of the aforementioned metal film; and The process of forming a pad opening in the protective film at the location overlapping the aforementioned thick film portion when viewed from above, with a portion of the aforementioned metal film exposed.

[0009] [Invention Effects] According to one aspect of the present invention, a semiconductor device can be provided that, even if the semiconductor device has two metal layers, can suppress the formation of cracks in the insulating film of the lower layer at the pad opening. Attached Figure Description

[0010] Figure 1 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment of the present invention.

[0011] Figure 2 This is a diagram illustrating the manufacturing process of a semiconductor device according to the first embodiment of the present invention.

[0012] Figure 3 It shows the continuation Figure 2 The following is a diagram of the manufacturing process of the semiconductor device in the first embodiment of the present invention.

[0013] Figure 4 It shows the continuation Figure 3 The following is a diagram of the manufacturing process of the semiconductor device in the first embodiment of the present invention.

[0014] Figure 5 This is a schematic cross-sectional view of the semiconductor device according to the second embodiment of the present invention.

[0015] Figure 6 This is a diagram illustrating the manufacturing process of a semiconductor device according to the second embodiment of the present invention.

[0016] Figure 7 This is a schematic cross-sectional view of a semiconductor device according to a modified example 1 of the second embodiment of the present invention.

[0017] Figure 8 This is a schematic cross-sectional view of a semiconductor device according to a modified example 2 of the second embodiment of the present invention. Detailed Implementation

[0018] Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the accompanying drawings. Furthermore, in the drawings, the same reference numerals are used to denote the same components, and repeated descriptions are sometimes omitted.

[0019] Additionally, the X, Y, and Z axes shown in the attached diagram are assumed to be orthogonal to each other. The Z-axis direction is sometimes referred to as the "height direction" or "thickness direction." The +Z-axis direction is sometimes referred to as "above," and the -Z-axis direction as "below." The surface on the +Z-direction side of each component is sometimes referred to as the "surface" or "top surface," and the surface on the -Z-direction side as the "back side" or "bottom surface." "Top view" refers to observing each component from the +Z-direction side towards the -Z-direction side.

[0020] Furthermore, the accompanying drawings are schematic, and the ratios of width, depth, and thickness are not as shown. The number, position, shape, structure, and size of the components are not limited to the embodiments shown below, and can be configured to be preferred in terms of implementing the present invention.

[0021] (First Embodiment) Figure 1 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment of the present invention. Figure 1 As shown, the semiconductor device 100 in the first embodiment of the present invention includes a semiconductor substrate 110, a first wiring layer 151, an insulating film 133, a metal film 152, a protective film 160, and a pad opening 180.

[0022] A MOS transistor 120, serving as a semiconductor element, is formed at a predetermined position on the surface of the semiconductor substrate 110. An element separation insulating film 121 is formed on the surface of the semiconductor substrate 110 in a region where the MOS transistor 120 is not formed. In this embodiment, the element separation insulating film 121 is a LOCOS oxide film.

[0023] An intermediate insulating film 131 is formed on top of the MOS transistor 120 and the device separation insulating film 121. The intermediate insulating film 131 is, for example, a silicon oxide film. A first wiring layer 151 is formed at a predetermined position on top of the intermediate insulating film 131. The first wiring layer 151 is, for example, an aluminum alloy film such as Al-Cu, or a laminate of an aluminum alloy film and titanium nitride.

[0024] Contact 141 is formed at a predetermined position in the intermediate insulating film 131, and a conductive material 141w is embedded therein. The conductive material 141w is, for example, titanium, titanium nitride, tungsten, etc. The conductive material 141w may also be made of the same material as the first wiring layer 151. The MOS transistor 120 is connected to the first wiring layer 151 via the contact 141. An interlayer insulating film 132 is formed on the upper layer of the intermediate insulating film 131 and the first wiring layer 151.

[0025] An insulating film 133 is formed on top of the interlayer insulating film 132. The insulating film 133 is, for example, a silicon oxide film. The insulating film 133 has a thick film portion 133a and a thin film portion 133b. The lower surface of the thick film portion 133a and the lower surface of the thin film portion 133b are formed on the same plane. Preferably, the thickness of the thin film portion 133b is set to 100 nm to 800 nm, and the thickness of the thick film portion 133a is 500 nm to 1000 nm thicker than the thickness of the thin film portion.

[0026] The connecting hole 142 is formed at a predetermined position in the thin film portion 133b of the interlayer insulating film 132 and the insulating film 133, and a conductive material 142w is embedded therein. The conductive material 142w is, for example, titanium, titanium nitride, tungsten, etc. The conductive material 142w may also be made of the same material as the metal film 152. Here, the connecting hole 142 is formed in the thin film portion 133c, which is thinner than the thick film portion 133a, thereby making the processing of the connecting hole 142 and the conductive material 142w easier and reducing manufacturing costs.

[0027] The metal film 152, serving as the second wiring layer, is formed at a predetermined position on top of the insulating film 133. The metal film 152 may be, for example, an aluminum alloy film such as Al-Cu, or a laminate of an aluminum alloy film and titanium nitride. The thickness of the metal film 152 can be appropriately varied. The metal film 152 is connected to the first wiring layer 151 via a connection hole 142.

[0028] A protective film 160 is formed on top of the metal film 152. In this embodiment, the protective film 160 is formed by a laminate of a silicon oxide film 161 and a silicon nitride film 162.

[0029] A pad opening 180 is formed at a predetermined position within the protective film 160, exposing a portion of the surface of the metal film 152. The pad opening 180 is formed at a position overlapping the thick film portion 133a when viewed from above. This exposed portion of the surface of the metal film 152 becomes the pad 181. The pad 181 is used to mount conductive leads via wire bonding technology for electrical connection to other semiconductor devices, etc. (Not shown) Therefore, the semiconductor device 100 can thicken the insulating film 133 under the pad opening 180. Thus, even in a semiconductor device with two metal layers, cracks can be suppressed in the insulating film under the pad opening 180.

[0030] Here, refer to Figures 2 to 4 The manufacturing method of the semiconductor device 100 is also explained.

[0031] like Figure 2As shown, a device separation film 121 and a MOS transistor 120 are formed on the surface of a semiconductor substrate 110 using known techniques. Next, an intermediate insulating film 131 is formed on top of the device separation film 121 and the MOS transistor 120 using CVD, and the upper surface of the intermediate insulating film 131 is planarized using CMP. Contact portions 141 are formed at predetermined locations on the intermediate insulating film 131 using photolithography and dry etching techniques. A conductive material 141w is embedded into the contact portions 141 using sputtering, CVD, or the like.

[0032] Next, after depositing the first wiring layer 151 on top of the intermediate insulating film 131 and the contact portion 141 using sputtering, the first wiring layer 151 is formed at predetermined locations using photolithography and dry etching techniques. Subsequently, after forming an interlayer insulating film 132 on top of the intermediate insulating film 131 and the first wiring layer 151 using CVD, the upper surface of the interlayer insulating film 132 is planarized using CMP. Then, on top of the interlayer insulating film 132, an insulating film 133 is formed with a thickness of thick film portion 133a using CVD.

[0033] Next, as Figure 3 As shown, after a photoresist film 190 is formed on top of an insulating film 133 with a thickness of 133a, the photoresist film 190 on top of the thin film portion 133b forming a predetermined area is removed using photolithography. Next, the remaining photoresist film 190 on top of the insulating film 133 is used as a mask, and an etching technique is employed to form the 133a and 133b portions of the insulating film 133. Examples of etching techniques include anisotropic dry etching. Subsequently, a chemical solution or ashing technique is used to remove the photoresist film 190.

[0034] Next, as Figure 4 As shown, the connection hole 142 is formed at predetermined positions on the interlayer insulating film 132 and the thin film portion 133b using photolithography and dry etching techniques. A conductive material 142w is embedded into the connection hole 142 using methods such as sputtering and CVD. Here, the connection hole 142 is formed on the thin film portion 133b, which is thinner than the thick film portion 133a, thereby simplifying the processing of the connection hole 142 and the conductive material 142w and reducing manufacturing costs. Subsequently, after depositing a metal film 152 on the insulating film 133 and the connection hole 142 using sputtering, the metal film 152 is formed at predetermined positions using photolithography and dry etching techniques.

[0035] Next, a protective film 160 is formed by laminating a silicon oxide film 161 and a silicon nitride film 162 on top of the insulating film 133 and the metal film 152 using a CVD method. Finally, a pad opening 180 is formed at the position overlapping the thick film portion 133a when viewed from above using photolithography and dry etching techniques, thereby enabling the fabrication of the semiconductor device 100.

[0036] (Second Implementation) Figure 5 This is a schematic cross-sectional view of the semiconductor device according to the second embodiment of the present invention. Figure 5 As shown, the semiconductor device 200 in the second embodiment is the same as that in the first embodiment, except that the insulating film 233 has a thick film portion 233a, a thin film portion 233b, and an inclined portion 233c. The inclined portion 233c is formed around the thick film portion 233a when viewed from above, and its upper surface is inclined in such a way that the thickness gradually decreases from the thick film portion 233a toward the thin film portion 233b.

[0037] When viewed from above, the semiconductor device 200 has an inclined portion 233c around the thick film portion 233a, thereby achieving the effect that the metal film 152 and the protective film 160, which are higher than the insulating film 233, can effectively cover the stepped portion of the thick film portion 233a and the thin film portion 233b.

[0038] exist Figure 5 In this configuration, the insulating film 233 on the lower layer of the pad opening 180 can also be thickened. Therefore, even if the semiconductor device 200 of the second embodiment of the present invention is a semiconductor device with two metal films, it is possible to suppress the generation of cracks in the insulating film on the lower layer of the pad opening 180.

[0039] Here, refer to Figure 6 The manufacturing method of the tilted portion 233c in the semiconductor device 200 will also be described.

[0040] like Figure 6 As shown, after a photoresist film 290 is formed on top of an insulating film 233 with a thickness of 233a, the photoresist film 290 on top of the thin film portion 233b forming a predetermined area is removed using photolithography. Next, the photoresist film 290 remaining on top of the insulating film 233 is used as a mask, and etching is employed to form the thick film portion 233a, the thin film portion 233b, and the inclined portion 233c in the insulating film 233. Thereafter, the photoresist film 290 is removed using a chemical solution or ashing technique.

[0041] As etching techniques, isotropic wet etching using a chemical solution, isotropic chemical dry etching, and anisotropic dry etching can be used to form the thick film portion 233a, the thin film portion 233b, and the inclined portion 233c in the insulating film 233. Alternatively, after forming the inclined portion 233c using isotropic wet etching or chemical dry etching, the thin film portion 233b can be formed using anisotropic dry etching.

[0042] When anisotropic dry etching is used to form the inclined portion 233c, during the etching process, a sidewall protective film, which is a reaction product of the photoresist film and the etching gas, adheres to the surface of the insulating film 233 exposed by etching. By adjusting this sidewall protective film, the inclined portion 233c can be formed.

[0043] (Modification 1 of the second embodiment) Figure 7 This is a schematic cross-sectional view showing the semiconductor device in a variation of the first embodiment, Example 1. Figure 7 As shown, the semiconductor device 300 in the first embodiment variation 1 is the same as that in the second embodiment, except that the upper surface of the inclined portion 333c of the insulating film 333 is formed in an arc shape with rounded corners.

[0044] exist Figure 7 In this configuration, the insulating film 333 on the lower layer of the pad opening 180 can also be thickened. Therefore, even in a semiconductor device with two metal layers, the modified example 1 of the second embodiment of the present invention can suppress the formation of cracks in the insulating film on the lower layer of the pad opening 180.

[0045] (Modification 2 of the second embodiment) Figure 8 This is a schematic cross-sectional view showing the semiconductor device in Modified Example 2 of the second embodiment. (As shown) Figure 8 As shown, the semiconductor device 400 in the second embodiment of the modified example 2 is the same as that in the second embodiment, except that the pad opening 480 is formed such that the thick film portion 233a and the inclined portion 233c become the inside of the pad opening 480 when viewed from above.

[0046] exist Figure 8 In this configuration, the insulating film 233 under the pad opening 480 can also be thickened. Therefore, even in a semiconductor device with two metal layers, the second variation of the second embodiment of the present invention can suppress the formation of cracks in the insulating film under the pad opening 480.

[0047] The embodiments of the present invention have been described above, but the present invention is not limited to these embodiments, and also includes designs that do not depart from the spirit of the present invention.

[0048] For example, in this embodiment, the semiconductor element is a MOS transistor, but it is not limited to this and other elements may also be used. Furthermore, it is configured to use a LOCOS oxide film on the element separation film, but it may also be configured to use STI (Shallow Trench Isolation). The interlayer insulating film may also be a laminated film consisting of an insulating film covering a planarized upper surface. The protective film is a laminated film of silicon oxide and silicon nitride, but it is not limited to this and may also be made of other materials or have other laminated structures.

[0049] [Explanation of Labels in the Attached Image] 100, 200, 300, 400 semiconductor devices 110 Semiconductor substrate 120 MOS transistor (semiconductor device) 121 Component Separation Insulating Film 131 Intermediate insulating film 132 interlayer insulating film 133, 233, 333 insulating film 133a, 233a, 333a Thick Film Section 133b, 233b, 333b Thin Film Section 233c, 333c inclined section 141 Contact Department 141W conductive material 142 Connecting hole 142W conductive material 151 First wiring layer 152 Metallic film (second wiring layer) 160 protective film 161 Silicon oxide film 162 Silicon Nitride Film 180 and 480 pad openings 181 pads 190, 290 photoresist film.

Claims

1. A semiconductor device, characterized in that, have: The first wiring layer is formed on the surface of the semiconductor substrate; An insulating film is formed on the upper layer of the first wiring layer and has a thick film portion and a thin film portion; A metal film is formed on the upper layer of the insulating film; A protective film is formed on top of the metal film; as well as The pad opening is formed on the protective film in such a way that a portion of the metal film is exposed, and is formed at a position that overlaps with the thick film portion when viewed from above.

2. The semiconductor device according to claim 1, wherein, The insulating film has an inclined portion around the thick film portion when viewed from above.

3. The semiconductor device according to claim 2, wherein, The upper surface of the inclined portion is arc-shaped.

4. The semiconductor device according to claim 1, wherein, The thin film portion has a connection hole for connecting the first wiring layer to the metal film.

5. The semiconductor device according to any one of claims 1 to 4, It also includes a semiconductor element formed on the surface of the semiconductor substrate and, when viewed from above, below the opening of the pad.

6. A method for manufacturing a semiconductor device, characterized in that, include: The process of forming the first wiring layer on the surface of a semiconductor substrate; A process in which an insulating film is formed on the upper layer of the first wiring layer, a photoresist film is formed on the upper layer of the insulating film, and the insulating film is etched using the photoresist film as a mask, thereby forming a thick film portion and a thin film portion; The process of forming a metal film on the upper layer of the insulating film; The process of forming a protective film on the upper layer of the metal film; and The process of forming pad openings on the protective film at a position overlapping the thick film portion when viewed from above, with a portion of the metal film exposed.

7. The method for manufacturing a semiconductor device according to claim 6, wherein, The etching is wet etching.

8. The method for manufacturing a semiconductor device according to claim 6, wherein, The etching is a chemical dry etching.

9. The method for manufacturing a semiconductor device according to claim 6, wherein, The etching is dry etching.

10. The method of manufacturing a semiconductor device according to claim 6, wherein, The etching is performed using either the wet etching or the chemical dry etching, or the dry etching.

11. The method of manufacturing a semiconductor device according to claim 6, wherein, The process includes forming a connection hole in the thin film portion prior to the process of forming the metal film.

12. A method for manufacturing a semiconductor device according to any one of claims 6 to 11, wherein, A process is provided to form a semiconductor element on the surface of a semiconductor substrate at a position overlapping the thick film portion in a top view prior to the process of forming the insulating film.

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