Multilayer ceramic capacitor

Abstract

The present application provides a kind of LW reverse type of laminated ceramic capacitor with improved mechanical strength and can inhibit crack inside even thickness is thinned.In the laminated ceramic capacitor (1), the size (w) of the size relationship of the size (1) of the size (t) of the laminated body (10) in width direction>length direction>height direction, the length direction (L) of the length (e1) of the side surface exposed part (33) in the first lead-out part (31B) and the second lead-out part (32B) of the internal electrode layer (30) as the part exposed in the part of the first side (WS1) and the part of the second side (WS2) respectively is 10% or more and 44% or less relative to the length direction (L) of the size of the laminated body (10), and the length (e2) of the length direction (L) of the external electrode (40) is 17% or more and 48% or less relative to the length direction (L) of the size of the laminated body (10).

Description

Technical Field

[0001] This invention relates to multilayer ceramic capacitors. Background Technology

[0002] Conventionally, multilayer ceramic capacitors are known in which external electrodes are provided on a multilayer structure consisting of alternating layers of dielectric and internal electrode layers. A typical multilayer ceramic capacitor has a generally rectangular parallelepiped-shaped stack with a dimension in the length direction L longer than its dimension in the width direction W, and external electrodes are provided at both ends of the stack in the length direction L. On the other hand, so-called LW-reversed type multilayer ceramic capacitors are also known, in which the relationship between the dimensions in the length direction L and the dimensions in the width direction W of the stack is reversed in order to reduce ESL (see Patent Documents 1 and 2).

[0003] Furthermore, in recent years, with the increasing density of substrate mounting, the mounting area of ​​multilayer ceramic capacitors has gradually decreased. Therefore, the demand for multilayer ceramic capacitors mounted using a PoP (Package on Package) mounting method and in LSC (Land Side Capacitor) type at the lower end of the substrate has been increasing. As such multilayer ceramic capacitors mounted in the LSC type, a low-height, thin-thickness multilayer ceramic capacitor is required.

[0004] Prior art literature

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 2020-57753

[0007] Patent Document 2: Japanese Patent Application Publication No. 2020-61524

[0008] However, as the thickness decreases, for example to less than 150 μm, the strength of the multilayer ceramic capacitor decreases, and cracks sometimes form inside when external forces are applied. Summary of the Invention

[0009] The problem the invention aims to solve

[0010] Therefore, the object of the present invention is to provide an LW inverted type multilayer ceramic capacitor that can improve mechanical strength, thereby suppressing the formation of internal cracks even when the thickness is reduced.

[0011] Technical solutions for solving the problem

[0012] The multilayer ceramic capacitor of the present invention comprises: a multilayer body including a plurality of dielectric layers and a plurality of internal electrode layers alternately stacked in a height direction, and having a first main surface and a second main surface opposite to each other in the height direction, a first end surface and a second end surface opposite to each other in a length direction orthogonal to the height direction, and a first side surface and a second side surface opposite to each other in a width direction orthogonal to the height direction and the length direction; and a pair of external electrodes, spaced apart from each other and respectively disposed at two ends in the length direction of the multilayer body, the internal electrode layers comprising: a first internal electrode layer extending to the first end surface; and a second internal electrode layer extending to the second end surface, the external electrodes comprising: a first external electrode connected to the first internal electrode layer, disposed on the first end surface, and disposed on at least one of a portion of the first main surface and a portion of the second main surface; and a second external electrode connected to the second internal electrode layer, disposed on... On the second end face, and disposed on at least one of a portion of the first main face and a portion of the second main face, in the multilayer ceramic capacitor, the length in the length direction connecting the first end face and the second end face of the multilayer is set to 1, the length in the width direction connecting the first side face and the second side face is set to w, and the length in the height direction connecting the first main face and the second main face is set to t. At this time, the size relationship is w > l > t. The first internal electrode layer is located inside the multilayer and has: a first opposing electrode portion opposing the second internal electrode layer; and a first lead-out portion, the width dimension of which is larger than the first opposing electrode portion, and is disposed to be exposed on the first end face, a portion of the first side face, and a portion of the second side face. The second internal electrode layer is located inside the multilayer and has: a second opposing electrode portion opposing the first internal electrode layer.The second lead-out portion has a width dimension larger than the second opposing electrode portion and is configured to expose a portion of the second end face, a portion of the first side face, and a portion of the second side face. The length dimension of the exposed side portion of the first and second lead-out portions, which is the portion exposed on the portion of the first side face and the portion of the second side face respectively, is defined as e1. In this case, e1 is 10% or more and 44% or less in the length direction relative to the laminate. The length in the length direction of the first external electrode disposed on at least one of the portions of the first and second main faces, from the front end on the second end face side to the end on the first end face side, and the length in the length direction of the second external electrode disposed on at least one of the portions of the first and second main faces, from the front end on the first end face side to the end on the second end face side, is defined as e2. In this case, e2 is 17% or more and 48% or less in the length direction relative to the laminate.

[0013] Invention Effects

[0014] According to the present invention, an LW-inverted type multilayer ceramic capacitor can be provided, which can improve mechanical strength, thereby suppressing the formation of internal cracks even when the thickness is reduced. Attached Figure Description

[0015] Figure 1 This is a perspective view of the stacked ceramic capacitor according to the embodiment.

[0016] Figure 2 yes Figure 1 View in direction II.

[0017] Figure 3 yes Figure 2 View in direction III.

[0018] Figure 4 yes Figure 2 The IV direction view.

[0019] Figure 5 yes Figure 3 VV sectional view.

[0020] Figure 6 yes Figure 5 Sectional view VI-VI.

[0021] Figure 7A yes Figure 5 Sectional view VIIA-VIIA.

[0022] Figure 7B yes Figure 5Sectional view VIIB-VIIB.

[0023] Figure 8 yes Figure 3 Sectional view of VIII-VIII.

[0024] Figure 9A yes Figure 5 An enlarged view of the portion shown using IXA.

[0025] Figure 9B yes Figure 5 An enlarged view of the portion shown in IXB.

[0026] Figure 10A This is a cross-sectional view showing a modified example of the layer structure of the external electrodes of the multilayer ceramic capacitor according to the above embodiment, and is related to... Figure 9A The corresponding diagram.

[0027] Figure 10B This is a cross-sectional view showing a modified example of the layer structure of the external electrodes of the multilayer ceramic capacitor according to the above embodiment, and is related to... Figure 9B The corresponding diagram.

[0028] Figure 11 This is a diagram showing an intermediate state in the manufacturing process of the multilayer ceramic capacitor according to the above embodiment.

[0029] Figure 12 This is a diagram showing an intermediate state in the manufacturing process of the multilayer ceramic capacitor according to the above embodiment.

[0030] Figure 13 This is a diagram showing an intermediate state in the manufacturing process of the multilayer ceramic capacitor according to the above embodiment.

[0031] Figure 14 This is a perspective view showing the appearance of a multilayer ceramic capacitor with a different shape of external electrodes in a first modified example of the multilayer ceramic capacitor according to the above embodiment. Figure 1 The corresponding diagram.

[0032] Figure 15 yes Figure 14 XV-XV sectional view.

[0033] Figure 16 yes Figure 15 An enlarged view of the portion shown using XVI.

[0034] Figure 17 This is a perspective view of a second modified example of a multilayer ceramic capacitor, which uses an external electrode with a different shape than the one described in the above-described embodiment. Figure 1 The corresponding diagram.

[0035] Figure 18 This is a perspective view of a second modified example of a multilayer ceramic capacitor, which uses an external electrode with a different shape than the one described in the above-described embodiment. Figure 1 The corresponding diagram.

[0036] Figure 19 This is a diagram illustrating the method of conducting the mechanical strength test in the embodiments.

[0037] Explanation of reference numerals in the attached figures

[0038] 1: Multilayer ceramic capacitor;

[0039] 10: Layered bodies;

[0040] 11: Inner layer;

[0041] 11H: The first outermost surface of the inner layer;

[0042] 11h: The extended surface of the first outermost surface;

[0043] 11F: The second outermost surface of the inner layer;

[0044] 11f: The extended surface of the second outermost surface;

[0045] 12: Outer layer of the first main surface;

[0046] 13: Outer layer of the second main surface;

[0047] 20: Dielectric layer;

[0048] 30: Internal electrode layer;

[0049] 31: First internal electrode layer;

[0050] 31A: First opposing electrode section;

[0051] 31B: First excerpt;

[0052] 32: Second inner electrode layer;

[0053] 32A: Second opposing electrode section;

[0054] 32B: Second lead-out section;

[0055] 33: Side exposed portion;

[0056] 40: External electrode;

[0057] 40A: First external electrode;

[0058] 40B: Second external electrode;

[0059] 40A3: Third facial region (lateral covered portion);

[0060] 40A4: Fourth face (lateral covered part);

[0061] 40B3: 8th facial region (lateral covered part);

[0062] 40B4: Ninth face (lateral covered part);

[0063] 41A: The front end of the second end face of the first external electrode;

[0064] 41B: The front end of the first end face of the second external electrode;

[0065] 42A: The end face of the first external electrode;

[0066] 42B: The end face of the second external electrode;

[0067] 46: concave part;

[0068] 50A: First substrate electrode layer (substrate electrode layer);

[0069] 51A: First thin film layer (thin film layer);

[0070] 50B: Second base electrode layer (base electrode layer);

[0071] 51B: Second thin film layer (thin film layer);

[0072] 61A: First Cu plating layer 61A (inner plating layer);

[0073] 61B: Second Cu plating layer 61B (inner plating layer);

[0074] 62A: First Ni plating layer (outer plating layer);

[0075] 62B: Second Ni plating layer (outer plating layer);

[0076] 63B: Second Sn plating layer (outer plating layer);

[0077] 63A: First Sn plating layer (outer plating layer);

[0078] L: Length direction;

[0079] W: Width direction;

[0080] T: Height direction;

[0081] l: Length of the laminate in the longitudinal direction;

[0082] w: Length of the laminate in the width direction;

[0083] t: Length of the stacked body along its height direction;

[0084] LS1: First end face;

[0085] LS2: Second end face;

[0086] WS1: First side;

[0087] WS2: Second side;

[0088] TS1: 1st main surface;

[0089] TS2: The second main side. Detailed Implementation

[0090] Hereinafter, the laminated ceramic capacitor 1 according to the embodiment will be described with reference to the accompanying drawings. Figure 1 This is a perspective view of the stacked ceramic capacitor 1 according to the embodiment. Figure 2 yes Figure 1 View in direction II. Figure 3 yes Figure 2 View in direction III. Figure 4 yes Figure 2 The IV direction view. Figure 5 yes Figure 3 VV sectional view. Figure 6 yes Figure 5 Sectional view VI-VI. Figure 7A yes Figure 5 Sectional view VIIA-VIIA. Figure 7B yes Figure 5 Sectional view VIIB-VIIB. Figure 8 yes Figure 3 Sectional view of VIII-VIII. Figure 9A yes Figure 5 An enlarged view of the portion shown using IXA. Figure 9B yes Figure 5 An enlarged view of the portion shown in IXB.

[0091] like Figure 1 As shown, the multilayer ceramic capacitor 1 according to the embodiment has a generally rectangular parallelepiped shape. The multilayer ceramic capacitor 1 includes a multilayer body 10 having a generally rectangular parallelepiped shape and a pair of external electrodes 40 disposed at two ends of the multilayer body 10 spaced apart from each other.

[0092] exist Figure 1 In the diagram, arrow T indicates the height direction of the multilayer ceramic capacitor 1 and the laminate 10. This height direction T is also the thickness direction of the multilayer ceramic capacitor 1 and the laminate 10. Figure 1In the diagram, arrow L indicates the length direction of the multilayer ceramic capacitor 1 and the laminate 10, which is orthogonal to the height direction T. Figure 1 In the diagram, arrow W indicates the width direction of the multilayer ceramic capacitor 1 and the multilayer 10, which is orthogonal to the height direction T and the length direction L. A pair of external electrodes 40 are respectively disposed at one end and the other end of the multilayer 10 along the length direction L.

[0093] exist Figures 1 to 8 An XYZ orthogonal coordinate system is shown. The length direction L of the stacked ceramic capacitor 1 and the stacked body 10 corresponds to the Y direction. The width direction W of the stacked ceramic capacitor 1 and the stacked body 10 corresponds to the X direction. The height direction T of the stacked ceramic capacitor 1 and the stacked body 10 corresponds to the Z direction. Here, Figure 5 The cross-section shown is also called the LT cross-section. Figure 6 The cross-section shown is also known as the WT cross-section. Figure 7A as well as Figure 7B The cross-section shown is also called the LW cross-section. Furthermore, as will be discussed later... Figure 14 , Figure 15 , Figure 17 as well as Figure 18 The XYZ orthogonal coordinate system is also shown in the same way.

[0094] (Layered structure)

[0095] like Figures 1-6 As shown, the laminate 10 includes a first main surface TS1 and a second main surface TS2 opposite to each other in the height direction T, a first end surface LS1 and a second end surface LS2 opposite to each other in the length direction L orthogonal to the height direction T, and a first side surface WS1 and a second side surface WS2 opposite to each other in the width direction W orthogonal to the height direction T and the length direction L.

[0096] The length connecting the first main surface TS1 and the second main surface TS2 of the laminate 10 is the dimension in the height direction T of the laminate 10. Hereinafter, this dimension in the height direction T of the laminate 10 is sometimes referred to as t or dimension t. The length connecting the first end surface LS1 and the second end surface LS2 of the laminate 10 is the dimension in the length direction L of the laminate 10. Hereinafter, this dimension in the length direction L of the laminate 10 is sometimes referred to as l or dimension l. The length connecting the first side surface WS1 and the second side surface WS2 of the laminate 10 is the dimension in the width direction W of the laminate 10. Hereinafter, this dimension in the width direction W of the laminate 10 is sometimes referred to as w or dimension w.

[0097] The laminate 10 preferably has rounded corners at its corners and edges. The corners are the parts where three faces of the laminate 10 intersect, and the edges are the parts where two faces of the laminate 10 intersect. Alternatively, some or all of the surfaces constituting the laminate 10 may be formed with irregularities or protrusions.

[0098] like Figure 5 as well as Figure 6 As shown, the laminate 10 has an inner layer 11 and a first main surface side outer layer 12 and a second main surface side outer layer 13 arranged in the height direction T to sandwich the inner layer 11.

[0099] The inner layer 11 includes a plurality of dielectric layers 20 and a plurality of internal electrode layers 30 alternately stacked in the height direction T. The height direction T is the stacking direction of the plurality of dielectric layers 20 and the plurality of internal electrode layers 30, and is also the thickness direction of the stacked ceramic capacitor 1 and the stack 10.

[0100] The inner layer 11 includes an inner electrode layer 30 extending from the side closest to the first main surface TS1 to the side closest to the second main surface TS2 in the height direction T. In the inner layer 11, multiple inner electrode layers 30 are arranged opposite each other with a dielectric layer 20 in between. The inner layer 11 is the part that generates electrostatic capacitance and essentially functions as a capacitor. Furthermore, the inner layer 11 is also referred to as the effective layer.

[0101] Multiple dielectric layers 20 comprise dielectric materials. The dielectric material is, for example, a ceramic material. The dielectric material can also be a dielectric ceramic containing components such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3. When these components are the main components, secondary components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds, in smaller quantities than the main components, can be added, depending on the desired characteristics of the laminate.

[0102] The thickness of the dielectric layer 20, which is dimension t, is preferably 0.4 μm or more and 2 μm or less. The number of stacked dielectric layers 20 is preferably 10 or more and 200 or less. In addition, the number of dielectric layers 20 is the total number of dielectric layers in the inner layer 11 and the number of dielectric layers in the outer layer 12 on the first main surface side and the outer layer 13 on the second main surface side.

[0103] The plurality of internal electrode layers 30 includes a plurality of first internal electrode layers 31 and a plurality of second internal electrode layers 32. The first internal electrode layers 31 and second internal electrode layers 32 are arranged alternately in the height direction T, with a dielectric layer 20 sandwiched between them. The first internal electrode layers 31 extend to a first end face LS1. The second internal electrode layers 32 extend to a second end face LS2. In addition, hereafter, without distinguishing between the first internal electrode layers 31 and the second internal electrode layers 32, the first internal electrode layers 31 and the second internal electrode layers 32 are sometimes collectively referred to as internal electrode layers 30.

[0104] like Figure 7AAs shown, the first internal electrode layer 31 has a first opposing electrode portion 31A and a first lead-out portion 31B. The first opposing electrode portion 31A is located inside the laminate 10, in a region that faces the second internal electrode layer 32 while the dielectric layer 20 is sandwiched in the middle. The first lead-out portion 31B is a portion that extends from the first opposing electrode portion 31A to a first end face LS1, a portion of the first side face WS1, and a portion of the second side face WS2. The first lead-out portion 31B is connected to the first opposing electrode portion 31A and is exposed on the first end face LS1, a portion of the first side face WS1, and a portion of the second side face WS2.

[0105] like Figure 7B As shown, the second internal electrode layer 32 has a second opposing electrode portion 32A and a second lead-out portion 32B. The second opposing electrode portion 32A is located inside the laminate 10, opposite the first internal electrode layer 31 and sandwiched between dielectric layers 20. The second lead-out portion 32B extends from the second opposing electrode portion 32A to a portion of the second end face LS2, a portion of the first side face WS1, and a portion of the second side face WS2. The second lead-out portion 32B is connected to the second opposing electrode portion 32A and is exposed on the second end face LS2, a portion of the first side face WS1, and a portion of the second side face WS2.

[0106] Figure 8 yes Figure 3 The cross-sectional view along line XIII-XIII of the multilayer ceramic capacitor 1 shown illustrates the first side WS1 of the multilayer 10. Additionally, in... Figure 7A as well as Figure 7B The text also shows the representation. Figure 8 The location of the sectional view is along line XIII-XIII. For example... Figure 8 As shown, on the first side WS1 of the laminate 10, the first lead-out portion 31B of the first internal electrode layer 31 and the second lead-out portion 32B of the second internal electrode layer 32 are exposed.

[0107] Furthermore, although the illustration is omitted, similar to the first side WS1 side, the first lead-out portion 31B of the first internal electrode layer 31 and the second lead-out portion 32B of the second internal electrode layer 32 are also exposed on the second side WS2 side.

[0108] This shortens the distance between the first lead-out portion 31B of the first internal electrode layer 31 and the second lead-out portion 32B of the second internal electrode layer 32, thus shortening the current flow path. Consequently, ESL can be reduced.

[0109] Hereinafter, the portions of the first lead-out portion 31B and the second lead-out portion 32B that are exposed on the first side surface WS1, and the portions of the first lead-out portion 31B and the second lead-out portion 32B that are exposed on the second side surface WS2, are collectively referred to as the side exposed portion 33 of the internal electrode layer 30. Furthermore, the dimension of the side exposed portion 33 in the longitudinal direction L is sometimes referred to as e1 or dimension e1.

[0110] In this embodiment, the first opposing electrode portion 31A and the second opposing electrode portion 32A are positioned opposite each other across the dielectric layer 20, thereby forming a capacitor and exhibiting the characteristics of a capacitor.

[0111] The shapes of the first opposing electrode portion 31A and the second opposing electrode portion 32A are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded, or the corners of the rectangular shape may be formed at an angle.

[0112] The shapes of the first lead-out portion 31B and the second lead-out portion 32B are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded, or the corners of the rectangular shape may be formed at an angle.

[0113] Furthermore, the dimension of the first lead-out portion 31B in the width direction W is larger than the dimension of the first counter electrode portion 31A in the width direction. The dimension of the second lead-out portion 32B in the width direction W is larger than the dimension of the second counter electrode portion 32A in the width direction. As a result, not only can the strength of the multilayer ceramic capacitor 1 be improved, but the contact area between the inner electrode layer 30 and the outer electrode 40 is also increased, thereby widening the current path and reducing the ESL of the multilayer ceramic capacitor 1.

[0114] Preferably, the dimension e1 of the side exposed portion 33 of the first lead-out portion 31B of the first internal electrode layer 31 and the second lead-out portion 32B of the second internal electrode layer 32 in the length direction is 10% or more and 44% or less relative to the dimension l in the length direction L of the laminate 10.

[0115] The aforementioned dimension e1 is 10% to 44% of the dimension l in the length direction L of the laminate 10. Therefore, even in a laminated ceramic capacitor 1 of the LW inverted type, the area of ​​the internal electrode layer 30 within the laminate 10 can be increased. Consequently, the proportion of the internal electrode layer 30 with a strength higher than that of the dielectric layer 20 can be increased. As a result, the strength of the laminated ceramic capacitor 1 can be improved, and the generation of internal cracks can be suppressed. Specifically, when manufacturing the laminated ceramic capacitor 1, the total amount of the internal electrode layer 30 is increased when the pattern of the internal electrode layer 30 is sintered to form the internal electrode layer 30, thereby increasing the compressive stress. As a result, the resistance to externally applied stress is strengthened, and the strength of the laminated ceramic capacitor 1 can be improved.

[0116] When the dimension e1 relative to the length L of the laminate 10 is less than 10%, the area of ​​the internal electrode layer 30 within the laminate 10 cannot be sufficiently increased, making it difficult to ensure mechanical strength. Therefore, when external stress is applied, cracks sometimes occur inside the laminated ceramic capacitor 1. Furthermore, when the dimension e1 relative to the length L of the laminate 10 becomes greater than 44%, the distance between the first external electrode 40A and the second external electrode 40B in the length L becomes shorter, thus causing a transition and potentially reducing moisture resistance.

[0117] Regarding the dimension e1 of the side exposed portion 33 in each of the plurality of first leads 31B in the length direction L, it is preferably 30 μm or more and 230 μm or less. Regarding the dimension e1 of the side exposed portion 33 in each of the plurality of second leads 32B in the length direction L, it is preferably 30 μm or more and 230 μm or less.

[0118] Furthermore, the aforementioned dimension e1 can be measured, for example, by the following method. The laminate 10 is ground to the exact center position in the height direction T, that is, ground to the position t / 2, so that the first main surface TS1 side is parallel to the LW cross-section. Then, using a microscope, the side exposed portions 33 of the first lead 31B on the first side surface WS1 side and the second side surface WS2 side, and the side exposed portions 33 of the second lead 32B on the first side surface WS1 side and the second side surface WS2 side, exposed in the LW cross-section through grinding, are measured respectively. Then, the average of these four measured values ​​is taken as the dimension e1 in the length direction L of the side exposed portions 33 in the laminated ceramic capacitor 1.

[0119] The laminate 10 has a counter electrode portion 11E. For example... Figures 5-7BAs shown, the counter electrode portion 11E is the portion of the first counter electrode portion 31A of the first inner electrode layer 31 and the second counter electrode portion 32A of the second inner electrode layer 32 that are opposite each other. The counter electrode portion 11E is configured as part of the inner layer portion 11. In addition, the counter electrode portion 11E is also referred to as the effective portion of the capacitor.

[0120] The first internal electrode layer 31 and the second internal electrode layer 32 may contain suitable conductive materials such as metals like Ni, Cu, Ag, Pd, and Au, or alloys containing at least one of these metals. When using an alloy, the first internal electrode layer 31 and the second internal electrode layer 32 may also contain, for example, an Ag-Pd alloy.

[0121] The thickness of each of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably 0.2 μm or more and 2.0 μm or less. The total number of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably 15 or more and 200 or less.

[0122] like Figure 5 as well as Figure 6 As shown, the first main surface side outer layer 12 is located on the first main surface TS1 side. The first main surface side outer layer 12 is located between the first main surface TS1 and the first outermost surface 11F of the first main surface TS1 side, which is the inner layer 11, and the extended surface 11f of the first outermost surface 11F. The second main surface side outer layer 13 is located on the second main surface TS2 side. The second main surface side outer layer 13 is located between the second main surface TS2 and the second outermost surface 11H of the second main surface TS2 side, which is the inner layer 11, and the extended surface 11h of the second outermost surface 11H. Both the first main surface side outer layer 12 and the second main surface side outer layer 13 are assemblies of multiple dielectric layers 20. The dielectric layers 20 used in the first main surface side outer layer 12 and the second main surface side outer layer 13 can also be the same as the dielectric layers 20 used in the inner layer 11.

[0123] The thickness of either or both of the first main surface outer layer 12 and the second main surface outer layer 13, i.e., the dimension in the height direction T, is preferably 15% or more and 35% or less of the thickness of the inner layer 11. This allows for a balance between ensuring electrostatic capacitance and improving the strength of the multilayer ceramic capacitor 1.

[0124] Furthermore, the thicknesses of the inner layer 11, the outer layer 12 on the first main surface side, and the outer layer 13 on the second main surface side can be measured, for example, by the following method: The first side of the multilayer ceramic capacitor 1 is ground until its length in the width direction W is half, thereby exposing the central LT cross-section in the width direction W. Then, the thicknesses of the inner layer 11, the outer layer 12 on the first main surface side, and the outer layer 13 on the second main surface side in this LT cross-section are measured using a microscope.

[0125] The laminate 10 has an outer layer portion on the end face side. For example... Figure 5 , Figure 7A as well as Figure 7B As shown, the outer layer on the end face side has a first end face side outer layer portion LG1 located on the first end face LS1 side and a second end face side outer layer portion LG2 located on the second end face LS2 side. The first end face side outer layer portion LG1 is a portion including a dielectric layer 20 located between the counter electrode portion 11E and the first end face LS1 and a first lead portion 31B. That is, the first end face side outer layer portion LG1 is an assembly of portions of multiple dielectric layers 20 on the first end face LS1 side and multiple first leads 31Bs. The second end face side outer layer portion LG2 is a portion including a dielectric layer 20 located between the counter electrode portion 11E and the second end face LS2 and a second lead portion 32B. That is, the second end face side outer layer portion LG2 is an assembly of portions of multiple dielectric layers 20 on the second end face LS2 side and multiple second leads 32Bs. In addition, the outer layer portion LG1 on the first end face side and the outer layer portion LG2 on the second end face side are also called L-spacers or end spacers.

[0126] The laminate 10 has a side outer layer. For example... Figure 6 , Figure 7A as well as Figure 7B As shown, the side outer layer has a first side outer layer WG1 located on the first side WS1 and a second side outer layer WG2 located on the second side WS2. The first side outer layer WG1 includes a portion of the dielectric layer 20 located between the counter electrode portion 11E and the first side WS1. That is, the first side outer layer WG1 is an assembly of portions of multiple dielectric layers 20 on the first side WS1 side. The second side outer layer WG2 includes a portion of the dielectric layer 20 located between the counter electrode portion 11E and the second side WS2. That is, the second side outer layer WG2 is an assembly of portions of multiple dielectric layers 20 on the second side WS2 side. Furthermore, the first side outer layer WG1 and the second side outer layer WG2 are also referred to as W-spacers or lateral spacers.

[0127] like Figures 4 to 7BAs shown, let l be the length in the longitudinal direction L of the first end face LS1 and the second end face LS2 connecting the laminate 10, w be the length in the width direction W of the first side face WS1 and the second side face WS2, and t be the length in the height direction T of the first main face TS1 and the second main face TS2. In this case, their dimensional relationship is w > l > t. That is, the length l of the laminate 10 is less than the width w. Therefore, not only is the current path between the first internal electrode layer 31 and the second internal electrode layer 32 shortened, but the area of ​​the first lead-out portion 31B of the first internal electrode layer 31 and the second lead-out portion 32B of the second internal electrode layer 32 can also be increased. Therefore, the ESL of the laminated ceramic capacitor 1 can be reduced.

[0128] Specifically, the length l in the longitudinal direction L connecting the first end face LS1 and the second end face LS2 of the laminate 10 is preferably 0.30 mm or more and 0.60 mm or less. Furthermore, the length w in the width direction W connecting the first side face WS1 and the second side face WS2 of the laminate 10 is preferably 0.60 mm or more and 1.0 mm or less.

[0129] Furthermore, the length t in the height direction T connecting the first main surface TS1 and the second main surface TS2 of the laminate 10 is preferably 150 μm or less. This allows for high-density installation. Furthermore, the length t in the height direction T connecting the first main surface TS1 and the second main surface TS2 of the laminate 10 is preferably 100 μm or less. This allows for even higher-density installation.

[0130] In addition, the dimensions of l, w, and t of the laminate 10 can be measured, for example, by the following method.

[0131] First, the dimension w of the laminate 10 is measured. Specifically, the dimension w of the laminate 10 is measured using a microscope at the exact midpoint of the length direction L of the laminate 10, that is, at the l / 2 position of the laminate 10.

[0132] Next, the dimensions l and t of the laminate 10 are measured. First, the same laminate 10 as the one with measured dimension w is ground to the exact midpoint of its width direction W, i.e., to half the width of the laminate 10, making it parallel to the LT section. Then, the LT section exposed by grinding is observed under a microscope. The dimension l of the laminate 10 is measured under a microscope at the exact midpoint of its height direction T in the LT section, i.e., the position of half the width of the laminate 10. The dimension t of the laminate 10 is measured under a microscope at the exact midpoint of its length direction L in the LT section, i.e., the position of half the width of the laminate 10.

[0133] (External electrode)

[0134] like Figure 5 As shown, the external electrode 40 has a first external electrode 40A disposed on the first end face LS1 side of the laminate 10 and a second external electrode 40B disposed on the second end face LS2 side of the laminate 10. The first external electrode 40A contacts the first lead-out portion 31B of each of the plurality of first internal electrode layers 31 exposed on the first end face LS1. Thus, the first external electrode 40A is electrically connected to the plurality of first internal electrode layers 31. The second external electrode 40B contacts the second lead-out portion 32B of each of the plurality of second internal electrode layers 32 exposed on the second end face LS2. Thus, the second external electrode 40B is electrically connected to the plurality of second internal electrode layers 32.

[0135] The first external electrode 40A is disposed on the first end face LS1, and is disposed on at least one of a portion of the first main face TS1 and a portion of the second main face TS2. Figure 5 , Figure 7A as well as Figure 7B As shown, in this embodiment, the first external electrode 40A is disposed on the first end face LS1, a portion of the first main face TS1, a portion of the first side face WS1, and a portion of the second side face WS2, but is not disposed on the second main face TS2. Furthermore, in the following description, without distinguishing between the first external electrode 40A and the second external electrode 40B, the first external electrode 40A and the second external electrode 40B are sometimes collectively referred to as external electrode 40.

[0136] The first external electrode 40A of this embodiment has a first face 40A1 located on the first end face LS1, a second face 40A2 located on a portion of the first main face TS1, a third face 40A3 located on a portion of the first side face WS1, and a fourth face 40A4 located on a portion of the second side face WS2.

[0137] The first face 40A1 is the portion that covers the entire first end face LS1 and is connected to the first lead-out portion 31B of the first internal electrode layer 31. The second face 40A2 is the portion that is connected to the connecting pad of the mounting substrate.

[0138] The third face 40A3 is the portion connected to the side exposed portion 33 of the first lead-out portion 31B of the first internal electrode layer 31 exposed on the first side WS1. The fifth face 40A5 is the portion connected to the side exposed portion 33 of the first lead-out portion 31B of the first internal electrode layer 31 exposed on the second side WS2.

[0139] The dimension e2 of the third facet 40A3 and the fourth facet 40A4 of the first external electrode 40A in the length direction L is preferably 17% or more and 48% or less relative to the dimension 1 in the length direction L of the laminate 10. For example... Figure 2 as well as Figure 3 As shown, dimension e2 is the length of the first external electrode 40A from the front end 41A on the second end face LS2 side to the end end 42A on the first end face LS1 side.

[0140] The second external electrode 40B is disposed on the second end face LS2, and is disposed on at least one of a portion of the first main face TS1 and a portion of the second main face TS2. Figure 5 , Figure 7A as well as Figure 7B As shown, in this embodiment, the second external electrode 40B is disposed on the second end face LS2, a portion of the first main face TS1, a portion of the first side face WS1, and a portion of the second side face WS2, but is not disposed on the second main face TS2.

[0141] The second external electrode 40B of this embodiment has a sixth face 40B1 located on the second end face LS2, a seventh face 40B2 located on a portion of the first main face TS1, an eighth face 40B3 located on a portion of the first side face WS1, and a ninth face 40B4 located on a portion of the second side face WS2.

[0142] The sixth face 40B1 is the portion that covers the entire second end face LS2 and is connected to the second lead-out portion 32B of the second internal electrode layer 32. The seventh face 40B2 is the portion that is connected to the connecting pad of the mounting substrate.

[0143] The eighth face 40B3 is the portion connected to the second lead-out portion 32B of the second internal electrode layer 32 exposed on the first side WS1. The tenth face 40B5 is the portion connected to the second lead-out portion 32B of the second internal electrode layer 32 exposed on the second side WS2.

[0144] The dimension e2 of the eighth face 40B3 and the ninth face 40B4 of the second external electrode 40B in the length direction L is preferably 17% or more and 48% or less relative to the dimension 1 in the length direction L of the laminate 10. The dimension e2 is the length of the second external electrode 40B from the front end 41B on the first end face LS1 side to the end end 42B on the second end face LS2 side.

[0145] The dimensions e2 of the first external electrode 40A and the second external electrode 40B are 17% or more and 48% or less of the dimension 1 in the length direction L of the laminate 10, thereby enabling the effect of suppressing crack generation by increasing mechanical strength, which is an effect of this embodiment, to be appropriately obtained without impairing the function of the external electrodes 40.

[0146] When the dimensions e2 of the first external electrode 40A and the second external electrode 40B are less than 17% of the dimension 1 in the length direction L of the laminate 10, the bonding area with the mounting substrate cannot be adequately ensured, thus reducing the self-alignment effect and sometimes causing poor mounting of the laminated ceramic capacitor 1.

[0147] Furthermore, when the dimension e2 of each of the first external electrode 40A and the second external electrode 40B is greater than 48% of the dimension 1 in the length direction L of the laminate 10, the laminated ceramic capacitor 1 may rotate during mounting to the mounting substrate, resulting in either the first external electrode 40A or the second external electrode 40B spanning two mounting pads, thus causing a short circuit. Consequently, the distance in the length direction L between the first external electrode 40A and the second external electrode 40B becomes shorter, leading to a transition and potentially reducing moisture resistance.

[0148] Furthermore, the aforementioned self-alignment effect refers to the effect of applying a force to the molten solder during soldering, reducing its surface area—that is, applying surface tension—thereby moving the electronic component, which is supported by the molten solder and is the object to be mounted, thereby positioning it. By achieving this self-alignment effect, positional misalignment during mounting can be suppressed.

[0149] Specifically, the size e2 of the first external electrode 40A and the second external electrode 40B is preferably 50 μm or more and 250 μm or less.

[0150] The method for measuring the dimensions e2 of the first external electrode 40A and the second external electrode 40B can be performed by visual inspection using a measuring instrument. Specifically, the e2 dimension at the exact midpoint of the width direction W of the first external electrode 40A and the e2 dimension at the exact midpoint of the width direction W of the second external electrode 40B are measured using a measuring instrument, and their average value is taken as e2.

[0151] like Figure 9A As shown, the first external electrode 40A has a first base electrode layer 50A as a base electrode layer and a first plating layer 60A disposed on the first base electrode layer 50A. The first base electrode layer 50A is disposed on the surface of the laminate 10. The first plating layer 60A is configured to cover the first base electrode layer 50A.

[0152] like Figure 9BAs shown, the second external electrode 40B has a second base electrode layer 50B as a base electrode layer and a second plating layer 60B disposed on the second base electrode layer 50B. The second base electrode layer 50B is disposed on the surface of the laminate 10. The second plating layer 60B is configured to cover the second base electrode layer 50B.

[0153] The first substrate electrode layer 50A and the second substrate electrode layer 50B include at least one selected from sintered layers, thin film layers, etc.

[0154] In this embodiment, the first substrate electrode layer 50A and the second substrate electrode layer 50B are thin film layers. The thin film layer is a layer on which metal particles are deposited.

[0155] When the first base electrode layer 50A and the second base electrode layer 50B are formed from thin film layers, it is preferable to form them by a thin film formation method such as sputtering or vapor deposition. Here, a sputtered electrode formed by sputtering will be described.

[0156] In this embodiment, the first base electrode layer 50A includes a first thin film layer 51A formed by a sputtering electrode. The second base electrode layer 50B includes a second thin film layer 51B formed by a sputtering electrode. When the first base electrode layer 50A and the second base electrode layer 50B are formed by sputtering electrodes, it is preferable to form the sputtering electrode directly on the first main surface TS1 of the laminate 10.

[0157] like Figure 5 as well as Figure 9A As shown, the first thin film layer 51A formed by the sputtering electrode is disposed on a portion of the first end face LS1 side of the first main surface TS1. Specifically, the first thin film layer 51A is preferably disposed on the first main surface TS1. Figure 4 The portion shown is covered by the first external electrode 40A.

[0158] Furthermore, the first thin film layer 51A is preferably disposed on a portion of the first main surface TS1, and extends slightly from a portion of the first main surface TS1 to a portion of the first end surface LS1.

[0159] For example, as used in the description of the manufacturing process described later. Figure 11 As shown, when the edge portion of the laminate 10 has a chamfered portion C such as a rounded corner, the first thin film layer 51A is preferably disposed on a portion of the first end face LS1 side of the first main surface TS1 and the chamfered portion C of the first end face LS1 side that is continuous with that portion. If this is the case, the thin film layer can be easily formed by sputtering or the like.

[0160] When forming the plating layer using the above method, the distance between the first thin film layer 51A disposed on a portion of the first end face LS1 and the internal electrode layer 30 exposed on the first end face LS1 can be controlled. Therefore, it becomes easier to deposit the plating layer on the surface of the laminate 10 between the first thin film layer 51A disposed on a portion of the first end face LS1 and the internal electrode layer 30 exposed on the first end face LS1.

[0161] like Figure 5 as well as Figure 9B As shown, the second thin film layer 51B formed by the sputtered electrode is disposed on a portion of the second end face LS2 side of the first main surface TS1. Specifically, the second thin film layer 51B is preferably disposed on the first main surface TS1. Figure 4 The portion shown is covered by the second external electrode 40B.

[0162] Furthermore, the second thin film layer 51B is preferably disposed on a portion of the first main surface TS1, and extends slightly from a portion of the first main surface TS1 to a portion of the second end surface LS2.

[0163] For example, as used in the description of the manufacturing process described later. Figure 11 As shown, when the edge portion of the laminate 10 has a chamfered portion C such as a rounded corner, the second thin film layer 51B is preferably disposed on a portion of the second end face LS2 side of the first main surface TS1 and the chamfered portion C of the second end face LS2 side that is continuous with that portion. If this is the case, the thin film layer can be easily formed by sputtering or the like.

[0164] When forming the plating layer using the above method, the distance between the portion of the second thin film layer 51B disposed on the second end face LS2 and the internal electrode layer 30 exposed on the second end face LS2 can be controlled. Therefore, it becomes easier to deposit the plating layer on the surface of the laminate 10 between the portion of the second thin film layer 51B disposed on the second end face LS2 and the internal electrode layer 30 exposed on the second end face LS2.

[0165] The first thin film layer 51A and the second thin film layer 51B formed by the sputtered electrode preferably contain at least one metal selected from the group consisting of Mg, Al, Ti, W, Cr, Cu, Ni, Ag, Co, Mo, and V. This improves the adhesion of the external electrode 40 to the laminate 10. The thin film layer can be a single layer or formed from multiple layers. For example, it can be formed as a two-layer structure consisting of a Ni-Cr alloy layer and a Ni-Cu alloy layer.

[0166] The thickness of the first thin film layer 51A and the second thin film layer 51B formed by the sputtering electrode, that is, the thickness in the height direction T connecting the first main surface TS1 and the second main surface TS2, is preferably 50 nm or more and 400 nm or less, and more preferably 50 nm or more and 130 nm or less.

[0167] When a sputtering electrode is directly formed on the first main surface TS1 of the laminate 10 and the first base electrode layer 50A and the second base electrode layer 50B are disposed there, it is preferable to form the base electrode layer with the sintered layer on the first end surface LS1 and the second end surface LS2, or to form the plating layer described later directly without forming the base electrode layer. In this embodiment, the plating layer described later is formed directly on the first end surface LS1 and the second end surface LS2 without forming the base electrode layer.

[0168] Additionally, as in the variations described later, the first base electrode layer 50A and the second base electrode layer 50B may also be sintered layers. The sintered layers preferably comprise one of a metallic component, a glass component, or a ceramic component, or both. The metallic component may include, for example, at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloys, Au, etc. The glass component may include, for example, at least one selected from B, Si, Ba, Mg, Al, Li, etc. The ceramic component may be the same type of ceramic material as the dielectric layer 20, or a different type of ceramic material. The ceramic component may include, for example, at least one selected from BaTiO3, CaTiO3, (Ba,Ca)TiO3, SrTiO3, CaZrO3, etc.

[0169] The sintered layer is, for example, a conductive paste comprising glass and metal applied to the laminate 10 and then sintered. The sintered layer can be formed by simultaneously firing a laminate having an internal electrode layer and a dielectric layer and a conductive paste applied to the laminate, or by applying a conductive paste to the laminate 10 after firing the laminate having the internal electrode layer and the dielectric layer to obtain the laminate 10, and then sintering it. Furthermore, when simultaneously firing the laminate having the internal electrode layer and the dielectric layer and a conductive paste applied to the laminate, the sintered layer is preferably formed by sintering a material to which ceramic material is added instead of glass. In this case, it is particularly preferable to use a ceramic material of the same type as the dielectric layer 20 as the added ceramic material. The sintered layer can also consist of multiple layers.

[0170] Alternatively, the structure can be as follows: without the first base electrode layer 50A and the second base electrode layer 50B, the first plating layer 60A and the second plating layer 60B (described later) are directly disposed on the laminate 10.

[0171] The first plating layer 60A is configured to cover the first substrate electrode layer 50A.

[0172] The second plating layer 60B is configured to cover the second base electrode layer 50B.

[0173] The first plating layer 60A and the second plating layer 60B may, for example, include at least one selected from Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc. The first plating layer 60A and the second plating layer 60B may also be formed from multiple layers.

[0174] When the substrate electrode layer is formed of a thin film layer, the plating layer is preferably formed of a three-layer structure: a Cu plating layer as the lower plating layer, a Ni plating layer as the middle plating layer, and a Sn plating layer as the upper plating layer. That is, the first plating layer 60A preferably has a first Cu plating layer 61A, a first Ni plating layer 62A, and a first Sn plating layer 63A. The second plating layer 60B preferably has a second Cu plating layer 61B, a second Ni plating layer 62B, and a second Sn plating layer 63B. However, the first plating layer 60A and the second plating layer 60B are not limited to a three-layer structure and may be other layer structures. The first Cu plating layer 61A and the second Cu plating layer 61B are examples of inner plating layers in this disclosure. The first Ni plating layer 62A, the first Sn plating layer 63A, the second Ni plating layer 62B, and the second Sn plating layer 63B are examples of outer plating layers in this disclosure.

[0175] The first Cu plating layer 61A is configured to cover the first end face LS1 of the laminate 10 and the first thin film layer 51A, which serves as the first base electrode layer 50A, disposed on the first main surface TS1 of the laminate 10. In this embodiment, the first Cu plating layer 61A is further configured to cover the exposed side portions 33 of the inner electrode layers 30 on the first side surface WS1 and the second side surface WS2 of the laminate 10. At this time, the gap between the first thin film layer 51A and the inner electrode layer 30 exposed on the first end face LS1 of the laminate 10, and the gap between the plurality of inner electrode layers 30 exposed on the surface of the laminate 10 are formed narrow, so a plating layer is also deposited in the regions of these gaps.

[0176] The first Ni plating layer 62A is configured to cover the first Cu plating layer 61A. The first Sn plating layer 63A is configured to cover the first Ni plating layer 62A. In this embodiment, the first plating layer 60A is directly electrically connected to the first internal electrode layer 31.

[0177] The second Cu plating layer 61B is configured to cover the second end face LS2 of the laminate 10 and the second thin film layer 51B, which serves as the second base electrode layer 50B, disposed on the first main face TS1 of the laminate 10. In this embodiment, the second Cu plating layer 61B is further configured to cover the exposed side portions 33 of the inner electrode layers 30 on the first side face WS1 and the second side face WS2 of the laminate 10. At this time, the gap between the second thin film layer 51B and the inner electrode layer 30 exposed on the second end face LS2 of the laminate 10, and the gap between the plurality of inner electrode layers 30 exposed on the surface of the laminate 10, are formed to be narrow, so a plating layer is also deposited in the regions of these gaps.

[0178] The second Ni plating layer 62B is configured to cover the second Cu plating layer 61B. The second Sn plating layer 63B is configured to cover the second Ni plating layer 62B. In this embodiment, the second plating layer 60B is directly electrically connected to the second internal electrode layer 32.

[0179] By providing a plating layer comprising both Cu and Ni plating layers to cover the base electrode layer, erosion of the base electrode layer by solder during the mounting of the multilayer ceramic capacitor 1 can be suppressed. Furthermore, by further providing a Sn plating layer on the surface of the Ni plating layer, the wettability of the solder during the mounting of the multilayer ceramic capacitor 1 can be improved. Thus, the multilayer ceramic capacitor 1 can be easily mounted.

[0180] The thickness of each plating layer is preferably 2 μm or more and 15 μm or less. That is, the average thickness of each of the first Cu plating layer 61A, the first Ni plating layer 62A, the first Sn plating layer 63A, the second Cu plating layer 61B, the second Ni plating layer 62B, and the second Sn plating layer 63B is preferably 2 μm or more and 15 μm or less. More specifically, the average thickness of each of the first Cu plating layer 61A and the second Cu plating layer 61B is more preferably 5 μm or more and 8 μm or less. Furthermore, the average thickness of each of the first Ni plating layer 62A, the first Sn plating layer 63A, the second Ni plating layer 62B, and the second Sn plating layer 63B is more preferably 2 μm or more and 4 μm or less.

[0181] As for the overall dimensions of the multilayer ceramic capacitor 1, which includes the laminate 10 and a pair of external electrodes 40, the dimension in the height direction T is preferably 0.06 mm or more and 0.15 mm or less, the dimension in the length direction L is preferably 0.30 mm or more and 0.60 mm or less, and the dimension in the width direction W is preferably 0.60 mm or more and 1.0 mm or less. In this embodiment, the dimension L in the length direction of the multilayer ceramic capacitor 1 is smaller than the dimension W in the width direction of the multilayer ceramic capacitor 1. That is, the multilayer ceramic capacitor 1 according to the embodiment is a multilayer ceramic capacitor of the LW inverted type.

[0182] (A modified example of the layered structure of the external electrode)

[0183] Next, a modified example of the layer structure of the external electrode 40 of the multilayer ceramic capacitor 1 of this embodiment will be described. Furthermore, in the following description, structures identical to those in the above embodiment will be labeled with the same reference numerals, and detailed descriptions will be omitted. Figure 10A as well as Figure 10B This is a cross-sectional view showing a modified example of the layer structure of the external electrode 40 of the multilayer ceramic capacitor 1 according to this embodiment, which is respectively compared with... Figure 9A as well as Figure 9B The corresponding figure. In this modified example, the structure of the external electrode 40 differs from that in the above embodiment.

[0184] The first external electrode 40A has a first base electrode layer 50A and a first plating layer 60A. In this modified example, the first base electrode layer 50A includes a first plating layer 52A. In this modified example, the first plating layer 60A has a first Ni plating layer 62A and a first Sn plating layer 63A.

[0185] The second external electrode 40B has a second base electrode layer 50B and a second plating layer 60B. In this modified example, the second base electrode layer 50B includes a second plating layer 52B. In this modified example, the second plating layer 60B has a second Ni plating layer 62B and a second Sn plating layer 63B.

[0186] In this modified example, the first base electrode layer 50A, for example, similar to the first external electrode 40A described above, has a first facet located on the first end face LS1, a second facet located on a portion of the first main face TS1, a third facet located on a portion of the first side face WS1, and a fourth facet located on a portion of the second side face WS2. Furthermore, in this modified example, the first base electrode layer 50A is connected to the first internal electrode layer 31.

[0187] The first Ni plating layer 62A is configured to cover the first substrate electrode layer 50A. The first Sn plating layer 63A is configured to cover the first Ni plating layer 62A.

[0188] In this modified example, the second base electrode layer 50B, for example, similar to the second external electrode 40B described above, has a sixth facet located on the second end face LS2, a portion of a seventh facet located on the first main face TS1, a portion of an eighth facet located on the first side face WS1, and a portion of a ninth facet located on the second side face WS2. Furthermore, in this modified example, the second base electrode layer 50B is connected to the second internal electrode layer 32.

[0189] The second Ni plating layer 62B is configured to cover the second substrate electrode layer 50B. The second Sn plating layer 63B is configured to cover the second Ni plating layer 62B.

[0190] The first sintered layer 52A constituting the first base electrode layer 50A and the second sintered layer 52B constituting the second base electrode layer 50B are, for example, sintered layers formed by applying a conductive paste containing glass and metal to the laminate and then sintering it. Furthermore, when the laminate and the conductive paste applied to it are simultaneously sintered, the sintered layer is preferably formed by sintering a material to which ceramic material is added instead of glass. In this case, it is particularly preferable to use a ceramic material of the same type as the dielectric layer 20 as the added ceramic material.

[0191] When the base electrode layer is formed by a sintered layer, the first plating layer 60A and the second plating layer 60B are preferably a two-layer structure in which a Sn plating layer is formed on a Ni plating layer. In this case, the Ni plating layer can suppress the erosion of the base electrode layer by the solder when mounting the multilayer ceramic capacitor 1. Furthermore, the Sn plating layer can improve the wettability of the solder when mounting the multilayer ceramic capacitor 1. As a result, the multilayer ceramic capacitor 1 can be mounted easily.

[0192] Furthermore, the first plating layer 60A and the second plating layer 60B are not limited to a two-layer structure; they can also be formed as in the above embodiment, consisting of a three-layer structure including Cu plating, or other layer structures. When a Cu plating layer is formed, the effect of inhibiting the penetration of plating solution and other water can be achieved.

[0193] The thickness of each plating layer is preferably 2 μm or more and 15 μm or less. That is, the average thickness of each of the first Ni plating layer 62A, the first Sn plating layer 63A, the second Ni plating layer 62B, and the second Sn plating layer 63B is preferably 2 μm or more and 15 μm or less. More specifically, the average thickness of each of the first Ni plating layer 62A, the first Sn plating layer 63A, the second Ni plating layer 62B, and the second Sn plating layer 63B is more preferably 2 μm or more and 4 μm or less.

[0194] (Manufacturing method)

[0195] Next, the manufacturing method of the multilayer ceramic capacitor 1 of this embodiment will be described.

[0196] Prepare a dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30. Both the dielectric sheet for the dielectric layer 20 and the conductive paste for the internal electrode layer 30 contain binders and solvents. The binders and solvents can be known binders and solvents. For example, a paste containing conductive materials is a paste in which organic binders and organic solvents are added to metal powder.

[0197] On the dielectric sheet, conductive paste for the internal electrode layer 30 is printed, for example, by screen printing, gravure printing, or using a printing plate with a pattern design of the shape of the internal electrode layer 30 in this embodiment. Thus, a dielectric sheet with a pattern of the first internal electrode layer 31 and a dielectric sheet with a pattern of the second internal electrode layer 32 are prepared.

[0198] A given number of dielectric sheets without the pattern of the internal electrode layer 30 are stacked to form a portion of the first main surface side outer layer 12 on the first main surface TS1 side. Thereon, dielectric sheets with the pattern of the first internal electrode layer 31 and dielectric sheets with the pattern of the second internal electrode layer 32 are sequentially and alternately stacked to form a portion of the inner layer 11. On this portion of the inner layer 11, a given number of dielectric sheets without the pattern of the internal electrode layer 30 are stacked to form a portion of the second main surface side outer layer 13 on the second main surface TS2 side. Thus, a laminated sheet is obtained.

[0199] Next, the laminated sheets are pressed in the stacking direction using methods such as isostatic pressing to produce a laminated block.

[0200] Next, the laminated blocks are cut into individual pieces to a given size, thus obtaining multiple laminated sheets. Then, the laminated sheets can be ground by means of tumbling or other methods to form rounded corners and edges.

[0201] Next, the laminate is fired to obtain the laminate 10. The firing temperature at this time depends on the materials of the dielectric layer 20 and the internal electrode layer 30, but is preferably 900°C or higher and 1400°C or lower.

[0202] In this embodiment, a base electrode layer is formed from a thin film layer. When the base electrode layer is formed from a thin film layer, the thin film layer is formed on the portion of the laminate 10 where an external electrode is desired to be formed by means of a mask setting, etc. The thin film layer can be formed by a thin film formation method such as sputtering or vapor deposition. In this embodiment, a sputtered electrode, serving as the thin film layer, is formed by sputtering.

[0203] Figures 11-13 This diagram shows an intermediate state in the manufacturing process of the multilayer ceramic capacitor of this embodiment, showing the state after the thin film layer is disposed on the laminate 10 and before the plating layer is disposed. Figure 11 This diagram shows the state in which the first thin film layer 51A and the second thin film layer 51B are disposed as thin film layers in the laminate 10, and is consistent with... Figure 5 The figure corresponding to the LT section. Figure 12 This diagram shows the state in which the first thin film layer 51A, as a thin film layer, is disposed in the laminate 10. Figure 6 The diagram corresponding to the WT cross-section. Figure 13 This diagram shows the state in which the first thin film layer 51A and the second thin film layer 51B are disposed in the laminate 10, and is related to... Figure 8 The corresponding diagram shows the surface of the first side surface WS1 of the laminate 10.

[0204] A first thin film layer 51A formed by a sputtering electrode is disposed on a portion of the first end face LS1 side of the first main surface TS1. A second thin film layer 51B formed by a sputtering electrode is disposed on a portion of the second end face LS2 side of the first main surface TS1.

[0205] In this embodiment, a thin film layer formed by sputtering electrodes is disposed on a portion of the first main surface TS1, and is configured to continuously extend slightly around a portion of the first end surface LS1 and a portion of the second end surface LS2 from the portion of the first main surface TS1. This allows control over the distance between the thin film layer disposed around the portion of the first end surface LS1 and the portion of the second end surface LS2, and the internal electrode layer 30 exposed on the first end surface LS1 and the second end surface LS2. Consequently, a plating layer can also be deposited on the surface of the laminate 10 between the thin film layer disposed around the portion of the first end surface LS1 and the portion of the second end surface LS2, and the internal electrode layer 30 exposed on the first end surface LS1 and the second end surface LS2.

[0206] Then, a plating layer is formed on the surface of the substrate electrode layer, including the thin film layer, and the laminate. In this embodiment, three plating layers are formed as plating layers: a Cu plating layer, a Ni plating layer, and a Sn plating layer.

[0207] The plating layer is formed by electrolytic plating. Roller plating is the preferred plating method.

[0208] Furthermore, the plating layer is configured to cover the exposed side portions 33 of the internal electrode layer 30 on the first side WS1 and the second side WS2 of the laminate 10. At this time, by narrowing the gaps between the thin film layer and the internal electrode layers 30 exposed on the surface of the laminate 10, and the gaps between the plurality of internal electrode layers 30 exposed on the surface of the laminate 10, a plating layer is also deposited in the regions of these gaps.

[0209] Alternatively, when it is difficult to control the formation of the plating layer, a mask can be placed at the location where the surface of the laminate 10 is exposed to form the plating layer. This makes it easier to form a plating layer with the desired shape.

[0210] Furthermore, when the base electrode layer is formed by sintering, a conductive paste that forms the first base electrode layer is applied to the first facet of the laminate 10 on the first end facet LS1, a portion of the second facet on the first main facet TS1, a portion of the third facet on the first side facet WS1, and a portion of the fourth facet on the second side facet WS2. Additionally, on the second end facet LS2 of the laminate 10, a conductive paste that forms the second base electrode layer is applied to the sixth facet on the second end facet LS2, a portion of the seventh facet on the first main facet TS1, a portion of the eighth facet on the first side facet WS1, and a portion of the ninth facet on the second side facet WS2.

[0211] In addition, a mask is pre-set for the portions where a base electrode layer is not desired. After masking, a conductive paste containing glass components and metal is applied to the laminate 10 by methods such as dipping or screen printing. Then, a sintering process is performed to form the base electrode layer. The sintering temperature is preferably, for example, 700°C or higher and 900°C or lower.

[0212] Furthermore, when the laminated sheet before firing and the conductive paste applied to the laminated sheet are fired simultaneously, the sintered layer is preferably formed by sintering a material to which ceramic material is added instead of glass. In this case, the ceramic material added is particularly preferably the same type of ceramic material as the dielectric layer 20. In this process, the laminated sheet before firing is coated with conductive paste, and the laminated sheet and the conductive paste applied to the laminated sheet are fired simultaneously to form a laminated body 10, which forms the sintered layer.

[0213] Then, a plating layer is formed on the surface of the base electrode layer, including the sintered layer, and the laminate 10. When the base electrode layer is formed from the sintered layer, two plating layers are formed, for example, a Ni plating layer and a Sn plating layer. The plating layer is formed by electrolytic plating. As the plating method, roller plating is preferred.

[0214] Alternatively, when it is difficult to control the formation of the plating layer, a mask can be placed at the location where the surface of the laminate 10 is exposed, thereby forming the plating layer. This makes it easier to form a plating layer of the desired shape.

[0215] Through this manufacturing process, a multilayer ceramic capacitor 1 is manufactured.

[0216] (Example of a variation in the shape of the external electrode)

[0217] The structure of the external electrode 40 is not limited to the structure of the above embodiment. Hereinafter, a first, second, and third modification example with different shapes of the external electrode 40 of the multilayer ceramic capacitor 1 of this embodiment will be described. In addition, in the following description, the same reference numerals are used for structures that are the same as those in the above embodiment, and detailed descriptions are omitted.

[0218] Figure 14 This is a perspective view showing the multilayer ceramic capacitor 1 with the external electrode 40 involved in the first modified example, which is related to... Figure 1 The corresponding diagram. Figure 15 yes Figure 14 The XV-XV sectional view, i.e., the LT sectional view, is the same as... Figure 5 The corresponding diagram.

[0219] In the first modified example, the first external electrode 40A, as a portion disposed on the second main surface TS2 of the laminate 10 (not present in the above embodiment), also has a fifth face portion 40A5. That is, the first external electrode 40A in the first modified example has a first face portion 40A1 located on the first end face LS1, a second face portion 40A2 located on the first main surface TS1, a third face portion 40A3 located on the first side surface WS1, a fourth face portion 40A4 located on the second side surface WS2, and a fifth face portion 40A5 located on the second main surface TS2. In the first external electrode 40A, either the second face portion 40A2 or the fifth face portion 40A5 is connected to a connection pad on the mounting substrate.

[0220] In the second external electrode 40B of the first modification, a tenth facet 40B5 is also provided as a portion disposed on the second main surface TS2 of the laminate 10, which is not present in the above embodiment. That is, the second external electrode 40B of the first modification has a sixth facet 40B1 located on the second end surface LS2, a seventh facet 40B2 located on a portion of the first main surface TS1, an eighth facet 40B3 located on a portion of the first side surface WS1, a ninth facet 40B4 located on a portion of the second side surface WS2, and a tenth facet 40B5 located on a portion of the second main surface TS2. In the second external electrode 40B, either the seventh facet 40B2 or the tenth facet 40B5 is connected to the connection pad of the mounting substrate.

[0221] The external electrode 40 in the first variation may also have a base electrode layer and a plating layer disposed on the base electrode layer, similar to the embodiments described above. The base electrode layer includes at least one selected from the sintered layer, thin film layer, etc.

[0222] Figure 16 yes Figure 15The enlarged view of the portion shown using XVI is compared with... Figure 9A The corresponding diagram. That is, Figure 16 The LT cross-section of the first external electrode 40A, which includes the first modified example, is shown. Furthermore, the second external electrode 40B, which includes the first modified example, has the same structure as the first external electrode 40A, therefore, the description of the second external electrode 40B is omitted by describing the first external electrode 40A.

[0223] like Figure 16 As shown, the first modified example involves a first external electrode 40A having a first base electrode layer 50A and a first plating layer 60A disposed on the first base electrode layer 50A. The first base electrode layer 50A is disposed on the surface of the laminate 10. The first plating layer 60A is configured to cover the first base electrode layer 50A.

[0224] The first modified example involves a first substrate electrode layer 50A comprising a first thin film layer 51A formed by a sputtering electrode. The first thin film layer 51A formed by the sputtering electrode is disposed on a portion of the first end face LS1 side on a first main surface TS1 and a portion of the first end face LS1 side on a second main surface TS2. Preferably, the first thin film layer 51A is disposed on a portion of the first main surface TS1 and extends continuously and slightly around a portion of the first end face LS1 from that portion. Preferably, the first thin film layer 51A is disposed on a portion of the second main surface TS2 and extends continuously and slightly around a portion of the first end face LS1 from that portion.

[0225] The first plating layer 60A is configured to cover the first substrate electrode layer 50A. The first plating layer 60A preferably has a first Cu plating layer 61A, a first Ni plating layer 62A, and a first Sn plating layer 63A. However, the first plating layer 60A is not limited to a three-layer structure and may also be other layer structures.

[0226] The first Cu plating layer 61A is configured to cover the first end face LS1 of the laminate 10 and the first thin film layer 51A, which serves as the first base electrode layer 50A, disposed on the first main face TS1 and the second main face TS2 of the laminate 10. In this case, the first Cu plating layer 61A is also configured to cover the exposed side portions 33 of the exposed internal electrode layer 30 on the first side face WS1 and the second side face WS2 of the laminate 10.

[0227] The first Ni plating layer 62A is configured to cover the first Cu plating layer 61A. The first Sn plating layer 63A is configured to cover the first Ni plating layer 62A. The first plating layer 60A is directly electrically connected to the first internal electrode layer 31.

[0228] like Figure 10AAs shown, in the first modified example, the first external electrode 40A may also include a first base electrode layer 50A containing a first plating layer 52A, and the first plating layer 60A may have a two-layer structure having a first Ni plating layer 62A and a first Sn plating layer 63A.

[0229] Next, refer to Figure 17 A second modified example of the external electrode 40 will be described. Figure 17 This is a perspective view of the multilayer ceramic capacitor 1 using the external electrode 40 of the second modified example, and... Figure 1 correspond.

[0230] The second variation involves an external electrode 40 that makes... Figure 1 The external electrode 40 of the above-described embodiment, which is a modified external electrode, has a shape in which portions of the portion disposed on the first side surface WS1 and the second side surface WS2 of the laminate 10, as well as the inner side (second external electrode 40B side) in the length direction L, are cut off. That is, as shown Figure 17 As shown, a cut-off portion 45 is formed on the second surface portion 40A2 of the first external electrode 40A, which removes the portion of the second main surface TS2 side and the inner side in the length direction L. Furthermore, a cut-off portion 45 is formed on the eighth surface portion 40B3 of the second external electrode 40B, which removes the portion of the second main surface TS2 side and the inner side in the length direction L. Although in Figure 17 Not shown, but the same cut portion 45 is also formed on the fourth facet 40A4 of the first external electrode 40A and the ninth facet 40B4 of the second external electrode 40B.

[0231] The external electrode 40 involved in the second variation can also use the same layer structure as the above embodiment, that is, it can also use a layer structure in which the base layer has a thin film layer or a sintered layer and two or three plating layers are formed on the base layer.

[0232] Next, refer to Figure 18 A third modified example of the external electrode 40 will be described. Figure 18 This is a perspective view of the multilayer ceramic capacitor 1 using the external electrode 40 of the third modification example, and... Figure 1 correspond.

[0233] The second variation involves an external electrode 40 that makes... Figure 14 The external electrode of the first modified example shown above has a recess formed on the portion of the external electrode 40 that is disposed on the first side WS1 and the second side WS2 of the laminate 10, respectively.

[0234] That is, such as Figure 18As shown, on the third surface portion 40A3 of the first external electrode 40A, a recess 46 is formed at the center in the height direction T, extending from the inside to the outside in the width direction W. The recess 46 opens on the inside side in the width direction W, i.e., on the side of the second end face LS2. Furthermore, on the eighth surface portion 40B3 of the second external electrode 40B, a recess 46 is formed at the center in the height direction T, extending from the inside to the outside in the width direction W. The recess 46 opens on the inside side in the width direction W, i.e., on the side of the first end face LS1. Although in Figure 18 Not shown, but the same recess 46 is also formed on the fourth facet 40A4 of the first external electrode 40A and the ninth facet 40B4 of the second external electrode 40B. The third facet 40A3, the fourth facet 40A4, the eighth facet 40B3 and the ninth facet 40B4 are examples of the side covering portions of this disclosure in which the recess 46 is formed.

[0235] The external electrode 40 involved in the third variation can also use the same layer structure as the above embodiment, that is, it can also use a layer structure in which the base layer has a thin film layer or a sintered layer and two or three plating layers are formed on the base layer.

[0236] The multilayer ceramic capacitor 1 described above achieves the following effects.

[0237] The multilayer ceramic capacitor 1 according to the embodiment includes: a multilayer body 10 comprising a plurality of dielectric layers 20 and a plurality of internal electrode layers 30 alternately stacked in the height direction T, and having a first main surface TS1 and a second main surface TS2 opposite to each other in the height direction T, a first end surface LS1 and a second end surface LS2 opposite to each other in the length direction L orthogonal to the height direction T, and a first side surface WS1 and a second side surface WS2 opposite to each other in the width direction W orthogonal to the height direction T and the length direction L; and a pair of external electrodes. 40, which are spaced apart from each other at both ends along the length direction L of the laminate 10, the inner electrode layer 30 includes: a first inner electrode layer 31 extending to a first end face LS1; and a second inner electrode layer 32 extending to a second end face LS2. The outer electrode 40 has: a first outer electrode 40A connected to the first inner electrode layer 31, disposed on the first end face LS1, and disposed on at least one of a portion on the first main surface TS1 and a portion on the second main surface TS2; and a second outer electrode 40B connected to the first inner electrode layer 31. 2. An internal electrode layer 32 is connected and disposed on the second end face LS2, and at least one of a portion disposed on the first main face TS1 and a portion disposed on the second main face TS2. In the multilayer ceramic capacitor 1, the length in the longitudinal direction L connecting the first end face LS1 and the second end face LS2 of the multilayer 10 is set to 1, the length in the width direction W connecting the first side face WS1 and the second side face WS2 is set to w, and the length in the height direction T connecting the first main face TS1 and the second main face TS2 is set to t. At this time, the capacitor is in the following position. Given the dimensional relationship w > l > t, the first internal electrode layer 31 is located inside the laminate 10 and has: a first opposing electrode portion 31A, which is opposite to the second internal electrode layer 32; and a first lead-out portion 31B, the width dimension W of which is greater than that of the first opposing electrode portion 31A, and is configured to be exposed on a part of the first end face LS1, a part of the first side face WS1, and a part of the second side face WS2. The second internal electrode layer 32 is located inside the laminate 10 and has: a second opposing electrode portion 32A, which is opposite to the first internal electrode layer 31.The second lead-out portion 32B has a width dimension W greater than that of the second counter electrode portion 32A, and is configured to expose a portion of the second end face LS2, a portion of the first side face WS1, and a portion of the second side face WS2. The dimension in the length direction L of the side exposed portions 33 of the first lead-out portion 31B and the second lead-out portion 32B, which are portions exposed as portions of the first side face WS1 and the second side face WS2 respectively, is set to e1. ​​At this time, e1 is 10% or more and 44% or less of the dimension in the length direction L relative to the laminate 10. A portion of the portion disposed on the first main surface TS1... The length in the longitudinal direction L of at least one of the first external electrodes 40A disposed on a portion of the first main surface TS2, from the front end 41A on the second end surface LS2 side to the end end 42A on the first end surface LS1 side, and the length in the longitudinal direction L of at least one of the second external electrodes 40B disposed on a portion of the first main surface TS1 and a portion of the second main surface TS2, from the front end 41B on the first end surface LS1 side to the end end 42B on the second end surface LS2 side, is set as e2. In this case, e2 is 17% or more and 48% or less of the dimension in the longitudinal direction L relative to the laminate 10.

[0238] Therefore, in the LW inverted type of multilayer ceramic capacitor 1, even if the thickness of the length t in the height direction T is reduced, the mechanical strength can be improved and the generation of internal cracks can be suppressed.

[0239] In the multilayer ceramic capacitor 1 according to the embodiment, the length t in the height direction T connecting the first main surface TS1 and the second main surface TS2 is 150 μm or less.

[0240] Therefore, even a multilayer ceramic capacitor 1 with a length t of less than 150 μm in the height direction T is less prone to cracking due to its improved mechanical strength.

[0241] In the multilayer ceramic capacitor 1 according to the embodiment, the length t in the height direction T connecting the first main surface TS1 and the second main surface TS2 is 100 μm or less.

[0242] Therefore, even a multilayer ceramic capacitor 1 with a length t of less than 100 μm in the height direction T is less prone to cracking due to its improved mechanical strength.

[0243] In the multilayer ceramic capacitor 1 according to the embodiment, preferably, the first external electrode 40A has a first base electrode layer 50A, an inner plating layer disposed on the first base electrode layer 50A and disposed on the first end face LS1, and a first Ni plating layer 62A and a first Sn plating layer 63A disposed on the first Cu plating layer 61A as an outer plating layer, and the second external electrode 40B has a second base electrode layer 50B, an inner plating layer disposed on the second base electrode layer 50B and disposed on the second end face LS2. The first base electrode layer 50A and the second base electrode layer 50B are respectively the outer plating layers of the second Cu plating layer 61B, the first Ni plating layer 62B and the second Sn plating layer 63B disposed on the second Cu plating layer 61B, the first base electrode layer 50A and the second base electrode layer 50B are respectively the first thin film layer 51A and the second thin film layer 51B containing at least one metal selected from the group of metals including Mg, Al, Ti, W, Cr, Cu, Ni, Ag, Co, Mo and V, and the inner plating layer contains the first Cu plating layer 61A and the second Cu plating layer 61B.

[0244] Therefore, the first Cu plating layer 61A and the second Cu plating layer 61B of the inner plating layer can suppress the erosion of the first base electrode layer 50A and the second base electrode layer 50B by the solder during the mounting of the multilayer ceramic capacitor 1. Furthermore, since the first thin film layer 51A and the second thin film layer 51B can be formed by a thin film formation method such as sputtering or vapor deposition, the first base electrode layer 50A and the second base electrode layer 50B can be easily formed.

[0245] In the multilayer ceramic capacitor 1 according to the embodiment, preferably, the outer plating layer of the first external electrode 40A includes a first Ni plating layer 62A and a first Sn plating layer 63A disposed on the first Ni plating layer 62A, and the outer plating layer of the second external electrode 40B includes a second Ni plating layer 62B and a second Sn plating layer 63B disposed on the second Ni plating layer 62B.

[0246] This improves the wettability of the solder when mounting the multilayer ceramic capacitor 1, making it easier to mount the multilayer ceramic capacitor 1.

[0247] [Example]

[0248] Hereinafter, embodiments of the present invention will be described. As shown in Table 1, test examples 1 to 13, were prepared in the required quantities having the same... Figures 1 to 9BThe multilayer ceramic capacitor 1 of the above-described embodiment has the same structure, but the dimensions e1 and e2 are changed. All multilayer ceramic capacitors manufactured are of the LW inverted type, and two types of multilayer ceramic capacitors were manufactured with capacitor dimensions of "1005" (W×L = 1.0mm × 0.5mm) and capacitor dimensions of "0603" (W×L = 0.6mm × 0.3mm). Table 1 shows the dimensions e1 and e2, the ratio of dimension e1 to the length direction L of the multilayer, and the ratio of dimension e2 to the length direction L of the multilayer for test examples 1 to 13, respectively. Furthermore, hereinafter, the ratio of dimension e1 to the length direction L of the multilayer will sometimes be simply referred to as "the ratio of dimension e1", and the ratio of dimension e2 to the length direction L of the multilayer will sometimes be simply referred to as "the ratio of dimension e2".

[0249] In addition, the specific dimensions and electrical characteristics of the 1005-size and 0603-size multilayer ceramic capacitors manufactured this time are shown in Table 2.

[0250] [Table 1]

[0251]

[0252] [Table 2]

[0253]

[0254] Test Examples 1, 2, and 8 are comparative examples where both the ratio of dimension e1 and the ratio of dimension e2 are below the scope of the present invention. Test Examples 7, 12, and 13 are comparative examples where both the ratio of dimension e1 and the ratio of dimension e2 are above the scope of the present invention. Test Examples 3 to 6 and Test Examples 9 to 11 are embodiments of the present invention where both the ratio of dimension e1 and the ratio of dimension e2 are within the scope of the present invention.

[0255] The mechanical strength test and moisture load test were conducted on the multilayer ceramic capacitors of Test Examples 1 to 13.

[0256] (Mechanical strength test)

[0257] like Figure 19As shown, the multilayer ceramic capacitor 1 is mounted onto one side of a mounting substrate 100 with a thickness of 1.6 mm using solder paste. Next, the substrate 100 is supported on a pair of rollers 101, and a load is applied to the other side of the substrate 100 without the multilayer ceramic capacitor 1 mounted, using a pressure bar 102 with a radius of curvature of 1 mm at a speed of 1.0 mm / s, thereby applying mechanical pressure to the multilayer ceramic capacitor 1. At this time, the bending amount of the substrate 100 is set to 3 mm, and the substrate 100 is bent after 5 ± 1 seconds.

[0258] Next, the laminated ceramic capacitor 1 removed from the substrate 100 was cross-sectionally ground to observe whether any cracks had formed inside. Regarding the number of tests, 10 tests were conducted for each case, and the presence of cracks was observed in at least one of the four cross-sections shown below; those with cracks were counted.

[0259] • An LT section that just exposes the internal electrode layer 30, formed by grinding the multilayer ceramic capacitor 1 from the first side WS1 or the second side WS2 to reduce the length in the width direction W.

[0260] • The multilayer ceramic capacitor 1 is ground from the first side WS1 or the second side WS2 to reduce the length in the width direction W, so that the length in the width direction W reaches 1 / 2 of the LT section.

[0261] • An LW profile that just exposes the internal electrode layer 30 when the length in the height direction T is reduced by grinding the multilayer ceramic capacitor 1 from the first main surface TS1 or the second main surface TS2.

[0262] • The stacked ceramic capacitor 1 is ground from the first main surface TS1 or the second main surface TS2 to reduce the length in the height direction T, so that the length T in the height direction reaches 1 / 2 of the LW profile.

[0263] (Moisture load test)

[0264] The moisture load test is conducted under high humidity conditions with an applied voltage load to investigate whether the electrical characteristics exhibit changes exceeding a specified limit. The following method was used: A multilayer ceramic capacitor, assembled with a specified fixture, was placed in a test chamber at 85% relative humidity and 85°C, and a rated voltage of 6.3V was applied to the capacitor for 1000 hours. Twenty tests were performed for each test case. The insulation resistance of the tested multilayer ceramic capacitor was measured and set to 1.0 × 10⁻⁶. 6 [Q] The following multilayer ceramic capacitors are counted as multilayer ceramic capacitors whose moisture resistance has deteriorated.

[0265] The results of the mechanical strength test and the moisture load test are recorded in Table 1.

[0266] Table 1 shows that a smaller ratio of dimension e1 increases the likelihood of crack formation. This is presumably due to the reduced area ratio of the internal electrode layers within the multilayer ceramic capacitor, leading to decreased mechanical strength. Conversely, a larger ratio of dimension e2 increases the likelihood of deteriorated moisture resistance. This is believed to be because the distance along the longitudinal direction L between the first and second external electrodes becomes shorter, resulting in a transition and thus reducing moisture resistance.

[0267] According to Table 1, in Test Examples 1-7 of the 1005 size, Test Example 1, where both the ratio of the internal electrode layer size e1 and the ratio of the internal electrode layer size e2 are below the scope of the present invention, exhibited a multilayer ceramic capacitor with cracks. Furthermore, in Test Example 7 of Test Examples 1-7 of the 1005 size, where both the ratio of the internal electrode layer size e1 and the ratio of the internal electrode layer size e2 are above the scope of the present invention, exhibited a multilayer ceramic capacitor with deteriorated moisture resistance. In contrast, in Test Example 2, a comparative example, no cracks occurred and no moisture resistance deteriorated. On the other hand, in Test Examples 8-13 of the 0603 size, Test Example 8, a comparative example where both the ratio of the internal electrode layer size e1 and the ratio of the internal electrode layer size e2 are below the scope of the present invention, exhibited a multilayer ceramic capacitor with cracks. Furthermore, in Test Example 13 of Test Examples 8-13 of the 1005 size, a comparative example where both the ratio of the internal electrode layer size e1 and the ratio of the internal electrode layer size e2 are above the scope of the present invention, exhibited a multilayer ceramic capacitor with deteriorated moisture resistance. In addition, no cracks or deterioration in moisture resistance occurred in comparative example 12.

[0268] In Comparative Example 2, no cracks or deterioration in moisture resistance occurred. However, in Comparative Example 8, which had a ratio of size e1 and size e2 similar to that of Comparative Example 2, a multilayer ceramic capacitor exhibited cracks. Therefore, it can be said that, based on capacitor size, multilayer ceramic capacitors with ratios of size e1 and size e2 similar to those in Comparative Examples 2 and 8 are at least susceptible to cracking. Furthermore, in Comparative Example 12, no cracks or deterioration in moisture resistance occurred. However, in Comparative Example 7, which had a ratio of size e1 and size e2 similar to that of Comparative Example 12, a multilayer ceramic capacitor exhibited deteriorated moisture resistance. Therefore, it can be said that, based on capacitor size, multilayer ceramic capacitors with ratios of size e1 and size e2 similar to those in Comparative Examples 7 and 12 are at least susceptible to deterioration in moisture resistance.

[0269] As described above, taking into account Test Examples 1 to 13, in the LW inverted type multilayer ceramic capacitor, the ratio of size e1 is preferably 10% or more and 44% or less, and the ratio of size e2 is preferably 17% or more and 48% or less.

Claims

1. A multilayer ceramic capacitor, comprising: A laminate comprising a plurality of dielectric layers and a plurality of internal electrode layers alternately stacked in a height direction, and having a first main surface and a second main surface opposite each other in the height direction, a first end surface and a second end surface opposite each other in a length direction orthogonal to the height direction, and a first side surface and a second side surface opposite each other in a width direction orthogonal to both the height direction and the length direction; and A pair of external electrodes are respectively disposed at both ends of the laminate along its length, spaced apart from each other. The internal electrode layer comprises: A first internal electrode layer, led out to the first end face; and The second internal electrode layer is led out to the second end face. The external electrode has: A first external electrode, connected to the first internal electrode layer, is disposed on the first end face, and is disposed on at least one of a portion of the first main surface and a portion of the second main surface; and A second external electrode, connected to the second internal electrode layer, is disposed on the second end face, and is disposed on at least one of a portion of the first main surface and a portion of the second main surface. In the stacked ceramic capacitor Let the length in the longitudinal direction connecting the first end face and the second end face of the laminate be l, the length in the width direction connecting the first side face and the second side face be w, and the length in the height direction connecting the first main face and the second main face be t. At this point, the dimensional relationship is w > l > t. The first inner electrode layer is located inside the laminate and has: a first opposing electrode portion opposite to the second inner electrode layer; and a first lead-out portion, the width of which is larger than the first opposing electrode portion, and configured to be exposed on a first end face, a portion of the first side face, and a portion of the second side face. The second inner electrode layer is located inside the laminate and has: a second opposing electrode portion opposite to the first inner electrode layer; and a second lead-out portion, the width of which is larger than the second opposing electrode portion, and configured to be exposed on the second end face, a portion of the first side face, and a portion of the second side face. Let e1 be the length of the exposed side portion of the first lead-out portion and the second lead-out portion, which is a portion exposed on the first side surface and a portion on the second side surface, respectively. In this case, e1 is 10% or more and 44% or less relative to the length of the laminate. Let e2 be the length in the length direction of the first external electrode disposed on at least one of the portions of the first main surface and the second main surface, from the front end on the second end face to the end on the first end face, and the length in the length direction of the second external electrode disposed on at least one of the portions of the first main surface and the second main surface, from the front end on the first end face to the end on the second end face. In this case, e2 is more than 17% and less than 48% of the dimension in the length direction of the laminate.

2. The multilayer ceramic capacitor according to claim 1, wherein, The length in the height direction connecting the first main surface and the second main surface is less than 150 μm.

3. The multilayer ceramic capacitor according to claim 1, wherein, The length in the height direction connecting the first main surface and the second main surface is less than 100 μm.

4. The multilayer ceramic capacitor according to any one of claims 1 to 3, wherein, The external electrode has: a base electrode layer; an inner plating layer disposed on the base electrode layer and respectively disposed on the first end face and the second end face; and an outer plating layer disposed on the plating layer. The substrate electrode layer is a thin film layer comprising at least one metal selected from the group consisting of Mg, Al, Ti, W, Cr, Cu, Ni, Ag, Co, Mo, and V. The inner plating layer includes a Cu plating layer.

5. The multilayer ceramic capacitor according to claim 4, wherein, The outer plating layer includes a Ni plating layer and a Sn plating layer disposed on the Ni plating layer.

6. The multilayer ceramic capacitor according to any one of claims 1 to 5, wherein, The first external electrode and the second external electrode each have a side-covered portion that covers at least one of the first side and the second side of the laminate. A recess is formed in the central portion of the side covering portion in the height direction, which is recessed from the inside to the outside in the length direction.

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