Transistor manufacturing method, transistor, and electronic device

Abstract

The application provides a transistor preparation method, a transistor and an electronic device. The preparation method comprises the following steps: providing a substrate; the substrate comprises first gates arranged at intervals along a first direction parallel to a first surface of the substrate, and a plurality of second gates arranged at intervals between adjacent first gates; the substrate comprises isolation structures arranged one by one with the first gates; a part of the isolation structures is removed to form a groove by taking the first gates as a mask; a cross section of the groove is a right-angled trapezoid, and an opening size of the groove gradually decreases along a second direction away from the first gates; after forming an epitaxial layer filling the groove and having a top surface flush with a top surface of the substrate, a sigma-shaped germanium-silicon layer is formed in the substrate between the first gates and the second gates; and the right-angled side length of the groove is related to a width of the germanium-silicon layer, a tip end depth and a pitch width. The application can solve the problems of poor symmetry and virtual connection of a device structure in an embedded germanium-silicon process, thereby improving the performance of the device.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a method for preparing a transistor, a transistor, and an electronic device. Background Technology

[0002] With the continuous development of semiconductor technology, the channel and gate dimensions of integrated circuit transistors have been continuously reduced proportionally, effectively improving the transistor integration density, computing speed, and integration level of chips. However, as process technology nodes continue to shrink, the short-channel effect continues to intensify, resulting in a decrease in transistor carrier mobility and insufficient conduction drive capability.

[0003] Source-drain embedded silicon-germanium strain technology, an important technology in integrated circuit manufacturing, refers to the introduction of lattice strain in the device channel through reasonable device design, which changes the band structure of silicon material in the channel to enhance carrier mobility and improve device speed.

[0004] However, the related germanium-silicon embedding process is difficult to adapt to miniaturized device structures, and is prone to derivative problems such as poor device structure symmetry and loose connections. Summary of the Invention

[0005] Therefore, it is necessary to provide a transistor fabrication method, transistor, and electronic device to address the technical problems in the existing technology, which can at least solve problems such as poor device structure symmetry and poor connection in embedded germanium-silicon processes, thereby improving device performance.

[0006] In a first aspect, this application provides a method for fabricating a transistor, comprising: providing a substrate; the substrate including first gates spaced apart along a first direction parallel to a first surface of the substrate, and a plurality of second gates spaced apart between adjacent first gates; and the substrate including an isolation structure disposed one-to-one with the first gates;

[0007] Using the first gate as a mask, part of the isolation structure is removed to form a groove; the cross section of the groove perpendicular to the substrate is a right trapezoid, and its opening size gradually decreases along a second direction away from the first gate;

[0008] After forming an epitaxial layer that fills the groove and whose top surface is flush with the top surface of the substrate, a sigma-type germanium-silicon layer is formed in the substrate between the first gate and the second gate.

[0009] The length of the right-angled side of the groove is related to the width of the germanium-silicon layer, the tip depth, and the pitch width; the width is used to characterize the dimension along the first direction, and the depth is used to characterize the dimension along the second direction.

[0010] In the above embodiments, selective etching removes part of the isolation structure to form a trench, and then an epitaxial layer is fabricated within the trench, with its upper surface flush with the substrate and integrally forming the substrate structure. After process modification, the top width of the isolation structure is narrowed, reserving sufficient lateral process space for sigma trench etching. This effectively improves the asymmetry problem of sigma trench etching caused by space constraints, allowing the subsequently formed germanium-silicon layer to be formed completely and symmetrically, reducing the risk of virtual connection between the source / drain and the channel, and introducing lattice strain more uniformly. To a certain extent, this improves carrier mobility and device driving capability while maintaining better compatibility with the miniaturized device structure.

[0011] In some embodiments, the length of the right-angled side of the groove is:

[0012] h = t + (y·tanθ);

[0013] (m-1)·pitch+da=2y;

[0014] pitch = c + d;

[0015] Where θ is the angle between the right-angled side and the {111} crystal plane, with a value ranging from 35.25° to 35.3°, m is the number of sigma-type germanium-silicon layers to be prepared, y is the required etching width at the tip of the germanium-silicon layer, h is the length of the right-angled side, pitch is the pitch width, a is the spacing between adjacent isolation structures, d is the width of the germanium-silicon layer, c is the spacing between adjacent germanium-silicon layer tips, and t is the tip depth of the germanium-silicon layer.

[0016] In some embodiments, the first gate and the second gate include a gate dielectric stack, a gate conductive layer and a gate dielectric layer arranged sequentially along a second direction.

[0017] The gate dielectric stack includes a nitride layer and an oxide layer arranged sequentially along the second direction;

[0018] Remove some of the isolation structures, including:

[0019] Using a nitride layer as a mask, a portion of the isolation structure is removed by selective etching with a target gas to form grooves on both sides of the first gate.

[0020] In some embodiments, the target gas includes a mixed gas doped with an inert gas; the mixed gas includes a fluorine-containing gas and a hydrogen-containing gas.

[0021] In some embodiments, forming an epitaxial layer includes:

[0022] A selective epitaxial growth process is used to form an epitaxial material layer extending away from the second direction on the exposed surfaces of the groove and the substrate;

[0023] After planarizing the epitaxial material layer, atomic layer etching is used to remove the epitaxial material layer whose top surface is higher than the bottom surface of the gate dielectric layer. The remaining epitaxial material layer constitutes the epitaxial layer.

[0024] In some embodiments, forming a sigma-type germanium-silicon layer includes:

[0025] After forming a mask layer covering the outer surfaces of the first gate and the second gate, a sigma trench is formed between the first gate and the second gate based on the mask layer;

[0026] After performing a pre-cleaning process on the sigma trench, an embedded germanium-silicon layer is formed in the sigma trench;

[0027] After forming the germanium-silicon layer, it includes:

[0028] After forming a capping layer on the top surface of the germanium-silicon layer, the mask layer is removed.

[0029] In a second aspect, this application provides a transistor, including a substrate; the substrate includes isolation structures spaced apart along a first direction parallel to the top surface of the substrate, and an active region located between adjacent isolation structures;

[0030] The top surface of the isolation structure is provided with a first gate in a one-to-one manner, and the top surface of the active region includes second gates arranged at intervals along a first direction.

[0031] The isolation structure includes a first part and a second part arranged sequentially along a second direction away from the first gate; the width of the first part is smaller than the width of the first gate, and the bottom surface of the first part is located inside the top surface of the second part; the width is used to characterize the dimension along the first direction;

[0032] The active region includes sigma-type germanium-silicon layers spaced apart along a first direction;

[0033] The depth of the first part is related to the width of the germanium-silicon layer, the tip depth, and the pitch width; the depth is used to characterize the dimension along the second direction.

[0034] In the above embodiments, the first part of the lateral thinning in the isolation structure can reserve the etching space required for the sigma trench, realize the symmetrical and regular preparation of the sigma-type germanium-silicon layer, optimize the strain introduction effect of germanium-silicon, and improve the electrical performance of the transistor.

[0035] In some embodiments, the depth of the first part is:

[0036] h = t + (y tan 35.275°);

[0037] (m-1)·pitch+da=2y;

[0038] pitch = c + d;

[0039] Where θ is the angle between the vertical direction and the {111} crystal plane, ranging from 35.25° to 35.3°, m is the number of sigma-type germanium-silicon layers to be prepared, y is the required etching width at the tip of the germanium-silicon layer, h is the depth of the first part, pitch is the pitch width, a is the spacing between adjacent isolation structures, d is the width of the germanium-silicon layer, c is the spacing between adjacent germanium-silicon layer tips, and t is the tip depth of the germanium-silicon layer; the depth is used to characterize the dimension along the second direction.

[0040] In some embodiments, the first gate and the second gate include a gate dielectric stack, a gate conductive layer and a gate dielectric layer arranged sequentially along a second direction;

[0041] A capping layer is provided on the top surface of the germanium-silicon layer.

[0042] Thirdly, this application also provides an electronic device, comprising: a transistor fabricated by the fabrication method described in any of the above embodiments; or a transistor as described in the above embodiments. This electronic device, transistor, and transistor fabrication method are based on the same inventive concept, and therefore possess all the advantages of transistors and their fabrication methods, which will not be elaborated upon here.

[0043] The transistor fabrication method, transistor, and electronic device provided in this application have the following unexpected technical effects:

[0044] By partially removing the isolation structure and backfilling the epitaxial layer, the size of the first part at the top of the isolation structure is appropriately reduced. This allows for more margin within the limited device area for subsequent etching of sigma trenches, effectively solving the trench morphology deviation problem caused by insufficient etching space. This promotes a more symmetrical growth morphology of the germanium-silicon layer in the source and drain regions. Thanks to the well-formed germanium-silicon layer, the lattice strain distribution within the channel is more uniform, effectively improving the carrier mobility and driving capability of the transistor without significantly changing the integration density of existing processes.

[0045] Furthermore, by establishing a quantitative correlation between the geometry parameters of the groove (or the first part) and the feature dimensions of the germanium-silicon layer, an adjustable basis is provided for device design at different nodes, thereby improving the overall robustness of the embedded germanium-silicon process. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 This is a schematic diagram of the longitudinal section of the structure obtained by each step of the embedded germanium-silicon process in the comparative embodiment.

[0048] Figure 2 This is a schematic flowchart of a transistor fabrication method provided in one embodiment of this application;

[0049] Figure 3 This is a schematic diagram of the structure obtained after forming the isolation structure in one embodiment of this application;

[0050] Figure 4 This is a schematic diagram of the structure obtained after forming the first gate and the second gate in one embodiment of this application;

[0051] Figure 5 This is a schematic diagram of the structure obtained after forming the groove in one embodiment of this application;

[0052] Figure 6 This is a schematic diagram illustrating the calculation principle of the required etching width y at the tip of the germanium-silicon layer in one embodiment of this application;

[0053] Figure 7 This is a schematic diagram of the structure obtained after forming an epitaxial material layer in one embodiment of this application;

[0054] Figure 8 This is a schematic diagram of the structure obtained after forming the epitaxial layer in one embodiment of this application;

[0055] Figure 9 This is a schematic diagram of the structure obtained after forming sigma trenches in one embodiment of this application;

[0056] Figure 10 This is a schematic diagram of the structure obtained after forming a germanium-silicon layer and a capping layer in one embodiment of this application;

[0057] Figure 11 This is a schematic diagram of the structure obtained after removing the mask layer in one embodiment of this application;

[0058] Figure 12 This is a schematic diagram of a transistor structure provided in one embodiment of this application.

[0059] Explanation of reference numerals in the attached figures:

[0060] 10. Substrate; 10a. First surface; 101. Epitaxial material layer; 102. Mask layer; 10b. Epitaxial layer; 11. Isolation structure; 11a. First part; 11b. Second part; G1. First gate; G2. Second gate; 21. Gate dielectric layer; 22. Gate conductive layer; 23. Gate dielectric stack; 231. Oxide layer; 232. Nitride layer; 30. Trench; 401. Sigma trench; 41. Germanium-silicon layer; 42. Cap layer. Detailed Implementation

[0061] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0062] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0063] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0064] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0065] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0066] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of this application, thus allowing for variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of this application.

[0067] Source-drain embedded silicon-germanium (SiGe) strain technology can significantly improve carrier mobility, thereby improving device performance and operating speed. Figure 1 This is a cross-sectional schematic diagram of a key step in the embedded SiGe source / drain process. In this process, the active region within the N-well is first etched with trenches to form Sigma trenches for the epitaxial growth of SiGe. However, due to local overlap between the active region and the shallow trench isolation structure (as shown in the yellow box in the diagram), the trenches in the edge portion of the source / drain region cannot form a complete Sigma morphology.

[0068] Compared to standard complete trenches, the epitaxial growth window of these incomplete trenches is limited, and the difference in growth rate across crystal orientations causes the SiGe layer to form a beveled morphology. In addition, due to the limitations of trench size and growth window, the overall height of the epitaxial layer is insufficient to fill the trench, affecting the strain introduction effect of the device, as well as the alignment and fabrication of subsequent contact holes, metal interconnects, and other processes, negatively impacting the device yield and long-term reliability.

[0069] Based on this, this application provides a method for fabricating a transistor, the specific process of which is as follows: Figure 2 As shown, it includes steps S102-S106.

[0070] Step S102: Provide a substrate; the substrate includes first gates spaced apart along a first direction parallel to a first surface of the substrate, and a plurality of second gates spaced apart between adjacent first gates; the substrate includes an isolation structure disposed one-to-one with the first gates.

[0071] Step S104: Using the first gate as a mask, remove part of the isolation structure to form a groove; the cross section of the groove perpendicular to the substrate is a right trapezoid, and its opening size gradually decreases along a second direction away from the first gate.

[0072] Step S106: After forming an epitaxial layer that fills the groove and whose top surface is flush with the top surface of the substrate, a sigma-type germanium-silicon layer is formed in the substrate between the first gate and the second gate; wherein, the right-angled side length of the groove is related to the width of the germanium-silicon layer, the tip depth, and the pitch width.

[0073] For ease of understanding, the substrate in this embodiment may include a first surface located on the front side and a back surface, i.e., a second surface, opposite to the front side. Ignoring the flatness of the first and second surfaces, a first direction parallel to the first surface is defined, and directions toward the substrate include a second direction perpendicular to the first surface of the substrate. Intersecting (e.g., perpendicular) first and third directions are defined on the top and bottom surfaces of the substrate (i.e., the plane in which the substrate lies). The first, second, and third directions may be mutually perpendicular. In this embodiment, the first direction is defined as the Y-axis direction, and the second direction is defined as the Z-axis direction.

[0074] Below, in conjunction with Figures 3-11 An exemplary method for manufacturing a transistor according to this application is described.

[0075] Please see Figures 3-4 In some embodiments, step S102 includes:

[0076] Step S1022: Provide a substrate 10, coat a photoresist layer on the first surface 10a of the substrate 10 and pattern it, then form isolation trenches based on the patterned photoresist layer using any etching process. Subsequently, use a deposition process and a chemical mechanical polishing process to form isolation structures 11 located within the substrate and spaced apart along the OY direction, resulting in the structure shown below. Figure 3 As shown.

[0077] For example, substrate 10 includes a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulating layer beneath a thin semiconductor layer that serves as the active layer of the SOI substrate. The semiconductor of the active layer and the bulk semiconductor typically include the crystalline semiconductor material silicon, but may also include one or more other semiconductor materials, oxide semiconductors, or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or mixed-orientation substrates. In this embodiment, the material of substrate 10 includes silicon (Si).

[0078] Step S1024: Based on the existing structure, a gate dielectric layer 21, a gate conductive layer 22, and a gate dielectric stack 23 arranged along the ZO direction (opposite to the OZ direction) are sequentially prepared by a deposition process. The patterning process is then completed using an etching process to form a first gate G1 disposed on the top surface of the isolation structure 11, and second gates G2 arranged between adjacent first gates G1 at intervals along the OY direction, resulting in the structure shown below. Figure 4 As shown.

[0079] For example, the gate dielectric layer 21 may be formed using a material with a high k dielectric constant. For example, the material of the gate dielectric layer 21 includes: aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), strontium titanium oxide (SrTiO3), or combinations thereof.

[0080] For example, the gate conductive layer 22 comprises polysilicon (poly-Si).

[0081] For example, the gate dielectric stack 23 includes an oxide layer 231 along the ZO direction and a nitride layer 232. The nitride layer 232 is made of silicon nitride (SiN). x ).

[0082] Please see Figure 5 In step S104, using the nitride layer 232 as a mask, the isolation structure is dry-etched with fluorine-containing gas and hydrogen-containing gas doped with inert gas to form grooves 30 on both sides of the first gate; wherein, the cross section of the groove 30 in the YOZ plane is a right trapezoid, and its opening size gradually decreases along the OZ direction.

[0083] For example, the power of the inductively coupled plasma (ICP) source is set to 1000-1500W, the substrate bias power is controlled at 100W-200W, the chamber pressure is maintained at 4mTorr-8mTorr, and the temperature is controlled at -10℃-0℃.

[0084] The etching gas is a mixture of CHF3 / CF4 / H2 / Ar, with the flow rates of each component controlled as follows: CHF3 40-60 sccm, CF4 10-20 sccm, H2 10-20 sccm, and Ar 100-120 sccm, maintaining the total gas flow rate at 160-200 sccm. The introduction of H2 can consume fluoride ions in the system to form HF, significantly suppressing the chemical etching of the substrate (Si) and the gate conductive layer (poly-Si), achieving high selectivity etching of SiO2 / Si. Ar serves as a dilution and auxiliary gas, used to stabilize the plasma and enhance the directionality of ion bombardment.

[0085] Furthermore, Figure 6 A schematic diagram illustrating the calculation principle of the required etching width y at the tip of a sigma-type germanium-silicon layer is shown, such as... Figure 6 As shown, the fabrication of four complete sigma-type germanium-silicon layers is taken as an example. The design has an active region (AA) width of a, a sigma trench width of d, c being the spacing between adjacent germanium-silicon layer tips, a tip depth of t, and a pitch width of c + d.

[0086] After TMAH wet etching, the sigma trench stops at the intersecting {111} crystal plane. The theoretical angle between {111} and the top plane {100} is 54.74°, corresponding to a theoretically calculated trench interior angle α of 109.48°. Due to process limitations, the actual measured angle range is 109.40°~109.50°. Based on the symmetry of the sigma trench shape, θ = 90° - (α / 2), that is, the value range of θ is 35.25°-35.3°. In this embodiment, α is only a typical engineering reference value of 109.45° within this range, and θ = 35.275°.

[0087] When m=4, 3·pitch+da=2y, y>0, indicating the existence of incomplete sigma trenches. To satisfy the required etching width y for the germanium-silicon layer tip, the formula for calculating the required etching depth h of the trench (i.e., the length of the right-angled side of the trench) is:

[0088] h = t + (y · tan35.275°);

[0089] Please see Figures 7-11 In some embodiments, step S106 includes:

[0090] Step S1062: Using a selective epitaxial growth process, an epitaxial material layer 101 extending along the ZO direction is formed on the exposed surfaces of the groove 30 and the substrate 10, with its top surface higher than the top surface of the nitride layer 232. Then, a chemical mechanical polishing process is used to make the top surface of the epitaxial material layer 101 flat, as shown in the specific structure. Figure 7 As shown.

[0091] Step S1064: Using atomic layer etching, the epitaxial material layer whose top surface is higher than the top surface of the gate dielectric layer 21 is removed to form an epitaxial layer 10b filling the groove, the specific structure of which is as follows. Figure 8 As shown.

[0092] For example, in atomic layer etching, halogen gases such as Cl2, BCl3, and SF6 are used as reaction precursors to form an extremely thin reaction layer (such as SiCl3) on the silicon surface. x This process has a self-limiting characteristic, meaning that the reaction will automatically stop when the surface reaction reaches saturation, avoiding over-reaction. Thanks to its high selectivity and high directionality, this process involves almost no lateral etching during the vertical removal of the epitaxial material layer and the reaction layer formed on its surface. Simultaneously, the reaction layer formed on the polysilicon surface acts as a protective layer, preventing damage to the polysilicon.

[0093] Atomic layer etching typically achieves a single-cycle etching depth of only 0.1 nm to 1 nm. This allows for precise control of the etching depth and endpoint, ensuring that only the required epitaxial layer thickness remains within the groove, avoiding damage to the underlying substrate. Once etching is complete, high-energy ion bombardment (such as Ar) can be applied. + Plasma or heat treatment can be used to selectively desorb and remove the surface-modified atomic layers.

[0094] Step S1066: Form a mask layer 102 covering the outer surfaces of the first gate G1 and the second gate G2. Based on the mask layer 102, an etching process is used to form spaced sigma trenches 401 in the substrate 10 between the first gate G1 and the second gate G2, as shown in the specific structure. Figure 9 As shown.

[0095] Step S1068: After performing a pre-cleaning process on the sigma trench 401, an embedded germanium-silicon layer 41 and a capping layer 42 covering the top surface of the germanium-silicon layer 41 are formed in the sigma trench 401 using a selective epitaxial growth process, as detailed below. Figure 10 As shown. Removing mask layer 102 yields the following structure. Figure 11 As shown.

[0096] Please see Figure 12In some embodiments, this application also provides a transistor, including a substrate 10, an isolation structure 11, and an active region. A first gate G1 is disposed one-to-one on the top surface of the isolation structure 11, and second gates G2 are disposed on the top surface of the active region at intervals along the OY direction. Between the first gate G1 and the second gate G2, and between adjacent second gates G2, the substrate 10 includes a sigma-type germanium-silicon layer 41, and a capping layer 42 is disposed on the top surface of the germanium-silicon layer 41.

[0097] For example, the first gate G1 and the second gate G2 include a gate dielectric stack 23, a gate conductive layer 22 and a gate dielectric layer 21 arranged sequentially along the OZ.

[0098] The isolation structure 11 consists of a first part 11a and a second part 11b arranged sequentially along the OZ direction. The bottom surface of the first part 11a is connected to the top surface of the second part 11b. The width of the first part 11a is smaller than the width of the first gate G1, and its depth satisfies the following relationship:

[0099] h = t + (y·tanθ);

[0100] (m-1)·pitch+da=2y;

[0101] pitch = c + d;

[0102] Where θ is the angle between the vertical direction and the {111} crystal plane, ranging from 35.25° to 35.3°, m is the number of sigma-type germanium-silicon layers to be prepared, y is the required etching width at the tip of the germanium-silicon layer, h is the depth of the first part, pitch is the pitch width, a is the spacing between adjacent isolation structures, d is the width of the germanium-silicon layer, c is the spacing between adjacent germanium-silicon layer tips, and t is the tip depth of the germanium-silicon layer. For a detailed schematic diagram of the calculation principle, please refer to [link to schematic diagram]. Figure 6 .

[0103] In the above embodiments, by defining the geometric relationship between the depth of the first part of the isolation structure and the tip depth, width, and spacing of the sigma-type germanium-silicon layer, it can be ensured that the laterally thinned first part of the isolation structure can reserve the etching space required for the sigma trench when forming the sigma-type germanium-silicon layer. By appropriately narrowing the first part of the isolation structure (removing only the non-functional neutral region), the lateral width of the active region is effectively increased without affecting device performance or causing breakdown. This allows the germanium-silicon layer adjacent to the isolation structure to maintain a complete sigma morphology, further improving carrier mobility and device electrical properties.

[0104] In some embodiments, this application also provides an electronic device, including a transistor as described in any of the foregoing embodiments; or a transistor fabricated using the fabrication method described in any of the foregoing embodiments.

[0105] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0106] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for fabricating a transistor, characterized in that, include: A substrate is provided; the substrate includes first gates spaced apart along a first direction parallel to a first surface of the substrate, and a plurality of second gates spaced apart between adjacent first gates; the substrate includes an isolation structure disposed one-to-one with the first gates; Using the first gate as a mask, a portion of the isolation structure is removed to form a groove; the cross-section of the groove perpendicular to the substrate is a right trapezoid, and its opening size gradually decreases along a second direction away from the first gate; After forming an epitaxial layer that fills the groove and whose top surface is flush with the top surface of the substrate, a sigma-type germanium-silicon layer is formed in the substrate between the first gate and the second gate. The length of the right-angled side of the groove is related to the width, tip depth, and pitch width of the germanium-silicon layer; the width is used to characterize the dimension along the first direction, and the depth is used to characterize the dimension along the second direction; the second direction is perpendicular to the first direction. The length of the right-angled side of the groove is: h = t + (y·tanθ); (m-1)·pitch+da=2y; pitch = c + d; Where θ is the angle between the right-angled side and the {111} crystal plane, with a value ranging from 35.25° to 35.3°; m is the number of sigma-type germanium-silicon layers to be prepared; y is the required etching width at the tip of the germanium-silicon layer; h is the length of the right-angled side; pitch is the pitch width; a is the spacing between adjacent isolation structures; d is the width of the germanium-silicon layer; c is the spacing between adjacent germanium-silicon layer tips; and t is the tip depth of the germanium-silicon layer.

2. The preparation method according to claim 1, characterized in that, The first gate and the second gate include a gate dielectric stack, a gate conductive layer and a gate dielectric layer arranged sequentially along the second direction; The gate dielectric stack includes a nitride layer and an oxide layer arranged sequentially along the second direction; Removing part of the isolation structure includes: Using the nitride layer as a mask, a portion of the isolation structure is removed by selective etching with a target gas to form grooves on both sides of the first gate.

3. The preparation method according to claim 2, characterized in that, The target gas includes a mixed gas doped with an inert gas; the mixed gas includes a fluorine-containing gas and a hydrogen-containing gas.

4. The preparation method according to claim 2, characterized in that, Forming the epitaxial layer includes: A selective epitaxial growth process is used to form an epitaxial material layer extending away from the second direction on the exposed surfaces of the groove and the substrate; After planarizing the epitaxial material layer, an atomic layer etching process is used to remove the epitaxial material layer whose top surface is higher than the bottom surface of the gate dielectric layer, and the remaining epitaxial material layer constitutes the epitaxial layer.

5. The preparation method according to any one of claims 1-4, characterized in that, Forming the sigma-type germanium-silicon layer includes: After forming a mask layer covering the outer surfaces of the first gate and the second gate, a sigma trench is formed between the first gate and the second gate based on the mask layer; After performing a pre-cleaning process on the sigma trench, an embedded germanium-silicon layer is formed in the sigma trench; After forming the germanium-silicon layer, the process includes: After forming a capping layer on the top surface of the germanium-silicon layer, the mask layer is removed.

6. A transistor, characterized in that, Includes a substrate; the substrate includes isolation structures spaced apart along a first direction parallel to a first surface of the substrate, and an active region located between adjacent isolation structures; The top surface of the isolation structure is provided with a first gate in a one-to-one manner, and the top surface of the active region includes second gates arranged at intervals along the first direction. The isolation structure includes a first part and a second part arranged sequentially along a second direction away from the first gate; the width of the first part is smaller than the width of the first gate, and the bottom surface of the first part is located within the top surface of the second part; the width is used to characterize the dimension along the first direction; The active region includes sigma-type germanium-silicon layers spaced apart along the first direction. The depth of the first part is related to the width of the germanium-silicon layer, the tip depth, and the pitch width; the depth is used to characterize the dimension along the second direction; the second direction is perpendicular to the first direction; The depth of the first part is: h = t + (y·tanθ); (m-1)·pitch+da=2y; pitch = c + d; Where θ is the angle between the vertical direction and the {111} crystal plane, ranging from 35.25° to 35.3°, m is the number of sigma-type germanium-silicon layers to be prepared, y is the required etching width at the tip of the germanium-silicon layer, h is the depth of the first part, pitch is the pitch width, a is the spacing between adjacent isolation structures, d is the width of the germanium-silicon layer, c is the spacing between adjacent germanium-silicon layer tips, and t is the tip depth of the germanium-silicon layer; the depth is used to characterize the dimension along the second direction.

7. The transistor according to claim 6, characterized in that, The first gate and the second gate include a gate dielectric stack, a gate conductive layer and a gate dielectric layer arranged sequentially along the second direction; A capping layer is provided on the top surface of the germanium-silicon layer.

8. An electronic device, characterized in that, include: A transistor fabricated by the method of any one of claims 1-5; or The transistor as described in any one of claims 6-7.

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