Semiconductor device and method for manufacturing semiconductor device

Abstract

A transistor with good electric characteristics, a transistor with a large on-state current, or a transistor with small parasitic capacitance is provided. The present invention is a semiconductor device including an oxide semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer over the first conductive layer, a second insulating layer over the oxide semiconductor layer and the first insulating layer, and the third conductive layer over the second insulating layer, wherein the first insulating layer and the second conductive layer include a first opening portion at a position overlapping with the first conductive layer, the second conductive layer includes a first layer and a second layer covering a top surface and side surfaces of the first layer, the oxide semiconductor layer has a portion over the second layer, a portion over the first conductive layer in the first opening portion, a portion covering a side wall of the first insulating layer in the first opening portion, and a portion facing a side surface of the first layer with the second layer interposed therebetween in the first opening portion, and the third conductive layer faces the oxide semiconductor layer with the second insulating layer interposed therebetween in the first opening portion.

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device, a storage device, a display device, and an electronic device. Furthermore, another aspect of the present invention relates to a method for manufacturing a semiconductor device.

[0002] Note that one aspect of the present invention is not limited to the technical fields described above. Examples of technical fields encompassing one aspect of the present invention include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), and driving or manufacturing methods for the aforementioned devices.

[0003] In this specification, etc., a semiconductor device refers to a device that utilizes the properties of semiconductors, as well as circuits that include semiconductor elements (transistors, diodes, photodiodes, etc.) and devices that include such circuits. Furthermore, a semiconductor device refers to all devices capable of functioning by utilizing the properties of semiconductors. Examples of semiconductor devices include integrated circuits, chips containing integrated circuits, and electronic components that house chips in packages. In addition, storage devices, display devices, light-emitting devices, lighting devices, and electronic devices are themselves semiconductor devices, and sometimes all include semiconductor devices. Background Technology

[0004] In recent years, semiconductor devices have been developed, with LSIs, CPUs, and memory being the main components used in them. A CPU is an assembly of semiconductor elements that include integrated circuits (including transistors and memory) formed by processing semiconductor wafers to create chips and having electrodes as connection terminals.

[0005] Integrated circuits (IC chips) such as LSI, CPU, and memory are mounted on circuit boards, such as printed circuit boards, and are used as components of various electronic devices.

[0006] Furthermore, the technique of constructing transistors using semiconductor thin films formed on substrates with insulating surfaces has attracted attention. These transistors are widely used in electronic devices such as integrated circuits (ICs) and display devices. Silicon-based semiconductor materials are widely known as suitable for use in transistors. Among other materials, oxide semiconductors have also garnered interest.

[0007] Furthermore, it is known that the leakage current of transistors using oxide semiconductors is extremely small in the off state. For example, Patent Document 1 discloses a low-power CPU that utilizes the characteristic of low leakage current of transistors using oxide semiconductors. Furthermore, for example, Patent Document 2 discloses a storage device that utilizes the characteristic of low leakage current of transistors using oxide semiconductors to achieve long-term retention of stored content.

[0008] In recent years, with the miniaturization and weight reduction of electronic devices, the demand for further high-density integrated circuits has increased. Furthermore, there is a need to improve the productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technique in which multiple memory cells are stacked in an overlapping manner by layering a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film, thereby increasing the density of integrated circuits. Furthermore, Patent Document 4 discloses a technique for achieving high-density integrated circuits by arranging the channels of transistors using oxide semiconductor films longitudinally.

[0009] [Preliminary Technology Documents]

[0010] [Patent Literature]

[0011] [Patent Document 1] Japanese Patent Application Publication No. 2012-257187

[0012] [Patent Document 2] Japanese Patent Application Publication No. 2011-151383

[0013] [Patent Document 3] International Patent Application Publication No. 2021 / 053473

[0014] [Patent Document 4] Japanese Patent Application Publication No. 2013-211537

[0015] [Non-patent literature]

[0016] [Non-patent literature 1] M. Oota et al., “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig., 2019, pp. 50-53 Summary of the Invention

[0017] The technical problem that the invention aims to solve

[0018] One objective of this invention is to provide a transistor with good electrical characteristics. Another objective of this invention is to provide a transistor with a large on-state current. Another objective of this invention is to provide a transistor with low parasitic capacitance. Another objective of this invention is to provide a transistor, semiconductor device, memory device, or display device with high reliability. Another objective of this invention is to provide a transistor, semiconductor device, or memory device capable of miniaturization or high integration. Another objective of this invention is to provide a semiconductor device, memory device, or display device with low power consumption. Another objective of this invention is to provide a memory device with high operating speed. Another objective of this invention is to provide a display device with high resolution or high aperture ratio. Another objective of this invention is to provide a method for manufacturing the above-mentioned transistor, semiconductor device, memory device, or display device.

[0019] Note that the description of these objectives does not preclude the existence of other objectives. One aspect of the invention does not require achieving all of the above objectives. Objectives other than those described above can be extracted from the description, drawings, and claims.

[0020] means of solving technical problems

[0021] One aspect of the present invention is a semiconductor device comprising an oxide semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, and a second insulating layer. The first insulating layer is located on the first conductive layer, and the second conductive layer is located on the first insulating layer. The first insulating layer and the second conductive layer include a first opening at a location where they overlap with the first conductive layer. The second conductive layer includes a first layer and a second layer on the first layer. The second layer has a portion covering the top surface of the first layer and a portion covering the side surface of the first layer. The oxide semiconductor layer has a portion located on the second layer, a portion located on the first conductive layer within the first opening, a portion within the first opening covering the sidewall of the first insulating layer, and a portion within the first opening that faces the side surface of the first layer across the second layer. The second insulating layer is located on the oxide semiconductor layer, and the third conductive layer is located on the second insulating layer. The third conductive layer faces the oxide semiconductor layer through the second insulating layer within the first opening.

[0022] In addition, in the above-described manner, it is preferable that the first conductive layer has a first recess, and the first openings included in the first insulating layer and the second conductive layer overlap with the first recess.

[0023] In addition, in the above-described manner, it is preferable that the first layer comprises a metal or alloy, and the second layer comprises a conductive material containing oxygen or a conductive material containing nitrogen.

[0024] In addition, in the above-described manner, it is preferred that the first layer contains tungsten and the second layer contains indium tin oxide containing silicon.

[0025] Another aspect of the present invention is a method for manufacturing a semiconductor device, comprising the following steps: forming a first insulating layer on a first conductive layer; forming a second conductive layer on the first insulating layer; removing a portion of the second conductive layer and a portion of the first insulating layer to form a first opening reaching the first conductive layer and exposing the top surface of the first conductive layer; forming a third conductive layer to cover the top surface of the second conductive layer and the side surface inside the first opening of the second conductive layer; forming a first oxide semiconductor layer to cover the top surface of the first conductive layer, the side surface inside the first opening of the first insulating layer, the side surface of the third conductive layer, and the top surface of the third conductive layer; forming a third insulating layer on the first oxide semiconductor layer; and forming a fourth conductive layer on the third insulating layer.

[0026] In addition, in the above method, it is preferable that when forming the first opening, a portion of the second conductive layer is removed by dry etching, and after dry etching and before forming the third conductive layer, a portion of the upper end of the first opening of the second conductive layer is removed by back sputtering.

[0027] Furthermore, in the above-described manner, it is preferable that, when forming the first opening, a recess overlapping the first opening is formed in the first conductive layer.

[0028] Furthermore, in the above-described manner, it is preferable that the third conductive layer contains a conductive material containing oxygen or a conductive material containing nitrogen, and that the third conductive layer is formed using a sputtering method.

[0029] In addition, in the above-described manner, it is preferable that the third conductive layer contains indium tin oxide comprising silicon, and that the third conductive layer is formed by sputtering.

[0030] Invention Effects

[0031] According to one aspect of the present invention, a transistor with good electrical characteristics can be provided. According to one aspect of the present invention, a transistor with a large on-state current can be provided. According to one aspect of the present invention, a transistor with small parasitic capacitance can be provided. According to one aspect of the present invention, a transistor, semiconductor device, memory device, or display device with high reliability can be provided. According to one aspect of the present invention, a transistor, semiconductor device, or memory device capable of miniaturization or high integration can be provided. According to one aspect of the present invention, a semiconductor device, memory device, or display device with low power consumption can be provided. According to one aspect of the present invention, a memory device with high operating speed can be provided. According to one aspect of the present invention, a display device with high resolution or high aperture ratio can be provided. According to one aspect of the present invention, a method for manufacturing the above-mentioned transistor, semiconductor device, memory device, or display device can be provided.

[0032] Note that the description of these effects does not preclude the existence of other effects. One aspect of the invention does not necessarily require all of the aforementioned effects. Effects other than those described above can be extracted from the specification, drawings, and claims. Attached Figure Description

[0033] Figure 1A and Figure 1B This is a plan view showing an example of a semiconductor device.

[0034] Figures 1C to 1E This is a cross-sectional view showing an example of a semiconductor device.

[0035] Figure 2A and Figure 2B This is a cross-sectional view showing an example of a semiconductor device.

[0036] Figure 3 This is a cross-sectional view showing an example of a semiconductor device.

[0037] Figure 4A and Figure 4B This is a cross-sectional view showing an example of a semiconductor device.

[0038] Figures 5A to 5D This is a cross-sectional view showing an example of a semiconductor device.

[0039] Figures 6A to 6D This is a cross-sectional view showing an example of a semiconductor device.

[0040] Figure 7 This is a cross-sectional view showing an example of a semiconductor device.

[0041] Figures 8A to 8C This is a cross-sectional view showing an example of a semiconductor device.

[0042] Figures 9A to 9C This is a cross-sectional view showing an example of a semiconductor device.

[0043] Figures 10A to 10D This is a cross-sectional view showing an example of a semiconductor device.

[0044] Figure 11A and Figure 11B This is a cross-sectional view showing an example of a semiconductor device.

[0045] Figure 12 This is a cross-sectional view showing an example of a semiconductor device.

[0046] Figure 13A and Figure 13B This is a cross-sectional view showing an example of a semiconductor device.

[0047] Figure 14A and Figure 14B This is a cross-sectional view showing an example of a semiconductor device.

[0048] Figures 15A to 15C This is a cross-sectional view showing an example of a semiconductor device.

[0049] Figure 16 This is a cross-sectional view showing an example of a semiconductor device.

[0050] Figure 17A and Figure 17B This is a cross-sectional view showing an example of a semiconductor device.

[0051] Figure 18A This is a plan view showing an example of a semiconductor device.

[0052] Figure 18B and Figure 18C This is a cross-sectional view showing an example of a semiconductor device.

[0053] Figure 19A This is a plan view showing an example of a semiconductor device.

[0054] Figure 19B and Figure 19C This is a cross-sectional view showing an example of a semiconductor device.

[0055] Figure 20A and Figure 20B This is a cross-sectional view showing an example of a semiconductor device.

[0056] Figures 21A to 21C This is a cross-sectional view showing an example of a semiconductor device.

[0057] Figure 22A This is a plan view showing an example of a semiconductor device.

[0058] Figure 22B and Figure 22C This is a cross-sectional view showing an example of a semiconductor device.

[0059] Figure 23A and Figure 23B This is a cross-sectional view showing an example of a semiconductor device.

[0060] Figure 24A and Figure 24B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0061] Figure 25A and Figure 25B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0062] Figure 26A and Figure 26B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0063] Figures 27A to 27C This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0064] Figure 28A and Figure 28B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0065] Figure 29A and Figure 29B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0066] Figure 30A and Figure 30B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0067] Figure 31A This is a floor plan showing an example of a storage device.

[0068] Figure 31B and Figure 31C This is a cross-sectional view showing an example of a storage device.

[0069] Figure 32A and Figure 32B This is a cross-sectional view showing an example of a storage device.

[0070] Figure 33A This is a floor plan showing an example of a storage device.

[0071] Figure 33B This is a cross-sectional view showing an example of a storage device.

[0072] Figure 34 This is a cross-sectional view showing an example of a storage device.

[0073] Figure 35 This is a cross-sectional view showing an example of a storage device.

[0074] Figure 36 This is a block diagram illustrating an example of the structure of a semiconductor device.

[0075] Figures 37A to 37G This is a diagram illustrating an example of the circuit structure of a memory cell.

[0076] Figure 38A and Figure 38B This is a three-dimensional diagram illustrating an example of the structure of a semiconductor device.

[0077] Figure 39 This is a block diagram illustrating the CPU.

[0078] Figure 40A and Figure 40B It is a 3D diagram of a semiconductor device.

[0079] Figure 41A and Figure 41B It is a 3D diagram of a semiconductor device.

[0080] Figure 42A and Figure 42B This is a circuit diagram of a semiconductor device according to one aspect of the present invention. Figure 42C This is a diagram illustrating an example of an electronic component of a semiconductor device using one aspect of the present invention.

[0081] Figure 43A and Figure 43B This is a perspective view showing an example of a display device.

[0082] Figure 44 This is a cross-sectional view showing an example of a display device.

[0083] Figure 45 This is a cross-sectional view showing an example of a display device.

[0084] Figures 46A to 46C This is a diagram showing an example of the structure of a display device.

[0085] Figure 47 This is a diagram showing an example of an electronic component.

[0086] Figures 48A to 48C This is a diagram illustrating an example of a large computer.

[0087] Figure 48D This is a diagram illustrating an example of a space device.

[0088] Figure 48E This is a diagram illustrating an example of a storage system that can be used in a data center.

[0089] Figures 49A to 49F This is a diagram illustrating an example of an electronic device.

[0090] Figures 50A to 50G This is a diagram illustrating an example of an electronic device.

[0091] Figures 51A to 51F This is a diagram illustrating an example of an electronic device.

[0092] Figure 52A The image shows a STEM image.

[0093] Figure 52B The EDX analysis results are shown.

[0094] Figure 53A The image shows a STEM image.

[0095] Figure 53B The EDX analysis results are shown.

[0096] Figure 54A The image shows a STEM image.

[0097] Figure 54B The EDX analysis results are shown.

[0098] Figure 55 The results of the resistance measurement are shown. Detailed Implementation

[0099] The embodiments will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and those skilled in the art will readily understand that its methods and details can be varied in many ways without departing from the spirit and scope of the invention. Therefore, the present invention should not be construed as being limited only to the contents described in the embodiments shown below.

[0100] Note that in the invention structure described below, the same reference numerals are used in different figures to denote the same parts or parts having the same function, and repeated descriptions are omitted. Furthermore, when showing parts with the same function, the same shading lines are sometimes used without special additional symbols.

[0101] Furthermore, for ease of understanding, the positions, sizes, and extents of the constituent elements shown in the accompanying drawings may not represent their actual positions, sizes, and extents. Therefore, the disclosed invention is not necessarily limited to the positions, sizes, and extents disclosed in the accompanying drawings.

[0102] In this specification and other documents, ordinal numbers such as "first" and "second" are used for convenience, but these do not limit the number of constituent elements or the order of the constituent elements (e.g., process sequence or stacking sequence). Furthermore, the ordinal numbers used for constituent elements in one part of this specification may sometimes differ from those used for the same constituent element in other parts of this specification or in the claims.

[0103] A transistor is a type of semiconductor device that can amplify current or voltage, control switching operations (turning on or off), etc. The transistors discussed in this specification include IGFETs (Insulated Gate Field Effect Transistors) and thin-film transistors (TFTs).

[0104] In this specification and other materials, transistors that use oxide semiconductors or metal oxides for the semiconductor layer and transistors whose channel formation region contains oxide semiconductors or metal oxides are sometimes referred to as OS transistors. Furthermore, transistors whose channel formation region contains silicon are sometimes referred to as Si transistors.

[0105] In this specification and the like, a transistor refers to a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a region (also called a channel-forming region) between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode) that forms a channel, and current can flow between the source and drain through the channel-forming region. Note that in this specification and the like, the channel-forming region refers to the region through which current primarily flows.

[0106] Furthermore, in cases where transistors of different polarities are used or the current direction changes during circuit operation, the functions of the source and drain may sometimes be interchanged. Therefore, in this specification, the source and drain may be interchanged.

[0107] Note that impurities in semiconductors refer to elements other than the main components of the semiconductor. For example, elements with a concentration below 0.1 atomic% can be considered impurities. The presence of impurities can sometimes lead to an increase in the defect state density or a decrease in crystallinity in the semiconductor. When the semiconductor is an oxide semiconductor, impurities that alter its properties include, for example, Group 1, Group 2, Group 13, Group 14, and Group 15 elements, as well as transition metals other than the main components of the oxide semiconductor. Specifically, examples include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Water sometimes also acts as an impurity. Furthermore, the incorporation of impurities can sometimes lead to oxygen vacancies (also referred to as V) in the oxide semiconductor. O The formation of ).

[0108] In this specification, etc., oxynitrides refer to materials in which the oxygen content is greater than the nitrogen content in their composition. Nitrogen oxides refer to materials in which the nitrogen content is greater than the oxygen content in their composition.

[0109] For example, the content of elements such as hydrogen, oxygen, carbon, or nitrogen in the membrane can be analyzed using secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS). XPS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more or 1 atomic% or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., less than 0.5 atomic% or less or 1 atomic% or less). When comparing elemental contents, it is more preferable to use a combined analysis technique of SIMS and XPS.

[0110] Note that in this specification, the content rate refers to the proportion of components contained in the film. For example, an oxide semiconductor layer contains metal elements X, Y, and Z, and the number of atoms of each of metal elements X, Y, and Z contained in the oxide semiconductor layer is A. X A Y A Z In this case, the content of metallic element X can be expressed as A. X / (A X +A Y +A Z Additionally, when the ratio (atomic number ratio) of the number of atoms of metal elements X, Y, and Z in the oxide semiconductor layer is changed from B... X B Y B Z When expressing this, the content of metallic element X can be represented as B. X / (B) X +B Y +B Z ).

[0111] Furthermore, depending on the situation or state, the "film" and "layer" can be interchanged. For example, a "conductive layer" can be changed into a "conductive film." Similarly, an "insulating film" can be changed into an "insulating layer."

[0112] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than or equal to -10 degrees and less than 10 degrees. Therefore, it also includes states where the angle is greater than or equal to -5 degrees and less than 5 degrees. "Approximately parallel" refers to a state where the angle formed by two straight lines is greater than or equal to -20 degrees and less than 20 degrees. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than or equal to 80 degrees and less than 100 degrees. Therefore, it also includes states where the angle is greater than or equal to 85 degrees and less than 95 degrees. "Approximately perpendicular" refers to a state where the angle formed by two straight lines is greater than or equal to 70 degrees and less than 110 degrees.

[0113] In this specification, "connection" includes, for example, "electrical connection." Note that sometimes "electrical connection" is used to describe the connection relationship of circuit elements as an object. Furthermore, "electrical connection" includes both "direct connection" and "indirect connection." "A and B directly connected" means that A and B are connected without any circuit elements (e.g., transistors, switches, etc. Note that wiring is not a circuit element). On the other hand, "A and B indirectly connected" means that A and B are connected through more than one circuit element.

[0114] For example, assuming a circuit including A and B is operating, if there are opportunities during circuit operation where electrical signals are exchanged or potentials interact between A and B, such a circuit can be defined as "A and B are indirectly connected". Furthermore, even if there are times during circuit operation where no electrical signals are exchanged or potentials interact between A and B, the opportunity where electrical signals are exchanged or potentials interact between A and B can still be defined as "A and B are indirectly connected".

[0115] An example of "A and B being indirectly connected" is a case where A and B are connected through the source and drain of more than one transistor. On the other hand, an example where "A and B being indirectly connected" cannot be said is a case where there is an insulator in the path from A to B. Specifically, this includes cases where a capacitor is connected between A and B, and cases where there is a gate insulating film of a transistor between A and B. Therefore, it cannot be said that "the gate (A) of a transistor is indirectly connected to the source or drain (B) of the transistor."

[0116] As another example where it cannot be said that "A and B are indirectly connected", there is the following situation: multiple transistors are connected through the source and drain along the path from A to B, and a fixed potential V is supplied from the power supply, GND, etc. to the nodes between the transistors and other transistors.

[0117] In this specification, unless otherwise specified, off-state current refers to the leakage current between the source and drain of a transistor when it is in the off state (also known as the non-conducting state or the blocked state). Unless otherwise specified, in an n-channel transistor, the off state refers to the voltage V between the gate and source. gs Below the threshold voltage V th (V in p-channel transistor) gs Higher than V th ) state.

[0118] In this specification, normally-on characteristic refers to the state in which a channel exists and current flows through the transistor even when no voltage is applied to the gate. Normally-off characteristic refers to the state in which no current flows through the transistor when no potential is applied to the gate or when the gate is supplied with a ground potential.

[0119] In this specification, a conical shape refers to a shape in which at least a portion of the side surface of a constituent element is inclined relative to the substrate surface or the surface to be formed. For example, it is preferable to have a region where the angle (also referred to as the cone angle) formed by the inclined side surface and the substrate surface or the surface to be formed is greater than 0 degrees and less than 90 degrees. Here, the side surface of the constituent element, the substrate surface, and the surface to be formed do not necessarily have to be completely flat; they may be approximately planar with slight curvature or approximately planar with slight irregularities.

[0120] In this specification, when it is stated that "A is located on B," at least a portion of A is located on B. Therefore, for example, it can be said that A has an area located on B. Similarly, when it is stated that "A is in contact with B" or "A overlaps with B," at least a portion of A is in contact with B or overlaps with B. Therefore, it can be said that A has an area in contact with B or A has an area overlapping with B. Likewise, in this specification, when it is stated that "A covers B," at least a portion of A covers B. Therefore, for example, it can be said that A has an area covering B.

[0121] In this specification, devices manufactured using a metal mask or FMM (Fine Metal Mask) are sometimes referred to as devices having an MM (Metal Mask) structure. Furthermore, devices manufactured without a metal mask or FMM are sometimes referred to as devices having an MML (Metal Mask Less) structure.

[0122] In this specification and other materials, the structure in which light-emitting elements (also known as light-emitting devices) with different emission wavelengths are fabricated separately is sometimes referred to as an SBS (Side By Side) structure. Because the materials and structures of each light-emitting element can be optimized separately in an SBS structure, the freedom of material and structure selection is increased, and it is easy to achieve improvements in brightness and reliability.

[0123] In this specification and other materials, holes or electrons are sometimes referred to as "carriers." Specifically, a hole injection layer or electron injection layer is sometimes called a "carrier injection layer," a hole transport layer or electron transport layer is sometimes called a "carrier transport layer," and a hole blocking layer or electron blocking layer is sometimes called a "carrier blocking layer." Note that sometimes it is not possible to clearly distinguish between the above-mentioned carrier injection layer, carrier transport layer, and carrier blocking layer. Furthermore, sometimes a single layer combines the functions of two or three of the following: carrier injection layer, carrier transport layer, and carrier blocking layer.

[0124] In this specification, the light-emitting element includes an EL layer between a pair of electrodes. The EL layer includes at least a light-emitting layer. Here, the layers included in the EL layer (also referred to as functional layers) can include a light-emitting layer, a carrier injection layer (hole injection layer and electron injection layer), a carrier transport layer (hole transport layer and electron transport layer), and a carrier blocking layer (hole blocking layer and electron blocking layer). In this specification, sometimes one of the pair of electrodes is referred to as the pixel electrode and the other as the common electrode.

[0125] In this specification, the sacrificial layer (also known as a mask layer) is located at least above the light-emitting layer (more specifically, the layer that is processed into an island shape in the layers constituting the EL layer) and has the function of protecting the light-emitting layer during the manufacturing process.

[0126] In this specification and the like, "disconnection" refers to the phenomenon where a layer, film, or electrode is disconnected due to the shape of the surface to which it is formed (e.g., a step).

[0127] Note that arrows indicating the X, Y, and Z directions are sometimes included in the accompanying drawings and other materials of this specification. In this specification, "X direction" refers to the direction along the X-axis, and unless explicitly stated otherwise, its direction (clockwise or counterclockwise) is not always distinguished. The same applies to "Y direction" and "Z direction." Furthermore, the X, Y, and Z directions are intersecting directions. For example, the X, Y, and Z directions are orthogonal to each other.

[0128] (Implementation Method 1)

[0129] In this embodiment, a semiconductor device and a method for manufacturing the same according to one aspect of the present invention are described.

[0130] One aspect of the semiconductor device of the present invention includes a transistor. Another aspect of the semiconductor device of the present invention includes an oxide semiconductor layer, first to third conductive layers, and first and second insulating layers.

[0131] An oxide semiconductor layer is used as the semiconductor layer of the transistor, a first conductive layer is used as one of the source and drain electrodes of the transistor, a second conductive layer is used as the other of the source and drain electrodes of the transistor, and a third conductive layer is used as the gate electrode of the transistor. A second insulating layer is used as the gate insulating layer of the transistor.

[0132] The first insulating layer is located on the first conductive layer, and the second conductive layer is located on the first insulating layer.

[0133] In one embodiment of the transistor of the present invention, the source electrode and the drain electrode are located at different heights (e.g., at heights perpendicular to the substrate surface or insulating plane on which the transistor is disposed), and the current flowing through the semiconductor layer flows in the height direction. That is to say, the channel length direction can be said to have a height direction (vertical) component, so the transistor of one embodiment of the present invention can also be referred to as VFET (Vertical Field Effect Transistor), vertical transistor, vertical channel transistor, or vertical channel transistor, etc.

[0134] Because the source electrode, semiconductor layer, and drain electrode can be stacked, the area occupied by a transistor of one aspect of the present invention can be much smaller than that of a so-called planar transistor in which the semiconductor layer is configured as a planar shape.

[0135] Furthermore, the channel length of the transistor in one embodiment of the present invention can be controlled according to the thickness of the first insulating layer, etc. Therefore, transistors with extremely short channel lengths, which are difficult to achieve with planar transistors, can be realized. Thus, transistors with small footprints and large on-state currents can be realized.

[0136] Furthermore, since transistors using oxide semiconductors have low off-state currents, they can retain stored content for extended periods, for example, when used in memory devices. In other words, since refresh operations are unnecessary or occur at extremely low frequencies, the power consumption of the memory device can be significantly reduced. By using transistors according to one aspect of the present invention in memory devices, high integration and low power consumption of the memory device can be achieved.

[0137] <Example 1-1 of a semiconductor device structure>

[0138] Reference Figures 1A to 8B The structure of a semiconductor device according to one aspect of the present invention is described.

[0139] Figure 1A It is a plan view of a semiconductor device including transistor 200. Figure 1B This is a plan view showing an example of a configuration of multiple transistors 200. Figure 1C It is along Figure 1A The cross-sectional view of the dotted line A1-A2 shown. Figure 1D It is along Figure 1A The cross-sectional view shown is the dotted-dash line A3-A4. Figure 1E It is along Figure 1C and Figure 1D The cross-sectional view shown is the dotted-dash line A5-A6. Figure 1E This is a diagram viewed from the Z-axis. Note that... Figure 1A and Figure 1B In the plan view, some constituent elements are omitted for clarity. Sometimes, some constituent elements are also omitted in subsequent plan views.

[0140] in addition, Figure 2A It is along Figure 1A The cross-sectional view shown is the dotted-dash line A3-A4. Figure 2B yes Figure 1E Enlarged image. Figure 2A and Figure 2B They are respectively equivalent to Figure 1D and Figure 1E An example of a magnified image.

[0141] Figures 1A to 2B The semiconductor device shown includes an insulating layer 210 on a substrate (not shown), a transistor 200 on the insulating layer 210, and an insulating layer 280 on the insulating layer 210. The insulating layers 210 and 280 are used as interlayer films.

[0142] [Transistor 200]

[0143] Transistor 200 includes a conductive layer 220, a conductive layer 240 on an insulating layer 280, an oxide semiconductor layer 230, an insulating layer 250 on the oxide semiconductor layer 230, and a conductive layer 260 on the insulating layer 250. The insulating layer 280 is located on the conductive layer 220.

[0144] In transistor 200, oxide semiconductor layer 230 is used as semiconductor layer, conductive layer 260 is used as gate electrode, insulating layer 250 is used as gate insulating layer, conductive layer 220 is used as one of source electrode and drain electrode, and conductive layer 240 is used as the other of source electrode and drain electrode. Additionally, conductive layer 260 has a region used for gate wiring.

[0145] like Figure 1C and Figure 1D As shown, the insulating layer 280 and the conductive layer 240 are provided with an opening 290 that reaches the conductive layer 220.

[0146] Figure 3 Showing omissions Figure 2A A diagram showing the shaded elements other than the oxide semiconductor layer 230. (See diagram.) Figure 3 As shown, the opening 290 includes an opening 290a included in the insulating layer 280 and an opening 290b included in the conductive layer 240. The opening 290a included in the region of the insulating layer 280 that overlaps with the conductive layer 220 is a part of the opening 290, and the opening 290b included in the region of the conductive layer 240 that overlaps with the conductive layer 220 is another part of the opening 290.

[0147] like Figure 3 As shown, a recess 290c is provided in the conductive layer 220_2.

[0148] The opening 290 overlaps with the recess 290c of the conductive layer 220_2. Here, the bottom of the opening 290 includes the bottom surface of the recess 290c of the conductive layer 220_2, and the sidewalls of the opening 290 include the side surface of the recess of the conductive layer 220_2, the side surface of the opening 290a in the insulating layer 280, and the side surface of the opening 290b in the conductive layer 240.

[0149] Furthermore, the shape and size of the openings 290 in each layer can be different when viewed from a plan view. In addition, when the top surface of the opening 290 is circular, the openings in each layer can be either concentric or non-concentric.

[0150] At least a portion of the constituent elements of transistor 200 are disposed within opening 290. Specifically, oxide semiconductor layer 230, insulating layer 250, and conductive layer 260 are all disposed such that at least a portion of each is located within opening 290. Furthermore, the portions of oxide semiconductor layer 230, insulating layer 250, and conductive layer 260 disposed within opening 290 are provided in accordance with the shape of opening 290.

[0151] The oxide semiconductor layer 230 is provided such that it covers the bottom and sidewalls of the opening 290. In addition, the oxide semiconductor layer 230 has a recess that reflects the shape of the opening 290.

[0152] The conductive layer 240 can be used as wiring in a semiconductor device. By increasing the conductivity of the conductive layer 240, the characteristics of the semiconductor device can be improved. For example, the operating speed can be increased. Therefore, a material with high conductivity is preferably used as the conductive layer 240.

[0153] Additionally, the conductive layer 240 can be used as one of the source and drain electrodes of a transistor. The conductive layer 240 has a region that contacts the oxide semiconductor layer 230. Therefore, the conductive layer 240 preferably has a low contact resistance with the oxide semiconductor layer 230.

[0154] Figure 1Cand Figure 1D An example of a two-layer structure is shown, comprising a conductive layer 240_1 and a conductive layer 240_2 on the conductive layer 240_1. The conductive layer 240_1 is, for example, a material with high conductivity, and the conductive layer 240_2 is, for example, a material with low contact resistance with the oxide semiconductor layer 230.

[0155] Here, the material used as conductive layer 240_1 sometimes has the property of extracting oxygen from oxide semiconductor layer 230. For example, when a metallic material is used as conductive layer 240_1, there is a concern that oxygen in oxide semiconductor layer 230 may be extracted by conductive layer 240_1.

[0156] On the other hand, oxygen-containing conductive materials can be cited as suitable materials for use as conductive layer 240_2. Oxygen-containing conductive materials can maintain a stable state even when in contact with oxide semiconductor layer 230, and oxygen is not easily extracted from oxide semiconductor layer 230 in conductive layer 240_2.

[0157] In one embodiment of the invention, the conductive layer 240_2 preferably covers at least a portion of the side surface of the opening 290 of the conductive layer 240_1. This reduces the contact area between the oxide semiconductor layer 230 and the conductive layer 240_1. When the conductive layer 240_1 has the property of extracting oxygen from the oxide semiconductor layer 230, reducing the contact area between the oxide semiconductor layer 230 and the conductive layer 240_1 can suppress oxygen vacancies (V0) in the oxide semiconductor layer 230. O In addition, the resistance increase of the conductive layer 240 caused by the oxidation of the conductive layer 240 due to the extraction of oxygen from the oxide semiconductor layer 230 can be suppressed.

[0158] The conductive layer 240_2 covers at least a portion of the side surface of the conductive layer 240_1 in the opening 290b. The side surface of the conductive layer 240_2 constitutes at least a portion of the side surface of the opening 290b in the conductive layer 240. Furthermore, as will be explained later... Figure 4B As shown, when the side of the conductive layer 240_1 has a region that is not covered by the conductive layer 240_2, this region constitutes part of the side of the opening 290b in the conductive layer 240.

[0159] The insulating layer 250 is provided to cover the oxide semiconductor layer 230. Furthermore, the insulating layer 250 is provided to cover the top and side surfaces of the oxide semiconductor layer 230 on the insulating layer 280. Additionally, the insulating layer 250 has recesses that reflect the shape of the recesses in the oxide semiconductor layer 230.

[0160] The conductive layer 260 is provided in such a way that at least a portion of the recess in the insulating layer 250 is embedded. In addition, the conductive layer 260 has a region in the opening 290 that is opposite to the oxide semiconductor layer 230 separated by the insulating layer 250.

[0161] Notice, Figure 1C and Figure 1D An example is shown where the conductive layer 220 has a two-layer structure of conductive layer 220_1 and conductive layer 220_2 on conductive layer 220_1, and the conductive layer 260 has a two-layer structure of conductive layer 260_1 and conductive layer 260_2 on conductive layer 260_1.

[0162] The oxide semiconductor layer 230 has a region opposite the conductive layer 260 separated by an insulating layer 250. At least a portion of this region is used as a channel formation region for the transistor 200. A region near the conductive layer 220 of the oxide semiconductor layer 230 is used as one of the source and drain regions, and a region near the conductive layer 240 of the oxide semiconductor layer 230 is used as the other of the source and drain regions. That is, the channel formation region is sandwiched between the source and drain regions.

[0163] An oxide semiconductor layer 230 is disposed inside the opening 290. Furthermore, one of the source and drain electrodes of the transistor 200 (here, conductive layer 220) is located below, and the other (here, conductive layer 240) is located above, so current flows in the vertical direction. That is, a channel is formed along the side of the opening 290.

[0164] For example, at least a portion of the region in the oxide semiconductor layer 230 that is in contact with the conductive layer 240 can be used as another of the source and drain regions of a transistor.

[0165] For example, at least a portion of the region in the oxide semiconductor layer 230 that is not in contact with the conductive layer 240 can be used as the channel formation region of the transistor.

[0166] Note that, due to manufacturing process reasons, sometimes a conductor derived from the material of the conductive layer 240 remains between the oxide semiconductor layer 230 and the insulating layer 280 inside the opening 290. This conductor, for example, contains at least one material common to the conductive layer 240. In this case, the remaining conductor is preferably insulated from the region of the conductive layer 240 that serves as either the source electrode or the drain electrode. For example, the remaining conductor is preferably separate from the region of the conductive layer 240 that serves as either the source electrode or the drain electrode.

[0167] Transistor 200 includes an oxide semiconductor layer 230 in the channel formation region. In other words, transistor 200 can be considered an OS transistor.

[0168] In OS transistors, the electrical characteristics are prone to variation and sometimes reduced reliability when oxygen vacancies and impurities are present in the channel formation region of the oxide semiconductor. Furthermore, defects that form hydrogen entering oxygen vacancies (sometimes referred to below as V0) can also occur. O H) may generate electrons that become charge carriers. Therefore, when oxygen vacancies are included in the channel formation region of an oxide semiconductor, the OS transistor tends to have always-on characteristics. Thus, it is preferable to minimize oxygen vacancies and impurities in the channel formation region of an oxide semiconductor. In other words, it is preferable to reduce the carrier concentration in the channel formation region of the oxide semiconductor to make it i-type (intrinsic) or substantially i-type.

[0169] Oxygen extraction from the oxide semiconductor layer 230 by the conductive layer 240 may lead to the generation of oxygen vacancies in the oxide semiconductor layer 230. Therefore, it is preferable to use a material that is not easily oxidized as the conductive layer 240. More specifically, for example, at least a portion of the region of the conductive layer 240 in contact with the oxide semiconductor layer 230 is made of a material that is not easily oxidized.

[0170] Compared to conductive layer 240_1, conductive layer 240_2 has a larger contact area with oxide semiconductor layer 230. Preferably, compared to conductive layer 240_1, conductive layer 240_2 is less prone to oxidation when in contact with oxide semiconductor layer 230. This suppresses oxygen extraction from oxide semiconductor layer 230 by conductive layer 240. Conductive layer 240_2 is preferably, for example, a conductive material that is not easily oxidized or a conductive material that has the function of suppressing oxygen diffusion.

[0171] Furthermore, the conductive layer 240_2 is preferably a conductive material that maintains low resistance even when in contact with the oxide semiconductor layer 230. For example, the conductive layer 240_2 is preferably a conductive material that maintains low resistance even when oxidized.

[0172] As the conductive layer 240_2, conductive materials containing oxygen and conductive materials containing nitrogen can be used. As the conductive layer 240_2, conductive metal oxides (also known as oxide conductors) can be appropriately used. For example, indium tin oxide (In-Sn oxide, also known as ITO), indium tin oxide containing titanium oxide, indium tin oxide containing silicon (In-Si-Sn oxide, also known as ITSO), indium zinc oxide (In-Zn oxide, also known as IZO (registered trademark)) and the like can be appropriately used.

[0173] Low-resistance conductive material is preferably used as conductive layer 240_1. Conductive layer 240_1 can be made of a metal element selected from tungsten, copper, aluminum, chromium, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., an alloy composed of the above metal elements, or an alloy combining the above metal elements. By using a low-resistance conductive material as conductive layer 240_1, the operating speed of the circuit can be improved when conductive layer 240 is used for wiring, etc., which is therefore preferred. Conductive layer 240_1 is, for example, a conductive material with a lower resistance than conductive layer 240_2. For example, tungsten, copper, aluminum, aluminum-containing alloys, etc., can be appropriately used as conductive layer 240_1.

[0174] Compared to conductive layer 240_2, the low-resistivity material used as conductive layer 240_1 is sometimes easily oxidized due to contact with the oxide semiconductor layer 230. When conductive layer 240_1 is oxidized, the resistance of conductive layer 240_1 may increase.

[0175] In one aspect of the semiconductor device of the present invention, by reducing the contact area between the easily oxidized region of the conductive layer 240 and the oxide semiconductor layer 230, the conductivity of the conductive layer 240 can be improved, and the oxygen vacancies in the channel formation region of the oxide semiconductor layer 230 can be reduced.

[0176] Furthermore, by supplying oxygen to the oxide semiconductor layer 230 from the layers included in the transistor 200 (e.g., insulating layers such as insulating layer 250) and the layers disposed around the transistor 200 (e.g., insulating layers such as insulating layer 280), oxygen vacancies in the oxide semiconductor layer 230 can be reduced. Consider the case where multiple transistors are disposed in a certain region of a semiconductor device. In this case, when the volume of each oxygen-supplying layer is small relative to the volume occupied by the transistor 200, the amount of oxygen supplied to a single transistor 200 decreases. As the integration density of the circuit increases, the transistors 200 are disposed more densely, so the amount of oxygen supplied to a single transistor 200 decreases. Therefore, in highly integrated circuits, the extraction of oxygen from the oxide semiconductor layer 230 by the conductive layer 240 may have a more significant impact on the characteristics of the transistor 200.

[0177] The semiconductor device according to one aspect of the present invention can also achieve excellent transistor characteristics when used in memory devices including high-density memory cell arrays, display devices having high-definition display sections, etc.

[0178] Furthermore, the source and drain regions of the OS transistor are preferably regions with higher carrier concentration and lower resistance compared to the channel formation region. For example, the source and drain regions of the OS transistor are regions with higher oxygen vacancies and lower resistance compared to the channel formation region. OWith higher concentrations of H or impurities such as hydrogen, nitrogen, and metal elements, the carrier concentration increases, resulting in lower resistance. By appropriately contacting the conductive layer 240_1 with the oxide semiconductor layer 230, oxygen vacancies used to form the source and drain regions can be introduced into the oxide semiconductor layer 230.

[0179] Furthermore, the conductive layer 240_2 is the main region of the conductive layer 240 that contacts the oxide semiconductor layer 230. Therefore, the conductive layer 240_2 is preferably made of a material that can form a good bond with the oxide semiconductor layer 230, and preferably a material with low contact resistance with the oxide semiconductor layer 230. For example, a material that can form an ohmic contact with the oxide semiconductor layer 230 can be used as the conductive layer 240_2.

[0180] Furthermore, in a transistor according to one aspect of the present invention, when a conductive layer 240_2 is sandwiched between the oxide semiconductor layer 230 and the conductive layer 240_1, compared to the case where the oxide semiconductor layer 230 and the conductive layer 240_1 are in direct contact, the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240_1 is sometimes more appropriately reduced.

[0181] Preferably, the conductive layer 240_2 is made of a material that can form a good bond with the oxide semiconductor layer 230, and also uses a material that can form a good bond with the conductive layer 240_1. This appropriately reduces the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240.

[0182] The above-described material is preferably used as conductive layer 240_1, and tungsten is particularly preferred as conductive layer 240_1. Furthermore, the above-described material is preferably used as conductive layer 240_2, and ITSO is particularly preferred as conductive layer 240_2.

[0183] Figure 16 An example is shown in which the sidewalls of conductive layer 240_1 in transistor 200 are not covered by conductive layer 240_2. Figure 16 In the process, the oxide semiconductor layer 230 is in contact with the side surface of the opening 290 in the conductive layer 240_1, the side surface of the opening 290 in the conductive layer 240_2, and the top surface of the conductive layer 240_2.

[0184] like Figure 1C , Figure 1D and Figure 2A As shown, by employing a structure in which a conductive layer 240_2 covers at least a portion of the side surface of the opening 290 in the conductive layer 240_1, the contact area between the oxide semiconductor layer 230 and the conductive layer 240_1 can be reduced. This allows for the suppression of oxygen vacancies (V0) in the oxide semiconductor layer 230. OFurthermore, since the oxidation of the conductive layer 240_1 can be suppressed, the resistance of the conductive layer 240_1 can be appropriately reduced.

[0185] like Figure 2A and Figure 3 As shown, when the conductive layer 220_2 has a recess at the position overlapping with the opening 290, compared to the case without the recess, the height of the bottom surface of the insulating layer 250 and the bottom surface of the conductive layer 260 within the opening 290 can be lower than the height of the top surface of the conductive layer 220_2 that contacts the insulating layer 280, with the top surface of the insulating layer 210 as a reference. Here, the height of each surface can be determined with reference to the surface on which the transistor is formed. Here, the top surface of the insulating layer 210 is used as the reference. The surface used as the reference is not limited to the surface on which the transistor is formed. For example, the top surface of the substrate on which the transistor or semiconductor device is disposed can also be used as the reference.

[0186] The oxide semiconductor layer 230 contacts the bottom and side surfaces of the recesses in the conductive layer 220_2 and the top surface of the conductive layer 240_2. By having recesses in the conductive layer 220_2, the contact area between the oxide semiconductor layer 230 and the conductive layer 220_2 can be increased. Therefore, the contact resistance between the oxide semiconductor layer 230 and the conductive layer 220_2 can be reduced.

[0187] Figure 1C The diagram shows a structure in which the ends of the conductive layer 240 and the oxide semiconductor layer 230 are aligned on the outer side of the opening 290. The conductive layer 240 and the oxide semiconductor layer 230 can be manufactured using the same mask. Therefore, the number of masks required for manufacturing the semiconductor device can be reduced, which is preferable. Note that the invention is not limited thereto. For example, a structure in which any one of the ends of the oxide semiconductor layer 230, the conductive layer 240_1, and the conductive layer 240_2 in the X or Y direction is located inside or outside the other ends can also be used.

[0188] As described above, a channel forming region, a source region, and a drain region can be formed within the opening 290. Therefore, compared to a planar transistor where the channel forming region, source region, and drain region are respectively provided on the XY plane, the occupied area of ​​the transistor 200 can be reduced. This allows for high integration of the semiconductor device. Furthermore, when the semiconductor device according to one aspect of the present invention is used in a memory device, the storage capacity per unit area can be increased. Additionally, when the semiconductor device according to one aspect of the present invention is used in a display device, the clarity of the display can be improved.

[0189] in addition, Figure 1B An example is shown where multiple transistors 200 are configured in a matrix. Specifically, Figure 1BThis illustrates an example of 4×4 transistors arranged in the X and Y directions. For example... Figure 1B As shown, transistor 200 is disposed at the intersection of conductive layer 260 extending in the X direction and conductive layer 240 extending in the Y direction. Figure 1B As shown, the diameter of the opening 290 can be smaller than the width of the short side of the conductive layer 240 and the width of the short side of the conductive layer 260. Thus, it can be said that the transistor 200 has a structure capable of achieving high integration and miniaturization.

[0190] like Figure 2B As shown, the oxide semiconductor layer 230, insulating layer 250, and conductive layer 260 are arranged in a concentric circle. Therefore, the side of the conductive layer 260 located at the center faces the side of the oxide semiconductor layer 230 across the insulating layer 250. In other words, when viewed from a plane, the entire edge of the oxide semiconductor layer 230 forms the channel formation region. At this time, for example, the channel width of the transistor 200 is determined based on the length of the outer periphery of the oxide semiconductor layer 230. That is, the channel width of the transistor 200 can be determined based on the size of the width of the opening 290 (which is the diameter when the opening 290 is circular when viewed from a plane). Figure 2A and Figure 2B The width D of the opening 290 is shown. Figure 2B The channel width W of transistor 200 is shown.

[0191] By increasing the width D of the opening 290, the channel width per unit area can be increased, thereby increasing the on-state current. On the other hand, the occupied area of ​​the transistor 200, for example, the area of ​​the transistor 200 when viewed from a plane, is approximately determined by the width of the opening 290. By decreasing the width D of the opening 290, the occupied area of ​​the transistor 200 can be reduced, thereby achieving high integration of the semiconductor device.

[0192] The width D of the opening 290 sometimes varies in the depth direction. Here, in particular, the shortest distance between the two sides of the opening 290 on one side of the conductive layer 240 in cross-section is used as the width D. In other words, the minimum width of the opening 290 in the conductive layer 240 is used as the width D. Alternatively, the width of the opening 290 at the highest position, the width of the opening 290 at the lowest position, the width of the opening 290 at their midpoint, or the average of these three widths can also be used as the width D. Here, an example of determining the width D using the width of the opening 290 of the conductive layer 240 is shown, but there are no particular limitations on the method of determining the width D. For example, the shortest distance between the two sides of the opening 290 on one side of the insulating layer 280 can be used as the width D. Alternatively, the width of the opening 290 at the highest position, the width of the opening 290 at the lowest position, the width of the opening 290 at their midpoint, or the average of these three widths can also be used as the width D.

[0193] When the opening 290 is formed using photolithography, the width D of the opening 290 is limited by the exposure limit of the photolithography. Furthermore, the width D of the opening 290 is set according to the thickness of each of the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 disposed within the opening 290. The width D of the opening 290 is preferably, for example, 5 nm or more, 10 nm or more, or 20 nm or more but 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less. When the opening 290 is circular when viewed from a plane, the width D of the opening 290 is equivalent to the diameter of the opening 290, and the channel width W can be calculated as "D×π".

[0194] The channel length of transistor 200 is the distance between the source and drain regions. In other words, the channel length of transistor 200 can be said to be determined by the thickness of the insulating layer 280 on the conductive layer 220. Figure 2A In the diagram, the channel length L of transistor 200 is indicated by a dashed double arrow. In cross-section, the channel length L can be considered as the distance between the ends of the regions where the oxide semiconductor layer 230 and the conductive layer 220 face each other and the ends of the regions where the oxide semiconductor layer 230 and the conductive layer 240 face each other. In this case, the channel length L is equivalent to the length of the side surface of the opening 290 of the insulating layer 280 in cross-section.

[0195] The channel length of a planar transistor is limited by the exposure limit of photolithography, making further miniaturization difficult. However, the channel length of transistor 200 can be set according to the thickness of the insulating layer 280. Therefore, the channel length of transistor 200 can be set to a very fine channel length below the exposure limit of photolithography (e.g., below 60nm, 50nm, 40nm, 30nm, 20nm, or below 10nm and above 0.1nm, 1nm, or 5nm). This increases the on-state current of transistor 200, thereby improving its frequency characteristics.

[0196] Note that the channel length of transistor 200 depends on the thickness of insulating layer 280 on conductive layer 220. Therefore, this channel length does not affect the occupied area of ​​transistor 200, for example, it does not affect the area of ​​transistor 200 when viewed from a plane. By setting the channel length of transistor 200 to, for example, 1 μm or less, 500 nm or less, or 300 nm or less, productivity and yield can be improved when forming insulating layer 280 and when forming opening 290 in insulating layer 280.

[0197] Therefore, the channel length of the transistor included in the semiconductor device of one aspect of the present invention is preferably 0.1 nm or more, 1 nm or more, or 5 nm or more and 1 μm or less, 500 nm or less, or 300 nm or less.

[0198] The channel length L of transistor 200 is preferably at least less than the channel width W of transistor 200. The channel length L of transistor 200 is preferably 0.1 times or more and 0.99 times or less than the channel width W of transistor 200, more preferably 0.5 times or more and 0.8 times or less. By adopting this structure, transistors with good electrical characteristics and high reliability can be realized.

[0199] As described above, by forming the opening 290 in a circular manner when viewed from a plane, the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are arranged in a concentric circle. As a result, the distance between the conductive layer 260 and the oxide semiconductor layer 230 is approximately uniform, so a gate electric field can be applied to the oxide semiconductor layer 230 approximately uniformly.

[0200] Note that this embodiment shows an example where the opening 290 is circular when viewed from a plane, but the invention is not limited thereto. When viewed from a plane, the opening 290 may be, for example, a circle, an ellipse or other approximate circle, a triangle, a quadrilateral (including rectangles, rhombuses, and squares), a pentagon, a star-shaped polygon, or a polygon with rounded corners. The polygon may also be a concave polygon (a polygon with at least one interior angle greater than 180 degrees) or a convex polygon (a polygon with all interior angles less than 180 degrees). Figure 1AAs shown, the opening 290 is preferably circular when viewed from a planar perspective. By using a circular shape, the machining accuracy when forming the opening can be improved, and openings of minute dimensions can be formed. Note that in this specification, the circular shape is not limited to a perfect circle.

[0201] Figure 1D The diagram shows a structure in which the lower end of the side surface of the conductive layer 240 within the opening 290 is aligned with the upper end of the side surface of the insulating layer 280 within the opening 290 to form a continuous side surface; however, the present invention is not limited to this. For example, the side surface of the conductive layer 240 within the opening 290 and the side surface of the insulating layer 280 within the opening 290 may also be discontinuous.

[0202] Figure 4A yes Figure 2A The diagram shows an enlarged view of region Q1. The top surface of conductive layer 240_1 and the side surface on the side of opening 290 are covered by conductive layer 240_2. Conductive layer 240_2 has a region sandwiched between the side surface of conductive layer 240_1 and oxide semiconductor layer 230. Oxide semiconductor layer 230 covers the side surface of conductive layer 240_1 through conductive layer 240_2.

[0203] When forming the conductive layer 240_2 on a surface perpendicular to the substrate surface, a method with a slower deposition rate than that used for surfaces parallel to the substrate surface can be employed. This deposition method can also be termed an anisotropic deposition rate method. By employing this method, a structure can be formed where the conductive layer 240_2 is not formed in the region of steep sidewalls of the opening 290, but rather in the region of gently sloping sidewalls of the opening 290 and on the top surface of the conductive layer 240_1.

[0204] The apex of the end portion of the conductive layer 240_1 on the side of the opening 290 is rounded. When the apex of this end portion is rounded, it is easy to cover the rounded area with the conductive layer 240_2.

[0205] Note that even when using deposition methods with anisotropic deposition rates, a thin conductive layer, which will become the conductive layer 240_2, can sometimes form in the steep sidewall region of the opening 290. In this case, by etching at a slow etching rate after the formation of this conductive layer, the thin conductive layer formed in the steep sidewall region can be removed, while the conductive layer formed in the region outside this region can remain. This etching is sometimes referred to as light etching. Various methods such as dry etching, wet etching, and plasma treatment can be used as light etching.

[0206] Furthermore, when a portion of the conductive layer 240_2 remains between the channel formation region of the oxide semiconductor layer 230 and the sidewall of the insulating layer 280 within the opening 290, the remaining conductive layer is preferably insulated from the region of the conductive layer 240 that serves as the source electrode and the drain electrode. For example, the remaining conductive layer is preferably separated from the region of the conductive layer 240 that serves as the source electrode and the drain electrode.

[0207] The conductive layer 240_2 can be formed on the top and side surfaces of the conductive layer 240_1 in a self-aligned manner without using a mask, taking advantage of the anisotropy of the deposition rate. Therefore, there is no need to consider the overlap accuracy with the conductive layer 240_1, and the occupied area of ​​the transistor 200 is not increased. Figures 1A to 2B The transistor 200 shown has a structure suitable for highly integrated semiconductor devices.

[0208] exist Figures 1A to 2B In the transistor 200 shown, the top surface of the insulating layer 210 can be approximately parallel to the substrate surface. Similarly, the top surface of the conductive layer 220 can be approximately parallel to the substrate surface.

[0209] The conductive layer 240_2 can be formed by a deposition method with anisotropic deposition rates. Therefore, when the top surface of the conductive layer 220 is substantially parallel to the substrate surface, a conductor derived from the material of the conductive layer 240_2 is sometimes formed on the conductive layer 220 during the formation of the conductive layer 240_2. This conductor, for example, contains at least one material common to the conductive layer 240_2. This conductor is sometimes used as part of the conductive layer 220. In this case, the conductive layer formed on the top and side surfaces of the conductive layer 240_1 and used as the conductive layer 240_2 is preferably separated from the conductor formed on the top surface of the conductive layer 220. On the other hand, when the width of the opening 290 is small and the aspect ratio of the opening 290 is high, and when the top surface of the conductive layer 220 is substantially parallel to the substrate surface, sometimes the conductor derived from the material of the conductive layer 240_2 is not formed on the top surface of the conductive layer 220 or the coverage of the conductor is reduced.

[0210] exist Figures 1A to 2BIn the structure shown, the conductive layer 240_2 is not formed on the top surface of the conductive layer 220 within the opening 290 or on the side surface of the insulating layer 280 at a deeper location within the opening 290. By reducing the width of the opening 290, the deposition rate of the conductive layer 240_2 on the sidewall of the opening 290 can sometimes be slowed down at a deeper location within the opening 290. For example, when using methods such as sputtering, which have high deposition rates and are suitable for forming thicker conductive layers, although the productivity is high, the coverage at a deeper location within the opening 290, which has a high aspect ratio and a small opening diameter, can sometimes be reduced. Therefore, it is easy to selectively form the conductive layer 240_2 at and near the upper end of the opening 290. For example, it is sufficient to set the width D of the opening 290 to 100 nm or less and set the channel length L of the transistor 200 to 0.5 times or more, preferably 0.8 times or more, the width D of the opening.

[0211] Furthermore, when using sputtering methods, deeper areas of the opening can be easily covered by methods such as collimated sputtering or long-throw sputtering that increases the distance between the target and the substrate. The distance between the target and the substrate can be set by the width of the opening (290°).

[0212] When conductive layer 240_2 is formed on the top surface of conductive layer 220, this conductive layer formed on the top surface is preferably separated from the region in conductive layer 240 that serves as another of the source and drain electrodes. For example, a structure can be adopted in which conductive layer 240_2 is selectively formed on the top surface of conductive layer 220 and the top and side surfaces of conductive layer 240_1, and conductive layer 240_2 is not formed in the region on the side surface of opening 290 in insulating layer 280 that covers the channel formation region of oxide semiconductor layer 230.

[0213] Furthermore, if a portion of the conductive layer 240_2 is formed on the top surface of the conductive layer 220, then according to the uppermost conductive layer of the conductive layer 220 ( Figure 1C , Figure 1D The materials of conductive layers 220_2 and 240_2 in the example can sometimes make it difficult to distinguish the boundary between the two layers. For example, if the material of conductive layer 240_2 is the same as the material of the uppermost layer of conductive layer 220 or a part of the elements constituting the material are the same, it can sometimes be difficult to distinguish that part of conductive layer 240_2 from conductive layer 220.

[0214] In addition, while fully obtaining the characteristics of transistor 200, the side of the opening 290 of conductive layer 240_1 may also have an area not covered by conductive layer 240_2. Figure 4B yes Figure 4A A modified example, wherein a region Q11 is not covered by the conductive layer 240_2 on the side of the opening 290 of the conductive layer 240_1. Figure 4B In the structure shown, with Figure 4A In comparison, the conductive layer 240_2 is sometimes easier to manufacture.

[0215] The conductive layer 240_2 preferably covers the area from the upper end of the side surface of the conductive layer 240_1 to a depth of more than half its thickness. For example, as Figure 4B As shown, conductive layer 240_2 covers the side of conductive layer 240_1 from the height of the top surface of conductive layer 240_1 to the height of the depth d_c2, and the value of the depth d_c2 is more than 0.3 times or more than half (0.5 times) of the thickness t240_1 of conductive layer 240_1.

[0216] The conductive layer 240_2 is the region in the conductive layer 240 that mainly contacts the oxide semiconductor layer 230. As mentioned above, it is preferable to use a material that can form a good bond with the oxide semiconductor layer 230.

[0217] Figure 5A Shown in Figure 4A Examples of cross-sections shown are not circular. Additionally, in... Figure 5A In the structure shown, at least some of the corners can also be rounded. Additionally, Figure 5B From Figure 5A The diagram shows the process of extracting the insulating layer 280, conductive layer 240_1, and conductive layer 240_2, and adding conductive layer 220_2.

[0218] exist Figure 5B In this design, the angle formed by the top surface of conductive layer 220_2 and the side surface of conductive layer 240_1 is denoted as angle An1, and the angle formed by the top surface of conductive layer 220_2 and the side surface of insulating layer 280 is denoted as angle An0. Both angle An0 and angle An1 are preferably greater than 45 degrees and less than 90 degrees, and angle An1 is preferably less than angle An0. Figures 5B to 5D In this context, for example, the difference between angles An1 and An0 is greater than 0 degrees and less than 10 degrees, or greater than 0 degrees and less than 5 degrees. Additionally, in... Figures 5B to 5D In this context, for example, the angle An0 is preferably greater than 75 degrees and less than 90 degrees, more preferably greater than 80 degrees and less than 90 degrees, and even more preferably greater than 85 degrees and less than 90 degrees. The angle An1 is preferably greater than 45 degrees and less than 90 degrees, more preferably greater than 45 degrees and less than 85 degrees, and even more preferably greater than 45 degrees and less than 80 degrees.

[0219] Note that, although Figure 5B The structure shown is such that conductive layer 240_2 covers the side of conductive layer 240_1, but as... Figure 5C As shown, sometimes the conductive layer 240_2 does not cover the area below the side of the conductive layer 240_1 (the area near the insulating layer 280). Furthermore, as... Figure 5DAs shown, sometimes the conductive layer 240_2 not only covers the side of the conductive layer 240_1 but also covers the area above the side of the insulating layer 280 (the area near the conductive layer 240_1).

[0220] Note that angle An1 can also be approximately the same as angle An0. For example, the difference between angle An1 and angle An0 can be greater than 0 degrees and less than 5 degrees, or greater than 0 degrees and less than 3 degrees. Figure 6A , Figure 6B , Figure 6C and Figure 6D Shown in Figure 5A , Figure 5B , Figure 5C and Figure 5D An example where the mid-angle An1 is approximately the same as the angle An0.

[0221] exist Figures 6A to 6D In the conductive layer 240_2, the side surface protrudes more than the side surface of the insulating layer 280. This is because the side surface of the conductive layer 240_1 is more than... Figures 5A to 5D The slope is steep, so by forming a conductive layer 240_2 on the side of the conductive layer 240_1, the side of the conductive layer 240_2 is shaped to protrude beyond the side of the insulating layer 280. As an example, Figure 6A An example is shown where angle An1 is approximately perpendicular. In Figures 6B to 6D In the above, the angles An0 and An1 are preferably greater than 75 degrees and less than 90 degrees, more preferably greater than 80 degrees and less than 90 degrees, and even more preferably greater than 85 degrees and less than 90 degrees.

[0222] like Figure 6B As shown, the side surface of the conductive layer 240 protrudes by a width Ts beyond the side surface of the insulating layer 280. Therefore, the width of the opening 290 in the conductive layer 240 is reduced by this protruding portion.

[0223] Figure 7 Showing includes Figure 6A An overall image of the opening 290 of the structure shown. Note that in... Figure 7 The oxide semiconductor layer 230, insulating layer 250, and conductive layer 260 are omitted in the text.

[0224] The width Dp of the protruding portion of the conductive layer 240 in the opening 290 is Ts×2 smaller than the width D of the opening 290 in the insulating layer 280. That is, it can be expressed as Dp=D-(Ts×2).

[0225] The conductive layer 240_2 is preferably formed using an anisotropic deposition method, and the thickness Tu of the region covering the top surface of the conductive layer 240_1 is greater than the width Ts. The width Ts is preferably greater than 0 and less than 0.8 times the thickness Tu, more preferably greater than 0 and less than 0.5 times the thickness Tu, even more preferably greater than 0 and less than 0.4 times the thickness Tu, and still more preferably greater than 0 and less than 0.3 times the thickness Tu.

[0226] When the width Dp is too small, the coverage of the oxide semiconductor layer 230, insulating layer 250, and conductive layer 260 over the opening 290 is reduced. Therefore, it is preferable to reduce the difference between the width Dp and the width D. Specifically, since D-Dp=Ts×2 holds true, the difference between the width D and the width Dp (D-Dp) is preferably greater than 0 and less than 1.6 times the thickness Tu, more preferably greater than 0 and less than 1 times the thickness Tu, further preferably greater than 0 and less than 0.8 times the thickness Tu, and even more preferably greater than 0 and less than 0.6 times the thickness Tu.

[0227] In addition, based on the deposition conditions and the etching conditions when forming the opening 290, the corners of the conductive layers 240_1 and 240_2 are rounded. Figure 8A , Figure 8B and Figure 8C Examples are shown where the upper corners of conductive layer 240_1 and conductive layer 240_2 are rounded. Figure 8B This illustrates an example where the area below the side of conductive layer 240_1 (near insulating layer 280) is not covered by conductive layer 240_2. Figure 8C An example is shown where the side surface of the insulating layer 280 is also covered by the conductive layer 240_2, in addition to the side surface of the conductive layer 240_1. Figure 8A For example, it can correspond to Figure 4A The structure shown, Figure 8B For example, it can correspond to Figure 4B The structure shown. In Figures 8A to 8C In this context, for example, the difference between angles An1 and An0 is greater than 0 degrees and less than 10 degrees, or greater than 0 degrees and less than 5 degrees. Additionally, in... Figures 8A to 8C In this context, for example, the angle An0 is preferably greater than 75 degrees and less than 90 degrees, more preferably greater than 80 degrees and less than 90 degrees, and even more preferably greater than 85 degrees and less than 90 degrees. The angle An1 is preferably greater than 45 degrees and less than 90 degrees, more preferably greater than 45 degrees and less than 85 degrees, and even more preferably greater than 45 degrees and less than 80 degrees.

[0228] in addition, Figure 9A , Figure 9B , Figure 9C All shown Figures 6B to 6DAn example where the upper corner of the conductive layer 240_1 is rounded and the side of the conductive layer 240_2 protrudes beyond the side of the insulating layer 280. Figure 9B This illustrates an example where the area below the side of conductive layer 240_1 (near insulating layer 280) is not covered by conductive layer 240_2. Figure 9C An example is shown where, in addition to the sides of the conductive layer 240_1, the sides of the insulating layer 280 are also covered by the conductive layer 240_2. Figures 9A to 9C In the above, the angles An0 and An1 are preferably greater than 75 degrees and less than 90 degrees, more preferably greater than 80 degrees and less than 90 degrees, and even more preferably greater than 85 degrees and less than 90 degrees.

[0229] Figure 10A and Figure 10B They are Figure 5A and Figure 5B In a modified example, the side surface of the conductive layer 240_1 has a region with angle An1_1 and a region with angle An1_2. Figure 10B From Figure 10A A diagram showing the removal of insulating layer 280, conductive layer 240_1, and conductive layer 240_2, and the addition of conductive layer 220_2.

[0230] exist Figure 10B In the conductive layer 240_1, the side surface has a region forming an angle of angle An1_1 with the top surface of the conductive layer 220_2, and a region forming an angle of angle An1_2 with the top surface of the conductive layer 220_2. Angle An1_2 is preferably smaller than angle An1_1. Angle An1_1 is preferably greater than 75 degrees and less than 90 degrees, more preferably greater than 80 degrees and less than 90 degrees, and even more preferably greater than 85 degrees and less than 90 degrees. Angle An1_2 is preferably greater than 45 degrees and less than 90 degrees, more preferably greater than 45 degrees and less than 85 degrees, and even more preferably greater than 45 degrees and less than 80 degrees.

[0231] Notice, Figure 10B The diagram shows the structure where conductive layer 240_2 covers a region at an angle of angle An1_2 on the side of conductive layer 240_1, but as... Figure 10C As shown, the conductive layer 240_2 can cover not only the region with an angle of angle An1_2 but also the region with an angle of angle An1_1. Furthermore, as... Figure 10D As shown, sometimes the conductive layer 240_2 not only covers the side of the conductive layer 240_1 but also covers the area above the side of the insulating layer 280 (the area near the conductive layer 240_1).

[0232] <Examples of semiconductor device structures 1-2>

[0233] Figure 11AThe cross-section of the transistor 200 shown illustrates an example where the width of the conductive layer 240 of the opening 290 is smaller than the width of the insulating layer 280 of the opening 290. Figure 11B yes Figure 11A An enlarged view of region Q1B is shown. Additionally, in Figure 12 in, omit Figure 11A The shaded lines of the constituent elements other than the oxide semiconductor layer 230 in the conductive layer 240 will be denoted as the width D of the part with the largest width in the opening 290 and the width Dp of the part with the smallest width in the opening 290 in the conductive layer 240.

[0234] exist Figure 11A In the insulating layer 280, the side surface of the opening 290 has a region with an angle slightly gentler than vertical. The angle formed between the top surface of the conductive layer 220 and the side surface of the insulating layer 280 is less than 90 degrees, for example, more than 80 degrees and less than 90 degrees.

[0235] Reference Figure 7 The difference between width D and width Dp (D-Dp) is preferably less than 1.6 times the thickness Tu, more preferably less than 1 times the thickness Tu, even more preferably less than 0.8 times the thickness Tu, and even more preferably less than 0.6 times the thickness Tu.

[0236] Furthermore, when the oxide semiconductor layer 230 and the insulating layer 250 are formed using a method with high coverage, the width variation of the opening 290 is reflected in the shape of the conductive layer 260. For example, in Figure 12 In the cross-section shown, the difference between the widest and narrowest regions within the opening 290 of the conductive layer 260 is sometimes approximately the same as the difference between width D and width Dp (D-Dp).

[0237] Furthermore, when a conductive layer 260_1 is formed in addition to the oxide semiconductor layer 230 and the insulating layer 250 using a method with high coverage, the change in the width of the opening 290 is reflected in the shape of the conductive layer 260_2. As an example, Figure 12 The width De1 of the widest region and the width De2 of the narrowest region of the conductive layer 260_2 within the opening 290 are shown. The difference between width De1 and width De2 (De1-De2) is preferably less than 1.6 times the thickness Tu of the conductive layer 240_2, more preferably less than 1 times the thickness Tu, even more preferably less than 0.8 times the thickness Tu, and still more preferably less than 0.6 times the thickness Tu.

[0238] Furthermore, the thickness Tu of the conductive layer 240_2 is preferably smaller than the width D of the opening 290.

[0239] <Structure Examples of Semiconductor Devices 1-3>

[0240] Figure 13AThe angle of at least a portion of the sidewall of the insulating layer 280 of the opening 290 is shown to be greater than that of the opening 290. Figure 2A , Figure 11A Examples of gentle angles. By making the angle of the sidewall of the opening 290 gentler, the coverage of the oxide semiconductor layer 230, insulating layer 250, etc., is improved, and defects such as voids can be reduced. For example, when the angle An0 is 45 degrees or more, or 50 degrees or more and less than 80 degrees, or 75 degrees or less, 70 degrees or less, 65 degrees or less, or 60 degrees or less, the coverage of the film formed in the opening 290 is improved, and therefore it is preferred.

[0241] On the other hand, due to the smaller angle An0, the conductive layer 240_2 may sometimes also form on a portion of the sidewall of the insulating layer 280. In this case, for example, it is preferable to prevent the formation of the conductive layer 240_2 in a deeper region of the opening 290 by increasing the aspect ratio of the opening 290. Alternatively, it is preferable to remove the conductive layer formed on the sidewall by the aforementioned slight etching.

[0242] <Structure Examples of Semiconductor Devices 1-4>

[0243] like Figure 13B As shown, in the oxide semiconductor layer 230, sometimes the ratio of the thickness of the portion where the top surface of the conductive layer 240 or conductive layer 220 is the formed surface (hereinafter referred to as the first thickness) to the thickness of the portion where the sidewall of the opening 290 is the formed surface (hereinafter referred to as the second thickness) is different. For example, when a portion of the oxide semiconductor layer 230 is deposited using a sputtering method, the ratio of the first thickness to the second thickness in the oxide semiconductor layer 230 is sometimes different. For example, as... Figure 13B As shown, sometimes the ratio of the second thickness to the first thickness is less than 1, less than 0.8, or less than 0.5. In particular, there is a tendency that the closer the angle formed by the top surface of the conductive layer 220_2 and the side surface of the opening 290 is to 90 degrees, the smaller the ratio of the second thickness to the first thickness in the oxide semiconductor layer 230.

[0244] <Structure Example of a Semiconductor Device 2>

[0245] exist Figure 14A In the cross-section of the transistor 200 shown, the conductive layer 240 includes a conductive layer 240_3 between conductive layers 240_1 and 240_2, mainly in this respect... Figure 2A different. Figure 14B yes Figure 14A A magnified view of region Q2 is shown. Additionally, with... Figure 2A Common structures and common layers can be appropriately referenced. Figure 2A The records.

[0246] exist Figure 14AIn this configuration, the end portion of the conductive layer 240_3 on one side of the opening 290 is aligned with the end portion of the conductive layer 240_1 on one side of the opening 290. Furthermore, in... Figure 14A In the middle, the conductive layer 240_3 covers the top surface of the conductive layer 240_1 but does not cover the side surface of the opening 290 of the conductive layer 240_3.

[0247] exist Figure 14A In the conductive layer 240_3, the upper part of the end of the opening 290 is circular.

[0248] Conductive layers 240_1 and 240_3 can be formed using the same mask. Alternatively, conductive layer 240_1 can also be formed using conductive layer 240_3 as a mask.

[0249] The conductive layer 240_2 is provided such that it covers the top surface of the conductive layer 240_3 and the side surface of the opening 290 of the conductive layer 240_3. In addition, the conductive layer 240_2 is provided such that it covers at least a portion of the side surface of the conductive layer 240_1.

[0250] The conductive layer 240_2 can be formed in a self-aligned manner on the top surface of the conductive layer 240_3, the side surface of the conductive layer 240_3, and the side surface of the conductive layer 240_1 without using a mask, taking advantage of the anisotropy of the deposition rate.

[0251] Figure 15A Shown in Figure 14B Examples of cross-sections shown are not circular. Additionally, in... Figure 15A In the structure shown, at least some of the corners can also be rounded. Additionally, Figure 15B From Figure 15A The diagram shows the process of removing insulating layer 280, conductive layer 240_1, conductive layer 240_2 and conductive layer 240_3 and adding conductive layer 220_2.

[0252] exist Figure 15B In this design, the angle formed by the top surface of conductive layer 220_2 and the side surface of conductive layer 240_3 is angle An4, the angle formed by the top surface of conductive layer 220_2 and the side surface of conductive layer 240_1 is angle An3, and the angle formed by the top surface of conductive layer 220_2 and the side surface of insulating layer 280 is angle An0. Angle An4 is preferably smaller than angle An3.

[0253] As conductive layer 240_3, the material described in the [Conductive Layer] section below can be used. Furthermore, as a material that can be used for conductive layer 240_3, the material that can be used for conductive layer 240_2 is particularly preferred.

[0254] Figure 15C Shown in Figure 15BAn example where the upper corner of the conductive layer 240_2 is rounded. Figure 15C For example, it can correspond to Figure 14B The structure shown.

[0255] Materials Constituting Semiconductor Devices

[0256] The following describes the materials that can be used in the semiconductor device of this embodiment. Note that each layer constituting the semiconductor device of this embodiment may have a single-layer structure or a stacked structure.

[0257] [Oxide semiconductor layer 230]

[0258] As described above, the oxide semiconductor layer 230 has a channel formation region. The oxide semiconductor layer 230 also has a source region and a drain region. The source region and drain region are n-type regions (low-resistance regions) with a higher carrier concentration than the channel formation region. The oxide semiconductor layer 230 may also have a stacked structure of two or more layers.

[0259] There are no particular restrictions on the crystallinity of the semiconductor material used for the oxide semiconductor layer 230; amorphous semiconductors, single-crystal semiconductors, or semiconductors with crystallinity other than single-crystal semiconductors (microcrystalline semiconductors, polycrystalline semiconductors, or semiconductors with a portion of crystalline regions) can be used. Using single-crystal semiconductors or crystalline semiconductors can suppress the degradation of transistor characteristics, and is therefore preferred.

[0260] The bandgap of the metal oxide used as the semiconductor is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wider bandgap in the oxide semiconductor layer 230, the off-state current of the transistor 200 can be reduced. The off-state current of the OS transistor is small, so the power consumption of the semiconductor device can be significantly reduced. In addition, the OS transistor has high frequency characteristics, so the semiconductor device can operate at high speed.

[0261] Regarding the oxide semiconductor layer that can be used as the semiconductor layer of a transistor according to one aspect of the present invention, refer to the description of Embodiment 2. Detailed description is omitted here.

[0262] Furthermore, transistors using other semiconductor materials in the channel formation region can also be used in the semiconductor device of this embodiment. Examples of such other semiconductor materials include semiconductors or compound semiconductors composed of a single element.

[0263] Examples of semiconductors composed of a single element that can be used as semiconductor materials include silicon and germanium. Furthermore, examples of silicon that can be used as semiconductor materials include monocrystalline silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low-temperature polycrystalline silicon (LTPS).

[0264] Examples of compound semiconductors that can be used as semiconductor materials include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide. Boron nitride, which can be used as a semiconductor layer, preferably has an amorphous structure. Boron arsenide, which can be used as a semiconductor layer, preferably comprises a crystal with a cubic structure. Furthermore, examples of compound semiconductors include organic semiconductors and nitride semiconductors. The aforementioned oxide semiconductors are also types of compound semiconductors. These semiconductor materials may also contain impurities as dopants.

[0265] Alternatively, transistors using a layered material as a semiconductor in the channel formation region can also be used in the semiconductor device of this embodiment. Note that details regarding the layered material will be described in Embodiment 5.

[0266] [Insulating layer]

[0267] The insulating layers (insulating layer 210, insulating layer 250, insulating layer 280, etc.) included in the semiconductor device are preferably inorganic insulating films. Examples of inorganic insulating films include oxide insulating films, nitride insulating films, oxynitride insulating films, and oxynitride insulating films. Examples of oxide insulating films include silicon oxide films, aluminum oxide films, magnesium oxide films, gallium oxide films, germanium oxide films, yttrium oxide films, zirconium oxide films, lanthanum oxide films, neodymium oxide films, hafnium oxide films, tantalum oxide films, cerium oxide films, gallium zinc oxide films, and hafnium aluminum oxide films. Examples of nitride insulating films include silicon nitride films and aluminum nitride films. Examples of oxynitride insulating films include silicon oxynitride films, aluminum oxynitride films, gallium oxynitride films, yttrium oxynitride films, and hafnium oxynitride films. Examples of oxynitride insulating films include silicon oxynitride films and aluminum oxynitride films. Furthermore, organic insulating films can also be used as insulating layers included in the semiconductor device.

[0268] For example, when miniaturizing and highly integrating transistors, problems such as leakage current sometimes occur due to the thinning of the gate insulating layer. By using a material with a high relative permittivity (high-k) in the gate insulating layer, it is possible to achieve low voltage during transistor operation while maintaining the physical thickness. Furthermore, the equivalent oxide thickness (EOT) of the gate insulating layer can be reduced. On the other hand, by using a material with a low relative permittivity in the insulating layer used as an interlayer film, parasitic capacitance generated between wirings can be reduced. Therefore, it is preferable to select materials based on the function of the insulating layer. Moreover, materials with a low relative permittivity are also materials with high dielectric strength.

[0269] Materials with relatively high permittivity include, for example, aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0270] Examples of materials with low relative permittivity include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon oxynitride, as well as resins such as polyesters, polyolefins, polyamides (nylon, aramids, etc.), polyimides, polycarbonates, and acrylic resins. Other inorganic insulating materials with low relative permittivity include fluorine-containing silicon oxide, carbon-containing silicon oxide, and silicon oxide containing both carbon and nitrogen. Furthermore, porous silicon oxides can also be used. These silicon oxides may also contain nitrogen.

[0271] Furthermore, ferroelectric materials can be used as the insulating layer included in the semiconductor device. Examples of ferroelectric materials include metal oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide. Additionally, examples of ferroelectric materials include hafnium oxide with the addition of element J1 (here, element J1 is selected from one or more of zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.). Here, the ratio of the number of hafnium atoms to the number of element J1 atoms can be appropriately set; for example, the ratio can be set to 1:1 or close to it. Furthermore, examples of ferroelectric materials include zirconium oxide with the addition of element J2 (here, element J2 is selected from one or more of hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.). Furthermore, the ratio of zirconium atoms to element J2 atoms can be appropriately set; for example, the ratio can be set to 1:1 or close to it. Additionally, lead titanate (PbTiO2) can also be used as a material that can exhibit ferroelectric properties. XPiezoelectric ceramics with perovskite structure include barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate.

[0272] Furthermore, metal nitrides containing elements M1, M2, and nitrogen can be cited as materials that can exhibit ferroelectric properties. Here, element M1 is selected from one or more of aluminum, gallium, indium, etc. Furthermore, element M2 is selected from one or more of boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. Furthermore, the ratio of the number of atoms of element M1 to the number of atoms of element M2 can be appropriately set. Furthermore, metal oxides containing elements M1 and nitrogen sometimes exhibit ferroelectric properties even without element M2. Furthermore, materials that can exhibit ferroelectric properties include those to which element M3 is added. Note that element M3 is selected from one or more of magnesium, calcium, strontium, zinc, cadmium, etc. Here, the ratio of the number of atoms of element M1, the number of atoms of element M2, and the number of atoms of element M3 can be appropriately set.

[0273] In addition, perovskite-type oxynitrides such as SrTaO2N and BaTaO2N, and κ-type alumina such as GaFeO3 can be cited as materials that can exhibit ferroelectric properties.

[0274] Note that examples of metal oxides and metal nitrides are shown in the above description, but the invention is not limited to these examples. For instance, metal oxynitrides with nitrogen added to the aforementioned metal oxides or metal oxynitrides with oxygen added to the aforementioned metal nitrides may also be used.

[0275] Furthermore, as a material that can be ferroelectric, for example, a mixture or compound composed of multiple materials selected from those listed above can be used. Alternatively, the insulating layer 130, which will be described in Embodiment 3, can have a stacked structure composed of multiple materials selected from those listed above. Note that the crystal structure (properties) of the materials listed above may vary not only depending on the deposition conditions but also depending on various processes, etc. Therefore, in this specification, materials exhibiting ferroelectricity are referred not only to ferroelectric materials but also to materials that can be ferroelectric.

[0276] Metal oxides containing one or both of hafnium and zirconium can exhibit ferroelectricity even in thin films of a few nanometers. Furthermore, metal oxides containing one or both of hafnium and zirconium can exhibit ferroelectricity even with a very small area. Therefore, by using metal oxides containing one or both of hafnium and zirconium, miniaturization of semiconductor devices can be achieved.

[0277] In this specification and the like, a ferroelectric material formed in a layered manner is sometimes referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Furthermore, in this specification and the like, a device comprising the aforementioned ferroelectric layer, metal oxide film, or metal nitride film is sometimes referred to as a ferroelectric device.

[0278] Furthermore, ferroelectricity is believed to arise from the displacement of oxygen or nitrogen in the crystal contained within the ferroelectric layer by an external electric field. Moreover, the presence of ferroelectricity is presumed to depend on the crystal structure of the crystal contained within the ferroelectric layer. Therefore, for the insulating layer to exhibit ferroelectricity, the insulating layer 130 needs to contain a crystal. In particular, the insulating layer preferably contains a crystal with an orthorhombic crystal structure, thereby exhibiting ferroelectricity. Additionally, the crystal structure of the crystal contained in the insulating layer can also be selected from one or more of the tetragonal, orthorhombic, monoclinic, and hexagonal crystal systems. Furthermore, the insulating layer can also have an amorphous structure. In this case, the insulating layer can also have a composite structure of amorphous and crystalline structures.

[0279] Furthermore, by adding a Group 3 element from the periodic table to an oxide containing one or both of hafnium and zirconium, the oxygen vacancy concentration in the oxide is increased, making it easier to form a crystal with an orthorhombic crystal structure. Therefore, the proportion of crystals with an orthorhombic crystal structure is increased, thereby improving remanent polarization, which is preferable. On the other hand, if too much Group 3 element is added, the crystallinity of the oxide may decrease, making it less likely to exhibit ferroelectricity. Therefore, the content of the Group 3 element in the oxide containing one or both of hafnium and zirconium is preferably 0.1 atomic% or more and 10 atomic% or less, more preferably 0.1 atomic% or more and 5 atomic% or less, and even more preferably 0.1 atomic% or more and 3 atomic% or less. Here, the content of the Group 3 element refers to the proportion of the number of Group 3 elements in the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably selected from one or more of scandium, lanthanum, and yttrium, more preferably from one or both of lanthanum and yttrium.

[0280] Furthermore, by surrounding a transistor using metal oxides with an insulating layer that suppresses the permeation of impurities and oxygen, the electrical characteristics of the transistor can be stabilized. For example, the insulating layer that suppresses the permeation of impurities and oxygen can be a single layer or a stack of insulating layers selected from one or more of boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, the material used for the insulating layer that suppresses the permeation of impurities and oxygen can be metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, as well as nitrides such as aluminum nitride and silicon nitride, and oxynitrides such as silicon oxynitride.

[0281] Specifically, materials used as insulating layers that suppress the permeation of water, impurities such as hydrogen, and oxygen include, for example, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and oxides containing aluminum and hafnium (hafnium aluminate). Additionally, nitrides such as aluminum nitride, titanium aluminum nitride, titanium nitride, and silicon nitride can be cited as examples. Furthermore, nitrogen oxides such as silicon oxynitride can be cited as examples.

[0282] Furthermore, the insulating layer, such as the gate insulating layer, that contacts the oxide semiconductor layer or is disposed near the oxide semiconductor layer is preferably an insulating layer having regions containing oxygen (hereinafter sometimes referred to as excess oxygen) that has been removed by heating. For example, when an insulating layer having regions containing excess oxygen contacts the oxide semiconductor layer or is disposed near the oxide semiconductor layer, the oxygen vacancies present in the oxide semiconductor layer can be reduced. Examples of materials that readily form insulating layers containing regions containing excess oxygen include silicon oxide, silicon oxynitride, or porous silicon oxide.

[0283] As an insulating layer in contact with or near the oxide semiconductor layer, a hydrogen-barrier insulating layer is preferably used. This insulating layer's hydrogen-barrier properties suppress hydrogen diffusion into the oxide semiconductor layer.

[0284] Materials used as insulating layers with the function of capturing or fixing hydrogen include metal oxides such as hafnium oxides, magnesium oxides, aluminum oxides, aluminum and hafnium oxides (hafnium aluminate), and hafnium and silicon oxides (hafnium silicate). Furthermore, these metal oxides may also contain zirconium, for example, oxides containing hafnium and zirconium.

[0285] An insulating layer with the function of trapping or fixing hydrogen preferably has an amorphous structure. In metal oxides with an amorphous structure, the ability to trap or fix hydrogen is high because some oxygen atoms have dangling bonds. Therefore, when the insulating layer has an amorphous structure, the function of trapping or fixing hydrogen can be improved. For example, silicon can be added to the above-mentioned metal oxide to achieve an amorphous structure. For example, an oxide containing hafnium and silicon (hafnium silicate) is preferred.

[0286] By giving the insulating layer an amorphous structure, the formation of grain boundaries can be suppressed. Suppressing grain boundary formation improves the flatness of the insulating layer. This results in a more uniform thickness distribution of the insulating layer, reducing extremely thin portions and thus improving its withstand voltage. Furthermore, the thickness distribution of the film disposed on the insulating layer can be made more uniform. Additionally, suppressing grain boundary formation in the insulating layer reduces leakage current caused by defect states at grain boundaries. Therefore, the insulating layer can be used as an insulating film with low leakage current.

[0287] Note that the aforementioned insulating layer sometimes has one or both of a crystalline region and a grain boundary in a portion thereof.

[0288] Furthermore, the ability to capture or fix the corresponding substance can also be described as a property that makes it difficult for the corresponding substance to diffuse. Therefore, the ability to capture or fix the corresponding substance can be referred to as a barrier property.

[0289] In this specification, the term "barrier insulating layer" refers to an insulating layer that possesses barrier properties. Furthermore, barrier properties refer to the property that makes it difficult for the corresponding substance to diffuse (also referred to as the property that makes it difficult for the corresponding substance to pass through, the property that the corresponding substance has low permeability, or the function of inhibiting the diffusion of the corresponding substance). Additionally, hydrogen, referred to as the corresponding substance, includes, for example, hydrogen atoms, hydrogen molecules, water molecules, and OH groups. - At least one of the following: substances bonded to hydrogen. Furthermore, unless otherwise specified, impurities referred to as corresponding substances refer to impurities in the channel-forming region or semiconductor layer, such as at least one of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N₂O, NO, NO₂, etc.), copper atoms, etc. Additionally, oxygen referred to as corresponding substances refers to at least one of oxygen atoms, oxygen molecules, etc.

[0290] Materials that can be used as hydrogen barrier insulating layers include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, or silicon oxynitride.

[0291] Materials used as oxygen barrier insulating layers include, for example, oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, zinc gallium oxide, silicon nitride, and silicon oxynitride. Furthermore, oxides containing one or both of aluminum and hafnium include, for example, aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate).

[0292] Since the insulating layer 210 is used as an interlayer film, it is preferable to use a material with a low relative permittivity. By using a material with a low relative permittivity as the interlayer film, the parasitic capacitance generated between the wirings can be reduced.

[0293] The insulating layer 210 is preferably a hydrogen-barrier insulating layer. When the insulating layer 210 disposed below the oxide semiconductor layer 230 has hydrogen-barrier properties, hydrogen diffusion from below the transistor 200 to the oxide semiconductor layer 230 can be suppressed. For example, a silicon nitride film is preferably used as the insulating layer 210.

[0294] Furthermore, the insulating layer 210 is preferably an insulating layer with the function of trapping or fixing hydrogen. When the insulating layer 210 has the function of trapping or fixing hydrogen, hydrogen in the oxide semiconductor layer 230 diffuses to the insulating layer 210 through the conductive layer 220, which can trap or fix the hydrogen in the insulating layer 210. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced.

[0295] Furthermore, the concentration of impurities such as water and hydrogen in the insulating layer 210 is preferably reduced. This suppresses the mixing of impurities such as water and hydrogen into the channel formation region of the oxide semiconductor layer 230.

[0296] Figure 2A An example of a single-layer structure is shown for insulating layer 210. Alternatively, insulating layer 210 may have a stacked structure of two or more layers. For example, insulating layer 210 may have a two-layer structure consisting of a first insulating layer and a second insulating layer on the first insulating layer. In this case, for example, it is preferable to use a hydrogen-blocking insulating layer as the first insulating layer and an insulating layer with the function of trapping or fixing hydrogen as the second insulating layer. Specifically, it is preferable to use a silicon nitride film as the first insulating layer and a hafnium oxide film, hafnium silicate film, or aluminum oxide film as the second insulating layer.

[0297] Since the insulating layer 280 is used as an interlayer film, it is preferable to use a material with a low relative permittivity. By using a material with a low relative permittivity as the interlayer film, the parasitic capacitance generated between the wirings can be reduced. For example, silicon oxide or silicon oxynitride can be used as the insulating layer 280.

[0298] Furthermore, the concentration of impurities such as water and hydrogen in the insulating layer 280 is preferably reduced. This suppresses the incorporation of impurities such as water and hydrogen into the channel formation region of the oxide semiconductor layer 230.

[0299] For example, an insulating layer having regions containing excess oxygen can be deposited using sputtering in an oxygen-containing atmosphere. By using sputtering, which does not require the use of hydrogen-containing molecules as a deposition gas, the hydrogen concentration in the insulating layer 280 can be reduced. Thus, by depositing at least a portion of the layer constituting the insulating layer 280 using sputtering, oxygen can be supplied from the insulating layer 280 to the channel formation region of the oxide semiconductor layer 230, thereby reducing oxygen vacancies and V. O H.

[0300] In addition, the thickness of the insulating layer 280 on the conductive layer 220 affects the channel length of the transistor 200, so the thickness of the insulating layer 280 is appropriately set according to the design value of the channel length of the transistor 200.

[0301] Figure 2A An example is shown where the insulating layer 280 has a single-layer structure. Alternatively, the insulating layer 280 may have a stacked structure of two or more layers. For example, as shown... Figure 17A As shown, the insulating layer 280 can have a three-layer structure consisting of insulating layer 280_1, insulating layer 280_2 on insulating layer 280_1, and insulating layer 280_3 on insulating layer 280_2. Preferably, the insulating layer 280_2 uses a material with a relatively low permittivity, and the insulating layers 280_1 and 280_3 use oxygen-barrier insulating layers. This suppresses oxidation of the conductive layers 220 and 240 and prevents high resistivity.

[0302] For example, preferably, silicon nitride film or aluminum oxide film is used as insulating layer 280_1 and insulating layer 280_3, and silicon oxide film is used as insulating layer 280_2. In addition, insulating layer 280_1 and insulating layer 280_3 may each have a stacked structure of two or more layers.

[0303] The insulating layer 250 is preferably a hydrogen-barrier insulating layer. When the insulating layer 250 disposed on the oxide semiconductor layer 230 has hydrogen-barrier properties, it can suppress the diffusion of hydrogen contained in the conductive layer 260 into the oxide semiconductor layer 230. For example, a silicon nitride film has high hydrogen-barrier properties, so it is suitable as the insulating layer 250.

[0304] Furthermore, since the insulating layer 250 is in contact with the oxide semiconductor layer 230, it is preferable to use an insulating layer with the function of trapping or fixing hydrogen. This allows for more effective trapping or fixing of hydrogen contained in the oxide semiconductor layer 230. Consequently, the hydrogen concentration in the oxide semiconductor layer 230 (especially in the channel formation region of the transistor) can be reduced. This, in turn, reduces the Vt in the channel formation region. O H, which can make the channel forming region type i or substantially type i.

[0305] Furthermore, the insulating layer 250 is preferably an insulating layer having regions containing excess oxygen. This allows oxygen to be supplied from the insulating layer 250 to the oxide semiconductor layer 230, thereby reducing oxygen vacancies in the oxide semiconductor layer 230. Silicon oxide films or silicon oxynitride films, etc., have thermal stability and are therefore suitable for use as the insulating layer 250.

[0306] Figure 2A An example of a single-layer structure for the insulating layer 250 is shown. Alternatively, the insulating layer 250 may have a stacked structure of two or more layers. In this case, the insulating layer 250 is preferably formed from two or more films. By using two or more films as the insulating layer 250, the insulating layer 250 can have multiple functions. Examples of functions of the insulating layer 250 include, for instance, the function of extracting hydrogen from the oxide semiconductor layer 230 and the function of suppressing hydrogen diffusion into the oxide semiconductor layer 230.

[0307] For example, insulating layer 250 may have a two-layer structure consisting of a first insulating layer and a second insulating layer on the first insulating layer. In this case, the first insulating layer is in contact with the oxide semiconductor layer 230. For example, it is preferable to use an insulating layer with hydrogen trapping or fixing function as the first insulating layer and a hydrogen barrier insulating layer as the second insulating layer. By adopting this structure, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced, and hydrogen diffusion into the oxide semiconductor layer 230 can be suppressed. Therefore, a highly reliable transistor can be realized.

[0308] Alternatively, for example, it is preferable to use an insulating layer having regions containing excess oxygen as the first insulating layer and a hydrogen-barrier insulating layer as the second insulating layer. Alternatively, for example, it is preferable to use an insulating layer having regions containing excess oxygen as the first insulating layer and an insulating layer having the function of trapping or fixing hydrogen as the second insulating layer. By employing this structure, the amount of oxygen vacancies and the hydrogen concentration in the oxide semiconductor layer 230 can be reduced, and hydrogen diffusion into the oxide semiconductor layer 230 can be suppressed. Therefore, a highly reliable transistor can be realized.

[0309] For example, insulating layer 250 may include a third insulating layer between oxide semiconductor layer 230 and first insulating layer. In other words, insulating layer 250 may have a three-layer structure consisting of a third insulating layer, a first insulating layer on the third insulating layer, and a second insulating layer on the first insulating layer.

[0310] For example, preferably, an insulating layer having a region containing excess oxygen or an insulating layer containing a material with a low relative permittivity is used as the third insulating layer, an insulating layer having the function of trapping or fixing hydrogen is used as the first insulating layer, and an insulating layer that blocks hydrogen and oxygen is used as the second insulating layer. The third insulating layer is preferably a silicon oxide film or a silicon oxynitride film. By using an oxide film as the third insulating layer in contact with the oxide semiconductor layer 230, oxygen can be supplied to the oxide semiconductor layer 230. Furthermore, by providing the second insulating layer, the diffusion of oxygen contained in the third insulating layer to the conductive layer 260 can be suppressed, thereby suppressing the oxidation of the conductive layer 260. In addition, the reduction in the amount of oxygen supplied from the third insulating layer to the oxide semiconductor layer 230 can be suppressed.

[0311] For example, insulating layer 250 may include a fourth insulating layer between oxide semiconductor layer 230 and third insulating layer. In other words, insulating layer 250 may have a four-layer structure consisting of a fourth insulating layer, a third insulating layer on the fourth insulating layer, a first insulating layer on the third insulating layer, and a second insulating layer on the first insulating layer.

[0312] As the fourth insulating layer, an oxygen-barrier insulating layer is preferably used. Alternatively, the first to third insulating layers can have the same structure as the layers used in the three-layer structure described above. The fourth insulating layer is the layer in contact with the oxide semiconductor layer 230 and the conductive layer 240. When the fourth insulating layer has oxygen-barrier properties, oxygen detachment from the oxide semiconductor layer 230 can be suppressed. Furthermore, oxidation of the side surface of the conductive layer 240, preventing the formation of an oxide film on that side, can be suppressed. Therefore, a decrease in the on-state current or field-effect mobility of the transistor 200 can be suppressed.

[0313] As the fourth insulating layer, an aluminum oxide film is preferably used, for example. The aluminum oxide film has the function of trapping or fixing hydrogen, and is therefore suitable as the fourth insulating layer in contact with the oxide semiconductor layer 230. Specifically, the insulating layer 250 preferably adopts a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are sequentially stacked from one side of the oxide semiconductor layer 230.

[0314] The insulating layer 250 is preferably a thin film. For example, by setting the thickness of the insulating layer 250 to 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less, the subthreshold swing value (also known as the S-value), one of the transistor characteristics, can be reduced. The S-value refers to the amount of change in gate voltage when the drain current changes by a single digit at a constant drain voltage in the subthreshold region.

[0315] Furthermore, the thickness of each layer constituting the insulating layer 250 is preferably 0.1 nm or more and 10 nm or less, more preferably 0.1 nm or more and 5 nm or less, even more preferably 0.5 nm or more and 5 nm or less, even more preferably 1 nm or more and less than 5 nm, and even more preferably 1 nm or more and 3 nm or less. At least a portion of each layer constituting the insulating layer 250 may include a region having the aforementioned thickness.

[0316] Typically, the thicknesses of the fourth, third, first, and second insulating layers are 1 nm, 2 nm, 2 nm, and 1 nm, respectively. This structure allows for good electrical characteristics even when transistors are miniaturized or highly integrated.

[0317] Alternatively, in the four-layer insulating layer 250, the second insulating layer may not be provided. For example, an insulating layer with oxygen-barrier properties can be used as the fourth insulating layer, an insulating layer containing a material with a relatively low permittivity can be used as the third insulating layer, and an insulating layer with hydrogen-trapping or fixing functions can be used as the first insulating layer. Specifically, a three-layer structure in which an aluminum oxide film, a silicon oxide film, and a hafnium oxide film are sequentially stacked from the oxide semiconductor layer 230 side can be adopted.

[0318] Furthermore, when forming the insulating layer 250 with a multilayer structure of multiple insulating films, it is preferable to use an atomic layer deposition (ALD) process performed twice or more. For example, it is preferable to form two or more insulating films among the multiple insulating films included in the insulating layer 250 using an ALD process. By forming at least two or more insulating films using an ALD process, the coverage and thickness uniformity of the insulating layer 250 can be improved. In addition, by continuously forming two or more films, such as two or more insulating films, using an ALD process, productivity can be improved.

[0319] [Conductive layer]

[0320] The conductive layers (conductive layer 220, conductive layer 240, conductive layer 260, etc.) included in the semiconductor device can be made of metal elements selected from tungsten, copper, aluminum, chromium, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., alloys containing the above-mentioned metal elements, or alloys combining the above-mentioned metal elements. Furthermore, nitrides of alloys containing the above-mentioned metal elements or oxides of such alloys can also be used. For example, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc., are preferred. In addition, semiconductors with high conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicides can also be used.

[0321] Furthermore, conductive materials containing nitrogen, such as tantalum nitrides, titanium nitrides, molybdenum nitrides, tungsten nitrides, ruthenium nitrides, tantalum and aluminum nitrides, or titanium and aluminum nitrides, as well as conductive materials containing oxygen, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel, and materials containing metallic elements such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are not easily oxidized, have the function of inhibiting oxygen diffusion, or maintain conductivity even when absorbing oxygen. Examples of oxygen-containing conductive materials include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, ITSO, indium zinc oxide, and indium zinc oxide containing tungsten oxide. In this specification, conductive films deposited using oxygen-containing conductive materials are sometimes referred to as oxide conductive films.

[0322] Conductive materials with tungsten, copper, or aluminum as the main components have high conductivity and are therefore preferred.

[0323] Furthermore, multiple conductive layers formed from the aforementioned materials can be stacked. For example, a stacked structure combining materials containing the aforementioned metallic elements and conductive materials containing oxygen can also be used. Furthermore, a stacked structure combining materials containing the aforementioned metallic elements and conductive materials containing nitrogen can also be used. Additionally, a stacked structure combining materials containing the aforementioned metallic elements, conductive materials containing oxygen, and conductive materials containing nitrogen can also be used.

[0324] Furthermore, when using metal oxides in the channel formation region of a transistor, a stacked structure combining a material containing the aforementioned metal element and an oxygen-containing conductive material is preferably used as the conductive layer serving as the gate electrode. In this case, it is preferable to provide the oxygen-containing conductive material on one side of the channel formation region. By providing the oxygen-containing conductive material on one side of the channel formation region, oxygen detached from this conductive material can be easily supplied to the channel formation region.

[0325] Both conductive layers 220 and 240 are conductive layers in contact with the oxide semiconductor layer 230. Therefore, it is preferable to use conductive materials that are not easily oxidized, conductive materials that maintain low resistance even if oxidized, conductive metal oxides (also known as oxide conductors), or conductive materials that have the function of inhibiting oxygen diffusion. Examples of such conductive materials include nitrogen-containing conductive materials and oxygen-containing conductive materials. As a result, the decrease in conductivity of conductive layers 220 and 240 can be suppressed.

[0326] By using an oxygen-containing conductive material as conductive layer 220, conductivity can be maintained even if conductive layer 220 absorbs oxygen. Similarly, by using an oxygen-containing conductive material as conductive layer 240, conductivity can be maintained even if conductive layer 240 absorbs oxygen. Furthermore, when an oxygen-containing insulating layer such as hafnium oxide is used as insulating layer 210, conductivity of conductive layer 220 can also be maintained, which is therefore preferred. As conductive layer 220 and conductive layer 240, ITO, ITSO, In-Zn oxides, etc., are preferred, for example.

[0327] When both conductive layer 220 and conductive layer 240 have a stacked structure, by using an oxygen-containing conductive material as the layer with the largest contact area with oxide semiconductor layer 230 in the stacked structure, the contact resistance between conductive layer 220 and oxide semiconductor layer 230 and between conductive layer 240 and oxide semiconductor layer 230 can be reduced.

[0328] The conductive layer 220_1 may also have a stacked structure of two or more layers. When the conductive layer 220_1 has a stacked structure of two layers, it is preferable that the lower layer of the conductive layer 220_1 uses a conductive material that is not easily oxidized or a conductive material that has the function of inhibiting oxygen diffusion, the upper layer of the conductive layer 220_1 uses a material with high conductivity, and the conductive layer 220_2 uses a conductive material containing oxygen (more preferably an oxide conductor). Specifically, it is preferable that titanium nitride is used as the lower layer of the conductive layer 220_1, tungsten is used as the upper layer of the conductive layer 220_1, and an oxide conductor (e.g., ITO, ITSO, or In-Zn oxide) is used as the conductive layer 220_2. In this case, the titanium nitride film is in contact with the insulating layer 210, and the oxide conductive film is in contact with the oxide semiconductor layer 230. Furthermore, the oxide conductor is used as the layer closest to the channel formation region of the oxide semiconductor layer 230. Compared to tungsten, the oxide conductor has a lower contact resistance with the oxide semiconductor layer 230, thus shortening the current path between the source and drain and increasing the on-state current of the transistor 200. When an oxide insulating layer is used as the insulating layer 210, excessive oxidation of the insulating layer 210 due to the conductive layer 220 can be suppressed. Furthermore, by using a metal material (in this case, tungsten) with higher conductivity than the oxide conductor and titanium nitride as the upper layer of the conductive layer 220_1, the conductivity of the conductive layer 220 can be improved.

[0329] Figure 2A The conductive layer 240 shown has a two-layer structure: a conductive layer 240_1 and a conductive layer 240_2 on the conductive layer 240_1. In this case, for example, it is preferable to use an oxide conductor as the conductive layer 240_2, and to use a material with higher conductivity than the conductive layer 240_2 as the conductive layer 240_1. Specifically, ITO, ITSO, or In-Zn oxide is preferably used as the conductive layer 240_2, and ITSO is particularly preferred. Tungsten, copper, aluminum, or an aluminum-containing alloy is preferably used as the conductive layer 240_1, and tungsten is particularly preferred. Furthermore, ruthenium, titanium nitride, or tantalum nitride can also be used as the conductive layer 240_1. By using an oxide conductor as the conductive layer 240_2, which mainly contacts the oxide semiconductor layer 230, the contact resistance between the conductive layer 240_2 and the oxide semiconductor layer 230 can be reduced. Furthermore, by using a material with higher conductivity than oxide conductors as a layer constituting conductive layer 240, the conductivity of conductive layer 240 can be improved.

[0330] Alternatively, an oxygen-containing conductive material can be used as conductive layer 240_1, and a material with higher conductivity than conductive layer 240_1 can be used as conductive layer 240_2. In this case, an oxide conductor is used as the layer in conductive layer 240 closest to the channel formation region of oxide semiconductor layer 230. Therefore, the current path between the source and drain can be shortened, thereby increasing the on-state current of transistor 200.

[0331] The conductive layer 260 includes a region used for gate wiring. The conductive layer 260 is preferably made of a highly conductive material such as tungsten. Furthermore, as the conductive layer 260, a conductive material that is not easily oxidized or a conductive material that has the function of suppressing oxygen diffusion is preferably used. As mentioned above, examples of such conductive materials include nitrogen-containing conductive materials (e.g., titanium nitride or tantalum nitride) and oxygen-containing conductive materials (e.g., ruthenium oxide). This suppresses the decrease in conductivity of the conductive layer 260.

[0332] The conductive layer 260 preferably uses a conductive material containing the metal element and oxygen contained in the metal oxide forming the channel. Alternatively, a conductive material containing the aforementioned metal element and nitrogen (e.g., titanium nitride, tantalum nitride, etc.) may be used. Furthermore, one or more selected from ITO, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, In-Zn oxide, and ITSO may be used. Additionally, indium gallium zinc oxide containing nitrogen may be used. By using the above materials, hydrogen contained in the metal oxide forming the channel can sometimes be trapped. Alternatively, hydrogen mixed in from an external insulating layer or the like can sometimes be trapped.

[0333] Figure 2A The conductive layer 260 shown has a two-layer structure: a conductive layer 260_1 and a conductive layer 260_2 on the conductive layer 260_1. Preferably, for example, a titanium nitride film is used as the conductive layer 260_1, and a tungsten film is used as the conductive layer 260_2. Alternatively, it is preferable to use a tantalum nitride film as the conductive layer 260_1 and a copper film as the conductive layer 260_2. By adopting this structure, the conductivity of the conductive layer 260 can be improved.

[0334] Furthermore, the conductive layer 260 may also have a stacked structure of three or more layers. For example, the conductive layer 260 may also have a three-layer structure of a tantalum nitride film, a titanium nitride film on the tantalum nitride film, and a tungsten film on the titanium nitride film.

[0335] [Substrate]

[0336] Substrates for forming transistors can be, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (yttrium-stabilized zirconia substrates, etc.), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon-germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, semiconductor substrates having insulating regions within the aforementioned semiconductor substrates, such as SOI (Silicon on Insulator) substrates, can also be used. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, or conductive resin substrates. Alternatively, substrates containing metal nitrides or metal oxides can be used. Furthermore, examples include insulating substrates with conductors or semiconductors, semiconductor substrates with conductors or insulators, and conductive substrates with semiconductors or insulators. Substrates on which elements are disposed can also be used. Examples of components mounted on a substrate include capacitors, resistors, switching elements, light-emitting elements, and storage elements.

[0337] The above is a description of the materials that can be used in the semiconductor device of this embodiment.

[0338] like Figure 17A As shown, in one embodiment of the present invention, the semiconductor device may also include an insulating layer 283 on the transistor 200. Specifically, the insulating layer 283 may also be provided on the conductive layer 260 and the insulating layer 250.

[0339] As the insulating layer 283, a hydrogen-blocking insulating layer is preferably used. By adopting this structure, hydrogen diffusion from above the transistor 200 to the oxide semiconductor layer 230 can be suppressed.

[0340] exist Figure 2A In the transistor 200 shown, both conductive layers 260_1 and 260_2 are located within the opening 290. Furthermore, as the miniaturization of the transistor 200 progresses and the width of the opening 290 decreases, it becomes difficult to arrange all the layers constituting the conductive layer 260 within the opening 290. Depending on the width of the opening 290 and the respective thicknesses of the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260_1, sometimes the conductive layer 260_1 is disposed within the opening 290, and the conductive layer 260_2 is disposed at a position overlapping with the opening 290 (see reference). Figure 17B ).

[0341] The following is for reference Figures 18A to 22CThis section illustrates examples of transistor structures that differ from transistor 200. Note that descriptions that are repeated above are omitted here; only the differences are explained in detail. Furthermore, even if components differ in location or shape, they may sometimes be given the same symbol and their descriptions omitted when their functions are the same.

[0342] [Transistor 200A]

[0343] Figure 18A This is a plan view of a semiconductor device including transistor 200A. Figure 18B It is along Figure 18A The cross-sectional view of the dotted line A1-A2 shown. Figure 18C It is along Figure 18A The cross-sectional view shown is along the dashed-dot line A3-A4. Note that along... Figure 18B and Figure 18C The cross-sectional view of the dotted lines A5-A6 shown can be referenced. Figure 1E .

[0344] Figures 18A to 18C The semiconductor device shown includes an insulating layer 210 on a substrate (not shown), a transistor 200A on the insulating layer 210, insulating layers 280 and 284 on the insulating layer 210, an insulating layer 285 on the insulating layer 284, and a conductive layer 265 on the transistor 200A, insulating layers 284, and insulating layers 285. Insulating layers 210, 280, 284, and 285 are used as interlayer films.

[0345] Figures 18A to 18C The semiconductor device shown includes a conductive layer 265, an insulating layer 284, and an insulating layer 285, which in this respect is similar to... Figures 1A to 1E The semiconductor devices shown are different.

[0346] Conductive layer 265 is used as gate wiring. Conductive layer 265 can use materials that are also available for conductive layer 260.

[0347] Transistor 200A includes a conductive layer 220, a conductive layer 240 on an insulating layer 280, an oxide semiconductor layer 230, an insulating layer 250 on the oxide semiconductor layer 230, and a conductive layer 260 on the insulating layer 250. The conductive layer 265 has a region in contact with the conductive layer 260. Note that the conductive layer 265 can also be considered as a component of transistor 200A. Additionally, an insulating layer 284 is disposed on the insulating layer 250.

[0348] In transistor 200A, the stacked structure of conductive layer 220 to insulating layer 250 is the same as that of transistor 200 described above, so detailed description is omitted.

[0349] like Figure 18B and Figure 18CAs shown, the insulating layer 284 is disposed on the insulating layer 250. Furthermore, an opening 270 extending into the insulating layer 250 is provided at a position on the insulating layer 284 that overlaps with the opening 290. The conductive layer 260 is disposed such that at least a portion of it is located within the opening 270. The conductive layer 260 contacts the insulating layer 250 within the opening 270.

[0350] The conductive layer 260 is provided in such a way that it is embedded in the openings 290 and 270. The conductive layer 260 has a portion that is opposite to the oxide semiconductor layer 230 separated by the insulating layer 250 in the opening 290 and a portion that is located in the opening 270.

[0351] Figure 18B and Figure 18C An example is shown in which conductive layers 260_1 and 260_2 are disposed within the opening 290. Furthermore, as transistor miniaturization progresses and the widths of the openings 290 and 270 decrease, it becomes difficult to arrange all layers constituting the conductive layer 260 within the openings 290 and 270. For example, sometimes only conductive layer 260_1 is disposed within the opening 290, and both conductive layers 260_1 and 260_2 are disposed within the opening 270. Additionally, sometimes only conductive layer 260_1 is disposed within the opening 270.

[0352] The portion of conductive layer 265 that does not overlap with opening 290 is primarily located on insulating layer 285. Therefore, conductive layer 265 mainly overlaps with conductive layer 240 through insulating layer 284 and insulating layer 285. This increases the physical distance between conductive layer 265 and conductive layer 240, reducing parasitic capacitance between them. Furthermore, conductive layer 240 and conductive layer 265 may also have portions that do not overlap through insulating layer 285.

[0353] Figure 18B and Figure 18C An example is shown where the width of opening 270 is smaller than the width of opening 290. A smaller opening 270 allows for a greater physical distance between conductive layer 240 and conductive layer 260, thus reducing parasitic capacitance between them, which is preferable. For example, the width of opening 270 is more preferably equal to or smaller than the width of opening 290.

[0354] The height of the top surface of the conductive layer 260 is preferably the same as or approximately the same as the height of the top surface of the insulating layer 285. The conductive layer 265 is disposed on the insulating layers 285, 284, and 260, and is in contact with the top surface of the conductive layer 260. Alternatively, it can be said that the conductive layer 260 and the conductive layer 265 are connected to each other.

[0355] In other words, transistor 200A has a structure that reduces another parasitic capacitance between the source and drain electrodes and the gate wiring. Therefore, the frequency characteristics of circuits using this transistor can be improved.

[0356] Note that this embodiment shows an example where the opening 270 is circular when viewed from a plane, but the invention is not limited thereto. The shape that can be used for the opening 270 is the same as the shape that can be used for the opening 290 described above.

[0357] The width of the opening 270 sometimes varies in the depth direction. Here, in particular, the maximum value of the width of the opening 270 provided in the insulating layer 284 in cross-section is used as the width of the opening 270.

[0358] The insulating layer 284 is preferably an insulating layer with the function of trapping or fixing hydrogen. By adopting this structure, the diffusion of hydrogen from above the insulating layer 284 to the oxide semiconductor layer 230 can be suppressed, and the hydrogen contained in the oxide semiconductor layer 230 can be trapped or fixed. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced. As the insulating layer 284, an alumina film, a hafnium oxide film, or a hafnium silicate film, etc., can be used.

[0359] Furthermore, a hydrogen barrier insulating layer can be used as the insulating layer 284. This can suppress the diffusion of hydrogen from above the insulating layer 284 into the oxide semiconductor layer 230. Both silicon nitride films and silicon oxynitride films have the characteristics of releasing few impurities (e.g., water and hydrogen) and not allowing oxygen and hydrogen to permeate easily, so they can be used for the insulating layer 284.

[0360] When a silicon nitride film is used as the insulating layer 284, it is preferably deposited using a sputtering method. Sputtering does not require the use of hydrogen-containing molecules as the deposition gas, thus reducing the hydrogen concentration in the insulating layer 284. Furthermore, by depositing the insulating layer 284 using a sputtering method, a high-density silicon nitride film can be formed.

[0361] Alternatively, the insulating layer 284 may also be a laminated structure of an insulating layer with the function of trapping or fixing hydrogen and a hydrogen barrier insulating layer. For example, an alumina film and a silicon nitride film on the alumina film may also be used as the insulating layer 284.

[0362] The insulating layer 285 is used as an interlayer film, and therefore a material with a relatively low permittivity as described above is preferred. For example, the insulating layer 285 preferably comprises a silicon oxide film.

[0363] Alternatively, the same structure as transistor 200 can be used for transistor 200A. For example, insulating layer 280 can have a three-layer structure of insulating layer 280_1, insulating layer 280_2 on insulating layer 280_1, and insulating layer 280_3 on insulating layer 280_2. In addition, insulating layer 283 can be provided on insulating layer 285 and conductive layer 265.

[0364] [Transistor 200B]

[0365] Figure 19A This is a plan view of a semiconductor device including transistor 200B. Figure 19B It is along Figure 19A The cross-sectional view of the dotted line A1-A2 shown. Figure 19C It is along Figure 19A The cross-sectional view shown is the dotted-dash line A3-A4.

[0366] Figure 20A Show Figure 19C A magnified image. Additionally... Figure 20B Show along Figure 19B and Figure 19C Enlarged view of the cross section of the dotted-dash lines A5-A6 shown. Figure 20B It can also be described as a cross-sectional view of the XY plane including the insulating layer 280.

[0367] Figures 19A to 19C The semiconductor device shown includes an insulating layer 210 on a substrate (not shown), a transistor 200B on the insulating layer 210, and an insulating layer 280 on the insulating layer 210.

[0368] Transistor 200B includes a conductive layer 220, a conductive layer 240 on an insulating layer 280, an insulating layer 225, an oxide semiconductor layer 230, an insulating layer 250 on an oxide semiconductor layer 230, and a conductive layer 260 on an insulating layer 250.

[0369] Figures 19A to 19C The transistor 200B shown includes an insulating layer 225, which is consistent with... Figures 1A to 1E The transistor 200 shown is different.

[0370] like Figure 20B As shown, when viewed from a planar perspective, transistor 200B has a structure in which an insulating layer 225 is disposed between an insulating layer 280 and an oxide semiconductor layer 230.

[0371] An insulating layer 225 is disposed along at least a portion of the sidewall of the opening 290. The insulating layer 225 has at least a region located between the oxide semiconductor layer 230 and the insulating layer 280. The insulating layer 225 may also be referred to as a sidewall, a sidewall insulating layer, or a sidewall protective layer, etc.

[0372] As described above, in the channel formation region of an oxide semiconductor, it is preferable to minimize oxygen vacancies and impurities. In particular, in the channel formation region of an oxide semiconductor, it is preferable to minimize hydrogen.

[0373] Therefore, a hydrogen barrier insulating layer is preferably used as the insulating layer 225 disposed on the outside of the oxide semiconductor layer 230. This can suppress hydrogen diffusion into the oxide semiconductor layer 230 and improve the reliability of the transistor 200. For example, a silicon nitride film, a silicon oxynitride film, or an aluminum oxide film is preferably used as the insulating layer 225, and a silicon nitride film is more preferred.

[0374] Furthermore, the silicon nitride film also possesses oxygen-barrier properties. Therefore, by using a silicon nitride film as the insulating layer 225, oxygen can be prevented from being extracted from the oxide semiconductor layer 230 and forming oxygen vacancies in the oxide semiconductor layer 230. Additionally, by using a silicon nitride film as the insulating layer 225, excess oxygen supply to the oxide semiconductor layer 230 can be prevented. Therefore, oxygen excess in the channel formation region of the oxide semiconductor layer 230 can be prevented, thus improving the reliability of the transistor 200B. Furthermore, the insulating layer 225 sometimes contacts the side surface of the conductive layer 240 in the opening 290. In this case, by using a silicon nitride film as the insulating layer 225, oxidation of the side surface of the conductive layer 240 in the opening 290, preventing the formation of an oxide film on that side surface, can be prevented.

[0375] The silicon nitride film included in the insulating layer 225 is preferably formed using the PEALD method. This improves the coverage of the insulating layer 225 over the sidewall of the opening 290, resulting in an insulating layer 225 of uniform thickness.

[0376] Alternatively, the insulating layer 225 can also be made of the aforementioned ferroelectric material.

[0377] exist Figure 19B In the structure shown, the conductive layer 220_2 has a first recess and a second recess located outside the first recess. The depth of the first recess is deeper than that of the second recess. In other words, the bottom surface of the first recess is located below the bottom surface of the second recess (on the side of the insulating layer 210). When forming the opening 290, the second recess is provided in the conductive layer 220_2, and the first recess is provided in the conductive layer 220_2 when processing the insulating layer 225. Therefore, in Figure 19B In the second recess, the side surface is aligned with the side surface of the insulating layer 280 in the opening 290, and the side surface of the first recess is aligned with the side surface of the oxide semiconductor layer 230 of the insulating layer 225. Hereinafter, the first recess and the second recess will sometimes be collectively referred to as recesses.

[0378] exist Figure 19BIn this configuration, the insulating layer 225 contacts the bottom and side surfaces of the recess (specifically, the second recess) of the conductive layer 220, and contacts the side surfaces of the insulating layer 280, the conductive layer 240_1, and the conductive layer 240_2 within the opening 290. The oxide semiconductor layer 230 is located inside the insulating layer 225 within the opening 290, the insulating layer 250 is located inside the oxide semiconductor layer 230 within the opening 290, and the conductive layer 260 is located inside the insulating layer 250 within the opening 290.

[0379] like Figure 20A As shown, the shortest distance Tc from the top surface of the insulating layer 210 to the top surface of the conductive layer 220_2 that contacts the insulating layer 280 is preferably longer than the shortest distance Ta from the top surface of the insulating layer 210 to the bottom surface of the insulating layer 250. This increases the area of ​​the side surface of the conductive layer 220_2 facing the oxide semiconductor layer 230, thereby reducing the contact resistance between the conductive layer 220_2 and the oxide semiconductor layer 230. Therefore, the decrease in the on-state current of the transistor 200B caused by the contact resistance between the conductive layer 220_2 and the oxide semiconductor layer 230 can be suppressed. The shortest distance Ta can be determined based on the bottom surface of the insulating layer 250 within the opening 290.

[0380] In addition, such as Figure 20A As shown, the shortest distance Tc is preferably greater than or equal to the shortest distance Tb from the top surface of the insulating layer 210 to the bottom surface of the conductive layer 260, and more preferably longer than the shortest distance Tb. This allows the gate electric field to be easily applied to the channel formation region of the oxide semiconductor layer 230, thereby improving the electrical characteristics of the transistor 200B. Furthermore, the gate electric field can be easily applied to the region of the oxide semiconductor layer 230 opposite to the conductive layer 220_2, thus increasing the on-state current of the transistor 200B. In addition, the electrical characteristics of the transistor 200B can be improved regardless of whether the conductive layer 220 or the conductive layer 240 is used as the drain electrode. The shortest distance Tb can be determined based on the bottom surface of the conductive layer 260 within the opening 290.

[0381] Here, as Figure 20A As shown, the width (thickness) of the insulating layer 225 is denoted as width Ts. Width Ts is preferably small. By reducing width Ts, the decrease in channel width of transistor 200B and the decrease in on-state current can be suppressed. On the other hand, by increasing width Ts, the function of insulating layer 225 can be improved. Therefore, width Ts is preferably 1 nm or more and 20 nm or less, more preferably 2 nm or more and 15 nm or less, and even more preferably 3 nm or more and 10 nm or less.

[0382] in addition, Figure 20BThe channel width W of transistor 200B is shown. When the opening 290 is circular when viewed from the plane, the width D of the opening 290 is equivalent to the diameter of the opening 290, and the channel width W can be calculated as "(D-2×Ts)×π".

[0383] The channel length of transistor 200B can be considered as the distance between the source and drain regions. That is, the channel length of transistor 200B can be determined by the height of insulating layer 225. Furthermore, the channel length of transistor 200B can be said to be determined by the depth of the recess in conductive layer 220 (specifically, the second recess), the thickness of insulating layer 280 on conductive layer 220, and the thickness of conductive layer 240. When the channel length of transistor 200B is considered as the distance between the source and drain regions, the channel length of transistor 200B can be described as... Figure 20A The length L shown is given.

[0384] Figure 20A The diagram shows the conductive layer 220_2 having a first recess and a second recess, but the invention is not limited thereto. For example, a structure without the second recess may also be used.

[0385] Figure 21A yes Figure 20A The enlarged view of region Q3 is shown. The insulating layer 225 contacts the side surface of the insulating layer 280 and the side surface of the conductive layer 240_2 within the opening 290. Furthermore, the upper end of the insulating layer 225 is lower than the top surface of the conductive layer 240_1.

[0386] Figure 21B Show Figure 21A Examples of variations. In Figure 21B In the middle, the upper end of the insulating layer 225 is lower than the top surface of the insulating layer 280, and the insulating layer 225 does not contact the side of the conductive layer 240_2 within the opening 290.

[0387] Figure 21C Show Figure 21A Examples of variations. In Figure 21C The upper end of the middle insulating layer 225 is higher than the top surface of the conductive layer 240_1, and at this point it is similar to... Figure 21A different.

[0388] [Transistor 200C]

[0389] Figure 22A This is a plan view of a semiconductor device including transistor 200C. Figure 22B It is along Figure 22A The cross-sectional view of the dotted line A1-A2 shown. Figure 22C It is along Figure 22A The cross-sectional view shown is the dotted-dash line A3-A4.

[0390] Figures 22A to 22C The semiconductor device shown includes an insulating layer 210 on a substrate (not shown), a transistor 200C on the insulating layer 210, an insulating layer 280 on the insulating layer 210, and an insulating layer 281 on the insulating layer 280.

[0391] Transistor 200C includes a conductive layer 220, a conductive layer 255 on an insulating layer 280, a conductive layer 240 on an insulating layer 281, an insulating layer 225, an oxide semiconductor layer 230, an insulating layer 250 on an oxide semiconductor layer 230, and a conductive layer 260 on an insulating layer 250.

[0392] Figures 22A to 22C The semiconductor device shown includes a conductive layer 255 and an insulating layer 281, mainly in this respect as... Figures 1A to 1E The semiconductor devices shown are different. Additionally, Figures 22A to 22C The transistor 200C shown includes a conductive layer 255, mainly in this respect with Figures 19A to 19C The transistor shown is different from the 200B.

[0393] Conductive layer 255 is located on insulating layer 280, and insulating layer 281 is located on both conductive layer 255 and insulating layer 280. In addition, conductive layer 240_1 is located on insulating layer 281.

[0394] An opening 290 is provided in the insulating layer 280, the conductive layer 255, the insulating layer 281 and the conductive layer 240 to reach the conductive layer 220.

[0395] In transistor 200C, oxide semiconductor layer 230 is used as semiconductor layer, conductive layer 260 is used as first gate electrode, insulating layer 250 is used as first gate insulating layer, conductive layer 220 is used as one of source electrode and drain electrode, conductive layer 240 is used as the other of source electrode and drain electrode, conductive layer 255 is used as second gate electrode, and insulating layer 225 is used as second gate insulating layer.

[0396] The oxide semiconductor layer 230 has a region that is opposite to the conductive layer 255 separated by an insulating layer 225 and opposite to the conductive layer 260 separated by an insulating layer 250. At least a portion of this region is used as a channel formation region for the transistor 200C.

[0397] Because transistor 200C includes a conductive layer that serves as a back gate electrode, the threshold voltage of transistor 200C can be controlled according to the potential supplied to this conductive layer. Therefore, by controlling the threshold voltage, a transistor with normally-off characteristics can be easily realized.

[0398] Furthermore, in transistor 200C, one of conductive layer 255 and conductive layer 260 may be used as the gate electrode and the back gate electrode, respectively. Sometimes, transistor 200C is particularly preferably configured such that conductive layer 260 is used as the gate electrode and conductive layer 255 is used as the back gate electrode. By using conductive layer 260, whose region opposite to oxide semiconductor layer 230 is larger than that of conductive layer 255, as the gate electrode, the gate electric field is applied to oxide semiconductor layer 230 more effectively, thus sometimes improving the electrical characteristics of the transistor. Note that when conductive layer 260 is used as the gate electrode and conductive layer 255 is used as the back gate electrode, insulating layer 250 is used as the gate insulating layer, and insulating layer 225 is used as the back gate insulating layer.

[0399] The conductive layer 255 can use a conductive material that can be used in the conductive layer 260.

[0400] Insulating layer 281 is used as an interlayer membrane. Insulating layer 281 can use the same insulating material that can be used for insulating layer 280.

[0401] Furthermore, the insulating layer 281 may have a stacked structure of two or more layers. For example, the insulating layer 281 may have a three-layer structure. In this case, it is preferable to use an oxygen-barrier insulating layer as the first and third insulating layers, and to use a material with a low relative permittivity as the second insulating layer sandwiched between the first and second insulating layers. As a result, oxidation of the conductive layer 255 and the conductive layer 240 can be suppressed, and high resistivity can be suppressed.

[0402] Alternatively, transistor 200C may also employ the same structure as at least one of transistors 200, 200A, and 200B. For example, insulating layer 280 may have a three-layer structure consisting of insulating layer 280_1, insulating layer 280_2 on insulating layer 280_1, and insulating layer 280_3 on insulating layer 280_2. Additionally, insulating layer 283 may be provided on insulating layer 250 and conductive layer 260.

[0403] <Structure Example of a Semiconductor Device 2>

[0404] The following is for reference Figure 23A and Figure 23B This section provides examples of semiconductor devices with structures that differ from those described above. Note that descriptions that are repeated above are omitted here; only the differences are explained in detail. Furthermore, even if components differ in location or shape, they may sometimes be given the same symbol and their descriptions omitted when their functions are the same.

[0405] Figure 23A This is a plan view of a semiconductor device including transistor 200. Note that the structure of transistor 200 is the same as in <Structure Example 1 of Semiconductor Device> above, so detailed description is omitted.

[0406] Figure 23A The semiconductor device shown includes a conductive layer 241 connected to the conductive layer 240. Additionally, an insulating layer 286 is disposed on the transistor 200.

[0407] Insulating layer 286 is used as an interlayer film. Insulating layer 286 is preferably made of a material with a low relative permittivity, as described above. By using a material with a low relative permittivity as the interlayer film, parasitic capacitance generated between wirings can be reduced. For example, insulating layer 286 preferably comprises a silicon oxide film.

[0408] Furthermore, the concentration of impurities such as water and hydrogen in the insulating layer 286 is preferably reduced. This suppresses the incorporation of impurities such as water and hydrogen into the channel formation region of the oxide semiconductor layer 230.

[0409] An opening 275 is provided in the insulating layer 286, the insulating layer 250, the oxide semiconductor layer 230, and the conductive layer 240_2, leading to the conductive layer 240_1. The bottom of the opening 275 includes the top surface of the conductive layer 240_1, and the sidewalls of the opening 275 include the side surface of the conductive layer 240_2, the side surface of the oxide semiconductor layer 230, the side surface of the insulating layer 250, and the side surface of the insulating layer 286.

[0410] A conductive layer 241 is disposed within the opening 275. The conductive layer 241 serves as a via for connecting wiring disposed on the transistor 200 to another of the source and drain electrodes of the transistor 200.

[0411] As the conductive layer 241, a single layer or a stack of layers containing the conductive material described above [conductive layer] can be used. For example, the conductive layer 241 preferably uses a conductive material with tungsten, copper or aluminum as the main component.

[0412] The conductive layer 241 can have a stacked structure of two or more layers. For example, as... Figure 23A As shown, the conductive layer 241 may have a three-layer structure consisting of a conductive layer 241_1, a conductive layer 241_2 on the conductive layer 241_1, and a conductive layer 241_3 on the conductive layer 241_2. The conductive layer 241_1 is disposed to cover the bottom and sidewalls of the opening 275, the conductive layer 241_2 is disposed to cover the conductive layer 241_1, and the conductive layer 241_3 is disposed to cover the conductive layer 241_2.

[0413] The conductive layer 241_1 is preferably made of a material with high conductivity. Conductive materials with tungsten, copper, or aluminum as their main components have high conductivity and are therefore preferred. Furthermore, since the conductive layer 241_1 is in contact with the conductive layer 240_1, it is preferable to use the same material as the conductive layer 240_1. This reduces wiring resistance.

[0414] The conductive layer 241_2 is preferably made of a conductive material that suppresses the permeation of impurities such as water and hydrogen. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide are preferred. Alternatively, a single layer or a stack of conductive materials that suppress the permeation of impurities such as water and hydrogen can be used. By providing the conductive layer 241_2, impurities such as water and hydrogen can be prevented from mixing into the oxide semiconductor layer 230 through the conductive layer 241_3.

[0415] The conductive layer 241_3 is preferably made of a material with high conductivity. The conductive layer 241_3 can use the same conductive material that can be used in the conductive layer 241_1.

[0416] In addition, such as Figure 23A As shown, the top surface of the conductive layer 241 can be formed in a manner that is aligned or substantially aligned with the top surface of the insulating layer 286.

[0417] During the process of forming the opening 275, the metal oxide used in the oxide semiconductor layer 230 sometimes reacts with the etching gas to become a byproduct, which remains inside the opening 275. Therefore, it is preferable to perform a washing process after forming the opening 275.

[0418] As a washing process, there are wet washing using washing liquids, plasma treatment using plasma, washing using heat treatment, and the above washing processes can also be combined appropriately.

[0419] As a wet cleaning method, aqueous solutions prepared by diluting ammonia, oxalic acid, phosphoric acid, or hydrofluoric acid with carbonated water or pure water, pure water or carbonated water, or hot water obtained by heating pure water can be used. Note that the hot water temperature is 25°C or higher and 95°C or lower, preferably 25°C or higher and 85°C or lower, and more preferably 30°C or higher and 65°C or lower. Alternatively, ultrasonic cleaning can be performed using the aforementioned aqueous solutions, pure water, hot water, or carbonated water. Furthermore, a frequency of 100 kHz or higher and 1 MHz or lower is preferably used for ultrasonic cleaning. Cleaning using this frequency is sometimes referred to as ultrasonic cleaning or megasonic cleaning. In addition, the above-mentioned cleaning methods can be appropriately combined.

[0420] For example, it is preferable to use the above-mentioned aqueous solution, pure water or carbonated water and perform QDR (QuickDump Rinse) washing treatment using a batch washing device.

[0421] For example, QDR washing includes: a first step of simultaneously supplying pure water or carbonated water to the washing tank in a spray manner while draining the pure water or carbonated water from the washing tank; a second step of rapidly supplying pure water or carbonated water into the washing tank; and a third step of supplying pure water or carbonated water in a manner that allows it to overflow from the washing tank. The first, second, and third steps constitute one cycle, and the number of cycles is set appropriately as needed. Furthermore, it is preferable to perform the third step before or after QDR washing.

[0422] By performing a washing process, byproducts remaining in the opening 275 can be removed. Removing byproducts from the opening 275 suppresses the increase in contact resistance between conductive layer 240 and conductive layer 241. Furthermore, when multiple connections between conductive layers 240 and 241 are provided in the semiconductor device, the unevenness of contact resistance between the conductive layers 240 and 241 can be reduced.

[0423] Furthermore, by employing a structure in which the oxide semiconductor layer 230 is not exposed in the opening 275, the formation of the aforementioned byproducts can be suppressed. Thus, for example, as... Figure 23B As shown, it is preferable to provide an opening 274 in the oxide semiconductor layer 230 whose width is greater than that of the opening 275. This prevents the side surfaces of the oxide semiconductor layer 230 from being exposed in the opening 275.

[0424] For example, by removing the region of the oxide semiconductor layer 230 that overlaps with at least a portion of the conductive layer 240 before forming the insulating layer 250, the opening 274 can be formed. Furthermore, by forming the insulating layer 250 after forming the opening 274, the sidewalls of the oxide semiconductor layer 230 can be covered by the insulating layer 250 in the opening 274. Additionally, by forming an opening 275 whose width is smaller than the width of the opening 274 after forming the insulating layer 286, the sidewalls of the oxide semiconductor layer 230 can be prevented from being exposed in the opening 275. In this case, the sidewalls of the opening 274 include the sidewalls of the conductive layer 240_2, the sidewalls of the insulating layer 250, and the sidewalls of the insulating layer 286.

[0425] By adopting the above structure, the formation of byproducts within the opening 275 can be suppressed. Therefore, the increase in contact resistance between conductive layer 240 and conductive layer 241 can be suppressed. Furthermore, when multiple connection portions between conductive layers 240 and conductive layer 241 are provided in the semiconductor device, the non-uniformity of contact resistance between conductive layers 240 and conductive layer 241 can be reduced.

[0426] Notice, Figure 23A and Figure 23BAn example of a structure in which the opening 275 is provided in the conductive layer 240_2 is shown, but the present invention is not limited thereto. The opening 275 may not be provided in the conductive layer 240_2. In this case, the conductive layer 241 contacts the top surface of the conductive layer 240_2. By adopting the above structure, the opening 275 can be easily manufactured with high precision.

[0427] In one aspect of the semiconductor device of the present invention, by disposing an oxide layer with a resistivity higher than that of the oxide semiconductor layer between the source electrode or drain electrode and the oxide semiconductor layer, the electrical characteristics of the transistor and the reliability of the transistor can be improved.

[0428] In one aspect of the semiconductor device of the present invention, a hydrogen-blocking insulating layer is used to surround an oxide semiconductor layer. One or both of an insulating layer having the function of trapping or fixing hydrogen and an insulating layer having a region containing excess oxygen are disposed near the oxide semiconductor layer, thereby reducing one or both of oxygen vacancies and impurities in the oxide semiconductor layer. Therefore, the transistor's electrical characteristics can be improved, thus increasing the transistor's reliability.

[0429] One aspect of the semiconductor device of the present invention has a structure that reduces parasitic capacitance generated between the source electrode and the gate electrode, and between the source electrode and the gate wiring, and another parasitic capacitance generated between the source electrode and the gate electrode. Therefore, the frequency characteristics of a circuit using this semiconductor device can be improved.

[0430] <Examples of Semiconductor Device Manufacturing Methods>

[0431] Reference Figures 24A to 30B This describes a method for manufacturing semiconductor devices. Here, as an example, it is illustrated... Figure 1C and Figure 1D The manufacturing method of the structure shown. Note that regarding the materials and forming methods of each component, parts that are the same as those already described are sometimes omitted. A in each figure corresponds to... Figure 1C The diagram shows an enlarged view of the structure, where B in each figure corresponds to... Figure 1D An enlarged view of the structure shown.

[0432] Thin films (insulating films, semiconductor films, and conductive films, etc.) that constitute semiconductor devices can be formed using sputtering, chemical vapor deposition (CVD), ALD, pulsed laser deposition (PLD), molecular beam epitaxy (MBE), vacuum evaporation, and other methods.

[0433] Note that examples of sputtering methods include RF sputtering, which uses a high-frequency power supply, DC sputtering, which uses a DC power supply, and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. Additionally, there is RF-DC sputtering, which combines RF and DC sputtering. RF sputtering is preferred for deposition using insulating targets. DC sputtering is primarily used when depositing conductive targets. Furthermore, in DC sputtering, in addition to forming conductive films, insulating films can also be formed by reactive sputtering using pulsed DC sputtering. Specifically, pulsed DC sputtering is mainly used when depositing compounds such as oxides, nitrides, and carbides using reactive sputtering. RF-DC sputtering allows for control of ion energy and the potential on the target side during deposition. Therefore, compared to RF sputtering, deposition-related damage can be reduced. Furthermore, films of high quality can be obtained.

[0434] Sputtering is a deposition method that utilizes the deposition of particles released from a target. It can be said to be a deposition method with anisotropic deposition rates.

[0435] As a sputtering method, ionization sputtering can be used, for example. Ionization sputtering is a method in which sputtering particles generated from a target are ionized using RF or the like, and deposited in a highly anisotropic manner by self-biasing or the like.

[0436] Furthermore, by using methods such as long-range sputtering and collimated sputtering as sputtering techniques, it is possible to achieve deposition with greater anisotropy. Long-range sputtering is a method of deposition with greater anisotropy by increasing the distance between the sputtering target and the substrate.

[0437] Note that CVD methods can be categorized into plasma-enhanced CVD (PECVD), thermal CVD (TCVD), and photo CVD. Furthermore, they can be classified based on the source gas used, such as metal CVD (MCVD) and metal-organic CVD (MOCVD).

[0438] By utilizing plasma CVD, high-quality films can be obtained at relatively low temperatures. Furthermore, because it does not use plasma, thermal CVD is a deposition method that reduces plasma damage to the workpiece. For example, wiring, electrodes, and components (transistors, capacitors, etc.) included in semiconductor devices sometimes accumulate charge due to receiving charge from plasma. This stored charge can sometimes damage these wiring, electrodes, and components. On the other hand, since thermal CVD does not produce this plasma damage, the yield of semiconductor devices can be improved. Moreover, since plasma damage during deposition is eliminated in thermal CVD, films with fewer defects can be obtained.

[0439] As ALD methods, there are thermal ALD (thermal ALD) methods that use only thermal energy to cause the precursors and reactants to react, and PEALD (Plasma Enhanced ALD) methods that use reactants excited by plasma.

[0440] The Alternating Layer Deposition (ALD) method can deposit atoms in each layer, resulting in the ability to deposit extremely thin films, deposit structures with high aspect ratios, deposit with fewer defects such as pinholes, achieve excellent coverage, and deposit at low temperatures. In the Plasma Enhanced Alternating Layer Deposition (PEALD), deposition can be performed at even lower temperatures by utilizing plasma, making it sometimes preferred. Furthermore, the precursors used in the ALD method sometimes contain impurities such as carbon. Therefore, films deposited using the ALD method sometimes contain more impurities such as carbon compared to films deposited using other deposition methods. Moreover, the quantification of impurities can be performed using X-ray photoelectron spectroscopy (XPS) or secondary ion mass spectrometry (SIMS). Note that while the metal oxide deposition method of this invention utilizes the ALD method, due to the use of high substrate temperatures during deposition and one or both of the impurity removal process, the amount of carbon and chlorine contained in the film is sometimes less compared to cases where the ALD method is used without these conditions.

[0441] Unlike deposition methods that deposit particles released from a target or similar material, ALD and CVD methods are methods for forming films by deposition based on the reaction of the surface of the workpiece. Therefore, ALD and CVD methods are deposition methods that are less affected by the shape of the workpiece and have good step coverage. In particular, ALD has good step coverage and thickness uniformity, making it suitable for forming surfaces covering openings with high aspect ratios. Furthermore, isotropic deposition can be achieved using ALD. ALD can be described as a deposition method with low anisotropy in deposition rate. However, the deposition rate of ALD is relatively slow, so it is sometimes preferable to use it in combination with other deposition methods such as sputtering or CVD, which have faster deposition rates. For example, when creating a stacked structure of a first metal oxide and a second metal oxide, a method can be used to deposit the first metal oxide by sputtering and then deposit the second metal oxide using ALD on the first metal oxide. For example, if the first metal oxide has crystalline portions, the second metal oxide may sometimes grow crystals using these crystalline portions as nuclei.

[0442] CVD and ALD methods allow for control of the film composition by adjusting the source gas flow rate ratio. For example, using CVD and ALD, films with arbitrary compositions can be deposited based on the source gas flow rate ratio. Furthermore, for instance, using CVD and ALD, films with continuously varying compositions can be deposited by changing the source gas flow rate ratio simultaneously with deposition. When deposition is performed while changing the source gas flow rate ratio, the time required for transmission and pressure adjustment is eliminated, thus reducing deposition time compared to using multiple deposition chambers. Therefore, this can sometimes improve the productivity of semiconductor devices.

[0443] Furthermore, when using the ALD method, films of arbitrary composition can be deposited by adjusting the amount of source gas introduced, the number of introductions (also known as the number of pulses), and the time required for one pulse (also known as the pulse time). When using the ALD method, films of arbitrary composition can be deposited by simultaneously introducing multiple different precursors. Alternatively, when introducing multiple different precursors, films of arbitrary composition can be deposited by controlling the number of cycles for each precursor.

[0444] Thin films (insulating films, semiconductor films, and conductive films, etc.) constituting semiconductor devices can be formed using wet deposition methods such as spin coating, dip coating, spray coating, inkjet coating, dispenser coating, screen printing, offset printing, doctor knife coating, slot coating, roller coating, curtain coating, or doctor blade coating.

[0445] Furthermore, when processing thin films constituting semiconductor devices, techniques such as lithography can be used. Alternatively, nanoimprinting, sandblasting, and lift-off methods can be employed to process the thin films. Additionally, island-shaped thin films can be directly formed using deposition methods that utilize metal masks or similar masking techniques.

[0446] Lithography typically employs two methods. One involves forming a resist mask on the thin film to be processed, then processing the film through etching or similar methods, and finally removing the resist mask. The other method involves depositing a photosensitive thin film, followed by exposure and development to shape the film into the desired form.

[0447] In lithography, the light used for exposure can be, for example, i-rays (365 nm wavelength), g-rays (436 nm wavelength), h-rays (405 nm wavelength), or a mixture of these rays. Additionally, ultraviolet light, KrF lasers, or ArF lasers can also be used. Furthermore, immersion lithography can also be used. Extreme ultraviolet (EUV) light or X-rays can also be used as the light for exposure. Alternatively, an electron beam can be used instead of the light for exposure. Extreme ultraviolet light, X-rays, or electron beams allow for extremely fine processing and are therefore preferred. Note that when exposure is performed by scanning with a beam such as an electron beam, a photomask is not required.

[0448] In thin film etching, various methods can be employed, including dry etching, wet etching, ashing, plasma treatment, and reverse sputtering. Additionally, sandblasting can also be used in thin film etching.

[0449] For example, a halogen-containing gas can be used as the etching gas for dry etching.

[0450] As a halogen-containing gas, an etching gas containing one or more of fluorine, chlorine, and bromine can be used, for example. Fluorocarbon gases, hydrofluorocarbon gases, SF6 gases, Cl2 gases, BCl3 gases, SiCl4 gases, or BBr3 gases can be used alone or in mixtures of two or more gases. Fluorocarbon gases can be represented as C... x F y Gases satisfying y ≤ 2x + 2. Examples of fluorocarbon gases that satisfy y = 2x + 2 include CF4, C2F6, C3F8, and C4F6. 10 C5F 12 Saturated fluorocarbons. Furthermore, examples of fluorocarbon gases satisfying y < 2x + 2 include C2F4, C2F2, C3F7, C3F4, C4F8, C4F6, C4F4, C4F2, and C5F4. 10Unsaturated fluorocarbons such as C5F8, C5F6, and C5F4. Examples of hydrofluorocarbon gases include CHF3 and CH2F2.

[0451] In addition, when using a halogen-containing gas as the etching gas, oxygen (O2), carbon dioxide, nitrogen (N2), helium, argon, hydrogen, or hydrocarbon gases can be added as appropriate.

[0452] Alternatively, a gas containing hydrocarbon or hydrogen gases but not halogen gases can be used as the etching gas.

[0453] As hydrocarbon gases, methane (CH4), ethane (C2H6), propane (C3H8), and butane (C4H4) can be used, for example. 10 One or more of ethylene (C2H4), propylene (C3H6), acetylene (C2H2), and propyne (C3H4).

[0454] In addition, when using hydrocarbon gas as etching gas, nitrogen, helium, argon or hydrogen can be added appropriately.

[0455] Alternatively, a capacitively coupled plasma (CCP) etching apparatus, including parallel planar electrodes, can be used as a dry etching apparatus. This apparatus can also employ a structure that applies a high-frequency voltage to one of the parallel planar electrodes. Alternatively, it can employ a structure that applies multiple different high-frequency voltages to one of the parallel planar electrodes. Alternatively, it can employ a structure that applies high-frequency voltages of the same frequency to each of the parallel planar electrodes. Alternatively, it can employ a structure that applies high-frequency voltages of different frequencies to each of the parallel planar electrodes. Alternatively, a dry etching apparatus with a high-density plasma source can be used. For example, an inductively coupled plasma (ICP) etching apparatus can be used as a dry etching apparatus with a high-density plasma source. The etching apparatus can be appropriately configured according to the object being etched.

[0456] First, a conductive layer 220 is formed on the insulating layer 210, an insulating layer 280 is formed on the conductive layer 220, and a conductive layer 240_1f is formed on the insulating layer 280.

[0457] Note that it is preferable to perform a planarization process using chemical mechanical polishing (CMP) after depositing the insulating layer 280 to planarize the top surface of the insulating layer 280. By performing the planarization process on the insulating layer 280, the surface on which the conductive layer 240 is formed for wiring can be flattened, thereby suppressing the breakage of the conductive layer 240. Alternatively, the planarization process can be omitted, which can reduce manufacturing costs.

[0458] Next, a mask 278 is formed on the conductive layer 240_1f. Figure 24A and Figure 24B As a mask 278, for example, a structure can be adopted in which SOC (Spin On Carbon) film, SOG (Spin On Glass) film, and resist mask are stacked in sequence.

[0459] Next, using mask 278, openings 290b and 290a are formed at the locations where the conductive layer 240_1f and the insulating layer 280 overlap with the conductive layer 220. Figure 25A and Figure 25B At this time, a recess 290c is formed in the conductive layer 220 at the position where it overlaps with the opening 290.

[0460] Because of the high aspect ratio of the opening 290, it is preferable to process a portion of the conductive layer 240_1f and a portion of the insulating layer 280 using anisotropic etching. In particular, processing using dry etching is suitable for micro-machining and is therefore preferred. Furthermore, this processing can also be performed under different conditions depending on the layers.

[0461] Figure 25A and Figure 25B An example is shown where the difference in inclination between the sidewalls of conductive layer 240_1f and insulating layer 280 is small (e.g., the difference between the angle formed by the top surface of conductive layer 220 and conductive layer 240_1f and the angle formed by the top surface of conductive layer 220 and insulating layer 280 is small).

[0462] In addition, such as Figure 26A and Figure 26B As shown, the conductive layer 240_1f can also be processed in such a way that the angle of the sidewall of the conductive layer 240_1f is gentler than that of the sidewall of the insulating layer 280 (for example, in such a way that the angle formed by the top surface of the conductive layer 220 and the conductive layer 240_1f is smaller than the angle formed by the top surface of the conductive layer 220 and the insulating layer 280).

[0463] Next, heat treatment may be performed. The heat treatment may be performed at a temperature of 100°C or higher and 800°C or lower, preferably 250°C or higher and 650°C or lower, and more preferably 350°C or higher and 550°C or lower. For example, the treatment may be performed at a temperature of 350°C or higher and 550°C or lower for 1 minute or more and 1 hour or more and 10 minutes or more and 30 minutes or lower.

[0464] The heat treatment is performed in an atmosphere of nitrogen or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen and oxygen gas, the oxygen gas ratio is preferably set to about 20%. The heat treatment can also be performed under reduced pressure. Alternatively, the heat treatment can be performed in a nitrogen or inert gas atmosphere, and then, in order to replenish the detached oxygen, the heat treatment is performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. By performing the above-described heat treatment, impurities such as water contained in the insulating layer 280 and the like can be reduced before depositing the oxide semiconductor layer 230.

[0465] The gas used in the heat treatment is preferably of high purity. For example, the water content in the gas used in the above-mentioned heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By using a high-purity gas for heat treatment, the absorption of moisture and the like by the insulating layer 280 can be prevented as much as possible.

[0466] Here, an example is shown of forming openings in conductive layer 240_1f and insulating layer 280 using the same mask, but different masks can also be used to form openings in conductive layer 240_1f and insulating layer 280.

[0467] Next, a portion of the conductive layer 240_1f is removed in a manner that makes the upper end of the conductive layer 240_1f circular. Figure 27A and Figure 27B ).

[0468] This removal process can utilize dry etching, wet etching, ashing, plasma treatment, back sputtering, etc. Here, by performing back sputtering before forming the conductive layer 240_2f, a portion of the conductive layer 240_1f can be removed. For example, by performing back sputtering, a portion of the upper end of the opening in the conductive layer 240_1f can be removed.

[0469] Figure 27C Show Figure 27A A magnified view of region Q4 shown. Figure 27CIn the cross-sectional view shown, the angle An1_r formed by the tangent of the rounded corner of the upper end of the conductive layer 240_1f and the top surface of the conductive layer 220_2 can be reduced. Figure 27C In this case, the angle An1_r is smaller than the angle An0 formed by the side surface of the insulating layer 280 and the top surface of the conductive layer 220_2 within the opening 290. Additionally, in Figure 27C In this case, the angle An1_r is smaller than the angle An1 formed by the lower end of the side surface of the conductive layer 240_1f and its surrounding area and the top surface of the conductive layer 220_2.

[0470] Next, a conductive layer 240_2f is formed on the conductive layer 240_1f. Figure 28A and Figure 28B ).

[0471] The conductive layer 240_2f is preferably formed using a deposition method with anisotropic deposition rate. Sputtering can be used as a method for forming the conductive layer 240_2f.

[0472] Furthermore, in sputtering, increasing the distance between the sputtering target and the substrate allows for deposition with greater anisotropy. On the other hand, increasing the distance between the sputtering target and the substrate can lead to the formation of a conductive layer deeper into the high aspect ratio opening, potentially forming the conductive layer 240_2f on the top surface of the conductive layer 220_2 exposed in the recess 290c. When it is desirable to reduce the coverage of the top surface of the conductive layer 220_2, the coverage can be reduced by appropriately setting the distance between the sputtering target and the substrate. For example, if the width of the upper end of the opening 290a is 40 nm or more and 100 nm or less, and the thickness of the insulating layer 280 is 40 nm or more and 300 nm or less, the distance between the target and the substrate in the sputtering process can be set to 50 mm or more and 1000 mm or less, for example, 200 mm or more and 400 mm or less, thereby enabling deposition with high anisotropy and high productivity.

[0473] Here, a conductive layer 240_2f is formed using sputtering. The reverse sputtering process prior to the deposition of the conductive layer 240_2f and the deposition of the conductive layer 240_2f are preferably performed using the same apparatus. By using the same apparatus, for example, the conductive layer 240_2f can be deposited while maintaining a reduced pressure atmosphere after the reverse sputtering process. This suppresses surface oxidation of the conductive layer 240_1f during the period between the reverse sputtering process and the deposition of the conductive layer 240_2f. By suppressing oxidation, the interface resistance between the conductive layers 240_1f and 240_2f can sometimes be further reduced, which is therefore preferred. Furthermore, by using the same apparatus, the manufacturing process is simplified by eliminating the need for inter-applied equipment movement.

[0474] Because the deposition rate of conductive layer 240_2f is anisotropic, the deposition rate is slow on steep sides, more specifically, for example, sides where the angle with the top surface of conductive layer 220 is perpendicular or near. On the other hand, the deposition rate is relatively high on gentle sides, more specifically, for example, sides where the angle with the top surface of conductive layer 220 is small. By making the upper end of conductive layer 240_1f rounded, a thick conductive layer 240_2f can be selectively formed at the rounded upper end.

[0475] Next, an oxide semiconductor layer 230f is formed to cover the top surface of the opening 290 and the conductive layer 240_2. Figure 29A and Figure 29B The oxide semiconductor layer 230f is the layer that will become the oxide semiconductor layer 230. The oxide semiconductor layer 230f is formed in a manner that contacts the top surface of the conductive layer 220, the side surface of the insulating layer 280, the side surface of the conductive layer 240_2, and the top surface of the conductive layer 240_2. In addition, when the side surface of the conductive layer 240_1 is exposed in the opening 290, the oxide semiconductor layer 230 is formed in a manner that contacts the exposed side surface.

[0476] The oxide semiconductor layer 230f can be formed by stacking and depositing multiple layers. Here, the oxide semiconductor layer 230f is formed by sequentially depositing the first to the third layers.

[0477] When forming the first layer, it is preferable to use a deposition method that minimizes damage to the insulating layer 280 and avoids alloying with the insulating layer 280. For example, it is preferable to use ALD, PECVD, thermal CVD, MOCVD, MBE, etc. to form the first layer.

[0478] Furthermore, the oxide semiconductor layer 230f preferably has high coverage over the sidewalls and bottom of the opening 290, which has a high aspect ratio and a small opening diameter. Therefore, at least a portion of the multiple layers deposited as the oxide semiconductor layer 230f is preferably formed using a method with high coverage. In particular, by using the ALD method, a film with small thickness non-uniformity can be formed within the opening 290 along the top surface of the conductive layer 220, the side surface of the insulating layer 280, and the side surface of the conductive layer 240.

[0479] Furthermore, the oxide semiconductor layer 230f preferably has high crystallinity. By increasing the crystallinity of the oxide semiconductor layer 230f, impurity diffusion in the oxide semiconductor layer 230f can be suppressed, thereby reducing the likelihood of changes in the electrical characteristics of the transistor and improving reliability. For example, metal oxides deposited by sputtering tend to have high crystallinity. Therefore, by forming at least a portion of the multiple layers deposited as the oxide semiconductor layer 230f using sputtering, the oxide semiconductor layer 230f can be made crystallized.

[0480] On the other hand, sputtering methods sometimes have lower coverage than methods such as ALD. Therefore, considering the coverage of the sidewalls and bottom of the opening 290, when sputtering is used to form one of a plurality of layers deposited as oxide semiconductor layer 230f, it is preferable to use layers deposited using methods with excellent coverage as other layers.

[0481] For the method of forming the oxide semiconductor layer 230f, please refer to Embodiment 2.

[0482] Here, the first layer is formed using the ALD method. Next, the second layer is formed using sputtering. Then, the third layer is formed using the ALD method.

[0483] Heat treatment can also be performed after the oxide semiconductor layer 230f is formed. By performing heat treatment, for example, the crystallinity of the oxide semiconductor layer 230f can be improved. As a heat treatment, for example, the heat treatment conditions and method shown in Embodiment 2 can be used. Alternatively, heat treatment may not be performed after the formation of the oxide semiconductor layer 230f. For example, heat treatment can be performed after the formation of the insulating layer 250 (described later). Or, for example, the crystallinity of the oxide semiconductor layer 230f can also be improved by utilizing the heat during the formation of the conductive layer 260 (described later). Furthermore, by performing heat treatment, impurities in the oxide semiconductor layer 230f can be reduced.

[0484] Alternatively, microwave treatment can be performed after the oxide semiconductor layer 230f is formed. Microwave treatment can, for example, reduce impurities in the oxide semiconductor layer 230f. Additionally, the crystallinity of the oxide semiconductor layer 230f may sometimes be improved.

[0485] In a method for manufacturing a semiconductor device according to one aspect of the present invention, since the conductive layer 240_2f covers the side surface of the conductive layer 240_1f, the contact area between the conductive layer 240_1f and the oxide semiconductor layer 230f can be reduced. Therefore, for example, during and after the formation of the oxide semiconductor layer 230f, in various processes (heat treatment, microwave treatment, etc.), oxygen extraction from the conductive layer 240_1f from the oxide semiconductor layer 230f can be suppressed. Thus, the formation of oxygen vacancies in the oxide semiconductor layer 230f can be suppressed. Furthermore, the consumption of oxygen supplied to the oxide semiconductor layer 230f by the conductive layer 240_1f through microwave treatment can be suppressed.

[0486] Next, conductive layer 240_1f, conductive layer 240_2f, and oxide semiconductor layer 230f are processed into islands to form conductive layer 240_1, conductive layer 240_2, and oxide semiconductor layer 230. Figure 30A and Figure 30BHere, the same mask can be used to process conductive layer 240_1, conductive layer 240_2 and oxide semiconductor layer 230 simultaneously.

[0487] Alternatively, the processes of fabricating conductive layer 240_1f, conductive layer 240_2f, and oxide semiconductor layer 230 into island shapes can be performed independently. For example, the processes of fabricating conductive layer 240_1f and conductive layer 240_2f into island shapes and fabricating oxide semiconductor layer 230f into island shapes can be performed independently.

[0488] Next, an insulating layer 250 is formed on the oxide semiconductor layer 230 and the insulating layer 280. The insulating layer 250 is formed in contact with the oxide semiconductor layer 230.

[0489] By utilizing the heat generated during the formation of the insulating layer 250, the crystallinity of the oxide semiconductor layer 230 can sometimes be improved. By setting the deposition temperature of the insulating layer, for example, to 250°C or higher, preferably to 350°C or higher, the crystallinity of the oxide semiconductor layer 230 is sometimes improved due to the heat generated during the deposition of the insulating layer.

[0490] Alternatively, heat treatment can be performed after the insulating layer 250 is formed. Heat treatment can, for example, improve the crystallinity of the oxide semiconductor layer 230. Furthermore, heat treatment can reduce the impurity concentration in the insulating layer 250. Note that heat treatment may also be omitted after the insulating layer 250 is formed.

[0491] The heat treatment can be performed at a temperature of 100°C or higher and 800°C or lower, preferably 250°C or higher and 650°C or lower, and more preferably 350°C or higher and 550°C or lower. For example, the treatment can be performed at a temperature of 350°C or higher and 550°C or lower for 1 minute or more and 1 hour or more and 10 minutes or more and 30 minutes or lower.

[0492] The gas used for heat treatment can be a nitrogen atmosphere, an inert gas atmosphere, or an oxidizing gas. For example, heat treatment can be performed in a nitrogen atmosphere, an inert gas atmosphere, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. By performing heat treatment containing oxygen gas, impurities such as carbon, water, and hydrogen in the oxide semiconductor layer 230 can be reduced.

[0493] In addition, heating treatment can also be performed under reduced pressure.

[0494] As for the conditions for heat treatment, please refer to the conditions mentioned above.

[0495] Furthermore, it is preferable to perform microwave treatment after forming the insulating layer 250. The insulating layer 250 serves as the gate insulating layer, so a low impurity concentration is preferred. This suppresses the incorporation of impurities into the channel formation region of the oxide semiconductor layer. By performing microwave treatment after forming the insulating layer 250, the impurity concentration in the insulating layer 250 can be reduced. Additionally, microwave treatment sometimes increases the crystallinity of the oxide semiconductor layer 230.

[0496] Additionally, microwave processing through insulating layer 250 can be used to remove V from the oxide semiconductor layer. O H is split into oxygen vacancies and hydrogen to remove hydrogen as an impurity from the oxide semiconductor layer. In this way, V in the oxide semiconductor layer can be reduced. O H. Furthermore, carbon bonded to oxygen or hydrogen can sometimes be removed at this time. Thus, impurities such as carbon or hydrogen can be reduced by microwave treatment. In addition, oxygen vacancies in the oxide semiconductor layer can be further reduced by supplying oxygen free radicals generated in the oxygen plasma through oxygen vacancies formed in the oxide semiconductor layer via the insulating layer 250.

[0497] The conditions for microwave processing can be found in the descriptions of microwave processing in other embodiments.

[0498] Furthermore, when the insulating layer 280 contains oxygen, it is preferable to supply oxygen from the insulating layer 280 to the channel formation region of the oxide semiconductor layer 230 via heat treatment. This reduces oxygen vacancies and Vo. O H.

[0499] Next, a conductive layer 260 is formed on the insulating layer 250.

[0500] Through the above steps, it is possible to manufacture Figure 1C and Figure 1D The semiconductor device shown.

[0501] This embodiment can be appropriately combined with other embodiments or examples. Furthermore, where multiple structural examples are shown in one embodiment in this specification, these structural examples can be appropriately combined.

[0502] (Implementation Method 2)

[0503] In this embodiment, an oxide semiconductor layer that can be used as a semiconductor layer for transistors is described. Additionally, in one embodiment of the invention, the oxide semiconductor layer has a stacked structure. As described later, sometimes determining the boundaries between the stacked films is difficult.

[0504] [Oxide Semiconductor Layer]

[0505] In one aspect of the present invention, the oxide semiconductor layer preferably comprises a crystalline metal oxide. Examples of structures with crystalline metal oxides include a CAAC (c-axis aligned crystal) structure, a polycrystalline structure, and a nanocrystalline structure. By using a crystalline metal oxide in the oxide semiconductor layer, the defect state density in the oxide semiconductor layer can be reduced. Therefore, the reliability of transistors using the oxide semiconductor layer of one aspect of the present invention can be improved, and the reliability of semiconductor devices in which transistors are mounted can be improved.

[0506] In one aspect of the present invention, the oxide semiconductor layer particularly preferably comprises a metal oxide having a CAAC structure. A CAAC structure is a crystal structure in which multiple microcrystals (typically multiple microcrystals with a hexagonal crystal structure) have a c-axis orientation and are connected without orientation on the ab plane. Furthermore, when a cross-section of the oxide semiconductor layer having a CAAC structure is observed using a high-resolution transmission electron microscope (TEM) image (also known as a multi-beam interferometry image), it can be confirmed that the metal atoms are arranged in layers within the crystalline region. Therefore, it can also be said that the oxide semiconductor layer having a CAAC structure has layered crystalline regions.

[0507] The CAAC structure is formed, for example, with the c-axis perpendicular or substantially perpendicular to the surface or plane of the oxide semiconductor layer. In the CAAC structure, metal atoms are arranged in layers in a direction parallel or substantially parallel to the surface to be formed. In the region having the CAAC structure, the angle of the c-axis relative to the surface to be formed is preferably within 90° ± 20° (70° or more and 110° or less), more preferably within 90° ± 15° (75° or more and 105° or less), further preferably within 90° ± 10° (80° or more and 100° or less), and even more preferably within 90° ± 5° (85° or more and 95° or less).

[0508] The crystallinity of oxide semiconductor layers can be analyzed, for example, by X-ray diffraction (XRD), TEM, or electron diffraction (ED). Furthermore, multiple methods can be combined for analysis.

[0509] When the oxide semiconductor layer has a CAAC structure, clusters of bright spots reflecting the layered arrangement of metal atoms (specifically, bright spots arranged in layers) are observed when the cross-section of the oxide semiconductor layer is viewed using TEM images. Specifically, the bright spots are observed to be arranged in layers in a direction parallel or approximately parallel to the surface to which they are formed.

[0510] When an oxide semiconductor layer with a CAAC structure is subjected to electron diffraction, spots (bright spots) indicating c-axis orientation are observed in the electron diffraction pattern.

[0511] Furthermore, the FFT map obtained by processing the TEM image with Fast Fourier Transform (FFT) reflects the same reciprocal space information as the electron diffraction map.

[0512] By obtaining a cross-sectional TEM image of an oxide semiconductor layer with a CAAC structure and performing FFT processing on each region in the cross-sectional TEM image to generate an FFT image, the crystal axis orientation of each region can be calculated from the generated FFT image. Specifically, in the specks observed in the generated FFT image, the direction of the line segment connecting two specks with high brightness and approximately equal distances from the center is taken as the crystal axis orientation. Regions whose angle relative to the formed surface, calculated from the FFT image, is preferably 70° or more and 110° or less (within 90° ± 20°), more preferably 75° or more and 105° or less (within 90° ± 15°), more preferably 80° or more and 100° or less (within 90° ± 10°), and even more preferably 85° or more and 95° or less (within 90° ± 5°) can be considered as CAAC structures.

[0513] When an oxide semiconductor layer with a CAAC structure is observed using TEM images from a direction perpendicular to the formed surface, triangular or hexagonal atomic arrangements with crystallinity are observed on the ab surface.

[0514] Note that there are no particular restrictions on the crystallinity of the metal oxide contained in the oxide semiconductor layer. For example, the oxide semiconductor layer may sometimes contain one or more of the following: amorphous semiconductor (semiconductor with an amorphous structure), single-crystal semiconductor (semiconductor with a single-crystal structure), and semiconductor with crystallinity other than single crystal (microcrystalline semiconductor, polycrystalline semiconductor, or semiconductor with partially crystalline regions). When the oxide semiconductor layer is crystallinity, it can sometimes suppress the degradation of transistor characteristics.

[0515] According to one aspect of the invention, the metal oxide preferably contains at least indium (In) or zinc (Zn), and particularly preferably contains indium as a main component. Furthermore, the metal oxide preferably contains two or three selected from indium, element M, and zinc, and particularly preferably contains indium and zinc as main components. Here, the metal oxide may contain indium and zinc as main components, and may also contain element M. Note that element M is a metallic or half-metallic element with a high bond energy with oxygen, for example, a metallic or half-metallic element with a higher bond energy with oxygen than indium. Specifically, examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably any one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably one or more selected from gallium and tin. When the element M contained in the metal oxide is gallium, the metal oxide according to one embodiment of the invention preferably contains one or more elements selected from indium, gallium, and zinc. In this specification and the like, metallic elements and half-metallic elements are sometimes collectively referred to as "metallic elements," and the term "metallic element" as used in this specification and the like sometimes includes half-metallic elements.

[0516] As a metal oxide according to one aspect of the present invention, for example, In-Zn oxide, ITO, indium titanium oxide (In-Ti oxide), In-Ga oxide, indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also referred to as IGTO), indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), In-Ga-Zn oxide, ITSO, indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO), etc., can be used. Alternatively, Ga-Zn oxide, Al-Zn oxide, gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc., can be used. Furthermore, as a metal oxide according to one aspect of the present invention, indium oxide can be used. Furthermore, as a metal oxide according to one aspect of the present invention, gallium oxide, zinc oxide, etc., can be used.

[0517] By increasing the indium content in metal oxides, transistors can achieve large on-state current and high frequency characteristics.

[0518] Note that metal oxides can also contain one or more metals with high period numbers in the periodic table to replace indium. Alternatively, metal oxides can also contain one or more metals with high period numbers in the periodic table in addition to indium. The greater the overlap of the orbitals of a metal element, the greater the carrier conduction in the metal oxide. Therefore, by including metals with high period numbers in the periodic table, the field-effect mobility of transistors can sometimes be improved. Examples of metals with high period numbers in the periodic table include metals belonging to period 5 and period 6. Specifically, examples of such metals include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0519] Furthermore, metal oxides can also contain one or more non-metallic elements. The inclusion of non-metallic elements in metal oxides can sometimes improve the field-effect mobility of transistors. Examples of non-metallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0520] Furthermore, by increasing the zinc content in the metal oxide, the metal oxide exhibits high crystallinity, thus suppressing the diffusion of impurities within the metal oxide. Consequently, variations in the electrical characteristics of the transistor are suppressed, thereby improving reliability.

[0521] Furthermore, by increasing the content of element M in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation caused by oxygen vacancies is suppressed, thereby enabling transistors with low off-state current. In addition, variations in the transistor's electrical characteristics are suppressed, thus improving reliability.

[0522] In this embodiment, In-M-Zn oxide is sometimes used as an example of a metal oxide.

[0523] [Manufacturing method of oxide semiconductor layer]

[0524] One embodiment of the oxide semiconductor layer of the present invention can be manufactured, for example, by forming a metal oxide using two deposition methods. In other words, one embodiment of the oxide semiconductor layer of the present invention can be manufactured by forming a metal oxide using a first deposition method and a second deposition method.

[0525] As an example, when an oxide semiconductor layer has a two-layer structure of a first layer and a second layer on the first layer, the oxide semiconductor layer can be manufactured by forming the first layer on the surface to be formed using a second deposition method and then forming the second layer on top of it using a first deposition method.

[0526] In addition, as an example, when the oxide semiconductor layer has a three-layer structure of a first layer, a second layer on the first layer and a third layer on the second layer, the oxide semiconductor layer can be manufactured by forming the first layer on the surface to be formed using a second deposition method, then forming the second layer using a first deposition method, and finally forming the third layer using a second deposition method.

[0527] As the second deposition method, it is preferable to use a deposition method that causes less damage to the surface to be formed compared to the first deposition method. This helps to suppress the formation of a mixed layer at the interface between the oxide semiconductor layer and the layer formed on the surface of the oxide semiconductor layer. Furthermore, since the incorporation of impurities such as silicon into the second layer formed on the first layer can be suppressed, the crystallinity of the oxide semiconductor layer can sometimes be further improved.

[0528] Examples of secondary deposition methods include ALD, CVD, and MBE. Examples of CVD methods include plasma CVD, thermal CVD, photocatalytic CVD, and metal-organic CVD (MOCVD). MBE is a deposition method that grows thin films with a crystal structure reflecting the crystal system of the substrate; it is considered one of the deposition methods that causes minimal damage to the surface being formed. Furthermore, wet deposition methods can be used as secondary deposition methods. Wet deposition methods are among the deposition methods that cause minimal damage to the surface being formed. Examples of wet deposition methods include spray coating.

[0529] As the first deposition method, a method capable of depositing crystalline metal oxides is preferred. The deposited metal oxides, in particular, preferably have a CAAC structure. Examples of first deposition methods include sputtering and PLD. Metal oxides deposited by sputtering tend to be crystalline, therefore sputtering is suitable as a first deposition method.

[0530] Furthermore, when a metal oxide is formed on the surface to be formed using a first deposition method, damage to the surface can sometimes lead to alloying of the components contained in the metal oxide with the components contained in the layer of the surface to be formed. When alloying occurs, a mixed layer may sometimes form at the interface between the metal oxide and the layer of the surface to be formed. This mixed layer can also be referred to as an alloyed region. Additionally, the formation of the mixed layer can also be described as alloying.

[0531] For example, when using sputtering as the first deposition method, a mixed layer may sometimes form due to particles released from the target (also called sputtered particles) or energy supplied to the substrate side by the sputtered particles. Specifically, when a metal oxide is deposited using a silicon-containing insulating layer, such as a silicon oxide film, as the surface to be formed, there is a concern that silicon may be mixed into the metal oxide. When impurities such as silicon are mixed into the metal oxide, the crystallization of the metal oxide may be hindered. Furthermore, when using an oxide semiconductor layer mixed with impurities in a transistor, there are concerns that it may negatively affect the initial characteristics or reliability of the transistor. In addition, it is difficult to improve the crystallinity of the alloyed region when performing the heat treatment described later.

[0532] Therefore, as described above, by forming the metal oxide using a second deposition method before forming it using the first deposition method, the incorporation of impurities into the oxide semiconductor layer can be suppressed. Furthermore, alloying can be suppressed. Thus, the initial characteristics and reliability of the transistor can be improved. In addition, the crystallinity of the oxide semiconductor layer can be further improved.

[0533] Compared to sputtering, ALD (Alternating Deposition) can suppress damage to the surface being formed, making it suitable as a second deposition method. Furthermore, ALD offers higher coverage than sputtering; by using ALD as the first and third layer deposition method, the coverage of the oxide semiconductor layer can be improved. Therefore, oxide semiconductor layers can effectively cover high aspect ratio steps, openings, and other similar areas.

[0534] Here, we will describe a method for forming In-M-Zn oxides using the ALD method as the first or third layer.

[0535] First, a source gas containing an indium-containing precursor is introduced into the reaction chamber (also called the processing chamber), causing the precursor to be adsorbed onto the surface to be formed. Next, an oxidant is introduced into the reaction chamber as a reactant, causing it to react with the adsorbed precursor. While the indium is adsorbed onto the substrate, components other than indium are desorbed, thereby forming a layer indium-oxygen bonded together.

[0536] Next, a source gas containing a precursor of element M is introduced into the reaction chamber and adsorbed onto the indium-oxygen bonded layer. Then, an oxidant is introduced into the reaction chamber as a reactant to react with the adsorbed precursor, thereby desorbing components other than element M while element M is adsorbed onto the substrate, thus forming a layer of element M bonded to oxygen.

[0537] Next, a source gas containing a zinc precursor is introduced into the reaction chamber and adsorbed onto the layer bonded to element M and oxygen. Then, an oxidant is introduced into the reaction chamber as a reactant to react with the adsorbed precursor, causing components other than zinc to detach while zinc is adsorbed onto the substrate, thereby forming a layer bonded to zinc and oxygen.

[0538] By repeating the above method, In-M-Zn oxide can be formed as an oxide semiconductor layer on the surface to be formed using the ALD method.

[0539] When forming an oxide semiconductor layer using the ALD method, ozone (O3), oxygen (O2), water (H2O), etc., can be used as oxidants. By using ozone (O3) or oxygen (O2), which do not contain hydrogen, as oxidants, the amount of hydrogen mixed into the oxide semiconductor layer can be reduced.

[0540] Here, the temperature at which the substrate is heated when the precursor is introduced into the reaction chamber is taken as the first temperature, and the temperature at which the substrate is heated when the oxidant is introduced into the reaction chamber is taken as the second temperature.

[0541] The first temperature is preferably a temperature corresponding to the decomposition temperature of the precursor. Here, in the case of using the thermal ALD method with triethylindium as a precursor containing indium, triethylgallium as a precursor containing gallium, and diethylzinc as a precursor containing zinc, for example, the first temperature is 100°C or higher and 350°C or lower, preferably 150°C or higher and 300°C or lower.

[0542] Note that the second temperature is preferably higher than the first temperature. For example, when the oxidant contains ozone, the second temperature is preferably higher than 200°C and lower than 450°C, more preferably higher than 250°C and lower than 400°C, and even more preferably higher than 300°C and lower than 350°C. By employing this structure, the hydrogen concentration in the oxide semiconductor layer can be reduced. In addition, by setting the first temperature lower than the second temperature, particles caused by the decomposition of the precursor can be suppressed.

[0543] Preferably, the reaction chamber for introducing the precursor is the same as the reaction chamber for introducing the oxidant. This structure allows deposition to be performed without substrate handling, thereby increasing productivity. Alternatively, the reaction chamber for introducing the precursor can be different from the reaction chamber for introducing the oxidant. By preparing a first reaction chamber set to a first temperature and a second reaction chamber set to a second temperature, the first and second temperatures can be maintained separately. Therefore, temperature control becomes easier, thereby improving efficiency and safety.

[0544] In the above embodiments, preferably, after the precursor is adsorbed, the introduction of the source gas including the precursor is stopped, the reaction chamber is purged, and then the remaining precursor and reaction products are discharged from the reaction chamber. Alternatively, preferably, after the adsorbed precursor reacts with the oxidant, the introduction of the oxidant is stopped, the reaction chamber is purged, and then the remaining reactants and reaction products are discharged from the reaction chamber.

[0545] Furthermore, in the descriptions in this specification and other documents, unless otherwise specified, when ozone, oxygen, and water are used as reactants or oxidants, they also include plasma states, free radical states, and ionic states, and are not limited to gaseous states or molecular states.

[0546] By adopting the above structure, the thickness of the hybrid layer can be reduced or thinned to the point where the alloyed region is not observable. For example, the thickness of the alloyed region can be 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and even more preferably 0 nm or more and less than 0.3 nm.

[0547] In addition, the thickness of the alloyed region can sometimes be calculated by performing a linear analysis of the composition of the region and its surroundings using SIMS or Energy Dispersive X-ray Spectroscopy (EDX).

[0548] For example, using the direction perpendicular to the surface to be formed of the first layer as the depth direction, EDX line analysis is performed on the alloyed region and its surroundings. Then, in the distribution of quantitative values ​​of each element relative to the depth direction obtained through this analysis, the depth (location) of the interface between the aforementioned region and the first layer is defined as the depth where the quantitative value of the metal that will be the main component of the first layer, but not the main component of the layer to be formed (In if the first layer contains In), reaches half its value. Similarly, the depth (location) of the interface between the aforementioned region and the layer to be formed is defined as the depth where the quantitative value of the element that will be the main component of the layer to be formed, but not the main component of the first layer (e.g., Si), reaches half its value. Through these steps, the thickness of the alloyed region can be calculated.

[0549] In one aspect of the oxide semiconductor layer of the present invention, when the thickness of the alloyed region is observed by EDX analysis, for example, its thickness is 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and even more preferably 0 nm or more and less than 0.3 nm.

[0550] Additionally, for example, when performing SIMS analysis on an oxide semiconductor layer formed on a silicon oxide film on the formed surface, the interface is defined as the depth at which the silicon concentration reaches 50% of the maximum concentration of the silicon oxide film, and the interface is defined as the depth at which the silicon concentration decreases to 1.0 × 10⁻⁶. 21 atoms / cm 3 The preferred reduction is 5.0 × 10 20 atoms / cm 3 More preferably, reduced to 1.0 × 10 20 atoms / cm 3The distance between the depth and the interface is the thickness t_s2. The thickness t_s2 is preferably less than 3 nm, and more preferably less than 2 nm.

[0551] By reducing the thickness of the alloyed region, the thickness t_s2 can be set to a value within the range mentioned above.

[0552] Furthermore, by reducing the alloying region, a CAAC structure can be formed near the surface to be formed. Here, "near the surface to be formed" refers, for example, to a region greater than 0 nm and less than 3 nm, preferably greater than 0 nm and less than 2 nm, and more preferably greater than 1 nm and less than 2 nm, in a direction substantially perpendicular to the surface to be formed of the oxide semiconductor layer.

[0553] Note that CAAC structures near the formed surface can sometimes be identified during TEM observation. For example, when observing a cross-section of an oxide semiconductor layer using high-resolution TEM, layered bright spots arranged in a direction parallel to the formed surface can be identified near the formed surface.

[0554] As the first layer, a metal oxide with a microcrystalline or amorphous structure, for example, is sometimes formed, exhibiting a lower crystallinity than the CAAC structure. The crystallinity of the first layer is sometimes improved by forming a highly crystalline second layer on top of the low-crystallinity first layer, or by performing heat treatment after the formation of the second layer, using the second layer as a nucleus. Thus, the crystallinity of the entire oxide semiconductor layer, including the area near the interface with the formed surface, can sometimes be improved.

[0555] Because the second layer has high crystallinity, the third layer can be grown using the crystals of the second layer as nuclei or seeds. Therefore, the third layer can be crystallized even without using a deposition method that easily imparts crystallinity as the deposition method for the third layer. Here, for example, by using a deposition method with higher coverage than the second layer as the deposition method for the third layer, the entire oxide semiconductor layer can have both high crystallinity and high coverage.

[0556] Furthermore, by setting a first layer to reduce the influence of the formed surface, the crystallinity of the second layer is improved, resulting in extremely excellent crystallinity. Therefore, it is expected that a layer with extremely excellent crystallinity can be formed in the third layer, which crystallizes with the second layer as the nucleus or seed.

[0557] Furthermore, when an oxide semiconductor layer is used as the semiconductor layer of a transistor, sometimes the third layer of the topmost oxide semiconductor layer is in contact with the gate insulating layer. By increasing the crystallinity of the layer in contact with the gate insulating layer, the carrier mobility of the transistor in the on state can be improved.

[0558] The oxide semiconductor layer in this embodiment can be used in the oxide semiconductor layer 230 or the like included in each transistor described in Embodiment 1. Furthermore, the layer on which the surface is formed corresponds to one or more of the conductive layer 220, insulating layer 280, conductive layer 240, and insulating layer 225 described in Embodiment 1.

[0559] As the layer to be formed, insulating films such as silicon oxide films, silicon oxynitride films, silicon nitride films, silicon oxynitride films, aluminum oxide films, and hafnium oxide films can be used, or conductive films such as titanium nitride films, tungsten films, and ITSO films can be used. Alternatively, the layer to be formed may not be crystalline. Furthermore, if the layer is crystalline, it may have a crystal structure with low lattice matching to the metal oxide contained in the oxide semiconductor layer.

[0560] Furthermore, it is preferable to perform heat treatment after forming the oxide semiconductor layer. Heat treatment can improve the crystallinity of the oxide semiconductor layer. Here, heat treatment is not limited to heating. For example, it can also be heat applied during the manufacturing process.

[0561] Microwave plasma treatment is preferably performed after the formation of the first layer.

[0562] In this specification and the like, microwaves refer to electromagnetic waves with frequencies of 300 MHz or higher and 300 GHz or lower. Microwave plasma treatment, for example, refers to a process using a device that includes a power source for generating high-density plasma using microwaves. Microwave plasma treatment may also be referred to as microwave-excited high-density plasma treatment.

[0563] Microwave plasma treatment is preferably performed in an oxygen-containing atmosphere, thereby reducing the impurity concentration in the oxide semiconductor layer 230. Hydrogen and carbon are particularly suitable impurities. Note that the above describes a structure in which the metal oxide is microwave-plasma-treated in an oxygen-containing atmosphere, but this is not a limitation. For example, an insulating film disposed near the metal oxide, more specifically, a silicon oxide film, can also be microwave-plasma-treated in an oxygen-containing atmosphere. Furthermore, due to the heat generated during microwave plasma treatment, the crystallinity of the oxide semiconductor layer is sometimes improved.

[0564] Microwave plasma treatment is preferably carried out under reduced pressure, preferably 10 Pa or more and 1000 Pa or less, more preferably 50 Pa or more and 700 Pa or less, and even more preferably 100 Pa or more and 400 Pa or less. Furthermore, the treatment temperature is preferably room temperature (25°C) or more and 750°C or less, more preferably 300°C or more and 500°C or less, and can be 400°C or more and 450°C or less.

[0565] The substrate can also be heated during microwave plasma treatment. The preferred heating temperature of the substrate is above room temperature (e.g., 25°C), above 100°C, above 200°C, above 300°C, or above 400°C and below 500°C, or below 450°C.

[0566] Microwave plasma treatment can be performed using, for example, oxygen gas and argon gas. For example, the oxygen flow rate ratio (O2 / (O2+Ar)) in microwave plasma treatment is preferably greater than 0% and less than 10%, more preferably more than 0.5% and less than 5%, even more preferably more than 0.5% and less than 3%, and typically preferably 1%.

[0567] By performing microwave plasma treatment in an oxygen-containing atmosphere, oxygen gas can be plasmaized using microwaves or high frequencies such as RF. The oxygen free radicals generated by the plasmaization of the oxygen gas can act on the oxide semiconductor layer. Through the action of plasma, microwaves, and oxygen free radicals, hydrogen can be introduced into defects in the oxygen vacancies (sometimes referred to as V0) in the oxide semiconductor layer. O H) is separated into oxygen vacancies and hydrogen, while hydrogen, which is an impurity, is removed from the oxide semiconductor layer. In this way, V in the oxide semiconductor layer can be reduced. O H. Furthermore, carbon bonded to oxygen or hydrogen can sometimes be removed at this time. Thus, by performing microwave plasma treatment, impurities such as carbon or hydrogen can be reduced. Additionally, by supplying the aforementioned oxygen radicals to oxygen vacancies formed in the oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be further reduced.

[0568] Furthermore, the crystallinity of the first layer can be improved by performing microwave plasma treatment. Here, the principle of improving the crystallinity of oxide semiconductors through microwave plasma treatment will be explained. First, active species such as oxygen free radicals excited by microwaves reach the surface of the oxide semiconductor, where a substitution reaction occurs between these active species and oxygen in the oxide semiconductor. At this time, nuclei or seeds are formed. Additionally, lateral growth of the nuclei or seeds occurs. Furthermore, when the microwave-excited active species contain oxygen (typically oxygen ions) that readily adsorbs onto the sides of the nuclei or seeds, this lateral growth is promoted, and is therefore preferred. By performing microwave plasma treatment, the formation of nuclei or seeds and their lateral growth occur, thereby improving the crystallinity of the oxide semiconductor.

[0569] On the other hand, when some of the oxygen in the oxide semiconductor present before microwave plasma treatment reacts with hydrogen in the oxide semiconductor, i.e., when the reaction "2H + O → H₂O↑" occurs, this hydrogen can be removed as H₂O (also known as dehydration or dehydrogenation). Since H₂O is one of the main factors hindering the improvement of crystallinity, it is preferable to remove H₂O from the oxide semiconductor. Removing hydrogen from the oxide semiconductor as H₂O reduces the hydrogen concentration in the oxide semiconductor, thereby promoting improved crystallinity. Furthermore, by increasing the temperature in the microwave plasma treatment, the hydrogen concentration in the oxide semiconductor can be further reduced.

[0570] Alternatively, the heating treatment can be performed continuously after microwave plasma treatment without exposure to outside air. The heating temperature is preferably 100°C or higher and 750°C or lower, more preferably 300°C or higher and 500°C or lower, and even more preferably 400°C or higher and 450°C or lower.

[0571] Note that plasma treatment containing oxygen gas can also be used instead of microwave plasma treatment to improve crystallinity.

[0572] By improving the crystallinity of the first layer, the crystallinity of the second layer formed on the first layer can be further improved. Therefore, the crystallinity of the entire oxide semiconductor layer can be improved.

[0573] The oxygen supplied to the oxide semiconductor layer can take various forms, such as oxygen atoms, oxygen molecules, oxygen ions (charged oxygen atoms or oxygen molecules), and oxygen free radicals (oxygen atoms, oxygen molecules, or oxygen ions containing unpaired electrons). Furthermore, the oxygen injected into the oxide semiconductor layer can be any one or more of the aforementioned states, with oxygen free radicals being particularly preferred.

[0574] The second layer is preferably formed using a sputtering method.

[0575] In-M-Zn oxides can be used as the target material for sputtering. For example, when forming metal oxides using sputtering, oxygen or a mixture of oxygen and rare gases can be used as the sputtering gas. Furthermore, by increasing the proportion of oxygen contained in the sputtering gas, the excess oxygen in the deposited oxide film can be increased.

[0576] In addition, sometimes the higher the oxygen flow rate ratio relative to the overall deposit gas used during formation (hereinafter also referred to as the oxygen flow ratio), the more crystalline metal oxides can be formed.

[0577] When forming metal oxides using sputtering, oxygen-excess metal oxides can sometimes be formed by depositing under conditions where the proportion of oxygen contained in the sputtering gas is higher than 30% and lower than 100%, preferably higher than 70% and lower than 100%. Transistors using oxygen-excess metal oxides in the channel formation region can achieve higher reliability. Note that one aspect of the invention is not limited to this. Oxygen-deficient metal oxides can be formed by depositing under conditions where the proportion of oxygen contained in the sputtering gas is higher than 1% and lower than 30%, preferably higher than 5% and lower than 20%. Transistors using oxygen-deficient metal oxides in the channel formation region can have higher field-effect mobility.

[0578] When forming metal oxides using sputtering, it is preferable to heat the substrate. By increasing the substrate temperature (stage temperature) during metal oxide formation, highly crystalline metal oxides can sometimes be formed. When forming metal oxides using sputtering, the substrate heating temperature is preferably 100°C or higher and 400°C or lower, more preferably 200°C or higher and 300°C or lower.

[0579] When a third layer is formed on a second layer with a CAAC structure using the ALD method, the third layer is sometimes epitaxially grown using the second layer as a core. Therefore, during the formation of the third layer, the third layer sometimes includes a region with a CAAC structure. Furthermore, this region with the CAAC structure is preferably formed integrally within the third layer.

[0580] After the third layer is formed, a heat treatment process can also be performed.

[0581] The heat treatment temperature can be, for example, 100°C or higher and 800°C or lower, preferably 250°C or higher and 650°C or lower, more preferably 350°C or higher and 550°C or lower. Typically, it can be 400°C ± 25°C (375°C or higher and 425°C or lower). Furthermore, the treatment time can be 10 hours or less, for example, 1 minute or more and 5 hours or 1 minute or more and 2 hours or less. Moreover, when using an RTA apparatus, the treatment time can be, for example, 1 second or more and 5 minutes or less. Through this heat treatment, it is expected that the gaps in the atomic-level crystalline portions of the CAAC structure of the second layer will be filled by a third layer (in other words, crystalline molecules formed using the ALD method).

[0582] There are no particular restrictions on the heating device used for heat treatment; it can be any device that uses heat conduction or thermal radiation from a heating element such as a resistance heating element to heat the workpiece. For example, an electric furnace or an RTA (Rapid Thermal Anneal) device such as LRTA (Lamp Rapid Thermal Anneal) or GRTA (Gas Rapid Thermal Anneal) device can be used. An LRTA device uses the radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, or high-pressure mercury lamp to heat the workpiece. A GRTA device uses high-temperature gas for heat treatment.

[0583] This heat treatment process sometimes improves the crystallinity of the region with the CAAC structure in the third layer. Furthermore, when the region only forms below the third layer after deposition using the ALD method, this heat treatment process sometimes expands the region to the top. That is, through this heat treatment, the region with the CAAC structure sometimes forms throughout the entire third layer.

[0584] Furthermore, it is preferable that at least a portion of the first layer is CAAC-treated through this heat treatment process. When forming the second layer, the mixed layer formed in the first layer becomes a nucleus or seed, thus CAAC-treatment is expected to occur readily. Preferably, the CAAC-treated area in the first layer is large and extends to the vicinity of the formed surface.

[0585] Furthermore, since CAAC is performed from the top to the bottom of the first layer, it is not limited by the material or crystallinity of the layer on which the surface is formed, and CAAC can also be performed near that layer. For example, even if the layer has an amorphous structure, a highly crystalline first layer can be formed. Therefore, the method for manufacturing an oxide semiconductor layer according to one aspect of the present invention is particularly suitable for cases where the layer on which the surface is formed has an amorphous structure.

[0586] Alternatively, microwave plasma treatment can be performed after the third layer is formed.

[0587] In addition, the crystallinity of the entire oxide semiconductor layer can be improved by performing one or both of the above-mentioned heat treatment and microwave plasma treatment.

[0588] As described above, impurities in the oxide semiconductor layer can be reduced. By performing crystal growth with a reduced impurity concentration in the oxide semiconductor layer, crystallinity can be further improved.

[0589] In addition, one or both of the above-mentioned heat treatment and microwave plasma treatment can be performed directly on the oxide semiconductor layer, or after forming an insulating film on the oxide semiconductor layer.

[0590] The crystallinity of the first and third layers is enhanced by using the highly crystalline second layer as a nucleus or seed. Specifically, the crystallinity of the first layer is sometimes enhanced by heat treatment during the deposition of the second layer or after the deposition of the third layer. Similarly, the crystallinity of the third layer is sometimes enhanced by heat treatment during or after the deposition of the third layer. Furthermore, the aforementioned heat treatment plays an auxiliary role in enhancing crystallinity.

[0591] Thus, in one aspect of the metal oxide deposition method of the present invention, the crystallinity of the metal oxides above and below (here, the first and third layers) can be improved by using a second layer containing a highly crystalline metal oxide (i.e., CAAC) as a nucleus or seed. This improves the overall crystallinity of the oxide semiconductor layer. In other words, by using the second layer as a nucleus or seed, the metal oxides above and below are grown in a solid phase, thereby forming a highly crystalline oxide semiconductor layer. The oxide semiconductor layer formed using the above deposition method, in this case, the CAAC film, can be referred to as axially grown CAAC (AGCAAC).

[0592] In an oxide semiconductor layer, regions with CAAC structures are preferably widely distributed throughout the entire layer. The CAAC-structured regions of the first layer are crystal-bonded with the CAAC-structured regions of the second layer. The CAAC-structured regions of the third layer are crystal-bonded with the CAAC-structured regions of the second layer. Therefore, sometimes the boundary between the first and second layers is not observable. Additionally, sometimes the boundary between the second and third layers is not observable. Sometimes the oxide semiconductor layer can be described as a single layer with no clearly observable interface. Sometimes the oxide semiconductor layer can be described as a monolayer.

[0593] In each of the first to third layers, for example, when cross-sectional observation is performed using a high-resolution TEM, bright spots arranged parallel to or substantially parallel to the surface being formed are identified in the region having the CAAC structure. Furthermore, the c-axis of the CAAC structure in each of the first to third layers is preferably parallel to or substantially parallel to the normal direction of the surface or plane of the oxide semiconductor layer being formed.

[0594] In addition, a portion of the first or third layer is sometimes not crystallized.

[0595] By improving the crystallinity of the oxide semiconductor layer, the increase in semiconductor layer resistance in transistors using oxide semiconductor layers is suppressed, or the initial characteristics of the transistor (especially the on-state current) are improved, thereby making it possible to realize transistors suitable for high-speed driving. In addition, the reliability of the transistor can be improved and the on-state current can be increased.

[0596] In one aspect of the present invention, the oxide semiconductor layer has high overall crystallinity. Therefore, in the oxide semiconductor layer, it is sometimes impossible to identify the boundaries between the stacked films from the first to the third layer. In particular, after heat treatment, it is sometimes difficult to identify the boundaries between the stacked films. For example, cross-sectional TEM, cross-sectional STEM (scanning transmission electron microscopy), etc., can be used to confirm whether there are boundaries between the stacked films.

[0597] As mentioned above, using metal oxides with a high In content in transistors can improve the field-effect mobility of the transistor. On the other hand, oxide semiconductors with a high In content tend to polycrystalline. When using metal oxides with polycrystalline structures in transistors, it negatively impacts the initial characteristics or reliability of the transistor. Therefore, by using oxide semiconductors with a high In content in one or both of the first and third layers, forming a crystal that reflects the orientation of the crystal contained in the second layer, polycrystalline formation can be suppressed.

[0598] Furthermore, the lattice mismatch between the crystals contained in the second layer and those contained in the first or third layer is preferably small. Thus, the first or third layer can form a crystal that reflects the orientation of the crystals contained in the second layer. In this case, for example, when observing a cross-section of the oxide semiconductor layer using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the surface to which they are formed are observed in the first or third layer.

[0599] There are no particular restrictions on the crystal structure of the first or third layer, provided that the lattice mismatch between the crystal contained in the second layer and the crystal contained in the first or third layer is small. The crystal structure of the first or third layer can be cubic, tetragonal, orthorhombic, hexagonal, monoclinic, or trigonal.

[0600] Furthermore, the oxide semiconductor layer of one aspect of the present invention can sometimes be fabricated using one or both of a second deposition method and microwave plasma treatment and heat treatment. In other words, sometimes the oxide semiconductor layer of one aspect of the present invention can be fabricated without forming a second layer. In this case, the oxide semiconductor layer has a two-layer structure of a first layer and a third layer. For example, by performing one or both of microwave plasma treatment and heat treatment after forming the first layer, the crystallinity of the first layer can be improved, and the crystallinity of the third layer can be improved using the first layer as a nucleus or seed. In addition, by performing one or both of microwave plasma treatment and heat treatment after forming the third layer, the crystallinity of the oxide semiconductor layer can be improved. Therefore, a CAAC structure can be formed in the oxide semiconductor layer.

[0601] As described above, in a structure without a second layer, the oxide semiconductor above can be grown in a solid phase using the first layer as a nucleus or seed to form a highly crystalline oxide semiconductor. The oxide semiconductor formed by the above deposition method can also be called AG CAAC.

[0602] [Composition of the oxide semiconductor layer]

[0603] The composition of the second layer is preferably different from that of the first layer. Furthermore, the composition of the second layer is preferably different from that of the third layer. Alternatively, the first layer may have the same composition as the third layer. Or, the compositions of the first and third layers may also be different from each other.

[0604] The second layer preferably contains In, and more preferably has a high In content. By using a metal oxide with a high In content as the oxide semiconductor layer 230b, the on-state current can be increased and the frequency characteristics can be improved when the oxide semiconductor layer is used in a transistor.

[0605] As described above, the second layer preferably has a composition suitable for forming a CAAC structure. The second layer preferably contains, for example, zinc. By including zinc, a highly crystalline metal oxide can be obtained.

[0606] The second layer can also be, for example, an In-Zn oxide. Specifically, it can be an In:Zn ratio of 1:1 or closer, an In:Zn ratio of 2:1 or closer, or an In:Zn ratio of 4:1 or closer. Alternatively, indium oxide can also be used. Furthermore, the "nearby" composition includes a range of ±30% of the desired atomic ratio. As element M, one or more of gallium, aluminum, and tin are preferably used.

[0607] The second layer preferably contains element M. When the second layer contains element M, for example, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, the reliability of transistors using oxide semiconductor layers can be improved. Specifically, the second layer can also use metal oxides with an In:M:Zn ratio of 1:1:1 or similar, an In:M:Zn ratio of 1:1:1.2 or similar, an In:M:Zn ratio of 1:1:0.5 or similar, an In:M:Zn ratio of 1:1:2 or similar, an In:M:Zn ratio of 4:2:3 or similar, an In:M:Zn ratio of 1:3:2 or similar, or an In:M:Zn ratio of 1:3:4 or similar.

[0608] Furthermore, the second layer can also contain trace amounts of element M. For example, it could be a composition with an In:Ga:Zn ratio of 4:0.1:1 or similar, an In:Ga:Zn ratio of 2:0.1:1 or similar, or an In:Ga:Zn ratio of 1:0.1:1 or similar. Alternatively, it could be a composition with an In:Sn:Zn ratio of 4:0.1:1 or similar, an In:Sn:Zn ratio of 2:0.1:1 or similar, or an In:Sn:Zn ratio of 1:0.1:1 or similar.

[0609] When metal oxides are formed using sputtering, the composition of the formed metal oxide sometimes differs from that of the sputtering target. In particular, the zinc content of the formed metal oxide sometimes decreases to about 50% of the zinc content in the sputtering target.

[0610] Both the first and third layers can use metal oxides that are also suitable for the second layer.

[0611] For example, the first and third layers can be metal oxides with a higher In content than the second layer. By using metal oxides with a high In content, the on-state current and frequency characteristics can be increased when using oxide semiconductor layers in transistors.

[0612] For example, metal oxides with a higher Ga content than the second layer can be used as the first and third layers. For instance, metal oxides with an In:Ga:Zn ratio of 1:1:1 or similar, an In:Ga:Zn ratio of 1:3:2 or similar, or an In:Ga:Zn ratio of 1:3:4 or similar can be preferred as the first and third layers. By increasing the Ga content, for example, the band gaps of the first and third layers can sometimes be made larger than those of the second layer. Thus, the second layer is sandwiched between the first and third layers with their large band gaps, and the second layer is primarily used as the current path (channel). Because the second layer is sandwiched between the first and third layers, the trap states at and near the interface of the second layer can be reduced. This allows for the realization of buried-channel transistors with the channel far from the insulating layer interface, thereby improving field-effect mobility. Furthermore, the influence of the interface energy level that can be formed on the back channel side is reduced, suppressing transistor optical degradation (e.g., optical negative bias degradation) and improving transistor reliability.

[0613] In addition, one of the first and third layers can be a metal oxide with a higher In content than the second layer and a metal oxide with a higher Ga content than the second layer, respectively.

[0614] Alternatively, the first, second, and third layers may each comprise a stack of multiple layers having the above-described composition. For example, the third layer may have a structure in which a metal oxide with a high content of Ga is stacked on a metal oxide with a high content of In.

[0615] Note that when depositing metal oxide films containing multiple metal elements, such as In-Ga-Zn oxides, using the ALD method, the cycle ratio of the precursors containing each metal element can be set according to the target composition. For example, when depositing In-Ga-Zn oxides with an In:Ga:Zn ratio of 1:3:2 (atomic number ratio), one cycle of depositing the In-containing precursor and treating with an oxidant can be performed, three cycles of depositing the Ga-containing precursor and treating with an oxidant can be performed, and two cycles of depositing the Zn-containing precursor and treating with an oxidant can be performed. Note that sometimes the cycle ratio of the precursors containing each metal element is not consistent with the atomic number ratio of each metal element in the deposited metal oxide film.

[0616] In one embodiment of the oxide semiconductor layer of the present invention, even if it is not easy to form a CAAC structure by forming a single layer when used as the first and third layers, since crystal growth is generated with the second layer as the nucleus, the entire oxide semiconductor layer including the first and third layers can have a CAAC structure. Alternatively, the region including at least a portion of each of the first and third layers to the region including the second layer can have a CAAC structure.

[0617] In particular, compositions with high In content in the first and third layers can also possess suitable crystallinity for use as a semiconductor layer in transistors. In an embodiment of the oxide semiconductor layer of the present invention, while increasing the In content to improve the turn-on characteristics of the transistor, a highly crystalline CAAC structure can be used to improve reliability.

[0618] Alternatively, the first and third layers can also use metal oxides with the same composition as the second layer. By using the same composition, it is sometimes easy to achieve CAAC formation after heat treatment.

[0619] Furthermore, compared to oxide semiconductor layers with CAAC structures formed using one deposition method, oxide semiconductor layers with CAAC structures formed using the two deposition methods described above sometimes have higher relative permittivity, film density, and film hardness, among one or more of these.

[0620] By using the oxide semiconductor layer with CAAC structure formed by the above two deposition methods to form the channel region of the transistor, transistors with excellent characteristics can be realized (e.g., transistors with large on-state current, transistors with high field-effect mobility, transistors with small S-value, transistors with high frequency characteristics (also known as f-characteristics), transistors with high reliability, etc.).

[0621] In the analysis of the composition of metal oxides used in oxide semiconductor layers, methods such as EDX, XPS, inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES) can be used. Furthermore, multiple methods can be combined. Note that the actual content of elements with low concentrations may differ from the analytically obtained content due to the limitations of analytical precision. For example, when the content of element M is low, the analytically obtained content of element M may sometimes be lower than the actual content.

[0622] [Oxide semiconductor layer of a transistor]

[0623] The oxide semiconductor layer in this embodiment can be used as the semiconductor layer of a transistor.

[0624] The oxide semiconductor layer of this embodiment has a CAAC structure. In the oxide semiconductor layer with a CAAC structure, metal atoms in the crystalline portion are arranged in layers in a direction parallel to or substantially parallel to the surface to be formed.

[0625] It can be inferred that oxide semiconductor layers with a CAAC structure exhibit current anisotropy. For example, in IGZO crystals, current flows more readily along the a-axis than along the c-axis. In other words, it can be inferred that in oxide semiconductor layers with a CAAC structure, current flows more readily in the transverse direction than in the longitudinal direction.

[0626] In the semiconductor device described in the above embodiments, metal atoms in the oxide semiconductor layer 230 are arranged in layers in a direction parallel to or substantially parallel to the surface to be formed. Alternatively, the ab plane of the CAAC structure can be provided in a direction parallel to or substantially parallel to the surface to be formed. Here, the oxide semiconductor layer 230 is provided along the sidewall of the opening 290. Therefore, in the oxide semiconductor layer 230, metal atoms are arranged in layers in a direction parallel to or substantially parallel to the sidewall of the opening 290. By employing this structure, the ab plane of the CAAC structure can be provided in the channel of the transistor along the direction of current flow. This increases the on-state current of the transistor.

[0627] When the oxide semiconductor layer of this embodiment is used as the semiconductor layer of a transistor, the thickness of the oxide semiconductor layer is preferably 3 nm or more and 200 nm or less, more preferably 3 nm or more and 100 nm or less, more preferably 5 nm or more and 100 nm or less, more preferably 10 nm or more and 100 nm or less, more preferably 10 nm or more and 70 nm or less, more preferably 15 nm or more and 70 nm or less, more preferably 15 nm or more and 50 nm or less, and more preferably 20 nm or more and 50 nm or less. Furthermore, in transistors used in more miniaturized semiconductor devices, the thickness of the oxide semiconductor layer is preferably 1 nm or more and 20 nm or less, more preferably 3 nm or more and 15 nm or less, more preferably 5 nm or more and 12 nm or less, and more preferably 5 nm or more and 10 nm or less. Additionally, the average thickness of the oxide semiconductor layer in the channel formation region of the transistor is preferably, for example, 2 nm or more and 15 nm or less.

[0628] The second layer is preferably 200 nm or less. Furthermore, when the second layer is layered, it is preferably 1 nm or more and 200 nm or less, more preferably 1 nm or more and 100 nm or less, and even more preferably 2 nm or more and 100 nm or less.

[0629] Alternatively, when the second layer can function as a crystal nucleus, it may not exist as a layer but as an aggregate of island-like regions. In this case, for example, the island-like regions included in the second layer may exist dispersedly.

[0630] The first and third layers are preferably 0.5 nm or more and 50 nm or less, more preferably 0.5 nm or more and 30 nm or less, more preferably 0.5 nm or more and 20 nm or less, more preferably 1 nm or more and 50 nm or less, more preferably 1 nm or more and 30 nm or less, more preferably 1 nm or more and 20 nm or less, and more preferably 2 nm or more and 20 nm or less. Furthermore, the first layer is more preferably 0.5 nm or more and 3 nm or less.

[0631] Impurities in oxide semiconductors

[0632] Here, we will explain the effects of various impurities in oxide semiconductors.

[0633] As described in the above embodiments, in a transistor using an oxide semiconductor as the semiconductor layer, when an oxygen vacancy (V0) exists in the channel formation region of the oxide semiconductor... O When impurities are present, electrical characteristics can easily change, leading to a decrease in reliability. Therefore, reducing the impurity concentration in the oxide semiconductor is effective in stabilizing the electrical characteristics of the OS transistor. To reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the nearby film. Examples of impurities include hydrogen, carbon, and nitrogen. Note that impurities in an oxide semiconductor refer to elements other than the main components constituting the oxide semiconductor. For example, elements with a concentration below 0.1 atomic% can be considered impurities.

[0634] When an oxide semiconductor contains silicon or carbon, one of Group 14 elements, defect states are formed in the oxide semiconductor. Therefore, the carbon concentration in the channel formation region of the oxide semiconductor, measured using SIMS, is set to 1 × 10⁻⁶. 20 atoms / cm 3 The following is preferred: 5×10 19 atoms / cm 3 The following is more preferably 3×10 19 atoms / cm 3 Hereinafter, 1×10 is more preferred. 19 atoms / cm 3 The following is more preferably 3×10 18 atoms / cm 3 Hereinafter, 1×10 is further preferred. 18 atoms / cm 3Below. Furthermore, the silicon concentration in the channel formation region of the oxide semiconductor, measured using SIMS, is set to 1 × 10⁻⁶. 20 atoms / cm 3 The following is preferred: 5×10 19 atoms / cm 3 The following is more preferably 3×10 19 atoms / cm 3 Hereinafter, 1×10 is more preferred. 19 atoms / cm 3 The following is more preferably 3×10 18 atoms / cm 3 Hereinafter, 1×10 is further preferred. 18 atoms / cm 3 the following.

[0635] Furthermore, when nitrogen is included in oxide semiconductors, electrons are generated as charge carriers, increasing the charge carrier concentration and making them more susceptible to n-type conversion. As a result, transistors using nitrogen-containing oxide semiconductors tend to exhibit always-on characteristics. Alternatively, when nitrogen is included in oxide semiconductors, trapped states sometimes form. Consequently, the electrical characteristics of the transistors can sometimes be unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor, measured using SIMS, is set to 1 × 10⁻⁶. 20 atoms / cm 3 The following is preferred: 5×10 19 atoms / cm 3 Hereinafter, 1×10 is more preferred. 19 atoms / cm 3 The following is more preferably 5×10 18 atoms / cm 3 Hereinafter, 1×10 is more preferred. 18 atoms / cm 3 The following is a further preferred option: 5×10 17 atoms / cm 3 the following.

[0636] Furthermore, hydrogen contained in oxide semiconductors reacts with oxygen bonded to metal atoms to form water, thus sometimes creating oxygen vacancies. When hydrogen enters these oxygen vacancies, electrons are sometimes generated as charge carriers. Additionally, sometimes a portion of the hydrogen bonds with oxygen bonded to metal atoms, generating electrons as charge carriers. Therefore, transistors using oxide semiconductors containing hydrogen tend to have always-on characteristics. Thus, it is preferable to minimize the amount of hydrogen in the channel formation region of the oxide semiconductor. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor, as measured using SIMS, is set to be less than 1 × 10⁻⁶. 20 atoms / cm3 Preferably below 5×10 19 atoms / cm 3 More preferably, less than 1×10 19 atoms / cm 3 Further optimization of less than 5×10 18 atoms / cm 3 Furthermore, a preference is given to products with a size lower than 1×10. 18 atoms / cm 3 Furthermore, it is preferred to select those with a density lower than 1×10 17 atoms / cm 3 .

[0637] Furthermore, when oxide semiconductors contain alkali metals or alkaline earth metals, defect states are sometimes formed, generating charge carriers. Therefore, transistors using oxide semiconductors containing alkali metals or alkaline earth metals tend to exhibit always-on characteristics. Consequently, the concentration of alkali metals or alkaline earth metals in the channel formation region of the oxide semiconductor, as measured by SIMS, is set to 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferred: 2×10 16 atoms / cm 3 the following.

[0638] By using oxide semiconductors with sufficiently reduced impurities in the channel formation region of a transistor, the transistor can have stable electrical characteristics.

[0639] This embodiment can be appropriately combined with other embodiments or examples. Furthermore, where multiple structural examples are shown in one embodiment in this specification, these structural examples can be appropriately combined.

[0640] (Implementation Method 3)

[0641] In this embodiment, refer to Figures 31A to 35 This invention describes a storage device according to one aspect of the present invention. The storage device according to one aspect of the present invention includes a storage cell. The storage cell includes a transistor and a capacitor.

[0642] <Example 1 of storage device structure>

[0643] Reference Figures 31A to 31C Describe the structure of a storage device that includes transistors and capacitors. Figure 31A It is a plan view of a storage device including transistor 200 and capacitor 100. Figure 31B It is along Figure 31A The cross-sectional view of the dotted line A1-A2 shown. Figure 31C It is along Figure 31A The cross-sectional view shown is the dotted-dash line A3-A4.

[0644] Figures 31A to 31C The storage device shown includes an insulating layer 140 on a substrate (not shown), a conductive layer 110 on the insulating layer 140, a storage cell 150 on the conductive layer 110, an insulating layer 180 on the conductive layer 110, and an insulating layer 280. The insulating layers 140, 180, and 280 are used as interlayer films. The conductive layer 110 is used for wiring.

[0645] The storage cell 150 includes a capacitor 100 on the conductive layer 110 and a transistor 200 on the capacitor 100.

[0646] The capacitor 100 includes a conductive layer 115 on the conductive layer 110, an insulating layer 130 on the conductive layer 115, and a conductive layer 220_1 on the insulating layer 130. The conductive layer 220_1 serves as one of a pair of electrodes (sometimes referred to as the upper electrode), the conductive layer 115 serves as the other of the pair of electrodes (sometimes referred to as the lower electrode), and the insulating layer 130 serves as the dielectric. That is, the capacitor 100 constitutes a MIM (Metal-Insulator-Metal) capacitor. Alternatively, the conductive layer 220_2 disposed on the conductive layer 220_1 can also be considered as part of the upper electrode of the capacitor 100.

[0647] like Figure 31B and Figure 31C As shown, the insulating layer 180 has an opening 190 extending to the conductive layer 110. At least a portion of the conductive layer 115 is disposed within the opening 190. Note that the conductive layer 115 has a region within the opening 190 that contacts the top surface of the conductive layer 110, a region within the opening 190 that contacts the side surface of the insulating layer 180, and a region that contacts at least a portion of the top surface of the insulating layer 180. The insulating layer 130 is disposed such that at least a portion of it is located within the opening 190. The conductive layer 220_1 is disposed such that at least a portion of it is located within the opening 190. Additionally, as... Figure 31B and Figure 31C As shown, the conductive layer 220_1 is preferably provided in a manner that embeds it into the opening 190. Furthermore, the films disposed inside the opening 190 are preferably formed using the ALD method. Thus, the film has good coverage. For example, the conductive layer 115, the insulating layer 130, and the conductive layer 220_1 are all preferably formed using the ALD method.

[0648] The capacitor 100 has a structure in which the upper and lower electrodes are opposed to each other by a dielectric material not only on the bottom surface but also on the side surface within the opening 190, thus increasing the electrostatic capacitance per unit area. Therefore, the deeper the opening 190, the larger the electrostatic capacitance of the capacitor 100 can be. In this way, by increasing the electrostatic capacitance per unit area of ​​the capacitor 100, the read operation of the storage device can be stabilized. Furthermore, it can promote the miniaturization or high integration of storage devices.

[0649] Figure 31B and Figure 31C An example is shown where the sidewall of the opening 190 is perpendicular to the top surface of the conductive layer 110. In this case, the opening 190 has a cylindrical shape. By adopting this structure, miniaturization or high integration of the storage device can be achieved.

[0650] A conductive layer 115 and an insulating layer 130 are stacked along the sidewall of the opening 190 and the top surface of the conductive layer 110. Additionally, a conductive layer 220_1 is provided on the insulating layer 130 in a manner that embeds into the opening 190. A capacitor 100 with this structure can also be referred to as a trench capacitor or a grooved capacitor.

[0651] In addition, an insulating layer 280 is disposed on the capacitor 100. The insulating layer 280 has a portion located on the insulating layer 130 and a portion located on the conductive layer 220_2.

[0652] The transistor 200 includes: a conductive layer 220 including conductive layers 220_1 and 220_2; a conductive layer 240 on an insulating layer 280; an oxide semiconductor layer 230; an insulating layer 250 on an oxide semiconductor layer 230; and a conductive layer 260 on an insulating layer 250.

[0653] In transistor 200, oxide semiconductor layer 230 is used as semiconductor layer, conductive layer 260 is used as gate electrode, insulating layer 250 is used as gate insulating layer, conductive layer 220 is used as one of source electrode and drain electrode, and conductive layer 240 is used as the other of source electrode and drain electrode.

[0654] Regarding transistor 200, please refer to Implementation Method 1 ( Figure 2A The description in () is omitted here. Furthermore, the transistors included in the storage cell 150 are not limited to transistor 200; the transistors shown in Embodiment 1 may also be used.

[0655] like Figures 31A to 31CAs shown, the transistor 200 is arranged to overlap with the capacitor 100. Furthermore, the opening 290 of the structure where the transistor 200 is disposed has a region that overlaps with the opening 190 of the structure where the capacitor 100 is disposed. In particular, the conductive layer 220 functions as one of the source and drain electrodes of the transistor 200 and the upper electrode of the capacitor 100, so the transistor 200 and the capacitor 100 share a portion of the structure. By adopting this structure, the transistor 200 and the capacitor 100 can be arranged in a way that does not significantly increase the occupied area when viewed from a planar perspective. Therefore, the occupied area of ​​the memory cell 150 can be reduced, and the storage capacity of the memory device can be increased by arranging the memory cells 150 at a high density. In other words, high integration of the memory device can be achieved. Figure 31B and Figure 31C An example is shown where the width of opening 190 is smaller than the width of opening 290. There are no particular limitations on the size relationship between the widths of opening 190 and opening 290. From a miniaturization point of view, the width of opening 190 is preferably equal to or smaller than the width of opening 290.

[0656] Furthermore, by placing the transistor 200 above the capacitor 100, the transistor 200 is not affected by the heat treatment during the manufacture of the capacitor 100. Therefore, it is possible to suppress the degradation of the electrical characteristics of the transistor 200, such as threshold voltage fluctuations and increased parasitic resistance, as well as the increase in uneven electrical characteristics caused by such degradation.

[0657] Figure 37A A circuit diagram of the storage device shown in this embodiment is illustrated. Figure 37A As shown, Figures 31A to 31C The structure shown is used as a storage cell. Storage cell 951 includes transistor M1 and capacitor CA. Here, transistor M1 corresponds to transistor 200, and capacitor CA corresponds to capacitor 100.

[0658] One of the source and drain terminals of transistor M1 is connected to one of the electrodes of capacitor CA. The other of the source and drain terminals of transistor M1 is connected to wiring BIL. The gate of transistor M1 is connected to wiring WOL. The other of the electrodes of capacitor CA is connected to wiring CAL.

[0659] Here, wiring BIL corresponds to conductive layer 240, wiring WOL corresponds to conductive layer 260, and wiring CAL corresponds to conductive layer 110. For example... Figures 31A to 31C As shown, preferably, the conductive layer 260 extends in the X direction and the conductive layer 240 extends in the Y direction. With this structure, the wiring BIL and wiring WOL intersect each other. Furthermore, in Figure 31AIn this embodiment, the wiring CAL (conductive layer 110) is configured as a planar shape, but the present invention is not limited thereto. For example, the wiring CAL may also be parallel to the wiring WOL (conductive layer 260) or the wiring BIL (conductive layer 240).

[0660] Note that the storage unit will be described in detail in the following implementation.

[0661] [Capacitor 100]

[0662] The capacitor 100 includes a conductive layer 115, an insulating layer 130, and a conductive layer 220_1. Furthermore, a conductive layer 110 is disposed below the conductive layer 115. The conductive layer 115 has a region that contacts the conductive layer 110.

[0663] A conductive layer 110 is disposed on the insulating layer 140. The conductive layer 110 is used as a wiring CAL, and may be disposed in a planar manner, for example. As the conductive layer 110, a single layer or a stack of conductive materials described in [Conductive Layer] of Embodiment 1 can be used. As the conductive layer 110, for example, a highly conductive material such as tungsten can be used. By using a highly conductive material in this way, the conductivity of the conductive layer 110 can be improved, thereby enabling the conductive layer 110 to fully perform its function as a wiring CAL.

[0664] Furthermore, as the conductive layer 115, it is preferable to use a conductive material that is not easily oxidized, either as a single layer or in a stack, or a conductive material that has the function of inhibiting oxygen diffusion. For example, titanium nitride or ITSO can also be used. Alternatively, for example, a structure in which titanium nitride is stacked on top of tungsten can also be used. Alternatively, for example, a structure in which first titanium nitride, tungsten, and second titanium nitride are stacked sequentially can also be used. By adopting this structure, oxidation of the conductive layer 110 due to the insulating layer 130 can be suppressed when an oxide is used in the insulating layer 130. Furthermore, oxidation of the conductive layer 110 due to the insulating layer 180 can be suppressed when an oxide is used as the insulating layer 180.

[0665] An insulating layer 130 is disposed on the conductive layer 115. The insulating layer 130 is disposed in contact with the top and side surfaces of the conductive layer 115. That is, the insulating layer 130 preferably covers the side ends of the conductive layer 110. This prevents short circuits between the conductive layer 115 and the conductive layer 220_1.

[0666] Alternatively, the side ends of the insulating layer 130 can be aligned with the side ends of the conductive layer 115. By using this structure, the insulating layer 130 and the conductive layer 115 can be formed using the same mask, thereby simplifying the manufacturing process of the storage device.

[0667] A material with a high relative permittivity (high-k) is preferably used as the insulating layer 130. By using a high-k material for the insulating layer 130, the thickness of the insulating layer 130 can be increased to a level that can suppress leakage current and sufficiently ensure the electrostatic capacitance of the capacitor 100.

[0668] Furthermore, as the insulating layer 130, it is preferable to use an insulating layer made of a high-k material, and more preferably, a laminated structure using a material with a high relative permittivity (high-k) and a material with a dielectric strength greater than that high-k material. For example, as the insulating layer 130, an insulating film in which zirconium oxide, alumina, and zirconium oxide are stacked sequentially can be used. Alternatively, for example, an insulating film in which zirconium oxide, alumina, zirconium oxide, and alumina are stacked sequentially can be used. Furthermore, for example, an insulating film in which hafnium zirconium oxide, alumina, hafnium zirconium oxide, and alumina are stacked sequentially can be used. By using an insulating layer with a high dielectric strength, such as alumina, the dielectric strength can be increased, thereby suppressing electrostatic discharge damage to the capacitor 100.

[0669] Furthermore, a ferroelectric material can also be used as the insulating layer 130. For details regarding ferroelectric materials, please refer to the description in Embodiment 1.

[0670] Metal oxides containing one or both of hafnium and zirconium can exhibit ferroelectricity even in thin films of a few nm, making them preferred as insulating layer 130. The thickness of insulating layer 130 can be 100 nm or less, more preferably 50 nm or less, further preferably 20 nm or less, and even more preferably 10 nm or less (typically, 2 nm or more and 9 nm or less). Furthermore, for example, the thickness is preferably 8 nm or more and 12 nm or less. By using a ferroelectric layer that can be thinned, capacitor 100 can be combined with miniaturized semiconductor elements such as transistors to form a semiconductor device.

[0671] Furthermore, metal oxides containing one or both of hafnium and zirconium can exhibit ferroelectricity even in small areas, making them preferred as insulating layer 130. For example, the ferroelectric layer can have an area (occupied area) of 100 μm when viewed from a planar surface. 2 Below, 10μm 2 Below, 1μm 2 Below or 0.1μm 2 The following can also exhibit ferroelectric properties. Furthermore, sometimes ferroelectric layers can exist even with a planar surface area (occupied area) of 10000 nm. 2 Below or 1000nm 2 The following also exhibit ferroelectric properties. By reducing the area of ​​the ferroelectric layer, the occupied area of ​​the capacitor 100 can be reduced.

[0672] Ferroelectric materials are insulators that exhibit the property of becoming internally polarized under the influence of an applied electric field and maintaining this polarization even when the electric field is zero. Therefore, non-volatile storage elements can be formed by using a capacitor (hereinafter sometimes referred to as a ferroelectric capacitor) that uses this material as the dielectric. Non-volatile storage elements using ferroelectric capacitors are sometimes called FeRAM (Ferroelectric Random Access Memory), ferroelectric memory, etc. For example, a ferroelectric memory includes a transistor and a ferroelectric capacitor, with one of the source and drain terminals of the transistor connected to a terminal of the ferroelectric capacitor. Thus, when a ferroelectric capacitor is used as capacitor 100, the storage device shown in this embodiment is used as a ferroelectric memory.

[0673] The conductive layer 220_1 is disposed in contact with a portion of the top surface of the insulating layer 130. Preferably, the side portion of the conductive layer 220_1 is located inside the side portion of the conductive layer 115 in both the X and Y directions. In a structure where the insulating layer 130 covers the side portion of the conductive layer 115, the side portion of the conductive layer 220_1 may also be located outside the side portion of the conductive layer 115.

[0674] Insulating layer 180 is used as an interlayer film, so its relative permittivity is preferably low. By using a material with a low relative permittivity in the interlayer film, parasitic capacitance generated between wirings can be reduced. As insulating layer 180, a single layer or a stack of insulating layers containing a material with a low relative permittivity can be used. Silicon oxide and silicon oxynitride have thermal stability and are therefore preferred.

[0675] Note that in Figure 31B and Figure 31C In this invention, the insulating layer 180 is a single layer, but the invention is not limited to this. The insulating layer 180 may also have a two-layer structure, or a stacked structure of three or more layers.

[0676] <Example 2 of storage device structure>

[0677] Figure 32A and Figure 32B It is a cross-sectional view of a memory device including transistors 200a and 200b.

[0678] Figure 32A and Figure 32B The storage device shown includes an insulating layer 140 on a substrate (not shown), a storage cell 150 on the insulating layer 140, an insulating layer 280a on the insulating layer 140, and an insulating layer 280b above the insulating layer 280a. The insulating layers 140, 280a, and 280b are used as interlayer films.

[0679] The storage cell 150 includes a transistor 200a on an insulating layer 140 and a transistor 200b on the transistor 200a.

[0680] Regarding transistors 200a and 200b, please refer to transistor 200 in Embodiment 1. Figure 2A The description of the conductive layer 220a and the oxide semiconductor layer 230a is omitted here. For example, regarding the structure of the conductive layer 220a and the oxide semiconductor layer 230a, etc., by replacing the conductive layer 220 with the conductive layer 220a and the oxide semiconductor layer 230 with the oxide semiconductor layer 230a, etc., please refer to [reference needed]. Figure 2A The explanation is as follows. Additionally, regarding the structure of conductive layer 220b and oxide semiconductor layer 230b, for example, by replacing conductive layer 220 with conductive layer 220b and oxide semiconductor layer 230 with oxide semiconductor layer 230b, etc., please refer to... Figure 2A Explanation.

[0681] Insulating layers 280a and 280b can adopt the same structure as that used for insulating layer 280.

[0682] The transistors included in the storage cell 150 are not limited to a combination of transistors 200a and 200b, and one or more of the transistors shown in Embodiment 1 may also be used.

[0683] exist Figure 32A and Figure 32B In the storage cell 150 shown, a capacitor generated between the conductive layer 220b and the conductive layer 240a can be used, thereby allowing data to be retained without forming a separate capacitor.

[0684] The preferred ratio of the shortest distance from the top surface of conductive layer 240a to conductive layer 220b is the distance from the top surface of conductive layer 240b to the gate wiring. Figure 32A The shortest distance between the conductive layer 260b and the conductive layer 240a is short. This increases the capacitance generated between the conductive layer 220b and the conductive layer 240a. Furthermore, it reduces the parasitic capacitance generated between the conductive layer 240b and the gate wiring. For example, the structure of the transistor 200A described in Embodiment 1 is preferably adopted as the transistor 200b.

[0685] like Figure 32A and Figure 32BAs shown, transistor 200b is arranged overlapping transistor 200a. Furthermore, the opening 290 of a portion of the structure where transistor 200b is disposed has a region overlapping with the opening 290a of a portion of the structure where transistor 200a is disposed. In particular, the conductive layer 220b functions as one of the source and drain electrodes of transistor 200b and the gate electrode of transistor 200a, so transistor 200b and transistor 200a share a portion of the structure. By adopting this structure, transistors 200b and 200a can be arranged with a relatively small increase in occupied area when viewed from a planar perspective. Therefore, the occupied area of ​​memory cells 150 can be reduced, and the storage capacity of the memory device can be increased by arranging memory cells 150 at a high density. In other words, high integration of the memory device can be achieved.

[0686] Figure 37E A circuit diagram of the storage device shown in this embodiment is illustrated. Figure 37E As shown, Figure 32A and Figure 32B The structure shown is used as a storage cell. Storage cell 955 includes transistor M2 and transistor M3. Here, transistor M2 corresponds to transistor 200b, and transistor M3 corresponds to transistor 200a.

[0687] One of the source and drain of transistor M2 is connected to the gate of transistor M3. The other of the source and drain of transistor M1 is connected to wiring WBL. The gate of transistor M2 is connected to wiring WOL. One of the source and drain of transistor M3 is connected to wiring RBL. The other of the source and drain of transistor M3 is connected to wiring SL.

[0688] Here, wiring WBL corresponds to conductive layer 240b, and wiring WOL corresponds to conductive layer 260b. For example... Figure 32A and Figure 32B As shown, preferably, conductive layer 260b extends in the X direction and conductive layer 240b extends in the Y direction. With this structure, wiring WBL and wiring WOL intersect each other.

[0689] Furthermore, transistor M2 may also include a back gate. Similarly, transistor M3 may also include a back gate.

[0690] <Example 3 of storage device structure>

[0691] The memory cell 150, including the transistor 200 and capacitor 100 shown in this embodiment, can be used as a memory cell of a memory device. The transistor 200 is a transistor whose channel is formed in a semiconductor layer containing oxide semiconductor. Because the transistor 200 has a small off-state current, its use in a memory device allows for long-term retention of stored content. In other words, since refresh operations are not required or occur at extremely low frequencies, the power consumption of the memory device can be significantly reduced. Furthermore, due to the high frequency characteristics of the transistor 200, high-speed read and write operations of the memory device are possible.

[0692] A storage cell array can be constructed by arranging the storage cells 150 in a three-dimensional and matrix manner.

[0693] Figure 33A This is a floor plan of the storage device. Figure 33A An example is shown where two × two storage cells (storage cells 150a to 150d) are arranged in the X and Y directions.

[0694] Figure 33B It is along Figure 33A The cross-sectional view shown is along the dotted-dash line A3-A4. Figure 33A and Figure 33B In the middle, two storage units (in Figure 33B In this case, storage cells 150a and 150b are connected to a common wiring (conductive layer 246).

[0695] Figure 37B The circuit diagram corresponding to two memory cells is shown. (Example) Figure 37B As shown, the storage device 952 includes two storage cells. One storage cell includes a transistor M1 and a capacitor CA1, and the other storage cell includes a transistor M2 and a capacitor CA2. For example, when using... Figure 37B and Figure 33B In the corresponding cases, transistor M1 corresponds to transistor 200a, capacitor CA1 corresponds to capacitor 100a, transistor M2 corresponds to transistor 200b, and capacitor CA2 corresponds to capacitor 100b.

[0696] One of the source and drain of transistor M1 is connected to one of the electrodes of capacitor CA1. The other of the source and drain of transistor M1 is connected to wiring BIL. The gate of transistor M1 is connected to wiring WOL1. The other of the electrodes of capacitor CA1 is connected to wiring CAL. One of the source and drain of transistor M2 is connected to one of the electrodes of capacitor CA2. The other of the source and drain of transistor M2 is connected to wiring BIL. The gate of transistor M2 is connected to wiring WOL2. The other of the electrodes of capacitor CA2 is connected to wiring CAL.

[0697] Here, wiring BIL corresponds to conductive layer 240, wiring WOL1 corresponds to conductive layer 260, wiring WOL2 corresponds to other conductive layers 260, and wiring CAL corresponds to conductive layer 110.

[0698] Figure 33A and Figure 33B The memory cells 150a and 150b shown both have the same structure as memory cell 150. Memory cell 150a includes a capacitor 100a and a transistor 200a, and memory cell 150b includes a capacitor 100b and a transistor 200b. Furthermore, Figure 33A The storage cells 150c and 150d shown also have the same structure as storage cell 150. Therefore, in Figure 33A and Figure 33B In the storage device shown, the same reference numerals are used for components that have the same function as the components constituting the storage device shown in FIG31. Furthermore, for details regarding storage cells 150a to 150d, please refer to the description of storage cell 150 in <Example 1 of Storage Device Structure>.

[0699] like Figure 33A and Figure 33B As shown, conductive layers 260 used for wiring WOL are respectively disposed in memory cells 150a and 150b. Furthermore, as... Figure 33A As shown, a conductive layer 260 is provided in a manner shared between memory cells 150a and 150c, and another conductive layer 260 is provided in a manner shared between memory cells 150b and 150d. Furthermore, a conductive layer 240, serving as part of the wiring BIL, is provided in a manner shared between memory cells 150a and 150b. In other words, the conductive layer 240 is in contact with the oxide semiconductor layer 230 of memory cells 150a and 150b. Additionally, another conductive layer 240 is provided in a manner shared between memory cells 150c and 150d.

[0700] Figure 33B An example is shown of a two-layer structure of conductive layer 240 having conductive layer 240_1 and conductive layer 240_2 on conductive layer 240_1.

[0701] Here, Figure 33A and Figure 33BThe illustrated storage device includes conductive layers 245 and 246, which are connected to storage cells 150a and 150b and serve as connectors (also referred to as connection electrodes). Conductive layer 245 is disposed within an opening formed in insulating layers 140, 180, 130, and 280, and contacts the bottom surface of conductive layer 240_1. Conductive layer 246 is disposed within an opening formed in insulating layers 286, 250, and oxide semiconductor layer 230, and contacts the top surface of conductive layer 240_2. Conductive materials suitable for conductive layer 240 can be used as conductive layers 245 and 246.

[0702] The conductive layer 246 may also contact the top surface of the conductive layer 240_1. Alternatively, the conductive layer 246 may also contact the top surface of the oxide semiconductor layer 230. That is, the conductive layer 240_2 may also have an opening at the location where it overlaps with the conductive layer 246. Furthermore, the oxide semiconductor layer 230 may not have an opening at the location where it overlaps with the conductive layer 246. As the connection portion between the memory cell and the connector, the layer with lower contact resistance to the conductive layer 246 among the layers constituting the conductive layer 240 and the oxide semiconductor layer 230 is preferably in contact with the conductive layer 246.

[0703] Similarly, conductive layer 245 may also contact the bottom surface of conductive layer 240_2 or the bottom surface of oxide semiconductor layer 230. That is, conductive layer 240_1 may also have an opening at the position where it overlaps with conductive layer 246. The layer constituting conductive layer 240 and oxide semiconductor layer 230 with a lower contact resistance to conductive layer 245 is preferably in contact with conductive layer 245.

[0704] Furthermore, the layers with lower wiring resistance among the layers constituting conductive layer 240 and oxide semiconductor layer 230 are preferably in contact with conductive layer 245 and conductive layer 246.

[0705] Conductive layers 245 and 246 are used as plugs or wiring to connect circuit elements such as switches, transistors, capacitors, inductors, resistors, and diodes, as well as wiring, electrodes, or terminals, to memory cells 150a and 150b. For example, conductive layer 245 is used to connect to the plugs or wiring of memory cells 150a and 150b. Figure 33B The read amplifier (not shown) under the storage device is connected, and the conductive layer 246 is disposed with the read amplifier (not shown). Figure 33B The same storage device (not shown) is connected to the storage device shown. In this case, conductive layers 245 and 246 are used as part of the wiring BIL. Thus, by... Figure 33B By placing storage device...

Claims

1. A semiconductor device, comprising: Oxide semiconductor layer; First conductive layer; Second conductive layer; Third conductive layer; First insulating layer; as well as Second insulating layer, The first insulating layer is located on the first conductive layer. The second conductive layer is located on the first insulating layer. The first insulating layer and the second conductive layer include a first opening at the location where they overlap with the first conductive layer. The second conductive layer includes a first layer and a second layer on top of the first layer. The second layer has a portion covering the top surface of the first layer and a portion covering the sides of the first layer. The oxide semiconductor layer has a portion located on the second layer, a portion within the first opening located on the first conductive layer, a portion within the first opening covering the sidewall of the first insulating layer, and a portion within the first opening opposite the sidewall of the first layer across the second layer. The second insulating layer is located on the oxide semiconductor layer. The third conductive layer is located on the second insulating layer. Furthermore, the third conductive layer is located within the first opening and faces the oxide semiconductor layer across the second insulating layer.

2. The semiconductor device according to claim 1, The first conductive layer has a first recess. Furthermore, the first opening in the first insulating layer and the second conductive layer overlaps with the first recess.

3. The semiconductor device according to claim 1, The first layer comprises a metal or alloy. Furthermore, the second layer contains a conductive material containing oxygen or a conductive material containing nitrogen.

4. The semiconductor device according to claim 1, The first layer contains tungsten. The second layer contains indium tin oxide containing silicon.

5. A method for manufacturing a semiconductor device, comprising the following steps: A first insulating layer is formed on the first conductive layer; A second conductive layer is formed on the first insulating layer; A portion of the second conductive layer and a portion of the first insulating layer are removed to form a first opening reaching the first conductive layer and to expose the top surface of the first conductive layer. A third conductive layer is formed in such a way that it covers the top surface of the second conductive layer and the side surface inside the first opening of the second conductive layer; A first oxide semiconductor layer is formed such that it covers the top surface of the first conductive layer, the side surface inside the first opening of the first insulating layer, the side surface of the third conductive layer, and the top surface of the third conductive layer. A third insulating layer is formed on the first oxide semiconductor layer; as well as A fourth conductive layer is formed on the third insulating layer.

6. The method for manufacturing a semiconductor device according to claim 5, During the formation of the first opening, a portion of the second conductive layer is removed using a dry etching process. Furthermore, after the dry etching process and before the formation of the third conductive layer, a portion of the upper end of the first opening of the second conductive layer is removed by a reverse sputtering process.

7. The method for manufacturing a semiconductor device according to claim 5, When forming the first opening, a recess overlapping the first opening is formed in the first conductive layer.

8. The method for manufacturing a semiconductor device according to claim 5 or 6, The third conductive layer contains a conductive material containing oxygen or a conductive material containing nitrogen. Furthermore, the third conductive layer is formed using a sputtering method.

9. The method for manufacturing a semiconductor device according to claim 5 or 6, The third conductive layer contains indium tin oxide comprising silicon. Furthermore, the third conductive layer is formed using a sputtering method.

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